US20190393327A1 - Finfet device with t-shaped fin and method for forming the same - Google Patents
Finfet device with t-shaped fin and method for forming the same Download PDFInfo
- Publication number
- US20190393327A1 US20190393327A1 US16/015,521 US201816015521A US2019393327A1 US 20190393327 A1 US20190393327 A1 US 20190393327A1 US 201816015521 A US201816015521 A US 201816015521A US 2019393327 A1 US2019393327 A1 US 2019393327A1
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- fin structure
- layer
- forming
- liner layer
- fin
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- 238000000034 method Methods 0.000 title claims abstract description 153
- 230000008569 process Effects 0.000 claims abstract description 114
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 238000001039 wet etching Methods 0.000 claims abstract description 27
- 230000000873 masking effect Effects 0.000 claims description 62
- 238000005530 etching Methods 0.000 claims description 28
- 238000002955 isolation Methods 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- 229910019142 PO4 Inorganic materials 0.000 claims description 7
- 239000012190 activator Substances 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 claims description 7
- 239000010452 phosphate Substances 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 239000007800 oxidant agent Substances 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 189
- 238000005229 chemical vapour deposition Methods 0.000 description 25
- 229910052751 metal Inorganic materials 0.000 description 25
- 239000002184 metal Substances 0.000 description 25
- 238000000231 atomic layer deposition Methods 0.000 description 20
- 238000005240 physical vapour deposition Methods 0.000 description 14
- 239000003989 dielectric material Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 2
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 2
- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 239000004254 Ammonium phosphate Substances 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- VQYPKWOGIPDGPN-UHFFFAOYSA-N [C].[Ta] Chemical compound [C].[Ta] VQYPKWOGIPDGPN-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- LFVGISIMTYGQHF-UHFFFAOYSA-N ammonium dihydrogen phosphate Chemical compound [NH4+].OP(O)([O-])=O LFVGISIMTYGQHF-UHFFFAOYSA-N 0.000 description 1
- 229910000387 ammonium dihydrogen phosphate Inorganic materials 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910000148 ammonium phosphate Inorganic materials 0.000 description 1
- 235000019289 ammonium phosphates Nutrition 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- MNNHAPBLZZVQHP-UHFFFAOYSA-N diammonium hydrogen phosphate Chemical compound [NH4+].[NH4+].OP([O-])([O-])=O MNNHAPBLZZVQHP-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- QLOAVXSYZAJECW-UHFFFAOYSA-N methane;molecular fluorine Chemical compound C.FF QLOAVXSYZAJECW-UHFFFAOYSA-N 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 235000019837 monoammonium phosphate Nutrition 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 235000011007 phosphoric acid Nutrition 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Definitions
- FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate.
- the channel of the FinFET is formed in this vertical fin.
- a gate is provided over three sides (e.g., wrapping) the fin.
- Advantages of the FinFET may include reducing the short channel effect and increasing the current flow.
- FIGS. 1A to 1J show perspective representations of various stages of forming a FinFET structure, in accordance with some embodiments of the disclosure.
- FIGS. 2A to 2H show cross-sectional representations of various stages of forming the FinFET structure after the structure of FIG. 1I , in accordance with some embodiments of the disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in some various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between some various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Embodiments of the disclosure form a semiconductor device structure with FinFETs.
- the fins may be patterned using any suitable method.
- the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
- double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
- Embodiments of methods of forming a semiconductor device structure include forming a masking cap to cover a top surface and a portion of a sidewall of a fin structure protruding from a substrate.
- the formation of the masking cap includes forming a first liner layer and a second liner layer over the first liner layer that cover a top surface and a sidewall of the fin structure.
- the first and second liner layers are patterned by a wet etching process, so as to remain a portion of the first liner layer covering the top surface of the fin structure and a portion of the sidewall of the fin structure. The remained portion of the first liner layer serves as the masking cap.
- a portion of the fin structure is thinned by using the masking cap as an etch mask, so that the fin structure has a top portion with a width greater than that of the portion of the fin structure that is thinned.
- the fin structure can be thinned for enhancement of device performance without fin loss or damage to its top portion.
- the wider top portion of the fin structure can provide an etch-compensation to mitigate the fin loss or damage to the top portion of the fin structure in subsequent etching and/or cleaning processes for device fabrication, if presented, thereby increasing the reliability of the device with a fin structure.
- FIGS. 1A to 1J show perspective representations of various stages of forming a fin field effect transistor (FinFET) structure, in accordance with some embodiments of the disclosure.
- a substrate 100 is provided, as shown in FIG. 1A in accordance with some embodiments.
- the substrate 100 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g. with a P-type or an N-type dopant) or undoped.
- the substrate 100 is a wafer, such as a silicon wafer.
- an SOI substrate includes a layer of a semiconductor material formed on an insulator layer.
- the insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like.
- the insulator layer is provided on a substrate, typically a silicon or glass substrate.
- the semiconductor material of the substrate 100 includes silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof.
- the substrate 100 includes silicon.
- the substrate 100 includes an epitaxial layer.
- the substrate 100 has an epitaxial layer overlying a bulk semiconductor.
- a first masking layer 101 and a second masking layer 102 successively stack over the substrate 100 for the subsequent patterning process, in accordance with some embodiments.
- the first masking layer 101 may be used as an etch stop layer when the second masking layer 102 is removed or etched.
- the first masking layer 101 may also be used as an adhesion layer that is formed between the substrate 100 and the second masking layer 102 .
- the first masking layer 101 is made of silicon oxide and is formed by a deposition process, such as a chemical vapor deposition (CVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, or another applicable process.
- CVD chemical vapor deposition
- LPCVD low-pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- HDPCVD high-density plasma chemical vapor deposition
- the second masking layer 102 is made of silicon oxide, silicon nitride, silicon oxynitride, or another applicable material. In some other embodiments, more than one second masking layer 102 is formed over the first masking layer 101 . In some embodiments, the second masking layer 102 is formed by a deposition process, such as a chemical vapor deposition (CVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, or another applicable process.
- CVD chemical vapor deposition
- LPCVD low-pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- HDPCVD high-density plasma chemical vapor deposition
- a patterned photoresist layer 105 may be formed over the second masking layer 102 for subsequent definition of one or more fin structures in the substrate 100 .
- the patterned photoresist layer 105 is formed by a photolithography process.
- the photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking).
- the first masking layer 101 and the overlying second masking layer 102 are patterned by using the patterned photoresist layer 105 as an etch mask, as shown in FIG. 1B in accordance with some embodiments. After the first masking layer 101 and the overlying second masking layer 102 are etched, a patterned first masking layer 101 and a patterned second masking layer 102 are formed, so that portions of the underlying substrate 100 are exposed.
- the patterned photoresist layer 105 is removed, as shown in FIG. 1C in accordance with some embodiments. Afterwards, the exposed portions of the substrate 100 are partially removed by an etching process using the patterned second masking layer 102 and the patterned first masking layer 101 as an etch mask. As a result, fin structures and trenches in the substrate 100 are formed. In order to simplify the diagram, two fin structures 108 protruding from the substrate 100 are depicted as an example.
- each of the fin structures 108 has a top width that is greater than a desired or target width, so as to increase the fin strength for mitigating the fin damage, distortion, and/or collapse during the subsequent processes, such as etching and/or cleaning processes. Therefore, a fin-trim process is performed after the subsequent formed dummy gate structure is removed, thereby narrowing the fin width to obtaining a desired fin width. As a result, the device performance can be increased due to the reduction of the fin width.
- the etching process for formation of fin structures 108 is a dry etching process or a wet etching process.
- the substrate 100 is etched by a dry etching process, such as a reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof.
- the dry etching process may be performed using a process gas including fluorine-based etchant gas.
- the process gas may include SF 6 , C x F y , NF 3 or a combination thereof.
- the etching process may be a time-controlled process, and continue until the fin structures 108 are formed and reach a predetermined height.
- a person of ordinary skill in the art will readily understand other methods of forming the fin structures, which are contemplated within the scope of some embodiments.
- an insulating layer 116 is formed to cover the fin structures 108 over the substrate 100 , as shown in FIG. 1D in accordance with some embodiments.
- the insulating layer 116 is made of silicon oxide, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or another suitable dielectric material or another low-k dielectric material.
- the insulating layer 116 may be deposited by a chemical vapor deposition (CVD) process, a spin-on-glass process, or another applicable process.
- one or more liners are formed on the sidewalls of the fin structures 108 and the bottom of the trenches in the substrate 100 .
- the liner(s) may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide (SiC), or a combination thereof.
- the liner(s) may be deposited by a chemical vapor deposition (CVD) process or another applicable process.
- the insulating layer 116 is etched back to expose the top surface of the patterned second masking layer 102 , in accordance with some embodiments.
- the insulating layer 116 is etched back by a chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- the patterned second masking layer 102 and the patterned first masking layer 101 are removed by one or more etching processes, so as to expose the top surfaces of the fin structures 108 .
- the patterned second masking layer 102 and the patterned first masking layer 101 are removed by a dry etching process, a wet etching process, or a combination thereof.
- the exposed insulating layer 116 is further etched back to form isolation features 116 a , as shown in FIG. 1E in accordance with some embodiments.
- the isolation feature 116 a includes the remaining insulating layer 116 and the liner(s) (not shown) surrounding the remaining insulating layer 116 .
- the isolation features 116 a may be shallow trench isolation (STI) structures surrounding the fin structures 108 , so as to prevent electrical interference or crosstalk.
- a portion of the fin structure 108 is embedded in the isolation features 116 a , so that the lower portion of each fin structure 108 is surrounded by the isolation features 116 a and the upper portion of each fin structure 108 protrudes from the isolation features 116 a.
- STI shallow trench isolation
- a dummy gate structure 120 is formed across the fin structures 108 and extends over the isolation features 116 a , as shown in FIG. 1F , in accordance with some embodiments.
- the dummy gate structure 120 includes a dummy gate dielectric layer 121 and a dummy gate electrode layer 123 over the dummy gate dielectric layer 121 .
- the dummy gate dielectric layer 121 is made of a high-k dielectric material such as metal oxide in accordance with some embodiments.
- high-k dielectric materials include hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, or other applicable dielectric materials.
- the dummy gate dielectric layer 121 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or other applicable processes.
- the dummy gate electrode layer 123 is formed over dummy gate dielectric layer 121 in accordance with some embodiments.
- the dummy gate electrode layer 123 is made of polysilicon.
- the dummy gate dielectric layer 121 and the dummy gate electrode layer 123 are patterned to form the dummy gate structure 120 over the fin structures 108 , in accordance with some embodiments.
- the dummy gate structure 120 further includes a dummy cap layer (not shown) formed over the dummy gate electrode layer 123 .
- gate spacer layers 126 are formed on opposite sidewall surfaces of the dummy gate structure 120 .
- the gate spacer layers 126 may be a single layer or multiple layers.
- the gate spacer layers 126 are formed of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or other applicable materials.
- Openings 111 are formed in each fin structure 108 and on opposing sidewall surfaces of the dummy gate structure 120 by a fin recess process after the gate spacer layers 126 are formed, as shown in FIG. 1G in accordance with some embodiments.
- the fin recess process is a dry etching process or a wet etching process.
- the bottom surfaces of the openings 111 are lower than the top surfaces of the isolation features 124 .
- source and drain features 130 is formed in the openings 111 (indicated by FIG. 1G ) of each fin structure 108 and protrudes from the openings 111 , as shown in FIG. 1H in accordance with some embodiments.
- portions of the fin structure 108 adjacent to the dummy gate structure 120 are recessed to form openings 111
- a strained material is grown in each opening 111 of the fin structure 108 by an epitaxial process to form the source and drain features 130 .
- the source and drain features 130 are formed over the fin structure 108 on opposing sidewall surfaces of the dummy gate structure 120 .
- the lattice constant of the strained material may be different from the lattice constant of the substrate 100 .
- the source and drain features 130 include Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, or the like.
- an insulating layer 136 (e.g., an inter-layer dielectric (ILD) layer) is formed over the substrate 100 and covers the source and drain features 130 , as shown in FIG. 1I in accordance with some embodiments.
- the insulating layer 136 may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other applicable dielectric materials.
- low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide.
- the insulating layer 136 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, or another applicable process.
- a contact etch stop layer (not shown) is formed between the substrate 100 and the insulating layer 136 .
- the contact etch stop layer is made of silicon nitride, silicon oxynitride, and/or other applicable materials, in accordance with some embodiments.
- the contact etch stop layer may be formed by plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or other applicable processes.
- PECVD plasma enhanced chemical vapor deposition
- LPCVD low-pressure chemical vapor deposition
- ALD atomic layer deposition
- a planarization process is performed on the insulating layer 136 until the top surface of the dummy gate structure 120 is exposed.
- the insulating layer 136 is planarized by a polishing process, such as a chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- the dummy gate structure 120 is removed to form an opening 140 in the insulating layer 136 , as shown in FIG. 1J in accordance with some embodiments.
- the dummy gate dielectric layer 121 and the dummy gate electrode layer 123 of the dummy gate structure 120 are removed by an etching process, such as a dry etching process or a wet etching process. After the dummy gate structure 120 is removed, a portion of each fin structure 108 and a portion of the isolation feature 116 a in the opening 140 are exposed.
- FIGS. 2A to 2H show cross-sectional representations of various stages of forming the FinFET structure after the structure of FIG. 1I , in accordance with some embodiments of the disclosure.
- FIG. 2A shows a cross-sectional representation taken along line 2 - 2 ′ of the structure shown in FIG. 1J .
- the structure shown in FIG. 1J is provided, as shown in FIG. 2A in accordance with some embodiments.
- the structure shown in FIG. 2A includes a substrate 100 having fin structures 108 protruding from the substrate 100 .
- Each fin structure 108 exposed in the opening 140 has a top surface 109 a and a sidewall 109 b .
- a portion of an isolation feature 116 a that is formed over the substrate 100 and surrounding the sidewall 109 b of a bottom portion of each fin structure 108 is also exposed in the opening 140 .
- a masking cap 170 (as indicated in FIG. 2D ) is formed over each exposed fin structure 108 in the opening 140 , as shown in FIGS. 2B to 2D in accordance with some embodiments.
- a first liner layer 150 is formed over the exposed isolation feature 116 a and conformally covers the top surface 109 a and the sidewall 109 b of each exposed fin structure 108 in the opening 140 .
- the first liner layer 150 has a thickness that is in a range from about 10 ⁇ to about 20 ⁇ .
- the first liner layer 150 is made of metal nitride, such as tantalum nitride (TaN), and is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or other applicable processes.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- ALD atomic layer deposition
- PECVD plasma enhanced chemical vapor deposition
- a second liner layer 152 is formed over the first liner layer 150 to conformally covers the top surface 109 a and the sidewall 109 b of each exposed fin structure 108 in the opening 140 , as shown in FIG. 2C in accordance with some embodiments.
- the second liner layer 152 has a thickness greater than that of the first liner layer 150 .
- the second liner layer 152 has a thickness that is in a range from about 20 ⁇ to about 60 ⁇ .
- the second liner layer 152 is made of a tungsten-containing material, such as tungsten carbide or tungsten nitride, or the like, and is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or other applicable processes.
- CVD chemical vapor deposition
- ALD atomic layer deposition
- the second liner layer 152 and the first liner layer 150 are patterned, as shown in FIG. 2C in accordance with some embodiments.
- the second liner layer 152 and the first liner layer 150 are patterned by performing a wet etching process 160 by using an etching solution including an oxidant and a phosphate-containing activator.
- the oxidant includes ozone or hydrogen peroxide and the phosphate-containing activator includes ammonium phosphate, ammonium dihydrogen phosphate, phosphoric acid, or the like.
- the concentration of the oxidant and the phosphate-containing activator in the etching solution is in a range from about 1 wt % to about 5 wt %, such as higher than 2%.
- the wet etching process 160 is performed for a sufficient time that is in a range from about 2 minutes to about 5 minutes at temperature in a range from about 40° C. to about 70° C.
- the material of the second liner layer 152 is selected, such that the second liner layer 152 a higher etching rate than the first liner layer 150 with respect to such an etching solution including the oxidant and the phosphate-containing activator.
- the second liner layer 152 is used or serves as an etch-assisted layer of the first liner layer 150 , so as to facilitate the removal of the first liner layer 150 during the wet etching process 160 . After the wet etching process 160 is performed, the second liner layer 152 is completely removed.
- the first liner layer 150 over the sidewall 109 b of the fin structure 108 and over the isolation feature 116 a has a deposition structure that is weaker than that of the first liner layer 150 near the top surface 109 a of the fin structure 108 .
- the phosphate-containing activator is employed to mitigate the etch of the second liner layer 152 and the first liner layer 150 formed over the top surface 109 a of the fin structure 108 . Therefore, the first liner layer 150 near the top surface 109 a of the fin structure 108 remains, and the other portions of the first liner layer 150 are entirely removed after the wet etching process 160 is performed.
- the masking cap 170 that is made of the remained first liner layer 150 and includes a plate portion 172 and a wall portion 174 extending from the plate portion 172 is formed, as shown in FIG. 2D .
- the plate portion 172 of the formed masking cap 170 covers the top surface 109 a of the respective exposed fin structure 108 in the opening 140 .
- the wall portion 174 of the formed masking cap 170 partially exposes the sidewall 109 b of the respective exposed fin structure 108 in the opening 140 .
- each fin structure 108 in the opening 140 is laterally recessed by performing an etching process 180 (which is also referred to as a fin-trim process), as shown in FIG. 2E in accordance with some embodiments.
- a portion of the fin structure 108 is removed or etched from the sidewall 109 b of the fin structure 108 by using the masking cap 170 (i.e., the remained first liner layer 150 ) as an etch mask, so as to form a lateral recess 182 in the fin structure 108 , as shown in FIG. 2F .
- the lateral recess 182 makes the fin structure 108 have different widths. More specifically, as shown in FIG. 2F , the fin structure 108 protruding from the substrate 100 and partially surrounded by the isolation feature 116 a includes a first portion 108 a (or middle portion), a second portion 108 b (or top portion), and a third portion 108 c (or bottom portion). The first portion 108 a protrudes above the isolation feature 116 a and has a first width W 1 .
- the second portion 108 b extends from the top of the first portion 108 a and has a second width W 2 greater than the first width W 1 , so that the fin structure 108 above the isolation feature 116 a including the first portion 108 a and the second portion 108 b has a T-shaped profile.
- the third portion is surrounded by the isolation feature 116 a and has a third width W 3 greater than the first width W 1 .
- the third width W 3 may be substantially equal to or slightly greater than the second width W 2 .
- the masking cap 170 provides a protection of the top portion (i.e., the second portion 108 b ) of the fin structure 108 during the fin-trim process (i.e., the etching process 180 ) is performed, so that the fin loss or damage at its top portion during the fin-trim process can be prevented. As a result, fin collapse can be prevented after the fin-trim process is performed, thereby maintain or increasing the reliability of the device with the fin structure.
- the etching process 180 is a wet etching process using an etching solution including a base (such as ammonium hydroxide, tetramethyl ammonium hydroxide, or the like).
- a base such as ammonium hydroxide, tetramethyl ammonium hydroxide, or the like.
- the concentration of the base in the etching solution is in a range from about 1 wt % to about 5 wt %, such as higher than 2%.
- the etching process 180 i.e., the wet etching process using an etching solution including a base
- the masking cap 170 (shown in FIG. 2F ) is removed from the fin structure 108 , as shown in FIG. 2G in accordance with some embodiments.
- the masking cap 170 is removed by a dry etching process, so as to expose the second portion 108 b of the fin structure 108 .
- the partially thinned fin structure 108 formed by the fin-trim process can enhance device performance.
- the wider top portion (i.e., the second portion 108 b ) of the fin structure 108 can provide an etch-compensation to mitigate the fin loss at the top portion of the fin structure 108 in subsequent processes (e.g., etching and/or cleaning processes), if presented, thereby preventing the thinned fin from collapsing, so as to maintain the reliability of the device with a fin structure.
- the width of the top portion i.e., the width W 2 of the second portion 108 b
- W 4 is denoted as W 4 (as indicated in FIG. 2H ).
- a gate structure 190 is formed in opening 140 , as shown in FIG. 2H in accordance with some embodiments. More specifically, a gate dielectric layer 191 is conformally formed over the insulating layer 136 (as shown in FIG. 1J ) and conformally covers the inner surface of the opening 140 (as shown in FIG. 1J ). The gate dielectric layer 191 formed in the opening 140 may cover the gate spacer layers 126 and each exposed fin structure 108 in the opening 140 . In some embodiments, the gate dielectric layer 191 is made of a high k dielectric material, such as metal oxide.
- the high-k dielectric material may include hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, or other applicable dielectric materials.
- the gate dielectric layer 191 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable process.
- An interfacial layer (not shown) may be formed between each exposed fin structure 108 and the gate dielectric layer 191 , so that the adhesion of the gate dielectric layer 191 can be improved.
- the interfacial layer is made of SiO 2 .
- the interfacial layer is formed by an atomic layer deposition (ALD) process, a thermal oxidation process, chemical vapor deposition (CVD) process, or another applicable process.
- a work functional metal layer (not shown) is conformally formed over the insulating layer 136 and conformally covers the inner surface of the opening 140 that is covered by the gate dielectric layer 191 , in accordance with some embodiments.
- the work function metal layer is tuned to have a proper work function.
- the work function metal layer is made of an N-type work-function metal or a P-type work-function metal.
- N-type work-function metals include titanium (Ti), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbon nitride (TaCN), and combinations thereof.
- the P-work-function metal includes titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof.
- the work function metal layer 162 is formed by atomic layer deposition (ALD), sputtering, physical vapor deposition (PVD), or another applicable process.
- a conformal capping or barrier layer (not shown) is formed over the gate dielectric layer 191 prior to formation of the work function metal layer, so that the capping or barrier layer is between gate dielectric layer 191 and the work function metal layer.
- the capping or barrier layer is employed to prevent the metal formed over it from penetrating into the channel region of the fin structure (e.g., the fin structure 108 in the opening 140 ) below the metal gate structure (e.g., the gate structure 190 ).
- the capping or barrier layer is made of metal nitride. Examples of the metal nitride include TiN, TaN, and WN.
- the capping or barrier layer may be formed by physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable process.
- a gate electrode layer 193 is formed over the insulating layer 136 and fills the opening 140 to cover the work functional metal layer, in accordance with some embodiments.
- the gate electrode layer 193 is made of tungsten (W). In some embodiments, the gate electrode layer 193 is formed by chemical vapor deposition (CVD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), or another applicable process.
- CVD chemical vapor deposition
- HDPCVD high density plasma CVD
- MOCVD metal organic CVD
- PECVD plasma enhanced CVD
- a conformal blocking layer (not shown) is formed over the work functional metal layer prior to formation of the gate electrode layer 193 , so that the blocking layer is between work functional metal layer and the gate electrode layer 193 .
- the blocking layer is employed to prevent the byproduct formed during the gate electrode layer 193 deposition from diffusing toward the layers below.
- the blocking layer is made of metal nitride. Examples of metal nitride include TiN, TaN, and WN.
- the blocking layer may be formed by physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable process.
- the gate electrode layer 193 , the work function metal layer, and the gate dielectric layer 191 over the insulating layer 136 are successively removed, as shown in FIG. 2H in accordance with some embodiments.
- the gate electrode layer 193 , the work function metal layer 162 , and the gate dielectric layer 191 over the insulating layer 136 are successively removed by a chemical mechanical polishing (CMP) process to expose a top surface of the insulating layer 136 .
- CMP chemical mechanical polishing
- the gate structure 190 is formed in the opening 140 .
- the gate structure 190 at least includes the gate dielectric layer 191 , the work function metal layer, and the gate electrode layer 193 .
- Embodiments of a semiconductor device structure and a method for forming the same are provided.
- the semiconductor device structure includes a first liner layer that covers a top surface and a sidewall of a fin structure.
- the first liner layer is patterned by a wet etching process, so as to form a masking cap that covers the top surface of the fin structure and a portion of the sidewall of the fin structure.
- the fin structure is thinned by using the masking cap as an etch mask.
- the masking cap provides a protection of the top portion of the fin structure during the fin structure is thinned, so that the fin structure has a top portion with a width greater than that of the other portion of the fin structure that is thinned.
- the partially thinned fin structure can enhance device performance.
- the wider top portion of the fin structure can also serve as an etch-compensation to mitigate the fin loss or damage at its top portion in subsequent etching and/or cleaning processes for device fabrication, thereby preventing device degradation.
- a method of forming a semiconductor device structure includes forming a fin structure protruding from a substrate and forming a first liner layer to cover a top surface and a sidewall of the fin structure.
- the method also includes patterning the first liner layer by performing a wet etching process, so as to remain a portion of the first liner layer covering the top surface of the fin structure and a portion of the sidewall of the fin structure.
- the method also includes removing a portion of the fin structure from the sidewall of the fin structure by using the remained portion of the first liner layer as an etch mask, so as to form a lateral recess in the fin structure.
- a method of forming a semiconductor device structure includes forming a first gate structure over a fin structure that protrudes from a substrate and forming source and drain features over the fin structure on opposing sidewall surfaces of the first gate structure.
- the method also includes forming an insulating layer over the substrate and covering the source and drain features and removing the first gate structure to form an opening in the insulating layer and expose the fin structure in the opening.
- the method also includes forming a masking cap over the exposed fin structure in the opening.
- the masking cap includes a plate portion covering a top surface of the exposed fin structure in the opening.
- the masking cap also includes a wall portion extending from the plate portion and partially exposing a sidewall of the exposed fin structure in the opening.
- the method also includes laterally recessing the partially exposed sidewall of the fin structure in the opening.
- a semiconductor device structure in some embodiments, includes an isolation feature over a substrate and a fin structure protruding from the substrate and partially surrounded by the isolation feature.
- the fin structure includes a first portion above the isolation feature and having a first width.
- the fin structure also includes a second portion extending from the top of the first portion and having a second width greater than the first width, so that the fin structure above the isolation feature has a T-shaped profile.
- the semiconductor device structure also includes a gate structure covering the first portion and the second portion of the fin structure.
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Abstract
Description
- The semiconductor industry has experienced rapid growth and demands for highly integrated semiconductor devices are increasing. Technological advances in integrated circuit (IC) design and materials have produced generations of ICs. Each generation has smaller and more complex circuits than previous generations. In the course of IC evolution, functional density has generally increased while geometric size (i.e., the smallest component (or line) that can be created through a fabrication process) has decreased.
- As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over three sides (e.g., wrapping) the fin. Advantages of the FinFET may include reducing the short channel effect and increasing the current flow.
- Although existing FinFETs and methods of fabricating FinFETs have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, as the size of the FinFET has been reduced, is has become a challenge to integrate a fin-trim process into the fabrication processes of the FinFET device.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIGS. 1A to 1J show perspective representations of various stages of forming a FinFET structure, in accordance with some embodiments of the disclosure. -
FIGS. 2A to 2H show cross-sectional representations of various stages of forming the FinFET structure after the structure ofFIG. 1I , in accordance with some embodiments of the disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows includes embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. The present disclosure may repeat reference numerals and/or letters in some various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between some various embodiments and/or configurations discussed.
- Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.
- Embodiments of the disclosure form a semiconductor device structure with FinFETs. The fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
- Embodiments of methods of forming a semiconductor device structure are provided. The method of forming a semiconductor device structure includes forming a masking cap to cover a top surface and a portion of a sidewall of a fin structure protruding from a substrate. The formation of the masking cap includes forming a first liner layer and a second liner layer over the first liner layer that cover a top surface and a sidewall of the fin structure. The first and second liner layers are patterned by a wet etching process, so as to remain a portion of the first liner layer covering the top surface of the fin structure and a portion of the sidewall of the fin structure. The remained portion of the first liner layer serves as the masking cap. Afterwards, a portion of the fin structure is thinned by using the masking cap as an etch mask, so that the fin structure has a top portion with a width greater than that of the portion of the fin structure that is thinned. As a result, the fin structure can be thinned for enhancement of device performance without fin loss or damage to its top portion. After the masking cap is removed, the wider top portion of the fin structure can provide an etch-compensation to mitigate the fin loss or damage to the top portion of the fin structure in subsequent etching and/or cleaning processes for device fabrication, if presented, thereby increasing the reliability of the device with a fin structure.
- Embodiments of a semiconductor device structure and a method of forming a semiconductor device structure are provided.
FIGS. 1A to 1J show perspective representations of various stages of forming a fin field effect transistor (FinFET) structure, in accordance with some embodiments of the disclosure. Asubstrate 100 is provided, as shown inFIG. 1A in accordance with some embodiments. In some embodiments, thesubstrate 100 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g. with a P-type or an N-type dopant) or undoped. In some embodiments, thesubstrate 100 is a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. - Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the
substrate 100 includes silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. In some embodiments, thesubstrate 100 includes silicon. In some embodiments, thesubstrate 100 includes an epitaxial layer. For example, thesubstrate 100 has an epitaxial layer overlying a bulk semiconductor. - A
first masking layer 101 and asecond masking layer 102 successively stack over thesubstrate 100 for the subsequent patterning process, in accordance with some embodiments. As an example, thefirst masking layer 101 may be used as an etch stop layer when thesecond masking layer 102 is removed or etched. Thefirst masking layer 101 may also be used as an adhesion layer that is formed between thesubstrate 100 and thesecond masking layer 102. - In some embodiments, the
first masking layer 101 is made of silicon oxide and is formed by a deposition process, such as a chemical vapor deposition (CVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, or another applicable process. - In some embodiments, the
second masking layer 102 is made of silicon oxide, silicon nitride, silicon oxynitride, or another applicable material. In some other embodiments, more than onesecond masking layer 102 is formed over thefirst masking layer 101. In some embodiments, thesecond masking layer 102 is formed by a deposition process, such as a chemical vapor deposition (CVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, or another applicable process. - After formation of the
first masking layer 101 and thesecond masking layer 102, a patternedphotoresist layer 105 may be formed over thesecond masking layer 102 for subsequent definition of one or more fin structures in thesubstrate 100. In some embodiments, the patternedphotoresist layer 105 is formed by a photolithography process. The photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). - The
first masking layer 101 and the overlyingsecond masking layer 102 are patterned by using the patternedphotoresist layer 105 as an etch mask, as shown inFIG. 1B in accordance with some embodiments. After thefirst masking layer 101 and the overlyingsecond masking layer 102 are etched, a patternedfirst masking layer 101 and a patternedsecond masking layer 102 are formed, so that portions of theunderlying substrate 100 are exposed. - After the portions of the
substrate 100 are exposed by forming the patternedfirst masking layer 101 and the patternedsecond masking layer 102, the patternedphotoresist layer 105 is removed, as shown inFIG. 1C in accordance with some embodiments. Afterwards, the exposed portions of thesubstrate 100 are partially removed by an etching process using the patternedsecond masking layer 102 and the patternedfirst masking layer 101 as an etch mask. As a result, fin structures and trenches in thesubstrate 100 are formed. In order to simplify the diagram, twofin structures 108 protruding from thesubstrate 100 are depicted as an example. In some embodiments, each of thefin structures 108 has a top width that is greater than a desired or target width, so as to increase the fin strength for mitigating the fin damage, distortion, and/or collapse during the subsequent processes, such as etching and/or cleaning processes. Therefore, a fin-trim process is performed after the subsequent formed dummy gate structure is removed, thereby narrowing the fin width to obtaining a desired fin width. As a result, the device performance can be increased due to the reduction of the fin width. - In some embodiments, the etching process for formation of
fin structures 108 is a dry etching process or a wet etching process. For example, thesubstrate 100 is etched by a dry etching process, such as a reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The dry etching process may be performed using a process gas including fluorine-based etchant gas. For example, the process gas may include SF6, CxFy, NF3 or a combination thereof. The etching process may be a time-controlled process, and continue until thefin structures 108 are formed and reach a predetermined height. A person of ordinary skill in the art will readily understand other methods of forming the fin structures, which are contemplated within the scope of some embodiments. - Afterwards, an insulating
layer 116 is formed to cover thefin structures 108 over thesubstrate 100, as shown inFIG. 1D in accordance with some embodiments. In some embodiments, the insulatinglayer 116 is made of silicon oxide, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or another suitable dielectric material or another low-k dielectric material. The insulatinglayer 116 may be deposited by a chemical vapor deposition (CVD) process, a spin-on-glass process, or another applicable process. - In some other embodiments, before the insulating
layer 116 is formed, one or more liners (not shown) are formed on the sidewalls of thefin structures 108 and the bottom of the trenches in thesubstrate 100. In those cases, the liner(s) may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide (SiC), or a combination thereof. The liner(s) may be deposited by a chemical vapor deposition (CVD) process or another applicable process. - Afterwards, the insulating
layer 116 is etched back to expose the top surface of the patternedsecond masking layer 102, in accordance with some embodiments. For example, the insulatinglayer 116 is etched back by a chemical mechanical polishing (CMP) process. After the top surface of the patternedsecond masking layer 102 is exposed, the patternedsecond masking layer 102 and the patternedfirst masking layer 101 are removed by one or more etching processes, so as to expose the top surfaces of thefin structures 108. For example, the patternedsecond masking layer 102 and the patternedfirst masking layer 101 are removed by a dry etching process, a wet etching process, or a combination thereof. - Afterwards, the exposed insulating
layer 116 is further etched back to form isolation features 116 a, as shown inFIG. 1E in accordance with some embodiments. In some embodiments, the isolation feature 116 a includes the remaining insulatinglayer 116 and the liner(s) (not shown) surrounding the remaining insulatinglayer 116. The isolation features 116 a may be shallow trench isolation (STI) structures surrounding thefin structures 108, so as to prevent electrical interference or crosstalk. A portion of thefin structure 108 is embedded in the isolation features 116 a, so that the lower portion of eachfin structure 108 is surrounded by the isolation features 116 a and the upper portion of eachfin structure 108 protrudes from the isolation features 116 a. - After formation of the isolation features 116 a, a
dummy gate structure 120 is formed across thefin structures 108 and extends over the isolation features 116 a, as shown inFIG. 1F , in accordance with some embodiments. In some embodiments, thedummy gate structure 120 includes a dummygate dielectric layer 121 and a dummygate electrode layer 123 over the dummygate dielectric layer 121. - The dummy
gate dielectric layer 121 is made of a high-k dielectric material such as metal oxide in accordance with some embodiments. Examples of high-k dielectric materials include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, or other applicable dielectric materials. In some embodiments, the dummygate dielectric layer 121 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or other applicable processes. - After the dummy
gate dielectric layer 121 is formed, the dummygate electrode layer 123 is formed over dummygate dielectric layer 121 in accordance with some embodiments. In some embodiments, the dummygate electrode layer 123 is made of polysilicon. Afterwards, the dummygate dielectric layer 121 and the dummygate electrode layer 123 are patterned to form thedummy gate structure 120 over thefin structures 108, in accordance with some embodiments. In some other embodiments, thedummy gate structure 120 further includes a dummy cap layer (not shown) formed over the dummygate electrode layer 123. - After the
dummy gate structure 120 is formed, gate spacer layers 126 are formed on opposite sidewall surfaces of thedummy gate structure 120. The gate spacer layers 126 may be a single layer or multiple layers. In some embodiments, the gate spacer layers 126 are formed of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or other applicable materials. -
Openings 111 are formed in eachfin structure 108 and on opposing sidewall surfaces of thedummy gate structure 120 by a fin recess process after the gate spacer layers 126 are formed, as shown inFIG. 1G in accordance with some embodiments. In some embodiments, the fin recess process is a dry etching process or a wet etching process. Moreover, after the fin recess process is performed, the bottom surfaces of theopenings 111 are lower than the top surfaces of the isolation features 124. - Afterwards, source and drain features 130 is formed in the openings 111 (indicated by
FIG. 1G ) of eachfin structure 108 and protrudes from theopenings 111, as shown inFIG. 1H in accordance with some embodiments. In some embodiments, portions of thefin structure 108 adjacent to thedummy gate structure 120 are recessed to formopenings 111, and a strained material is grown in each opening 111 of thefin structure 108 by an epitaxial process to form the source and drain features 130. The source and drain features 130 are formed over thefin structure 108 on opposing sidewall surfaces of thedummy gate structure 120. - In some embodiments, the lattice constant of the strained material may be different from the lattice constant of the
substrate 100. In some embodiments, the source and drain features 130 include Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, or the like. - After the source and drain features 130 are formed, an insulating layer 136 (e.g., an inter-layer dielectric (ILD) layer) is formed over the
substrate 100 and covers the source and drain features 130, as shown inFIG. 1I in accordance with some embodiments. In some embodiments, the insulatinglayer 136 may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The insulatinglayer 136 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, or another applicable process. - In some other embodiments, a contact etch stop layer (not shown) is formed between the
substrate 100 and the insulatinglayer 136. The contact etch stop layer is made of silicon nitride, silicon oxynitride, and/or other applicable materials, in accordance with some embodiments. The contact etch stop layer may be formed by plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or other applicable processes. - Afterwards, a planarization process is performed on the insulating
layer 136 until the top surface of thedummy gate structure 120 is exposed. In some embodiments, the insulatinglayer 136 is planarized by a polishing process, such as a chemical mechanical polishing (CMP) process. - Afterwards, the
dummy gate structure 120 is removed to form anopening 140 in the insulatinglayer 136, as shown inFIG. 1J in accordance with some embodiments. The dummygate dielectric layer 121 and the dummygate electrode layer 123 of thedummy gate structure 120 are removed by an etching process, such as a dry etching process or a wet etching process. After thedummy gate structure 120 is removed, a portion of eachfin structure 108 and a portion of the isolation feature 116 a in theopening 140 are exposed. -
FIGS. 2A to 2H show cross-sectional representations of various stages of forming the FinFET structure after the structure ofFIG. 1I , in accordance with some embodiments of the disclosure.FIG. 2A shows a cross-sectional representation taken along line 2-2′ of the structure shown inFIG. 1J . - The structure shown in
FIG. 1J is provided, as shown inFIG. 2A in accordance with some embodiments. In some embodiments, the structure shown inFIG. 2A includes asubstrate 100 havingfin structures 108 protruding from thesubstrate 100. Eachfin structure 108 exposed in theopening 140 has atop surface 109 a and asidewall 109 b. A portion of anisolation feature 116 a that is formed over thesubstrate 100 and surrounding thesidewall 109 b of a bottom portion of eachfin structure 108 is also exposed in theopening 140. - Afterwards, a masking cap 170 (as indicated in
FIG. 2D ) is formed over each exposedfin structure 108 in theopening 140, as shown inFIGS. 2B to 2D in accordance with some embodiments. As shown inFIG. 2B , afirst liner layer 150 is formed over the exposed isolation feature 116 a and conformally covers thetop surface 109 a and thesidewall 109 b of each exposedfin structure 108 in theopening 140. In some embodiments, thefirst liner layer 150 has a thickness that is in a range from about 10 Å to about 20 Å. In some embodiments, thefirst liner layer 150 is made of metal nitride, such as tantalum nitride (TaN), and is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or other applicable processes. - Afterwards, a
second liner layer 152 is formed over thefirst liner layer 150 to conformally covers thetop surface 109 a and thesidewall 109 b of each exposedfin structure 108 in theopening 140, as shown inFIG. 2C in accordance with some embodiments. In some embodiments, thesecond liner layer 152 has a thickness greater than that of thefirst liner layer 150. As an example, thesecond liner layer 152 has a thickness that is in a range from about 20 Å to about 60 Å. In some embodiments, thesecond liner layer 152 is made of a tungsten-containing material, such as tungsten carbide or tungsten nitride, or the like, and is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or other applicable processes. - After the
second liner layer 152 and thefirst liner layer 150 are formed, thesecond liner layer 152 and thefirst liner layer 150 are patterned, as shown inFIG. 2C in accordance with some embodiments. In some embodiments, thesecond liner layer 152 and thefirst liner layer 150 are patterned by performing a wet etching process 160 by using an etching solution including an oxidant and a phosphate-containing activator. - In some embodiments, the oxidant includes ozone or hydrogen peroxide and the phosphate-containing activator includes ammonium phosphate, ammonium dihydrogen phosphate, phosphoric acid, or the like. In some embodiments, the concentration of the oxidant and the phosphate-containing activator in the etching solution is in a range from about 1 wt % to about 5 wt %, such as higher than 2%. In some embodiments, the wet etching process 160 is performed for a sufficient time that is in a range from about 2 minutes to about 5 minutes at temperature in a range from about 40° C. to about 70° C.
- The material of the
second liner layer 152 is selected, such that the second liner layer 152 a higher etching rate than thefirst liner layer 150 with respect to such an etching solution including the oxidant and the phosphate-containing activator. Thesecond liner layer 152 is used or serves as an etch-assisted layer of thefirst liner layer 150, so as to facilitate the removal of thefirst liner layer 150 during the wet etching process 160. After the wet etching process 160 is performed, thesecond liner layer 152 is completely removed. - It should be noted that the
first liner layer 150 over thesidewall 109 b of thefin structure 108 and over the isolation feature 116 a has a deposition structure that is weaker than that of thefirst liner layer 150 near thetop surface 109 a of thefin structure 108. Moreover, in the etching solution used for the wet etching process 160, the phosphate-containing activator is employed to mitigate the etch of thesecond liner layer 152 and thefirst liner layer 150 formed over thetop surface 109 a of thefin structure 108. Therefore, thefirst liner layer 150 near thetop surface 109 a of thefin structure 108 remains, and the other portions of thefirst liner layer 150 are entirely removed after the wet etching process 160 is performed. Namely, a portion of thefirst liner layer 150 covering thetop surface 109 a of thefin structure 108 and a portion of thesidewall 109 b of thefin structure 108 are remained after the wet etching process 160 is completed. As a result, the maskingcap 170 that is made of the remainedfirst liner layer 150 and includes aplate portion 172 and awall portion 174 extending from theplate portion 172 is formed, as shown inFIG. 2D . - As shown in
FIG. 2D , theplate portion 172 of the formedmasking cap 170 covers thetop surface 109 a of the respective exposedfin structure 108 in theopening 140. Moreover, thewall portion 174 of the formedmasking cap 170 partially exposes thesidewall 109 b of the respective exposedfin structure 108 in theopening 140. - Afterwards, the partially exposed
sidewall 109 b of eachfin structure 108 in theopening 140 is laterally recessed by performing an etching process 180 (which is also referred to as a fin-trim process), as shown inFIG. 2E in accordance with some embodiments. In some embodiments, a portion of thefin structure 108 is removed or etched from thesidewall 109 b of thefin structure 108 by using the masking cap 170 (i.e., the remained first liner layer 150) as an etch mask, so as to form alateral recess 182 in thefin structure 108, as shown inFIG. 2F . - The
lateral recess 182 makes thefin structure 108 have different widths. More specifically, as shown inFIG. 2F , thefin structure 108 protruding from thesubstrate 100 and partially surrounded by the isolation feature 116 a includes afirst portion 108 a (or middle portion), asecond portion 108 b (or top portion), and athird portion 108 c (or bottom portion). Thefirst portion 108 a protrudes above the isolation feature 116 a and has a first width W1. Thesecond portion 108 b extends from the top of thefirst portion 108 a and has a second width W2 greater than the first width W1, so that thefin structure 108 above the isolation feature 116 a including thefirst portion 108 a and thesecond portion 108 b has a T-shaped profile. The third portion is surrounded by the isolation feature 116 a and has a third width W3 greater than the first width W1. The third width W3 may be substantially equal to or slightly greater than the second width W2. - The masking
cap 170 provides a protection of the top portion (i.e., thesecond portion 108 b) of thefin structure 108 during the fin-trim process (i.e., the etching process 180) is performed, so that the fin loss or damage at its top portion during the fin-trim process can be prevented. As a result, fin collapse can be prevented after the fin-trim process is performed, thereby maintain or increasing the reliability of the device with the fin structure. - In some embodiments, the
etching process 180 is a wet etching process using an etching solution including a base (such as ammonium hydroxide, tetramethyl ammonium hydroxide, or the like). In some embodiments, the concentration of the base in the etching solution is in a range from about 1 wt % to about 5 wt %, such as higher than 2%. In some embodiments, the etching process 180 (i.e., the wet etching process using an etching solution including a base) is performed for a sufficient time that is in a range from about 2 minutes to about 10 minutes at temperature in a range from about 40° C. to about 70° C. - After the
lateral recess 182 is formed to partially thinning thefin structure 108 in theopening 140, the masking cap 170 (shown inFIG. 2F ) is removed from thefin structure 108, as shown inFIG. 2G in accordance with some embodiments. In some embodiments, the maskingcap 170 is removed by a dry etching process, so as to expose thesecond portion 108 b of thefin structure 108. In the structure shown inFIG. 2G , the partially thinnedfin structure 108 formed by the fin-trim process can enhance device performance. - Similarly, although the
masking cap 170 is removed from thefin structure 108, the wider top portion (i.e., thesecond portion 108 b) of thefin structure 108 can provide an etch-compensation to mitigate the fin loss at the top portion of thefin structure 108 in subsequent processes (e.g., etching and/or cleaning processes), if presented, thereby preventing the thinned fin from collapsing, so as to maintain the reliability of the device with a fin structure. Accordingly, in some embodiments, the width of the top portion (i.e., the width W2 of thesecond portion 108 b) is reduced after such subsequent processes (e.g., etching and/or cleaning processes) are performed and is denoted as W4 (as indicated inFIG. 2H ). - After the
masking cap 170 is removed, a gate structure 190 is formed inopening 140, as shown inFIG. 2H in accordance with some embodiments. More specifically, agate dielectric layer 191 is conformally formed over the insulating layer 136 (as shown inFIG. 1J ) and conformally covers the inner surface of the opening 140 (as shown inFIG. 1J ). Thegate dielectric layer 191 formed in theopening 140 may cover the gate spacer layers 126 and each exposedfin structure 108 in theopening 140. In some embodiments, thegate dielectric layer 191 is made of a high k dielectric material, such as metal oxide. Examples of the high-k dielectric material may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, or other applicable dielectric materials. In some embodiments, thegate dielectric layer 191 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable process. - An interfacial layer (not shown) may be formed between each exposed
fin structure 108 and thegate dielectric layer 191, so that the adhesion of thegate dielectric layer 191 can be improved. In some embodiments, the interfacial layer is made of SiO2. In some embodiments, the interfacial layer is formed by an atomic layer deposition (ALD) process, a thermal oxidation process, chemical vapor deposition (CVD) process, or another applicable process. - After the
gate dielectric layer 191 is formed, a work functional metal layer (not shown) is conformally formed over the insulatinglayer 136 and conformally covers the inner surface of theopening 140 that is covered by thegate dielectric layer 191, in accordance with some embodiments. The work function metal layer is tuned to have a proper work function. In some embodiments, the work function metal layer is made of an N-type work-function metal or a P-type work-function metal. N-type work-function metals include titanium (Ti), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbon nitride (TaCN), and combinations thereof. The P-work-function metal includes titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof. In some embodiments, the work function metal layer 162 is formed by atomic layer deposition (ALD), sputtering, physical vapor deposition (PVD), or another applicable process. - In some other embodiments, a conformal capping or barrier layer (not shown) is formed over the
gate dielectric layer 191 prior to formation of the work function metal layer, so that the capping or barrier layer is between gatedielectric layer 191 and the work function metal layer. The capping or barrier layer is employed to prevent the metal formed over it from penetrating into the channel region of the fin structure (e.g., thefin structure 108 in the opening 140) below the metal gate structure (e.g., the gate structure 190). In some embodiments, the capping or barrier layer is made of metal nitride. Examples of the metal nitride include TiN, TaN, and WN. The capping or barrier layer may be formed by physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable process. - After the work functional metal layer is formed, a gate electrode layer 193 is formed over the insulating
layer 136 and fills theopening 140 to cover the work functional metal layer, in accordance with some embodiments. - In some embodiments, the gate electrode layer 193 is made of tungsten (W). In some embodiments, the gate electrode layer 193 is formed by chemical vapor deposition (CVD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), or another applicable process.
- In some other embodiments, a conformal blocking layer (not shown) is formed over the work functional metal layer prior to formation of the gate electrode layer 193, so that the blocking layer is between work functional metal layer and the gate electrode layer 193. The blocking layer is employed to prevent the byproduct formed during the gate electrode layer 193 deposition from diffusing toward the layers below. In some embodiments, the blocking layer is made of metal nitride. Examples of metal nitride include TiN, TaN, and WN. The blocking layer may be formed by physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable process.
- After the gate electrode layer 193 is formed, the gate electrode layer 193, the work function metal layer, and the
gate dielectric layer 191 over the insulatinglayer 136 are successively removed, as shown inFIG. 2H in accordance with some embodiments. For example, the gate electrode layer 193, the work function metal layer 162, and thegate dielectric layer 191 over the insulatinglayer 136 are successively removed by a chemical mechanical polishing (CMP) process to expose a top surface of the insulatinglayer 136. As a result, the gate structure 190 is formed in theopening 140. In some embodiments, the gate structure 190 at least includes thegate dielectric layer 191, the work function metal layer, and the gate electrode layer 193. - Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a first liner layer that covers a top surface and a sidewall of a fin structure. The first liner layer is patterned by a wet etching process, so as to form a masking cap that covers the top surface of the fin structure and a portion of the sidewall of the fin structure. Afterwards, the fin structure is thinned by using the masking cap as an etch mask. The masking cap provides a protection of the top portion of the fin structure during the fin structure is thinned, so that the fin structure has a top portion with a width greater than that of the other portion of the fin structure that is thinned. As a result, the partially thinned fin structure can enhance device performance. The wider top portion of the fin structure can also serve as an etch-compensation to mitigate the fin loss or damage at its top portion in subsequent etching and/or cleaning processes for device fabrication, thereby preventing device degradation.
- In some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a fin structure protruding from a substrate and forming a first liner layer to cover a top surface and a sidewall of the fin structure. The method also includes patterning the first liner layer by performing a wet etching process, so as to remain a portion of the first liner layer covering the top surface of the fin structure and a portion of the sidewall of the fin structure. The method also includes removing a portion of the fin structure from the sidewall of the fin structure by using the remained portion of the first liner layer as an etch mask, so as to form a lateral recess in the fin structure.
- In some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a first gate structure over a fin structure that protrudes from a substrate and forming source and drain features over the fin structure on opposing sidewall surfaces of the first gate structure. The method also includes forming an insulating layer over the substrate and covering the source and drain features and removing the first gate structure to form an opening in the insulating layer and expose the fin structure in the opening. The method also includes forming a masking cap over the exposed fin structure in the opening. The masking cap includes a plate portion covering a top surface of the exposed fin structure in the opening. The masking cap also includes a wall portion extending from the plate portion and partially exposing a sidewall of the exposed fin structure in the opening. The method also includes laterally recessing the partially exposed sidewall of the fin structure in the opening.
- In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes an isolation feature over a substrate and a fin structure protruding from the substrate and partially surrounded by the isolation feature. The fin structure includes a first portion above the isolation feature and having a first width. The fin structure also includes a second portion extending from the top of the first portion and having a second width greater than the first width, so that the fin structure above the isolation feature has a T-shaped profile. The semiconductor device structure also includes a gate structure covering the first portion and the second portion of the fin structure.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (21)
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170148890A1 (en) * | 2015-11-19 | 2017-05-25 | International Business Machines Corporation | Stable work function for narrow-pitch devices |
CN113851529A (en) * | 2021-09-07 | 2021-12-28 | 上海集成电路装备材料产业创新中心有限公司 | Fin type semiconductor device and manufacturing method thereof |
CN113851530A (en) * | 2021-09-07 | 2021-12-28 | 上海集成电路装备材料产业创新中心有限公司 | Fin type semiconductor device and manufacturing method thereof |
TWI844090B (en) | 2021-10-15 | 2024-06-01 | 台灣積體電路製造股份有限公司 | Semiconductor device and method for forming the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11211479B2 (en) * | 2018-08-14 | 2021-12-28 | Taiwan Semiconductor Manufaciuring Co., Ltd. | Method of fabricating trimmed fin and fin structure |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8058692B2 (en) * | 2008-12-29 | 2011-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-gate transistors with reverse T-shaped fins |
CN102983073B (en) * | 2011-09-05 | 2015-12-09 | 中国科学院微电子研究所 | The manufacture method of small size fin structure |
US8815712B2 (en) | 2011-12-28 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for epitaxial re-growth of semiconductor region |
US9236267B2 (en) | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US9171929B2 (en) | 2012-04-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device and method of making the strained structure |
US9093530B2 (en) | 2012-12-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
US9214555B2 (en) | 2013-03-12 | 2015-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer for FinFET channels |
US8963258B2 (en) | 2013-03-13 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company | FinFET with bottom SiGe layer in source/drain |
US8796666B1 (en) | 2013-04-26 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with strain buffer layer and methods of forming the same |
US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
US9548303B2 (en) | 2014-03-13 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with unique fin shape and the fabrication thereof |
US9472446B2 (en) * | 2014-06-18 | 2016-10-18 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device with a unique gate configuration, and the resulting FinFET device |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US20170309623A1 (en) * | 2016-04-21 | 2017-10-26 | Globalfoundries Inc. | Method, apparatus, and system for increasing drive current of finfet device |
-
2018
- 2018-06-22 US US16/015,521 patent/US10522662B1/en active Active
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170148890A1 (en) * | 2015-11-19 | 2017-05-25 | International Business Machines Corporation | Stable work function for narrow-pitch devices |
CN113851529A (en) * | 2021-09-07 | 2021-12-28 | 上海集成电路装备材料产业创新中心有限公司 | Fin type semiconductor device and manufacturing method thereof |
CN113851530A (en) * | 2021-09-07 | 2021-12-28 | 上海集成电路装备材料产业创新中心有限公司 | Fin type semiconductor device and manufacturing method thereof |
TWI844090B (en) | 2021-10-15 | 2024-06-01 | 台灣積體電路製造股份有限公司 | Semiconductor device and method for forming the same |
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US10971628B2 (en) | 2021-04-06 |
US10522662B1 (en) | 2019-12-31 |
US20200144398A1 (en) | 2020-05-07 |
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