US20190392890A1 - Memory apparatus and operating method thereof - Google Patents
Memory apparatus and operating method thereof Download PDFInfo
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- US20190392890A1 US20190392890A1 US16/018,060 US201816018060A US2019392890A1 US 20190392890 A1 US20190392890 A1 US 20190392890A1 US 201816018060 A US201816018060 A US 201816018060A US 2019392890 A1 US2019392890 A1 US 2019392890A1
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- temperature
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- sensing signal
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40626—Temperature related aspects of refresh operations
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
Definitions
- the disclosure relates to an electronic device, and particularly relates to a memory apparatus and an operating method thereof.
- DRAM Dynamic Random Access Memory
- DRAM Dynamic Random Access Memory
- the controller of the memory device will lower the refresh frequency of the memory device to reduce power con consumption when the temperature of the memory device is lower than a predetermined temperature.
- the temperature of the memory device changes frequently around the predetermined temperature, system crash may occur due to the unstable temperature.
- it is chosen not to change the refresh frequency of the memory device in response to the temperature of the memory device, which will result in the increase in power consumption of the memory device.
- the disclosure is directed to a memory apparatus and an operating method thereof, by which high reliability and low power consumption of the memory apparatus are achieved at the same time.
- An embodiment of the disclosure provides a memory apparatus.
- the memory apparatus includes a memory, a temperature sensor and a control circuit.
- the temperature sensor senses a temperature of the memory and generating a temperature sensing signal.
- the control circuit is coupled to the memory and the temperature sensor. The control circuit performs access operation on the memory and changes a frequency of the access operation with reference of a delay curve according to the temperature sensing signal.
- control circuit decreases the frequency of the access operation when the temperature of the memory changing from a temperature above a first threshold to a temperature below the first threshold and increases the frequency of the access operation when the temperature of the memory changing from a temperature below a second threshold to a temperature above the second threshold.
- the first threshold is smaller than the second threshold.
- the temperature sensor includes a hysteresis comparator, a first resistance and a second resistance.
- the negative input terminal of the hysteresis comparator receives a threshold voltage.
- the first resistance is coupled between a positive input terminal of the hysteresis comparator and a temperature sensing voltage.
- the second resistance is coupled to the positive input terminal of the hysteresis comparator and an output terminal of the hysteresis comparator, the output terminal of the hysteresis comparator outputs the temperature sensing signal.
- the access operation includes refresh operation.
- the memory apparatus further includes a storage storing the temperature sensing signal.
- the storage includes a multi-purpose register.
- An embodiment of the disclosure provides an operating method of a memory apparatus includes the following steps. Sense a temperature of a memory and generating a temperature sensing signal. Change a frequency of access operation with reference of a delay curve according to the temperature sensing signal.
- the operating method of a memory apparatus includes the following steps. Decrease the frequency of the access operation when the temperature of the memory changing from a temperature above a first threshold to a temperature below the first threshold. Increase the frequency of the access operation when the temperature of the memory changing from a temperature below a second threshold to a temperature above the second threshold, wherein the first threshold is smaller than the second threshold.
- the operating method of a memory apparatus includes the step of storing the temperature sensing signal into a storage.
- the storage comprises a multi-purpose register.
- the control circuit changes the frequency of the access operation with reference of the delay curve according to the temperature sensing signal, so as to avoid changing the frequency of the access operation frequently when the temperature of the memory apparatus changing frequently around a predetermined temperature, and thus high reliability and low power consumption of the memory apparatus can be achieved at the same time.
- FIG. 1 is a schematic diagram of a memory apparatus according to an embodiment of the disclosure.
- FIG. 2 is schematic diagram illustrates the relationship between the refresh frequency of the memory and temperature of memory the according to an embodiment of the disclosure.
- FIG. 3 is another schematic diagram illustrates the relationship between the refresh frequency of the memory and temperature of memory the according to an embodiment of the disclosure.
- FIG. 4 is a schematic diagram of a temperature sensor according to an embodiment of the disclosure.
- FIG. 5 is the flowchart of an operating method of the memory apparatus according to an embodiment of the disclosure.
- FIG. 6 is the flowchart of operating method of the memory apparatus according to another embodiment of the disclosure.
- FIG. 1 is a schematic diagram of a memory apparatus according to an embodiment of the disclosure.
- the memory apparatus 100 may be a computer or a mobile phone for example, which includes memory 110 , a temperature sensor 120 , and a control circuit 130 .
- the control circuit 130 is coupled to the memory 110 and the temperature sensor 120 , the control circuit 130 may be implemented with a processor or a microcontroller, but is not limited thereto.
- the memory 110 may be implemented with a dynamic random access memory (DRAM), though the disclosure is not limited thereto.
- DRAM dynamic random access memory
- the temperature sensor 120 senses the temperature TC of the memory 110 and generating a temperature sensing signal ST, where the temperature sensor 120 may be implemented with a thermistor, for example, though the disclosure is not limited thereto.
- the temperature sensor 120 may be integrated into the memory 110 in some embodiments, and the memory 110 may include a storage (for example, multi-purpose register, but is not limited thereto) to store the temperature sensing signal ST.
- the control circuit 130 may access the storage to obtain the temperature sensing signal ST.
- the control circuit 130 performs access operation on the memory, the access operation is refresh operation in the embodiment of FIG. 1 , but is not limited thereto, in some embodiments, the embodiment may include write operation or verification operation for example.
- the temperature sensor 120 compares the temperature of the memory 110 to determine whether the temperature of the memory 110 changes from a temperature above a first threshold to a temperature below the first threshold or changes from a temperature below a second threshold to a temperature above the second threshold, and output the temperature sensing signal ST corresponsively.
- the control circuit 130 changes the frequency of the access operation with reference of a delay curve according to the temperature sensing signal ST.
- FIG. 2 is schematic diagram illustrates the relationship between the refresh frequency of the memory and temperature of memory the according to an embodiment of the disclosure.
- the control circuit 130 changes the refresh frequency of refresh operation (that is, the number of the refresh operations performed per unit time) with reference of a delay curve according to the temperature sensing signal ST.
- the temperature sensor 120 outputs the temperature sensing signal ST (a bit value “00”, for example) to inform the control circuit 130 to decrease the refresh frequency to frequency F 1 , and when the temperature of the memory 110 changing from a temperature below 50° C.
- the temperature sensor 120 outputs the temperature sensing signal ST (a bit value “01” for example) to inform the control circuit 130 to increase the refresh frequency to frequency F 2 . That is, the temperature margin Tm 1 of the delay curve shown in FIG. 2 is 5° C., though the disclosure is not limited thereto. Therefore, when the temperature of the memory 110 changes frequently around the predetermined temperature (which is 45° C. in this embodiment), crush of the memory apparatus 100 can be avoided and lower the power consumption of the memory apparatus 100 can be achieved.
- the predetermined temperature which is 45° C. in this embodiment
- the temperature sensor 120 may further output the temperature sensing signal ST with respect to another predetermined temperature.
- FIG. 3 is another schematic diagram illustrates the relationship between the refresh frequency of the memory and temperature of memory the according to an embodiment of the disclosure.
- the temperature sensor 120 further outputs the temperature sensing signal ST with respect to 95° C. to inform the control circuit 130 to adjust the refresh frequency.
- the temperature sensor 120 may output a bit value “01” when the temperature of the memory 110 changing from a temperature above 90° C. to a temperature below 90° C., and the control circuit 130 decreases the refresh frequency corresponsively.
- the temperature sensor 120 may output a bit value “10” when the temperature of the memory 110 changing from a temperature below 100° C.
- the control circuit 130 increase the refresh frequency corresponsively.
- FIG. 4 is a schematic diagram of a temperature sensor according to an embodiment of the disclosure.
- the temperature sensor 120 may include a temperature sensor A 1 and resistances R 1 and R 2 , the resistance R 1 is coupled between the positive input terminal of the hysteresis comparator A 1 and a temperature sensing voltage VS (the temperature sensing voltage VS reflects the temperature of the memory 110 ), the resistance R 2 is coupled between the positive input terminal of the hysteresis comparator A 1 and the output terminal of the hysteresis comparator A 1 , and the negative input terminal of the hysteresis comparator A 1 receives a threshold voltage VT.
- the hysteresis comparator A 1 may output an output voltage as the temperature sensing signal ST to the control circuit 130 or output a bit value as the temperature sensing signal ST to the control circuit 130 , so as to make the control circuit 130 adjust the refresh frequency of the memory 110 according to the temperature sensing signal ST.
- the temperature margin Tm 1 and the temperature margin Tm 2 can be changed by adjusting the resistance values of the resistances R 1 and R 2 .
- FIG. 5 is the flowchart of an operating method of the memory apparatus according to an embodiment of the disclosure. It can be seen from the above embodiments, the operating method of the memory apparatus may at least include the following steps. First, sensing the temperature of the memory and generating the temperature sensing signal (step S 502 ), and then changing the frequency of access operation with reference of a delay curve according to the temperature sensing signal (step S 504 ).
- FIG. 6 is the flowchart of operating method of the memory apparatus according to another embodiment of the disclosure.
- the temperature sensor 120 of the embodiment of FIG. 1 senses the temperature of the memory 110 .
- the temperature sensor 120 determines whether the temperature of the memory 110 changing from a temperature above a first threshold to a temperature below the first threshold, when the temperature of the memory 110 changes from a temperature above the first threshold to a temperature below the first threshold, the temperature sensor 120 outputs the temperature sensing signal ST (for example, bit value “00”) to inform the control circuit 130 to decrease the frequency of the access operation (step S 606 ).
- the temperature sensor 120 keeps senses the temperature of the memory 110 (step S 602 ).
- step S 608 the temperature sensor 120 determines whether the temperature of the memory 110 changing from a temperature below a first threshold to a temperature above the second threshold, the first threshold is smaller than the second threshold.
- the temperature sensor 120 outputs the temperature sensing signal ST (for example, bit value “01”) to inform the control circuit 130 to increase the frequency of the access operation (step S 610 ).
- the temperature sensor 120 keeps senses the temperature of the memory 110 (step S 602 ).
- the frequency of the access operation will not be changed frequently when the temperature of the memory apparatus changing frequently around the predetermined temperature, and high reliability, high stability and the low power consumption of the memory apparatus can be achieved at the same time.
- the temperature sensing signal may be stored into a storage (multi-purpose register, for example), and the temperature sensing signal can be obtaining by accessing the storage.
- the access operation is refresh operation for example, but is not limited thereto.
- control circuit changes the frequency of the access operation with reference of the delay curve according to the temperature sensing signal, so as to avoid changing the frequency of the access operation frequently when the temperature of the memory apparatus changing frequently around a predetermined temperature, and thus high reliability, high stability and low power consumption of the memory apparatus can be achieved at the same time.
Abstract
Description
- The disclosure relates to an electronic device, and particularly relates to a memory apparatus and an operating method thereof.
- Dynamic Random Access Memory (DRAM) devices continue to be a preferred memory for storing data in electronic systems. Since the leakage current is small at low temperature, the controller of the memory device will lower the refresh frequency of the memory device to reduce power con consumption when the temperature of the memory device is lower than a predetermined temperature. However, if the temperature of the memory device changes frequently around the predetermined temperature, system crash may occur due to the unstable temperature. In order to avoid the system crash, it is chosen not to change the refresh frequency of the memory device in response to the temperature of the memory device, which will result in the increase in power consumption of the memory device.
- The disclosure is directed to a memory apparatus and an operating method thereof, by which high reliability and low power consumption of the memory apparatus are achieved at the same time.
- An embodiment of the disclosure provides a memory apparatus. The memory apparatus includes a memory, a temperature sensor and a control circuit. The temperature sensor senses a temperature of the memory and generating a temperature sensing signal. The control circuit is coupled to the memory and the temperature sensor. The control circuit performs access operation on the memory and changes a frequency of the access operation with reference of a delay curve according to the temperature sensing signal.
- In an embodiment of the disclosure, the control circuit decreases the frequency of the access operation when the temperature of the memory changing from a temperature above a first threshold to a temperature below the first threshold and increases the frequency of the access operation when the temperature of the memory changing from a temperature below a second threshold to a temperature above the second threshold. The first threshold is smaller than the second threshold.
- In an embodiment of the disclosure, the temperature sensor includes a hysteresis comparator, a first resistance and a second resistance. The negative input terminal of the hysteresis comparator receives a threshold voltage. The first resistance is coupled between a positive input terminal of the hysteresis comparator and a temperature sensing voltage. The second resistance is coupled to the positive input terminal of the hysteresis comparator and an output terminal of the hysteresis comparator, the output terminal of the hysteresis comparator outputs the temperature sensing signal.
- In an embodiment of the disclosure, the access operation includes refresh operation.
- In an embodiment of the disclosure, the memory apparatus further includes a storage storing the temperature sensing signal.
- In an embodiment of the disclosure, the storage includes a multi-purpose register.
- An embodiment of the disclosure provides an operating method of a memory apparatus includes the following steps. Sense a temperature of a memory and generating a temperature sensing signal. Change a frequency of access operation with reference of a delay curve according to the temperature sensing signal.
- In an embodiment of the disclosure, the operating method of a memory apparatus includes the following steps. Decrease the frequency of the access operation when the temperature of the memory changing from a temperature above a first threshold to a temperature below the first threshold. Increase the frequency of the access operation when the temperature of the memory changing from a temperature below a second threshold to a temperature above the second threshold, wherein the first threshold is smaller than the second threshold.
- In an embodiment of the disclosure, the operating method of a memory apparatus includes the step of storing the temperature sensing signal into a storage.
- In an embodiment of the disclosure, the storage comprises a multi-purpose register.
- According to the above description, in the embodiment of the disclosure, the control circuit changes the frequency of the access operation with reference of the delay curve according to the temperature sensing signal, so as to avoid changing the frequency of the access operation frequently when the temperature of the memory apparatus changing frequently around a predetermined temperature, and thus high reliability and low power consumption of the memory apparatus can be achieved at the same time.
- In order to make the aforementioned and other features and advantages of the disclosure comprehensible, several exemplary embodiments accompanied with figures are described in detail below.
- The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
-
FIG. 1 is a schematic diagram of a memory apparatus according to an embodiment of the disclosure. -
FIG. 2 is schematic diagram illustrates the relationship between the refresh frequency of the memory and temperature of memory the according to an embodiment of the disclosure. -
FIG. 3 is another schematic diagram illustrates the relationship between the refresh frequency of the memory and temperature of memory the according to an embodiment of the disclosure. -
FIG. 4 is a schematic diagram of a temperature sensor according to an embodiment of the disclosure. -
FIG. 5 is the flowchart of an operating method of the memory apparatus according to an embodiment of the disclosure. -
FIG. 6 is the flowchart of operating method of the memory apparatus according to another embodiment of the disclosure. - Reference will now be made in detail to the present preferred embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIG. 1 is a schematic diagram of a memory apparatus according to an embodiment of the disclosure. Referring toFIG. 1 , thememory apparatus 100 may be a computer or a mobile phone for example, which includesmemory 110, atemperature sensor 120, and acontrol circuit 130. Thecontrol circuit 130 is coupled to thememory 110 and thetemperature sensor 120, thecontrol circuit 130 may be implemented with a processor or a microcontroller, but is not limited thereto. Thememory 110 may be implemented with a dynamic random access memory (DRAM), though the disclosure is not limited thereto. Thetemperature sensor 120 senses the temperature TC of thememory 110 and generating a temperature sensing signal ST, where thetemperature sensor 120 may be implemented with a thermistor, for example, though the disclosure is not limited thereto. Thetemperature sensor 120 may be integrated into thememory 110 in some embodiments, and thememory 110 may include a storage (for example, multi-purpose register, but is not limited thereto) to store the temperature sensing signal ST. Thecontrol circuit 130 may access the storage to obtain the temperature sensing signal ST. - The
control circuit 130 performs access operation on the memory, the access operation is refresh operation in the embodiment ofFIG. 1 , but is not limited thereto, in some embodiments, the embodiment may include write operation or verification operation for example. Thetemperature sensor 120 compares the temperature of thememory 110 to determine whether the temperature of thememory 110 changes from a temperature above a first threshold to a temperature below the first threshold or changes from a temperature below a second threshold to a temperature above the second threshold, and output the temperature sensing signal ST corresponsively. Thecontrol circuit 130 changes the frequency of the access operation with reference of a delay curve according to the temperature sensing signal ST. - For example,
FIG. 2 is schematic diagram illustrates the relationship between the refresh frequency of the memory and temperature of memory the according to an embodiment of the disclosure. Thecontrol circuit 130 changes the refresh frequency of refresh operation (that is, the number of the refresh operations performed per unit time) with reference of a delay curve according to the temperature sensing signal ST. As shown inFIG. 2 , when the temperature of thememory 110 changing from a temperature above 40° C. to a temperature below 40° C., thetemperature sensor 120 outputs the temperature sensing signal ST (a bit value “00”, for example) to inform thecontrol circuit 130 to decrease the refresh frequency to frequency F1, and when the temperature of thememory 110 changing from a temperature below 50° C. to a temperature above 50° C., thetemperature sensor 120 outputs the temperature sensing signal ST (a bit value “01” for example) to inform thecontrol circuit 130 to increase the refresh frequency to frequency F2. That is, the temperature margin Tm1 of the delay curve shown inFIG. 2 is 5° C., though the disclosure is not limited thereto. Therefore, when the temperature of thememory 110 changes frequently around the predetermined temperature (which is 45° C. in this embodiment), crush of thememory apparatus 100 can be avoided and lower the power consumption of thememory apparatus 100 can be achieved. - It is noted that, in some embodiments, the
temperature sensor 120 may further output the temperature sensing signal ST with respect to another predetermined temperature. For example,FIG. 3 is another schematic diagram illustrates the relationship between the refresh frequency of the memory and temperature of memory the according to an embodiment of the disclosure. In this embodiment, thetemperature sensor 120 further outputs the temperature sensing signal ST with respect to 95° C. to inform thecontrol circuit 130 to adjust the refresh frequency. For example, thetemperature sensor 120 may output a bit value “01” when the temperature of thememory 110 changing from a temperature above 90° C. to a temperature below 90° C., and thecontrol circuit 130 decreases the refresh frequency corresponsively. Thetemperature sensor 120 may output a bit value “10” when the temperature of thememory 110 changing from a temperature below 100° C. to a temperature above 100° C. (that is, the temperature margin Tm2 is 5° C., but is not limited thereto, the temperature margin Tm2 may be different from the temperature margin Tm1 in other embodiments), and thecontrol circuit 130 increase the refresh frequency corresponsively. -
FIG. 4 is a schematic diagram of a temperature sensor according to an embodiment of the disclosure. Referring toFIG. 4 , in some embodiments, thetemperature sensor 120 may include a temperature sensor A1 and resistances R1 and R2, the resistance R1 is coupled between the positive input terminal of the hysteresis comparator A1 and a temperature sensing voltage VS (the temperature sensing voltage VS reflects the temperature of the memory 110), the resistance R2 is coupled between the positive input terminal of the hysteresis comparator A1 and the output terminal of the hysteresis comparator A1, and the negative input terminal of the hysteresis comparator A1 receives a threshold voltage VT. The hysteresis comparator A1 may output an output voltage as the temperature sensing signal ST to thecontrol circuit 130 or output a bit value as the temperature sensing signal ST to thecontrol circuit 130, so as to make thecontrol circuit 130 adjust the refresh frequency of thememory 110 according to the temperature sensing signal ST. The temperature margin Tm1 and the temperature margin Tm2 can be changed by adjusting the resistance values of the resistances R1 and R2. -
FIG. 5 is the flowchart of an operating method of the memory apparatus according to an embodiment of the disclosure. It can be seen from the above embodiments, the operating method of the memory apparatus may at least include the following steps. First, sensing the temperature of the memory and generating the temperature sensing signal (step S502), and then changing the frequency of access operation with reference of a delay curve according to the temperature sensing signal (step S504). - For example,
FIG. 6 is the flowchart of operating method of the memory apparatus according to another embodiment of the disclosure. In step S602, thetemperature sensor 120 of the embodiment ofFIG. 1 senses the temperature of thememory 110. In step S604, thetemperature sensor 120 determines whether the temperature of thememory 110 changing from a temperature above a first threshold to a temperature below the first threshold, when the temperature of thememory 110 changes from a temperature above the first threshold to a temperature below the first threshold, thetemperature sensor 120 outputs the temperature sensing signal ST (for example, bit value “00”) to inform thecontrol circuit 130 to decrease the frequency of the access operation (step S606). In contrast, if the temperature of thememory 110 does not change from a temperature above the first threshold to a temperature below the first threshold, thetemperature sensor 120 keeps senses the temperature of the memory 110 (step S602). - In step S608, the
temperature sensor 120 determines whether the temperature of thememory 110 changing from a temperature below a first threshold to a temperature above the second threshold, the first threshold is smaller than the second threshold. When the temperature of thememory 110 changes from a temperature below the second threshold to a temperature above the second threshold, thetemperature sensor 120 outputs the temperature sensing signal ST (for example, bit value “01”) to inform thecontrol circuit 130 to increase the frequency of the access operation (step S610). In contrast, if the temperature of thememory 110 does not change from a temperature below the second threshold to a temperature above the second threshold, thetemperature sensor 120 keeps senses the temperature of the memory 110 (step S602). Thus, the frequency of the access operation will not be changed frequently when the temperature of the memory apparatus changing frequently around the predetermined temperature, and high reliability, high stability and the low power consumption of the memory apparatus can be achieved at the same time. In some embodiment, the temperature sensing signal may be stored into a storage (multi-purpose register, for example), and the temperature sensing signal can be obtaining by accessing the storage. The access operation is refresh operation for example, but is not limited thereto. - In summary, in the embodiment of the disclosure, the control circuit changes the frequency of the access operation with reference of the delay curve according to the temperature sensing signal, so as to avoid changing the frequency of the access operation frequently when the temperature of the memory apparatus changing frequently around a predetermined temperature, and thus high reliability, high stability and low power consumption of the memory apparatus can be achieved at the same time.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.
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US16/018,060 US10504581B1 (en) | 2018-06-26 | 2018-06-26 | Memory apparatus and operating method thereof |
TW107136629A TWI675376B (en) | 2018-06-26 | 2018-10-18 | Memory apparatus and operating method thereof |
EP18208225.5A EP3588503A1 (en) | 2018-06-26 | 2018-11-26 | Memory apparatus and operating method thereof |
CN201811542007.0A CN110648702A (en) | 2018-06-26 | 2018-12-17 | Memory device and operation method thereof |
JP2018236238A JP2020004471A (en) | 2018-06-26 | 2018-12-18 | Memory device and operation method thereof |
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US16/018,060 US10504581B1 (en) | 2018-06-26 | 2018-06-26 | Memory apparatus and operating method thereof |
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US5276843A (en) | 1991-04-12 | 1994-01-04 | Micron Technology, Inc. | Dynamic RAM array for emulating a static RAM array |
US7027343B2 (en) * | 2003-09-22 | 2006-04-11 | Micron Technology | Method and apparatus for controlling refresh operations in a dynamic memory device |
KR20050118952A (en) | 2004-06-15 | 2005-12-20 | 삼성전자주식회사 | Temperature sensor having hysteresis characteristic |
KR100816690B1 (en) * | 2006-04-13 | 2008-03-27 | 주식회사 하이닉스반도체 | Semiconductor memory device with temperature sensing device |
US7535786B1 (en) | 2006-04-19 | 2009-05-19 | Darryl Walker | Semiconductor device having variable parameter selection based on temperature and test method |
US8531225B1 (en) * | 2012-05-18 | 2013-09-10 | Mediatek Singapore Pte. Ltd. | Configurable critical path emulator |
US9323320B2 (en) * | 2012-05-18 | 2016-04-26 | Mediatek Singapore Pte. Ltd. | Weighted control in a voltage scaling system |
KR102193790B1 (en) * | 2014-02-13 | 2020-12-21 | 에스케이하이닉스 주식회사 | Semiconductor device comprising period signal generation circuit and semiconductor system using the same |
KR102372888B1 (en) * | 2015-06-15 | 2022-03-10 | 삼성전자주식회사 | Method for managing data of storage device by temperature |
KR102354987B1 (en) * | 2015-10-22 | 2022-01-24 | 삼성전자주식회사 | Refresh method for controlling self refresh cycle with temperature |
US10141044B2 (en) * | 2016-02-02 | 2018-11-27 | Mediatek Inc. | Memory interface circuit having signal detector for detecting clock signal |
JP6171066B1 (en) * | 2016-09-01 | 2017-07-26 | ウィンボンド エレクトロニクス コーポレーション | Semiconductor memory device |
CN108107344B (en) * | 2017-12-05 | 2020-07-14 | 武汉英弗耐斯电子科技有限公司 | Overheat protection circuit suitable for IGBT driver chip |
JP2019110218A (en) * | 2017-12-19 | 2019-07-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device, sensor terminal, and control method for semiconductor device |
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TW202001882A (en) | 2020-01-01 |
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