US20190379379A1 - Level shifter - Google Patents
Level shifter Download PDFInfo
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- US20190379379A1 US20190379379A1 US16/275,401 US201916275401A US2019379379A1 US 20190379379 A1 US20190379379 A1 US 20190379379A1 US 201916275401 A US201916275401 A US 201916275401A US 2019379379 A1 US2019379379 A1 US 2019379379A1
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- voltage latch
- latch circuit
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- pulse generator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
Definitions
- Electronic systems often include circuits that are powered by different power supply voltages, or that require different signal levels to activate circuit components. Such systems include circuitry to translate signals between different voltage levels. For example, some such systems include level shifting circuits (level shifters) are used to translate signals from one voltage level to another. A level shifter may be used to translate a signal from a lower voltage to a higher voltage, or to translate a signal from a higher voltage to a lower voltage.
- level shifting circuits level shifters
- a level shifter circuit includes a high voltage latch circuit, a low voltage latch circuit, a high state pulse generator, and a low state pulse generator.
- the high voltage latch circuit includes a non-inverting output terminal, an inverting output terminal, a high state trigger input terminal, and a low state trigger input terminal.
- the low voltage latch circuit is coupled to the high voltage latch circuit, and includes a high state trigger input terminal and a low state trigger input terminal.
- the high state trigger input terminal is coupled to the inverting output terminal of the high voltage latch circuit.
- the low state trigger input terminal is coupled to the non-inverting output terminal of the high voltage latch circuit.
- the high state pulse generator is coupled to the high state trigger input terminal of the high voltage latch circuit.
- the low state pulse generator is coupled to the low state trigger input terminal of the high voltage latch circuit.
- a level shifter circuit in another example, includes a high voltage latch circuit, a low voltage latch circuit, a high state pulse generator, and a low state pulse generator.
- the high voltage latch circuit is configured to generate a high voltage output of the level shifter circuit.
- the low voltage latch circuit is coupled to the high voltage latch circuit, and is configured to change states responsive to a change in state of the high voltage latch circuit.
- the high state pulse generator is coupled to the high voltage latch circuit and the low voltage latch circuit, and configured to generate a first pulse to set the high voltage latch circuit, and to terminate the first pulse responsive to the low voltage latch being set.
- the low state pulse generator is coupled to the high voltage latch circuit and the low voltage latch circuit, and is configured to generate a second pulse to reset the high voltage latch circuit, and to terminate the second pulse responsive to the low voltage latch being reset.
- a level shifter circuit includes a high voltage latch circuit, a low voltage latch circuit, a high state pulse generator, a low state pulse generator, and sample control circuitry.
- the high voltage latch circuit is configured to generate a high voltage output of the level shifter circuit.
- the low voltage latch circuit is coupled to the high voltage latch circuit, and is configured to change states responsive to a change in state of the high voltage latch circuit.
- the high state pulse generator is coupled to the high voltage latch circuit and the low voltage latch circuit, and configured to generate a first pulse to set the high voltage latch circuit, and to terminate the first pulse responsive to the low voltage latch being set.
- the low state pulse generator is coupled to the high voltage latch circuit and the low voltage latch circuit, and is configured to generate a second pulse to reset the high voltage latch circuit, and to terminate the second pulse responsive to the low voltage latch being reset.
- the sample control circuitry is coupled to the low voltage latch circuit, the high state pulse generator, and the low state pulse generator. The sample control circuitry is configured to enable a state change of the low voltage latch circuit responsive to generation of a pulse by the high state pulse generator or the low state pulse generator.
- FIG. 1 shows a block diagram for an example system that controls an N-channel metal oxide semiconductor field effect transistor (MOSFET) using a level shifter circuit powered by bootstrap voltage in accordance with the present disclosure
- MOSFET metal oxide semiconductor field effect transistor
- FIG. 2 shows a schematic diagram for an example level shifter circuit that includes adaptive pulse generation in accordance with the present disclosure
- FIG. 3 shows a schematic diagram for an example pulse generation circuit in accordance with the present disclosure
- FIG. 4 shows an example timing diagram for operation of the pulse generation circuit of FIG. 3 ;
- FIG. 5 shows a graph illustrating example pulse times for a fixed pulse width level shifter circuit and a level shifter circuit that includes adaptive pulse generation in accordance with the present disclosure.
- Some high voltage switching applications use an N-channel metal oxide semiconductor field effect transistor (MOSFET) to switch high voltage due to the smaller size of the N-channel MOSFET relative to a P-channel MOSFET having similar channel resistance.
- MOSFET metal oxide semiconductor field effect transistor
- Such applications employ bootstrapped MOSFET gate drive that keeps a bootstrap capacitor charged several volts above the high voltage switched by the MOSFET.
- a level shifter translates ground-referenced input signal to the high voltages needed to control the MOSFET. Because the charge stored on the bootstrap capacitor is limited, the current drawn from the bootstrap capacitor by the level shifter should be minimized.
- Some level shifters use floating latch stages cascoded with high voltage P-channel MOSFETs in the high voltage domain.
- the cascodes work well down to about 3 volts (V), but in battery powered electronics, voltage supplies of 3 V or less are common. Cascode headroom requirements prevent operation below about 2.5 V.
- Pulse-driven level shifters drive P-channel MOSFET bootstrap-referenced trigger devices that control a high voltage latch.
- High speed and high noise immunity require that high trigger currents be pulled from the bootstrap capacitor. Accordingly, the pulses controlling the latch must be as narrow as possible.
- the duration of the pulses needed to change the state of the latch varies with voltage, process, and temperature. For example, a 10:1 ratio of pulse width is commonly needed to accommodate the strongest and weakest conditions. Thus, using a fixed pulse width wastes bootstrap current in normal operating conditions.
- the level shifter circuits disclosed herein include a pulse generator that is controlled by feedback from the high voltage latch that generates the level shifted output. State change in the high voltage latch terminates the pulse signal provided by the pulse generator so that the pulse duration is only as long as is needed to change the state of the high voltage latch. Thus, the width of the pulse, and the current drawn from the bootstrap capacitor by operation of the level shifter are minimized. Implementations of the level shifter circuits include a low voltage latch that changes state responsive to state change of the high voltage latch. The pulse generators terminate pulse output responsive to state change in the low voltage latch.
- FIG. 1 shows a block diagram for an example system 100 in accordance with the present disclosure.
- the system 100 includes a level shifter circuit 102 , a gate driver 104 , an N-channel MOSFET 106 , a bootstrap capacitor 108 , a diode 112 , a voltage source 110 , a gate driver 118 , and an N-channel MOSFET 120 .
- Implementations of the system 100 may be included in circuitry for a variety of applications.
- a class-D amplifier includes an implementation of the system 100 to drive a loudspeaker.
- the N-channel MOSFET 120 and the gate driver 118 are referenced to ground, and the gate driver 118 drives an inverted version of the input signal VIN to the N-channel MOSFET 120 .
- the level shifter circuit 102 , the gate driver 104 and the N-channel MOSFET 106 are referenced to VOUT 116 .
- the bootstrap capacitor 108 , the diode 112 and voltage source 110 produce a bootstrap voltage (VBOOT) 114 that powers the level shifter circuit 102 and the gate driver 104 , and allows the level shifter circuit 102 and the gate driver 104 to provide a control voltage higher than VOUT 116 to turn on the N-channel MOSFET 106 .
- VBOOT bootstrap voltage
- the voltage source 110 is a battery and/or generates the voltage (VDD) 126 that powers low voltage circuitry of the system 100 .
- the level shifter circuit 102 shifts the input signal VIN from a ground referenced signal to the power rails defined by VOUT 116 and VBOOT 114 .
- the level shifter circuit 102 includes adaptive pulse generation circuitry that reduces the current drawn from the bootstrap capacitor 108 .
- FIG. 2 shows a schematic diagram for an example level shifter circuit 200 that includes adaptive pulse generation in accordance with the present disclosure.
- the level shifter circuit 200 is an implementation of the level shifter circuit 102 .
- the level shifter circuit 200 includes a high state pulse generator 202 , a low state pulse generator 222 , a high voltage latch 208 , and a low voltage latch 216 .
- the high state pulse generator 202 is coupled to the level shifter input terminal 218 to generate a pulse at a rising edge of the signal received at the level shifter input terminal 218 .
- the low state pulse generator 222 is coupled to the level shifter input terminal 218 via the inverter 220 to generate a pulse at a falling edge of the signal received at the level shifter input terminal 218 .
- An input 220 A of the inverter 220 is coupled to the level shifter input terminal 218 , and an output 220 B of the inverter 220 is coupled to the low state pulse generator 222 .
- the high voltage latch 208 is powered by VBOOT 114 and generates the high voltage output (LSOUT) 124 of the level shifter circuit 200 .
- the high state pulse generator 202 (output 202 C) is coupled to a high state trigger input terminal 208 C of the high voltage latch 208 , and generates a pulse to set the high voltage latch 208 via the transistor 204 and the transistor 206 .
- the low state pulse generator 222 (output 222 C) is coupled to a low state trigger input terminal 208 D of the high voltage latch 208 , and resets the high voltage latch 208 via the transistor 224 and the transistor 226 .
- the high voltage latch 208 includes a pair of cross-coupled inverters.
- a first of the inverters includes transistor 238 and transistor 240 .
- a second of the inverters includes transistor 242 and transistor 244 .
- the high state pulse generator 202 generates a pulse when the signal VIN 122 transitions from logic low voltage to logic high voltage.
- the pulse turns on the transistor 204 , which enables current flow in the transistor 206 and turns on the transistor 246 to set the high voltage latch 208 .
- the low state pulse generator 222 generates a pulse when the signal VIN 122 transitions from logic high voltage to logic low voltage.
- the pulse turns on the transistor 224 , which enables current flow in the transistor 226 and turns on the transistor 236 to reset the high voltage latch 208 .
- the duration of the pulses generated by the high state pulse generator 202 and the low state pulse generator 222 is a function of the time needed for the high voltage latch 208 to change state responsive to the pulses.
- the low voltage latch 216 is coupled to the high voltage latch 208 and changes state responsive to change in state of the high voltage latch 208 .
- the outputs of the low voltage latch 216 are fed back to the high state pulse generator 202 and the low state pulse generator 222 to reset the pulses generated by the high state pulse generator 202 and the low state pulse generator 222 .
- a pulse termination input 202 A of the high state pulse generator 202 is coupled to the high state output terminal 216 C of the low voltage latch 216 and a pulse termination input 222 A of the low state pulse generator 222 is coupled to the low state output terminal 216 D of the low voltage latch 216 .
- the low voltage latch 216 includes a pair of cross-coupled inverters.
- a first of the inverters includes transistor 250 and transistor 252 .
- a second of the inverters includes transistor 254 and transistor 256 .
- State change in the low voltage latch 216 is enabled by the sample control circuitry 260 .
- the sample control circuitry 260 is coupled to the low voltage latch 216 , the high state pulse generator 202 and the low state pulse generator 222 , and generates an enable signal that combines the outputs of the high state pulse generator 202 and the low state pulse generator 222 .
- the sample control circuitry 260 includes a NOR gate 262 that combines the outputs of the high state pulse generator 202 and the low state pulse generator 222 , and an inverter 264 to produce an output that is complementary to the output of the NOR gate 262 .
- Other implementations of the sample control circuitry 260 include different logical circuitry. When the high state pulse generator 202 or the low state pulse generator 222 generates a pulse, the sample control circuitry 260 enables sampling of the outputs of the high voltage latch 208 by the low voltage latch 216 , which in turn enables a state change of the low voltage latch circuit 216 .
- the sample control circuitry 260 is coupled to a transistor 212 , a transistor 214 , a transistor 232 , and a transistor 234 to control operation of the low voltage latch 216 .
- the transistor 214 and the transistor 234 are coupled to the output of the NOR gate 262 . More specifically, the transistor 214 includes a first terminal 214 B that is coupled to the high state pulse generator 202 and the low state pulse generator 222 through the sample control circuitry 260 , and a second terminal 214 A that is coupled to the low state trigger input terminal 216 B of the low voltage latch 216 .
- the transistor 234 includes a first terminal 234 B that is coupled to the high state pulse generator 202 and the low state pulse generator 222 through the sample control circuitry 260 , and a second terminal 234 A that is coupled to the high state trigger input terminal 216 A of the low voltage latch 216 .
- the transistor 214 and the transistor 234 are turned on to pull the high state trigger input terminal 216 A and the low state trigger input terminal 216 B, the gate terminal of the transistor 248 and the gate terminal of the transistor 258 , low and disable state change in the low voltage latch 216 .
- the transistor 214 and the transistor 234 are turned off to allow the low voltage latch 216 to sample the outputs of the high voltage latch 208 .
- the low voltage latch 216 is coupled to the high voltage latch 208 via a transistor 212 , a transistor 210 , a transistor 232 , and a transistor 230 .
- the high state trigger input terminal 216 A of the low voltage latch 216 is coupled to the inverting output terminal 208 B of the high voltage latch 208 via the transistor 230 and the transistor 232 .
- the low state trigger input terminal 216 B of the low voltage latch 216 is coupled to the non-inverting output terminal 208 A of the high voltage latch 208 via the transistor 210 and the transistor 212 . More specifically, the terminal 210 A of the transistor 210 is coupled to the non-inverting output terminal 208 A of the high voltage latch 208 , and the terminal 210 B of the transistor 210 is coupled to the terminal 212 C of the 212 (the terminal 212 C of the transistor 212 is coupled to the high voltage latch 208 ).
- the terminal 212 A of the transistor 212 is coupled to the low state trigger input terminal 216 B of the low voltage latch 216 and the terminal 214 A of the transistor 214 , and the terminal 212 B of the transistor 212 is coupled to the high state pulse generator 202 and the low state pulse generator 222 via the sample control circuitry 260 (the inverter 264 of the sample control circuitry 260 ).
- the terminal 230 A of the transistor 230 is coupled to the inverting output terminal 208 B of the high voltage latch 208
- the terminal 230 B of the transistor 230 is coupled to the terminal 232 C of the transistor 232 (the terminal 232 C of the transistor 232 is coupled to the high voltage latch 208 ).
- the terminal 232 A of the transistor 232 is coupled to the high state trigger input terminal 216 A of the low voltage latch 216 and the terminal 234 A of the transistor 234 , and the terminal 232 B of the transistor 232 is coupled to the high state pulse generator 202 and the low state pulse generator 222 via the sample control circuitry 260 (the inverter 264 of the sample control circuitry 260 ).
- the transistor 212 and the transistor 232 are turned on to connect the low voltage latch 216 to the high voltage latch 208 .
- the state of the high voltage latch 208 is set responsive the pulse, and either the transistor 210 or the transistor 230 is turned on. If the non-inverting output terminal 208 A is set to a logic high level, then the transistor 230 is turned on. If the non-inverting output terminal 208 A is set to a logic low level, then the transistor 210 is turned on.
- the one of the transistor 210 or the transistor 230 that is turned on passes a voltage to the low voltage latch 216 (via either the transistor 212 or the transistor 232 ) that changes the state of the low voltage latch 216 , and in turn terminates the pulse generated by the high state pulse generator 202 or the low state pulse generator 222 . Termination of the pulse turns off the transistor 212 and the transistor 232 and turns on the transistor 214 and the transistor 234 to disable further state change of the low voltage latch 216 until a next pulse is generated by the high state pulse generator 202 or the low state pulse generator 222 .
- FIG. 3 shows a schematic diagram for an example pulse generation circuit 300 in accordance with the present disclosure.
- the pulse generation circuit 300 is an implementation of the high state pulse generator 202 or the low state pulse generator 222 .
- the pulse generation circuit 300 includes an AND gate 302 , a NOR gate 304 , and a delay circuit 306 .
- the AND gate 302 includes an input 302 A that is coupled to a level shifter input terminal 218 of the level shifter circuit 200 (or the output 220 B of the inverter 220 ), and an input 302 B that is coupled the output 304 C of the NOR gate 304 .
- the NOR gate 304 includes an input 304 A that is coupled to an output of the low voltage latch 216 .
- the input 304 A is coupled to the high state output terminal 216 C or the low state output terminal 216 D.
- the NOR gate 304 also includes an input 304 B that is coupled to the output 306 B of the delay circuit 306 .
- the input 306 A of the delay circuit 306 is coupled to the input 302 A of the AND gate 302 and the level shifter input terminal 218 of the level shifter circuit 200 (or the output of the inverter 220 ).
- FIG. 4 shows an example timing diagram for operation of the pulse generation circuit 300 .
- the signal VIN 122 transitions from a logic low level to a logic high level.
- both the input 302 A and the input 302 B of the AND gate 302 are at a logic high level, and the AND gate 302 initiates a pulse 408 at time 404 .
- the signal VIN 122 is delayed by the delay circuit 306 , and at time 406 the delayed version of the signal VIN 122 is provided at the input 304 B of the NOR gate 304 , which in turn sets the input 302 B of the AND gate 302 to a logic low level and terminates the pulse 408 generated at the output of the AND gate 302 .
- the duration of the pulse 408 is determined by the time delay provided by the delay circuit 306 because no feedback from the low voltage latch circuit 216 is received to terminate the pulse 408 .
- the signal VIN 122 again transitions for a logic low level to a logic high level.
- both the input 302 A and the input 302 B of the AND gate 302 are at a logic high level, and the AND gate 302 initiates a pulse 418 at time 414 .
- the high voltage latch 208 and low voltage latch 216 have changed state responsive to the pulse 418 , and the change in the output of the low voltage latch 216 at time 410 is provided at the input 304 A of the NOR gate 304 , which in turn sets the input 302 B of the AND gate 302 to a logic low level and terminates the pulse 418 generated at the output of the AND gate 302 .
- the duration of the pulse 418 is determined by the time needed to change the state of the high voltage latch 208 and the low voltage latch 216 responsive to the pulse 418 .
- FIG. 5 shows a graph illustrating example pulse times for a fixed pulse width level shifter circuit and a level shifter circuit in accordance with the present disclosure.
- the bootstrap supply voltage powering the level shifter circuit 200 is shown as ranging from about 0.7 V to 2.7 V.
- the pulse width needed to change the state of the high voltage latch 208 is set to about 31 nanosecond (ns) (e.g., by the delay circuit 306 ).
- the pulse width 502 is set to about 31 ns for all bootstrap voltages.
- pulse width 504 is reduced below about 1.2 V as the time required to change the state of the high voltage latch 208 decreases with increasing bootstrap supply voltage. Accordingly, the current drawn from the bootstrap supply by the level shifter circuit 200 over the illustrated range of voltages is lower than the current drawn from the bootstrap supply over the illustrated range of voltages using a fixed pulse width.
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Abstract
Description
- The present application claims priority to U.S. Provisional Patent Application No. 62/682,435, filed Jun. 8, 2018, entitled “High Voltage Level Shift with Adaptive Trigger,” which is hereby incorporated herein by reference in its entirety.
- Electronic systems often include circuits that are powered by different power supply voltages, or that require different signal levels to activate circuit components. Such systems include circuitry to translate signals between different voltage levels. For example, some such systems include level shifting circuits (level shifters) are used to translate signals from one voltage level to another. A level shifter may be used to translate a signal from a lower voltage to a higher voltage, or to translate a signal from a higher voltage to a lower voltage.
- In one example, a level shifter circuit, includes a high voltage latch circuit, a low voltage latch circuit, a high state pulse generator, and a low state pulse generator. The high voltage latch circuit includes a non-inverting output terminal, an inverting output terminal, a high state trigger input terminal, and a low state trigger input terminal. The low voltage latch circuit is coupled to the high voltage latch circuit, and includes a high state trigger input terminal and a low state trigger input terminal. The high state trigger input terminal is coupled to the inverting output terminal of the high voltage latch circuit. The low state trigger input terminal is coupled to the non-inverting output terminal of the high voltage latch circuit. The high state pulse generator is coupled to the high state trigger input terminal of the high voltage latch circuit. The low state pulse generator is coupled to the low state trigger input terminal of the high voltage latch circuit.
- In another example, a level shifter circuit includes a high voltage latch circuit, a low voltage latch circuit, a high state pulse generator, and a low state pulse generator. The high voltage latch circuit is configured to generate a high voltage output of the level shifter circuit. The low voltage latch circuit is coupled to the high voltage latch circuit, and is configured to change states responsive to a change in state of the high voltage latch circuit. The high state pulse generator is coupled to the high voltage latch circuit and the low voltage latch circuit, and configured to generate a first pulse to set the high voltage latch circuit, and to terminate the first pulse responsive to the low voltage latch being set. The low state pulse generator is coupled to the high voltage latch circuit and the low voltage latch circuit, and is configured to generate a second pulse to reset the high voltage latch circuit, and to terminate the second pulse responsive to the low voltage latch being reset.
- In a further example, a level shifter circuit includes a high voltage latch circuit, a low voltage latch circuit, a high state pulse generator, a low state pulse generator, and sample control circuitry. The high voltage latch circuit is configured to generate a high voltage output of the level shifter circuit. The low voltage latch circuit is coupled to the high voltage latch circuit, and is configured to change states responsive to a change in state of the high voltage latch circuit. The high state pulse generator is coupled to the high voltage latch circuit and the low voltage latch circuit, and configured to generate a first pulse to set the high voltage latch circuit, and to terminate the first pulse responsive to the low voltage latch being set. The low state pulse generator is coupled to the high voltage latch circuit and the low voltage latch circuit, and is configured to generate a second pulse to reset the high voltage latch circuit, and to terminate the second pulse responsive to the low voltage latch being reset. The sample control circuitry is coupled to the low voltage latch circuit, the high state pulse generator, and the low state pulse generator. The sample control circuitry is configured to enable a state change of the low voltage latch circuit responsive to generation of a pulse by the high state pulse generator or the low state pulse generator.
- For a detailed description of various examples, reference will now be made to the accompanying drawings in which:
-
FIG. 1 shows a block diagram for an example system that controls an N-channel metal oxide semiconductor field effect transistor (MOSFET) using a level shifter circuit powered by bootstrap voltage in accordance with the present disclosure; -
FIG. 2 shows a schematic diagram for an example level shifter circuit that includes adaptive pulse generation in accordance with the present disclosure; -
FIG. 3 shows a schematic diagram for an example pulse generation circuit in accordance with the present disclosure; -
FIG. 4 shows an example timing diagram for operation of the pulse generation circuit ofFIG. 3 ; and -
FIG. 5 shows a graph illustrating example pulse times for a fixed pulse width level shifter circuit and a level shifter circuit that includes adaptive pulse generation in accordance with the present disclosure. - Certain terms have been used throughout this description and claims to refer to particular system components. As one skilled in the art will appreciate, different parties may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In this disclosure and claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation “based on” is intended to mean “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.
- Some high voltage switching applications use an N-channel metal oxide semiconductor field effect transistor (MOSFET) to switch high voltage due to the smaller size of the N-channel MOSFET relative to a P-channel MOSFET having similar channel resistance. Such applications employ bootstrapped MOSFET gate drive that keeps a bootstrap capacitor charged several volts above the high voltage switched by the MOSFET. A level shifter translates ground-referenced input signal to the high voltages needed to control the MOSFET. Because the charge stored on the bootstrap capacitor is limited, the current drawn from the bootstrap capacitor by the level shifter should be minimized.
- Some level shifters use floating latch stages cascoded with high voltage P-channel MOSFETs in the high voltage domain. The cascodes work well down to about 3 volts (V), but in battery powered electronics, voltage supplies of 3 V or less are common. Cascode headroom requirements prevent operation below about 2.5 V.
- Pulse-driven level shifters drive P-channel MOSFET bootstrap-referenced trigger devices that control a high voltage latch. High speed and high noise immunity require that high trigger currents be pulled from the bootstrap capacitor. Accordingly, the pulses controlling the latch must be as narrow as possible. Unfortunately, the duration of the pulses needed to change the state of the latch varies with voltage, process, and temperature. For example, a 10:1 ratio of pulse width is commonly needed to accommodate the strongest and weakest conditions. Thus, using a fixed pulse width wastes bootstrap current in normal operating conditions.
- The level shifter circuits disclosed herein include a pulse generator that is controlled by feedback from the high voltage latch that generates the level shifted output. State change in the high voltage latch terminates the pulse signal provided by the pulse generator so that the pulse duration is only as long as is needed to change the state of the high voltage latch. Thus, the width of the pulse, and the current drawn from the bootstrap capacitor by operation of the level shifter are minimized. Implementations of the level shifter circuits include a low voltage latch that changes state responsive to state change of the high voltage latch. The pulse generators terminate pulse output responsive to state change in the low voltage latch.
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FIG. 1 shows a block diagram for anexample system 100 in accordance with the present disclosure. Thesystem 100 includes alevel shifter circuit 102, agate driver 104, an N-channel MOSFET 106, abootstrap capacitor 108, adiode 112, avoltage source 110, agate driver 118, and an N-channel MOSFET 120. Implementations of thesystem 100 may be included in circuitry for a variety of applications. For example, a class-D amplifier includes an implementation of thesystem 100 to drive a loudspeaker. - The N-
channel MOSFET 120 and thegate driver 118 are referenced to ground, and thegate driver 118 drives an inverted version of the input signal VIN to the N-channel MOSFET 120. Thelevel shifter circuit 102, thegate driver 104 and the N-channel MOSFET 106 are referenced toVOUT 116. Thebootstrap capacitor 108, thediode 112 andvoltage source 110 produce a bootstrap voltage (VBOOT) 114 that powers thelevel shifter circuit 102 and thegate driver 104, and allows thelevel shifter circuit 102 and thegate driver 104 to provide a control voltage higher thanVOUT 116 to turn on the N-channel MOSFET 106. In some implementations of thesystem 100, thevoltage source 110 is a battery and/or generates the voltage (VDD) 126 that powers low voltage circuitry of thesystem 100. Thelevel shifter circuit 102 shifts the input signal VIN from a ground referenced signal to the power rails defined byVOUT 116 andVBOOT 114. Thelevel shifter circuit 102 includes adaptive pulse generation circuitry that reduces the current drawn from thebootstrap capacitor 108. -
FIG. 2 shows a schematic diagram for an examplelevel shifter circuit 200 that includes adaptive pulse generation in accordance with the present disclosure. Thelevel shifter circuit 200 is an implementation of thelevel shifter circuit 102. Thelevel shifter circuit 200 includes a highstate pulse generator 202, a lowstate pulse generator 222, ahigh voltage latch 208, and alow voltage latch 216. The highstate pulse generator 202 is coupled to the levelshifter input terminal 218 to generate a pulse at a rising edge of the signal received at the levelshifter input terminal 218. The lowstate pulse generator 222 is coupled to the levelshifter input terminal 218 via theinverter 220 to generate a pulse at a falling edge of the signal received at the levelshifter input terminal 218. Aninput 220A of theinverter 220 is coupled to the levelshifter input terminal 218, and anoutput 220B of theinverter 220 is coupled to the lowstate pulse generator 222. Thehigh voltage latch 208 is powered byVBOOT 114 and generates the high voltage output (LSOUT) 124 of thelevel shifter circuit 200. The high state pulse generator 202 (output 202C) is coupled to a high statetrigger input terminal 208C of thehigh voltage latch 208, and generates a pulse to set thehigh voltage latch 208 via thetransistor 204 and thetransistor 206. The low state pulse generator 222 (output 222C) is coupled to a low statetrigger input terminal 208D of thehigh voltage latch 208, and resets thehigh voltage latch 208 via thetransistor 224 and thetransistor 226. - The
high voltage latch 208 includes a pair of cross-coupled inverters. A first of the inverters includestransistor 238 andtransistor 240. A second of the inverters includestransistor 242 andtransistor 244. The highstate pulse generator 202 generates a pulse when thesignal VIN 122 transitions from logic low voltage to logic high voltage. The pulse turns on thetransistor 204, which enables current flow in thetransistor 206 and turns on the transistor 246 to set thehigh voltage latch 208. Similarly, the lowstate pulse generator 222 generates a pulse when thesignal VIN 122 transitions from logic high voltage to logic low voltage. The pulse turns on thetransistor 224, which enables current flow in thetransistor 226 and turns on thetransistor 236 to reset thehigh voltage latch 208. - The duration of the pulses generated by the high
state pulse generator 202 and the lowstate pulse generator 222 is a function of the time needed for thehigh voltage latch 208 to change state responsive to the pulses. Thelow voltage latch 216 is coupled to thehigh voltage latch 208 and changes state responsive to change in state of thehigh voltage latch 208. The outputs of thelow voltage latch 216 are fed back to the highstate pulse generator 202 and the lowstate pulse generator 222 to reset the pulses generated by the highstate pulse generator 202 and the lowstate pulse generator 222. More specifically, apulse termination input 202A of the highstate pulse generator 202 is coupled to the highstate output terminal 216C of thelow voltage latch 216 and apulse termination input 222A of the lowstate pulse generator 222 is coupled to the lowstate output terminal 216D of thelow voltage latch 216. - The
low voltage latch 216 includes a pair of cross-coupled inverters. A first of the inverters includestransistor 250 andtransistor 252. A second of the inverters includestransistor 254 andtransistor 256. State change in thelow voltage latch 216 is enabled by thesample control circuitry 260. Thesample control circuitry 260 is coupled to thelow voltage latch 216, the highstate pulse generator 202 and the lowstate pulse generator 222, and generates an enable signal that combines the outputs of the highstate pulse generator 202 and the lowstate pulse generator 222. In the examplesample control circuitry 260 shown inFIG. 2 , thesample control circuitry 260 includes a NORgate 262 that combines the outputs of the highstate pulse generator 202 and the lowstate pulse generator 222, and aninverter 264 to produce an output that is complementary to the output of the NORgate 262. Other implementations of thesample control circuitry 260 include different logical circuitry. When the highstate pulse generator 202 or the lowstate pulse generator 222 generates a pulse, thesample control circuitry 260 enables sampling of the outputs of thehigh voltage latch 208 by thelow voltage latch 216, which in turn enables a state change of the lowvoltage latch circuit 216. - The
sample control circuitry 260 is coupled to atransistor 212, atransistor 214, a transistor 232, and atransistor 234 to control operation of thelow voltage latch 216. Thetransistor 214 and thetransistor 234 are coupled to the output of the NORgate 262. More specifically, thetransistor 214 includes afirst terminal 214B that is coupled to the highstate pulse generator 202 and the lowstate pulse generator 222 through thesample control circuitry 260, and asecond terminal 214A that is coupled to the low statetrigger input terminal 216B of thelow voltage latch 216. Thetransistor 234 includes afirst terminal 234B that is coupled to the highstate pulse generator 202 and the lowstate pulse generator 222 through thesample control circuitry 260, and asecond terminal 234A that is coupled to the high statetrigger input terminal 216A of thelow voltage latch 216. When neither the highstate pulse generator 202, nor the lowstate pulse generator 222 is generating a pulse, thetransistor 214 and thetransistor 234 are turned on to pull the high statetrigger input terminal 216A and the low statetrigger input terminal 216B, the gate terminal of thetransistor 248 and the gate terminal of thetransistor 258, low and disable state change in thelow voltage latch 216. - When either the high
state pulse generator 202 or the lowstate pulse generator 222 is generating a pulse, thetransistor 214 and thetransistor 234 are turned off to allow thelow voltage latch 216 to sample the outputs of thehigh voltage latch 208. Thelow voltage latch 216 is coupled to thehigh voltage latch 208 via atransistor 212, atransistor 210, a transistor 232, and atransistor 230. The high statetrigger input terminal 216A of thelow voltage latch 216 is coupled to the invertingoutput terminal 208B of thehigh voltage latch 208 via thetransistor 230 and the transistor 232. The low statetrigger input terminal 216B of thelow voltage latch 216 is coupled to thenon-inverting output terminal 208A of thehigh voltage latch 208 via thetransistor 210 and thetransistor 212. More specifically, the terminal 210A of thetransistor 210 is coupled to thenon-inverting output terminal 208A of thehigh voltage latch 208, and the terminal 210B of thetransistor 210 is coupled to the terminal 212C of the 212 (the terminal 212C of thetransistor 212 is coupled to the high voltage latch 208). The terminal 212A of thetransistor 212 is coupled to the low statetrigger input terminal 216B of thelow voltage latch 216 and the terminal 214A of thetransistor 214, and the terminal 212B of thetransistor 212 is coupled to the highstate pulse generator 202 and the lowstate pulse generator 222 via the sample control circuitry 260 (theinverter 264 of the sample control circuitry 260). Similarly, the terminal 230A of thetransistor 230 is coupled to the invertingoutput terminal 208B of thehigh voltage latch 208, and the terminal 230B of thetransistor 230 is coupled to the terminal 232C of the transistor 232 (the terminal 232C of the transistor 232 is coupled to the high voltage latch 208). The terminal 232A of the transistor 232 is coupled to the high statetrigger input terminal 216A of thelow voltage latch 216 and the terminal 234A of thetransistor 234, and the terminal 232B of the transistor 232 is coupled to the highstate pulse generator 202 and the lowstate pulse generator 222 via the sample control circuitry 260 (theinverter 264 of the sample control circuitry 260). - When either the high
state pulse generator 202 or the lowstate pulse generator 222 is generating a pulse, thetransistor 212 and the transistor 232 are turned on to connect thelow voltage latch 216 to thehigh voltage latch 208. The state of thehigh voltage latch 208 is set responsive the pulse, and either thetransistor 210 or thetransistor 230 is turned on. If thenon-inverting output terminal 208A is set to a logic high level, then thetransistor 230 is turned on. If thenon-inverting output terminal 208A is set to a logic low level, then thetransistor 210 is turned on. The one of thetransistor 210 or thetransistor 230 that is turned on passes a voltage to the low voltage latch 216 (via either thetransistor 212 or the transistor 232) that changes the state of thelow voltage latch 216, and in turn terminates the pulse generated by the highstate pulse generator 202 or the lowstate pulse generator 222. Termination of the pulse turns off thetransistor 212 and the transistor 232 and turns on thetransistor 214 and thetransistor 234 to disable further state change of thelow voltage latch 216 until a next pulse is generated by the highstate pulse generator 202 or the lowstate pulse generator 222. -
FIG. 3 shows a schematic diagram for an examplepulse generation circuit 300 in accordance with the present disclosure. Thepulse generation circuit 300 is an implementation of the highstate pulse generator 202 or the lowstate pulse generator 222. Thepulse generation circuit 300 includes an ANDgate 302, a NORgate 304, and adelay circuit 306. The ANDgate 302 includes aninput 302A that is coupled to a levelshifter input terminal 218 of the level shifter circuit 200 (or theoutput 220B of the inverter 220), and aninput 302B that is coupled theoutput 304C of the NORgate 304. - The NOR
gate 304 includes aninput 304A that is coupled to an output of thelow voltage latch 216. For example, theinput 304A is coupled to the highstate output terminal 216C or the lowstate output terminal 216D. The NORgate 304 also includes aninput 304B that is coupled to theoutput 306B of thedelay circuit 306. Theinput 306A of thedelay circuit 306 is coupled to theinput 302A of the ANDgate 302 and the levelshifter input terminal 218 of the level shifter circuit 200 (or the output of the inverter 220). -
FIG. 4 shows an example timing diagram for operation of thepulse generation circuit 300. Attime 402 thesignal VIN 122 transitions from a logic low level to a logic high level. As a result, both theinput 302A and theinput 302B of the ANDgate 302 are at a logic high level, and the ANDgate 302 initiates apulse 408 attime 404. Thesignal VIN 122 is delayed by thedelay circuit 306, and attime 406 the delayed version of thesignal VIN 122 is provided at theinput 304B of the NORgate 304, which in turn sets theinput 302B of the ANDgate 302 to a logic low level and terminates thepulse 408 generated at the output of the ANDgate 302. Thus, the duration of thepulse 408 is determined by the time delay provided by thedelay circuit 306 because no feedback from the lowvoltage latch circuit 216 is received to terminate thepulse 408. - At
time 412 thesignal VIN 122 again transitions for a logic low level to a logic high level. As a result, both theinput 302A and theinput 302B of the ANDgate 302 are at a logic high level, and the ANDgate 302 initiates apulse 418 attime 414. Attime 410, thehigh voltage latch 208 andlow voltage latch 216 have changed state responsive to thepulse 418, and the change in the output of thelow voltage latch 216 attime 410 is provided at theinput 304A of the NORgate 304, which in turn sets theinput 302B of the ANDgate 302 to a logic low level and terminates thepulse 418 generated at the output of the ANDgate 302. Thus, the duration of thepulse 418 is determined by the time needed to change the state of thehigh voltage latch 208 and thelow voltage latch 216 responsive to thepulse 418. -
FIG. 5 shows a graph illustrating example pulse times for a fixed pulse width level shifter circuit and a level shifter circuit in accordance with the present disclosure. InFIG. 5 , the bootstrap supply voltage powering thelevel shifter circuit 200 is shown as ranging from about 0.7 V to 2.7 V. With bootstrap supply voltages below a minimum functional value of about 1.2 V, the pulse width needed to change the state of thehigh voltage latch 208 is set to about 31 nanosecond (ns) (e.g., by the delay circuit 306). Accordingly, in a level shifter circuit that employs a fixed pulse width, thepulse width 502 is set to about 31 ns for all bootstrap voltages. - In the
level shifter circuit 200,pulse width 504 is reduced below about 1.2 V as the time required to change the state of thehigh voltage latch 208 decreases with increasing bootstrap supply voltage. Accordingly, the current drawn from the bootstrap supply by thelevel shifter circuit 200 over the illustrated range of voltages is lower than the current drawn from the bootstrap supply over the illustrated range of voltages using a fixed pulse width. - The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Claims (20)
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US5539334A (en) | 1992-12-16 | 1996-07-23 | Texas Instruments Incorporated | Method and apparatus for high voltage level shifting |
US5821800A (en) | 1997-02-11 | 1998-10-13 | Advanced Micro Devices, Inc. | High-voltage CMOS level shifter |
US6828825B2 (en) | 2002-08-27 | 2004-12-07 | Texas Instruments Incorporated | Pulse response of fast level shifter |
JP4149968B2 (en) * | 2004-07-08 | 2008-09-17 | 松下電器産業株式会社 | Voltage level conversion circuit |
US7236020B1 (en) | 2004-12-17 | 2007-06-26 | 02Micro Inc. | Pulse translation method from low to high voltage level in half and full bridge application |
US7227400B1 (en) | 2005-03-30 | 2007-06-05 | Integrated Device Technology, Inc. | High speed MOSFET output driver |
US20070164789A1 (en) * | 2006-01-17 | 2007-07-19 | Cypress Semiconductor Corp. | High Speed Level Shift Circuit with Reduced Skew and Method for Level Shifting |
US8218377B2 (en) | 2008-05-19 | 2012-07-10 | Stmicroelectronics Pvt. Ltd. | Fail-safe high speed level shifter for wide supply voltage range |
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