US20190372583A1

US20190372583A1 - Successive Approximation Register (SAR) Analog to Digital Converter (ADC) Dynamic Range Extension

Info

Publication number: US20190372583A1
Application number: US16/398,188
Authority: US
Inventors: Ali Farid; Ahmed Emira; Mohamed Aboudina; Hassan Elwan
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2018-05-31
Filing date: 2019-04-29
Publication date: 2019-12-05
Anticipated expiration: 2038-05-31
Also published as: EP3607659A4; CN111313903B; CN109565285B; EP3607659A1; CN111313903A; US10491232B1; US10291252B1; WO2019227845A1; CN109565285A; EP3607659B1

Abstract

An ADC, including a DAC which receives an analog input voltage and a digital input word from SAR logic, and generates a first voltage based on the analog input voltage and the digital word. The ADC also includes a comparator, which receives the first voltage and a reference voltage, and generates a second voltage based on the first voltage and on the reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The ADC also includes the SAR logic circuit which receives the second voltage from the comparator. The SAR logic generates a digital output word based on a second voltages received from the comparator. A difference between the minimum input voltage on the maximum input voltage is substantially equal to two times a difference between reference voltage and the minimum input voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 15/993,625, entitled “Successive Approximation Register (SAR) Analog to Digital Converter (ADC) Dynamic Range Extension,” filed May 31, 2018, which is incorporated herein by reference for all purposes.

FIELD OF THE INVENTION

The present invention relates generally to a successive approximation register (SAR) analog to digital converter (ADC), and more particularly to a SAR ADC which has a reference voltage which is about half the voltage of the difference between the maximum input voltage and the minimum input voltage.

BACKGROUND OF THE INVENTION

Conventional SAR ADC architectures use reference voltages which are equal to or are substantially equal to the maximum input voltage. Because the reference voltage is used in a capacitive digital to analog converter (CDAC), the power used by the CDAC is significantly affected by the value of the reference voltage.

BRIEF SUMMARY OF THE INVENTION

One inventive aspect is a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a DAC, a comparator, and an SAR logic circuit, where the DAC, the comparator, and the SAR logic circuit are in electrical communication with one another and are collectively configured to generate a digital output word based on an analog input voltage and on a reference voltage, where the digital output word represents the value of the analog input voltage with reference to a range of analog values bounded by a minimum analog input voltage and a maximum analog input voltage, and where a difference between the minimum analog input voltage and the maximum analog input voltage is substantially equal to two times a difference between the reference voltage and the minimum analog input voltage.
In some embodiments, the SAR logic is configured to determine the MSB of the digital output word as a result of a comparison of the analog input voltage with the reference voltage.
In some embodiments, the DAC is configured to receive the analog input voltage and a digital input word, and to generate a first voltage based on the analog input voltage and the digital word, and where the SAR logic is configured to determine whether the digital input word causes the DAC to generate the first voltage such that the first voltage is greater than or is less than the analog input voltage.
In some embodiments, the SAR logic is configured to determine whether the digital input word causes the DAC to generate the first voltage such that the first voltage is greater than or is less than the analog input voltage based on whether the analog input voltage is determined to be less than or greater than the reference voltage by the comparator.
In some embodiments, the SAR logic is configured to generate the digital input word to cause the DAC to generate the first voltage such that the first voltage is greater than the analog input voltage in response to the analog input voltage being less than the reference voltage.
In some embodiments, the SAR logic is configured to generate the digital input word to cause the DAC to generate the first voltage such that the first voltage is less than the analog input voltage in response to the analog input voltage being greater than the reference voltage.
In some embodiments, the SAR logic is configured to determine a digital representation of a difference between the analog input voltage and the reference voltage.
In some embodiments, the SAR logic is configured to determine the digital representation with a linear search.
In some embodiments, the SAR logic is configured to determine the digital representation with a binary search.
In some embodiments, the SAR logic is configured to determine the MSB of the digital output word by comparing the analog input voltage with the reference voltage, to determine a digital representation of a difference between the analog input voltage and the reference voltage, and to generate the bits of the digital output word other than the MSB based on the digital representation of the difference between the analog input voltage and the reference voltage.
Another inventive aspect is a method of determining a digital output word having a value corresponding with an analog input value with a successive approximation register (SAR) analog to digital converter (ADC) including a DAC, a comparator, and an SAR logic circuit in electrical communication with one another. The method includes, with the SAR ADC receiving an analog input voltage, receiving a reference voltage, and generating a digital output word based on the analog input voltage and on the reference voltage, where the digital output word represents the value of the analog input voltage with reference to a range of analog values bounded by a minimum analog input voltage and a maximum analog input voltage, and where a difference between the minimum analog input voltage and the maximum analog input voltage is substantially equal to two times a difference between the reference voltage and the minimum analog input voltage.
In some embodiments, the method further includes, with the SAR logic circuit, determining the MSB of the digital output word as a result of a comparison of the analog input voltage with the reference voltage.
In some embodiments, the method further includes, with the DAC, receiving the analog input voltage and a digital input word, and generating a first voltage based on the analog input voltage and the digital word, and, with the SAR logic circuit, determining whether the digital input word causes the DAC to generate the first voltage such that the first voltage is greater than or is less than the analog input voltage.
In some embodiments, the method further includes, with the SAR logic circuit, determining whether the digital input word causes the DAC to generate the first voltage such that the first voltage is greater than or is less than the analog input voltage based on whether the analog input voltage is determined to be less than or greater than the reference voltage by the comparator.
In some embodiments, the method further includes, with the SAR logic circuit, generating the digital input word to cause the DAC to generate the first voltage such that the first voltage is greater than the analog input voltage in response to the analog input voltage being less than the reference voltage.
In some embodiments, the method further includes, with the SAR logic circuit, generating the digital input word to cause the DAC to generate the first voltage such that the first voltage is less than the analog input voltage in response to the analog input voltage being greater than the reference voltage.
In some embodiments, the method further includes, with the SAR logic circuit, determining a digital representation of a difference between the analog input voltage and the reference voltage.
In some embodiments, the method further includes, with the SAR logic circuit, determining the digital representation with a linear search.
In some embodiments, the method further includes, with the SAR logic circuit, determining the digital representation with a binary search.
In some embodiments, the method further includes, with the SAR logic circuit, determining the MSB of the digital output word by comparing the analog input voltage with the reference voltage, determining a digital representation of a difference between the analog input voltage and the reference voltage, and generating the bits of the digital output word other than the MSB based on the digital representation of the difference between the analog input voltage and the reference voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of an SAR ADC according to one embodiment.

FIG. 2 is a schematic illustration of an embodiment of a CDAC which may be used in the SAR ADC of FIG. 1.

FIG. 3 is a waveform diagram illustrating operation of the SAR ADC of FIG. 1.

FIG. 4 is a waveform diagram illustrating operation of the SAR ADC of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

Particular embodiments of the invention are illustrated herein in conjunction with the drawings.
Various details are set forth herein as they relate to certain embodiments. However, the invention can also be implemented in ways which are different from those described herein. Modifications can be made to the discussed embodiments by those skilled in the art without departing from the invention. Therefore, the invention is not limited to particular embodiments disclosed herein.
The present invention is related to an SAR ADC. The SAR ADC determines a corresponding digital value for an analog input based on a successive approximation system. A particular embodiment of the SAR ADC is designed to generate digital values for analogue inputs ranging between a minimum input value and a maximum input value. As discussed in further detail below, the successive approximation system uses a reference voltage value to generate the digital values. In the embodiments discussed, the reference voltage is approximately or substantially equal to 1 half the difference between the maximum input value and the minimum input value.
FIG. 1 is a schematic illustration of an SAR ADC 100 according to one embodiment. SAR ADC 100 includes CDAC 110, comparator 120, SAR logic 130 and clock generator 140.
SAR ADC 100 receives an analog input value at Vin. In response to a start signal, SAR ADC 100 calculates and generates a digital value corresponding with the analog input value Vin. Once calculated, SAR ADC 100 provides the digital value as output word Dout.
To determine the digital value, SAR ADC 100 determines a most significant bit (MSB), and subsequently determines each of the other bits of the digital output word. To determine the MSB, in response to one or more clock signals from clock generator 140, the analog input voltage Vin is provided to comparator 120 as voltage Vcomp, and comparator 120 compares voltage Vcomp with reference voltage Vref and generates an output voltage corresponding with the results of the comparison. In addition, in response to one or more clock signals from clock generator 140, SAR logic 130 receives the output from the comparator 120, and determines and stores an MSB based on the output from the comparator 120.
To determine each of the other bits of the digital output word, in response to each of one or more clock signals from clock generator 140, SAR logic 130 determines a next digital input word for CDAC 110, and CDAC 110 generates a next voltage Vcomp. In addition, in response to each of one or more clock signals from clock generator 140, comparator 120 compares the next voltage Vcomp with reference voltage Vref and generates an output voltage corresponding with the results of the comparison. Furthermore, in response to one or more clock signals from clock generator 140, SAR logic 130 receives the output from the comparator 120, and determines whether a next digital input word for CDAC 110 should be generated.
In some embodiments, in may be beneficial to determine whether the analog input voltage Vin is greater than or is less than the reference voltage Vref. In such embodiments, the comparison used to determine the MSB may be used as an indication of whether the analog input voltage Vin is greater than or is less than the reference voltage Vref.
In some embodiments, SAR logic 130 uses the information regarding whether the analog input voltage Vin is greater than or is less than the reference voltage Vref to determine a next digital input word for CDAC 110. For example, SAR logic 130 may use the information regarding whether the analog input voltage Vin is greater than or is less than the reference voltage Vref to determine whether each next Vcomp should be greater than the analog input voltage Vin or should be less than the analog input voltage Vin.
If sufficient digital input words for CDAC 110 have been generated and corresponding comparison results has been received by SAR logic 130, SAR logic 130 determines that the digital output word may be generated and provided to output Dout. If sufficient digital input words for CDAC 110 and corresponding comparison results has been received by SAR logic 130, SAR logic 130 generates a next digital input port for CDAC 110.
SAR logic 130 may include circuitry configured to implement any of a number of SAR calculations. For example, SAR logic 130 may include circuitry configured to implement either a linear or a binary SAR calculation, as understood by those of ordinary skill in the art. The circuitry of SAR logic 130 may be designed and built using processes known to those of skill in the art.
FIG. 2 is a schematic illustration of an embodiment of a CDAC 200 which may be used in the SAR ADC of FIG. 1. CDAC 200 includes switch 210 and an array of capacitors. The capacitors are by binary waited, such that capacitors having values C, 2×C, 4×C, 2^(N−1)×C are included, where N is equal to the number of bits of resolution of CDAC 200. Each of the capacitors is connected to a switch configured to selectively connect the capacitor to either a ground voltage or a reference voltage Vref.
When used in the SAR ADC 100 illustrated in FIG. 1 to determine the MSB of the digital output word, switch 210 is closed such that the analog input voltage Vin is provided to comparator 120 as voltage Vcomp. In addition, while comparator 120 compares voltage Vcomp with reference voltage Vref, the switches connected to each of the capacitors are each connected to either the ground voltage or the reference voltage Vref, and are not changed during the comparison.
When used in the SAR ADC 100 illustrated in FIG. 1 to determine each of the other bits of the digital output word, during a first period, the output node out is charged to analog input voltage Vin through conducting switch 210 while the switches connected to each of the capacitors are each connected to either the ground voltage or the reference voltage Vref, and during a second period, switch 210 is opened and one or more of the switches are switched, such that the one or more capacitors connected to the one or more switches are then connected to the other of the ground voltage or the reference voltage.
For example, during the first period the output node may be charged to analog input voltage Vin through the switch 210, which is closed. Additionally, during the first period, the switch connected to the capacitor having weight C is connected to the ground voltage. Subsequently, during the second period, switch 210 is opened, and the switch connected to the capacitor having weight C is switched so as to be connected to the reference voltage Vref. As a result, the voltage at the output node out is increased from the analog input voltage Vin by an amount corresponding with the charge stored on the capacitor having weight C.
In some embodiments, CDAC 120 includes a sample and hold amplifier between the analog input and switch 210. When present, the sample and hold amplifier samples the analog input voltage Vin, stores the sample voltage, and drives the switch 210 with a voltage substantially equal to the stored voltage. Sample and hold amplifiers known to those of skill in the art may be used.
Similarly, in some embodiments, SAR ADC 100 may include a sample and hold amplifier between the analog input and CDAC 120. When present, the sample and hold amplifier samples the analog input voltage Vin, stores the sample voltage, and drives CDAC 120 with a voltage substantially equal to the stored voltage. Sample and hold amplifiers known to those of skill in the art may be used.
As another example, during the first period the output node may be charged to analog input voltage Vin through the switch 210, which is closed. Additionally, during the first period, the switch connected to the capacitor having weight C is connected to the reference voltage Vref. Subsequently, during the second period, switch 210 is opened, and the switch connected to the capacitor having weight C is switched so as to be connected to the ground voltage. As a result, the voltage at the output node out is decreased from the analog input voltage Vin by an amount corresponding with the charge stored on the capacitor having weight C.
FIG. 3 is a waveform diagram illustrating operation of an embodiment of an SAR ADC, such as the SAR ADC 100 of FIG. 1. As shown, analog input voltage Vin is greater than a reference voltage Vref and is less than the maximum analog input voltage Vmax. In addition, as shown, reference voltage Vref is substantially equal to half the difference between maximum analog input voltage Vmax and minimum analog input voltage Vmin.
In the example illustrated in FIG. 3, the SAR ADC uses a linear search SAR method. As understood by those of skill in the art, other SAR methods, such as a binary search, may be used.
During the time period Ti, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the analog voltage Vin, and comparator 120 generates a comparison value indicating that the analog voltage Vin is greater than the reference voltage Vref. In addition, based on the comparison value, SAR logic 130 determines the MSB of the digital output, and determines that subsequent values of voltage Vcomp will be less than the analog input value Vin.
Furthermore, in response to the comparison value indicating that the analog voltage Vin is greater than the reference voltage Vref, SAR logic 130 determines that the digital word for CDAC 110 is to be all ones during the time period T2, while the analog voltage Vin is sampled. As a result, digital words during time periods subsequent to time period T2, cause the voltage Vcomp to decrease toward Vref because the digital words during the subsequent time periods are less than all ones.
During the time period T2, as a result of the digital input word from SAR logic 130 being all ones, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, comparator 120 generates a comparison value indicating that the voltage Vcomp is greater than the voltage Vref as a result of the voltage Vcomp being greater than the voltage Vref, and SAR logic 130 determines that the next Vcomp is to be less than the current Vcomp as a result of the voltage Vcomp being greater than the voltage Vref.
In alternative embodiments, during time period T2, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, minus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all ones minus 1 lsb. Also, in such embodiments, the operation of comparator 120 and SAR logic 130 may remain unchanged.
During the time period T3, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, minus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all ones minus 1 lsb.
In addition, during time period T3, comparator 120 generates a comparison value indicating that the voltage Vcomp is greater than the voltage Vref as a result of the voltage Vcomp being greater than the voltage Vref, and SAR logic 130 determines that the next Vcomp is to be less than the current Vcomp as a result of the voltage Vcomp being greater than the voltage Vref.
During the time period T4, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, minus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all ones minus 2 lsbs.
In addition, during time period T4, comparator 120 generates a comparison value indicating that the voltage Vcomp is greater than the voltage Vref as a result of the voltage
Vcomp being greater than the voltage Vref, and SAR logic 130 determines that the next Vcomp is to be less than the current Vcomp as a result of the voltage Vcomp being greater than the voltage Vref.
During the time period T5, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, minus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all ones minus 3 lsbs.
In addition, during time period T5, comparator 120 generates a comparison value indicating that the voltage Vcomp is greater than the voltage Vref as a result of the voltage Vcomp being greater than the voltage Vref, and SAR logic 130 determines that the next Vcomp is to be less than the current Vcomp as a result of the voltage Vcomp being greater than the voltage Vref.
During the time period T6, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, minus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all ones minus 4 lsbs.
In addition, during time period T6, comparator 120 generates a comparison value indicating that the voltage Vcomp is less than the voltage Vref as a result of the voltage Vcomp being less than the voltage Vref, and SAR logic 130 determines that the next Vcomp is to be greater than the current Vcomp as a result of the voltage Vcomp being less than the voltage Vref.
In some embodiments, because all the information for determining the digital output word is available after time period T6, the SAR logic 130 determines the digital output word according to principles and aspects discussed elsewhere herein and/or otherwise known to those of skill in the art.
In the exemplary embodiment of FIG. 3, during the time period T7, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, plus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all ones minus 3 lsbs.
As a result of the voltage Vcomp being less than the voltage Vref during time period T6, the SAR logic 130 generates the digital output word corresponding to the analog input voltage Vin.
Because analog input voltage Vin was determined to be greater than the reference voltage Vref during time period T1, the MSB of the digital output word corresponds with that determination. In addition, because the digital input word from SAR logic 130 for CDAC 110 of time period T7 corresponds with the voltage difference between the reference voltage Vref and analog input voltage Vin, and the bits of the digital output word other than the MSB also correspond with the voltage difference between the reference voltage Vref and analog input voltage Vin, the digital input word from SAR logic 130 for CDAC 110 of time period T7 corresponds with the bits of the digital output word other than the MSB.
For example, if, in the example of FIG. 3, the maximum input voltage Vmax is 1 V, and the analog input voltage Vin is 0.74 V, a 4-bit digital word corresponding to the analog input voltage, may be 1011. The value of 1 for the MSB is determined during time period T1. In addition, because the digital input word from SAR logic 130 for CDAC 110 of time period T6 causes the voltage Vcomp to be equal to or substantially equal to the analog input voltage Vin, minus four voltage steps, where the magnitude of the voltage steps each correspond with the charge of the capacitor of CDAC 110 having value C, the other bits of the digital output word correspond with a voltage difference between the analog input voltage Vin and the reference voltage Vref, which corresponds digitally to 100. Accordingly, the digital output word is determined to be the expected 1011 because 0111+0100=1011, where 0111 represents the digitized value of the analog input voltage Vin minus four times the voltage corresponding with the charge of the capacitor of CDAC 110 having value C.
Once determined, the SAR ADC 100 represents the digital output word on the output Dout.
FIG. 4 is a waveform diagram illustrating operation of an embodiment of an SAR ADC, such as the SAR ADC 100 of FIG. 1. As shown, analog input voltage Vin is less than a reference voltage Vref and is less than the maximum analog input voltage Vmax. In addition, as shown, reference voltage Vref is substantially equal to half the difference between maximum analog input voltage Vmax and minimum analog input voltage Vmin.
In the example illustrated in FIG. 4, the SAR ADC uses a linear search SAR method. As understood by those of skill in the art, other SAR methods, such as a binary search, may be used.
During the time period Ti, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the analog voltage Vin, and comparator 120 generates a comparison value indicating that the analog voltage Vin is less than the reference voltage Vref. In addition, based on the comparison value, SAR logic 130 determines the MSB of the digital output, and determines that subsequent values of voltage Vcomp will be greater than the analog input value Vin.
Furthermore, in response to the comparison value indicating that the analog voltage Vin is less than the reference voltage Vref, SAR logic 130 determines that the digital word for CDAC 110 is to be all zeros during the time period T2, while the analog voltage Vin is sampled. As a result, digital words during time periods subsequent to time period T2, cause the voltage Vcomp to increase toward Vref because the digital words during the subsequent time periods are greater than all zeros.
During the time period T2, as a result of a digital input word from SAR logic 130 being all zeros, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, comparator 120 generates a comparison value indicating that the voltage Vcomp is less than the voltage Vref as a result of the voltage Vcomp being less than the voltage Vref, and SAR logic 130 determines that the next Vcomp is to be greater than the current Vcomp as a result of the voltage Vcomp being less than the voltage Vref.
In alternative embodiments, during time period T2, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, plus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all zeros plus 1 lsb. Also, in such embodiments, the operation of comparator 120 and SAR logic 130 may remain unchanged.
During the time period T3, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, plus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all zeros plus 1 lsb.
In addition, during time period T3, comparator 120 generates a comparison value indicating that the voltage Vcomp is less than the voltage Vref as a result of the voltage Vcomp being less than the voltage Vref, and SAR logic 130 determines that the next Vcomp is to be greater than the current Vcomp as a result of the voltage Vcomp being less than the voltage Vref.
During the time period T4, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, plus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all zeros plus 2 lsbs.
In addition, during time period T4, comparator 120 generates a comparison value indicating that the voltage Vcomp is less than the voltage Vref as a result of the voltage Vcomp being less than the voltage Vref, and SAR logic 130 determines that the next Vcomp is to be greater than the current Vcomp as a result of the voltage Vcomp being greater than the voltage Vref.
During the time period T5, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, plus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all zeros plus 3 lsbs.
In addition, during time period T5, comparator 120 generates a comparison value indicating that the voltage Vcomp is less than the voltage Vref as a result of the voltage Vcomp being less than the voltage Vref, and SAR logic 130 determines that the next Vcomp is to be greater than the current Vcomp as a result of the voltage Vcomp being less than the voltage Vref.
During the time period T6, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, plus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all zeros plus 4 lsbs.
In addition, during time period T6, comparator 120 generates a comparison value indicating that the voltage Vcomp is greater than the voltage Vref as a result of the voltage Vcomp being greater than the voltage Vref, and SAR logic 130 determines that the next Vcomp is to be less than the current Vcomp as a result of the voltage Vcomp being greater than the voltage Vref.
In some embodiments, because all the information for determining the digital output word is available after time period T6, the SAR logic 130 determines the digital output word according to principles and aspects discussed elsewhere herein and/or otherwise known to those of skill in the art.
In the exemplary embodiment of FIG. 4, during the time period T7, as a result of a next digital input word from SAR logic 130, CDAC 110 causes voltage Vcomp to be equal to or substantially equal to the previous voltage Vcomp, minus a voltage step, where the magnitude of the voltage step corresponds with the charge of the capacitor of CDAC 110 having value C. In such embodiments, the value of the next digital word may be all zeros plus 3 lsbs.
The digital input word from SAR logic 130 for CDAC 110 of time period T7 corresponds with the voltage difference between the reference voltage Vref and analog input voltage Vin.
As a result of the voltage Vcomp being greater than the voltage Vref during time period T6, the SAR logic 130 generates the digital output word corresponding to the analog input voltage Vin.
Because analog input voltage Vin was determined to be less than the reference voltage Vref during time period Ti, the MSB of the digital output word corresponds with that determination. In addition, because the digital input word from SAR logic 130 for CDAC 110 of time period T7 corresponds with the voltage difference between the reference voltage Vref and analog input voltage Vin, and the bits of the digital output word other than the MSB also correspond with the voltage difference between the reference voltage Vref and analog input voltage Vin, the digital input word from SAR logic 130 for CDAC 110 of time period T7 corresponds with the bits of the digital output word other than the MSB.
For example, if, in the example of FIG. 4, the maximum input voltage Vmax is 1 V, and the analog input voltage Vin is 0.26 V, a 4-bit digital word corresponding to the analog input voltage, may be 0100. The value of 0 for the MSB is determined during time period T1. In addition, because the digital input word from SAR logic 130 for CDAC 110 of time period T6 causes the voltage Vcomp to be equal to or substantially equal to the analog input voltage Vin, plus four voltage steps, where the magnitude of the voltage steps each correspond with the charge of the capacitor of CDAC 110 having value C, the other bits of the digital output word correspond with a voltage difference between the analog input voltage Vin and the reference voltage Vref, which corresponds digitally to 100. Accordingly, the digital output word is determined to be the expected 0100 because 1000−0100=0100, where 1000 represents the digitized value of the analog input voltage Vin plus four times the voltage corresponding with the charge of the capacitor of CDAC 110 having value C.
Once determined, the SAR ADC 100 represents the digital output word on the output Dout.
Though the present invention is disclosed by way of specific embodiments as described above, those embodiments are not intended to limit the present invention. Based on the methods and the technical aspects disclosed above, variations and changes may be made to the presented embodiments by those skilled in the art without departing from the spirit and the scope of the present invention.

Claims

What is claimed is:

1. A successive approximation register (SAR) analog to digital converter (ADC), comprising a DAC, a comparator, and an SAR logic circuit, wherein the DAC, the comparator, and the SAR logic circuit are in electrical communication with one another and are collectively configured to generate a digital output word based on an analog input voltage and on a reference voltage, wherein the digital output word represents the value of the analog input voltage with reference to a range of analog values bounded by a minimum analog input voltage and a maximum analog input voltage, and wherein the most significant bit (MSB) of the digital output word is determined based on a comparison of the analog input voltage and the reference voltage.

2. The SAR ADC of claim 1, wherein, during a first time period, the comparator is configured to receive the reference voltage and the analog input voltage and to generate a first comparison value based on a sign of the difference between the reference voltage and the analog input voltage.

3. The SAR ADC of claim 2, wherein the comparator is configured to receive the analog input voltage from the DAC.

4. The SAR ADC of claim 2, wherein the SAR logic is configured to receive the first comparison value and to generate the MSB of the digital output word based on the comparison value.

5. The SAR ADC of claim 2, wherein, during a second time period, the comparator is configured to receive the reference voltage and a second voltage and to generate a second comparison value based on a sign of the difference between the reference voltage and the second voltage.

6. The SAR ADC of claim 5, wherein the comparator is configured to receive the second voltage from the DAC, and wherein the DAC is configured to generate the second voltage based on the analog input voltage and the MSB.

7. The SAR ADC of claim 5, wherein the SAR logic is configured to receive the second comparison value and to generate a next bit of the digital output word based on the second comparison value.

8. The SAR ADC of claim 7, wherein the SAR logic is configured to generate a digital input word for the DAC based on the first and second comparison values, and the DAC is configured to generate a comparison voltage for the comparator based on the first and second comparison values.

9. The SAR ADC of claim 7, wherein the SAR logic is configured to determine the digital output word with a linear search.

10. The SAR ADC of claim 7, wherein the SAR logic is configured to determine the digital output word with a binary search.

11. A method of determining a digital output word having a value corresponding with an analog input value with a successive approximation register (SAR) analog to digital converter (ADC) comprising a DAC, a comparator, and an SAR logic circuit in electrical communication with one another, the method comprising:

with the SAR ADC:

receiving an analog input voltage;

receiving a reference voltage; and

generating a digital output word based on an analog input voltage and on the reference voltage, wherein the digital output word represents the value of the analog input voltage with reference to a range of analog values bounded by a minimum analog input voltage and a maximum analog input voltage, and wherein the most significant bit (MSB) of the digital output word is determined based on a comparison of the analog input voltage and the reference voltage.

12. The method claim 11, further comprising, during a first time period, with the comparator:

receiving receive the reference voltage;

receiving the analog input voltage; and

generating a first comparison value based on a sign of the difference between the reference voltage and the analog input voltage.

13. The method claim 12, further comprising, with the comparator, receiving the analog input voltage from the DAC.

14. The method claim 12, further comprising, with the SAR logic:

receiving the first comparison value; and

generating the MSB of the digital output word based on the comparison value.

15. The method claim 12, further comprising, during a second time period, with the comparator:

receiving receive the reference voltage;

receiving a second voltage; and

generating a second comparison value based on a sign of the difference between the reference voltage and the second voltage.

16. The method claim 15, further comprising:

with the comparator, receiving the second voltage from the DAC; and

with the DAC, generating the second voltage based on the analog input voltage and the MSB.

17. The method claim 15, further comprising:

with the SAR logic, receiving the second comparison value; and

with the SAR logic, generating a next bit of the digital output word based on the second comparison value.

18. The method claim 17, further comprising:

with the SAR logic, generating a digital input word for the DAC based on the first and second comparison values; and

with the DAC, generating a comparison voltage for the comparator based on the first and second comparison values.

19. The method claim 17, further comprising, with the SAR logic, determining the digital output word with a linear search.

20. The method claim 17, further comprising, with the SAR logic, determining the digital output word with a binary search.