US20190333782A1 - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
- Publication number
- US20190333782A1 US20190333782A1 US15/964,092 US201815964092A US2019333782A1 US 20190333782 A1 US20190333782 A1 US 20190333782A1 US 201815964092 A US201815964092 A US 201815964092A US 2019333782 A1 US2019333782 A1 US 2019333782A1
- Authority
- US
- United States
- Prior art keywords
- power device
- device die
- semiconductor package
- pattern
- back side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 163
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000000465 moulding Methods 0.000 claims abstract description 81
- 150000001875 compounds Chemical class 0.000 claims abstract description 53
- 230000017525 heat dissipation Effects 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 claims description 112
- 239000012790 adhesive layer Substances 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 64
- 230000001070 adhesive effect Effects 0.000 claims description 37
- 239000000853 adhesive Substances 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 33
- 238000000059 patterning Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 36
- UHNRLQRZRNKOKU-UHFFFAOYSA-N CCN(CC1=NC2=C(N1)C1=CC=C(C=C1N=C2N)C1=NNC=C1)C(C)=O Chemical compound CCN(CC1=NC2=C(N1)C1=CC=C(C=C1N=C2N)C1=NNC=C1)C(C)=O UHNRLQRZRNKOKU-UHFFFAOYSA-N 0.000 description 28
- 230000008569 process Effects 0.000 description 26
- 230000015572 biosynthetic process Effects 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000002093 peripheral effect Effects 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229920000800 acrylic rubber Polymers 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/2402—Laminated, e.g. MCM-L type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24101—Connecting bonding areas at the same height
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Definitions
- High-power device dies usually need effective heat dissipation paths.
- heat dissipation of the packaged device die(s) has become an important issue for packaging technology.
- the arrangement of the dies and the corresponding connecting elements has impacts on the reliability of the packaged products.
- FIG. 1 is an exemplary flow chart showing the process steps of a manufacturing method of semiconductor package according to some embodiments of the present disclosure.
- FIG. 2A through FIG. 2G are schematic cross-sectional views illustrating intermediate structures and package structures at various stages according to the manufacturing method of semiconductor package shown in FIG. 1 .
- FIG. 2C ′ is a schematic top view of the intermediate structure shown in FIG. 2C .
- FIG. 2C ′′ is a schematic top view illustrating an arrangement of semiconductor dies and an opening of the adhesive pattern according to some embodiments of the present disclosure.
- FIG. 3 is an exemplary flow chart showing the process steps of a manufacturing method of semiconductor package according to some embodiments of the present disclosure.
- FIG. 4A through FIG. 4G are schematic cross-sectional views illustrating intermediate structures and package structures at various stages according to the manufacturing method of semiconductor package shown in FIG. 3 .
- FIG. 5 is a schematic cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure.
- FIG. 6A through FIG. 6I are schematic cross-sectional views illustrating intermediate structures and package structures at various stages following a manufacturing method of semiconductor package according to some embodiments of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices.
- the testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like.
- the verification testing may be performed on intermediate structures as well as the final structure.
- the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
- FIG. 1 is an exemplary flow chart showing the process steps of a manufacturing method of a semiconductor package 10 according to some embodiments of the present disclosure.
- FIG. 2A through FIG. 2G are schematic cross-sectional views illustrating intermediate structures and package structures at various stages according to the manufacturing method of the semiconductor package 10 according to some embodiments of the present disclosure.
- step S 100 is performed, and an adhesive layer 102 is formed on a provided carrier substrate 100 .
- the carrier substrate 100 is a glass substrate.
- the adhesive layer 102 may include a de-bonding layer 104 and a die attach film 106 , which are sequentially formed on the carrier substrate 100 .
- the de-bonding layer 104 may be a light-to-heat conversion (LTHC) layer or a thermal release layer.
- the die attach film 106 is a photo-sensitive die attach film.
- a material of the die attach film 106 may include epoxy resin, phenol resin, acrylic rubber, silica filler, a combination thereof or the like.
- step S 102 is performed, and the adhesive layer 102 is patterned.
- the die attach film 106 of the adhesive layer 102 is patterned to form a die attach pattern 106 a having an opening AM therein.
- the die attach pattern 106 a and the de-bonding layer 104 are collectively referred as an adhesive pattern 102 a .
- the opening AM may be formed in a device region, such that the opening AM would not be cut off but still remain in the semiconductor package after the singulation process has been performed.
- the opening AM is located in a peripheral part of the device region, i.e., located beside the die-disposing central part of the device region but not located within the scribe line region, and spaced from the desired locations of the subsequently disposed die(s) with a distance.
- the region enclosed by a dash line in FIG. 2B shows an enlarged schematic top view of the adhesive pattern 102 a .
- the opening AM may be formed as a hollow cross or in a cross shape.
- a line width W of the cross-shaped opening AM may range from 10 ⁇ m to 100 ⁇ m. It is understood that the line width or the size of the opening may be tuned according to the material or thickness of the adhesive layer and/or the die attach film.
- the shape of the opening AM may include a cross shape, a circular shape, a polygonal shape or a combination thereof.
- the opening AM can be served as an alignment mark during subsequently performed steps. It is understood that the shape(s), the pattern or the size of the alignment mark may be modified or adjusted according to the alignment requirements of the manufacturing processes.
- the opening AM may be formed in a scribe line region (not shown) of the semiconductor package 10 , such that the opening AM would be removed after a singulation process has been performed.
- step S 104 is performed, and at least one high-power device die is placed on the adhesive pattern 102 a and aside the opening AM.
- a semiconductor die 108 A and a semiconductor die 108 B are placed on the adhesive pattern 102 a .
- the semiconductor die 108 A includes a high bandwidth memory (HBM) chip.
- the semiconductor die 108 B includes a high bandwidth memory (HBM) chip.
- the semiconductor die 108 B includes a system chip, a memory chip or a processor chip.
- the opening AM in the adhesive pattern 102 a functions as an alignment mark when positioning each of the semiconductor dies 108 A, 108 B.
- a die-to-die offset (the compensated distance relative to the predetermined desired location) regarding the deviated or shifted semiconductor die can be reduced to 5 ⁇ m or less.
- Each of the semiconductor dies 108 A, 108 B has a plurality of conductive pads 110 , a front side FS and a back side BS opposite to the front side FS.
- the back side BS faces the adhesive pattern 102 a , and the conductive pads 110 located at the front side FS are at least partially exposed from the front side FS of the semiconductor dies 108 A, 108 B.
- the conductive pads 110 may be protruded from the front side FS of the semiconductor dies 108 A, 108 B.
- FIG. 2C ′ is a schematic top view of the intermediate structure shown in FIG. 2C .
- FIG. 2C ′′ is a schematic top view illustrating an arrangement of semiconductor dies 108 A, 108 B and an opening AM of the adhesive pattern 102 a according to some embodiments of the present disclosure.
- the opening AM is located beside the semiconductor dies 108 A, 108 B, closer to the location of the semiconductor die 108 A but farther from the location of the semiconductor die 108 B.
- the opening AM may be located beside and between the semiconductor dies 108 A, 108 B and equally spaced from the semiconductor dies 108 A, 108 B.
- step S 106 may be performed, and a molding compound 112 is formed on the adhesive pattern 102 a , surrounding the semiconductor dies 108 A, 108 B and filling up the opening AM.
- a molding compound material layer (not shown) is formed to cover and over-mold the adhesive structure 102 a and the semiconductor dies 108 A, 108 B, and then thinned to expose the front side FS of the semiconductor dies 108 A, 108 B, so as to form the molding compound 112 .
- a material of the molding compound 112 includes an epoxy resin, polyimide, silica, a combination thereof or the like.
- a planarization process such as a chemical mechanical polishing (CMP) process or a grinding process, may be performed for thinning the molding compound material layer and hence forming the molding compound 112 .
- a front surface FS 1 of the molding compound 112 is coplanar with the front side FS of the semiconductor dies 108 A, 108 B.
- the molding compound 112 formed on the adhesive pattern 102 a fills up and extends into the opening AM.
- the molding compound 112 has a body portion 112 a located right above the adhesive pattern 102 a and an extended portion 112 b extended into the opening AM.
- the body portion 112 a spreads from the front surface FS 1 of the molding compound 112 to a front surface FS 2 of the adhesive pattern 102 a , and surrounds each of the semiconductor dies 108 A, 108 B.
- the semiconductor dies 108 A, 108 B are located in the body portion 112 a of the molding compound 112 .
- the extended portion 112 b is located aside semiconductor dies 108 A, 108 B and spreads from the front surface FS 1 of the molding compound 112 into the opening AM of the adhesive pattern 102 a .
- a lower part 112 bb of the extended portion 112 b fitted within the opening AM has a shape complementary to the shape of the opening AM.
- the part 112 bb of the extended portion 112 b has a shape complementary to the shape of the opening AM
- the part 112 bb has a shape of a cross shape, a circular shape, a polygonal shape or a combination thereof.
- the opening AM exposes the de-bonding layer 104
- the extended portion 112 b is in contact with the de-bonding layer 104 .
- the body portion 112 a has a first thickness Ta (measuring from the front surface FS 1 of the molding compound 112 to the front surface FS 2 of the adhesive pattern 102 a ), and the extended portion 112 b has a second thickness Tb (measuring from the front surface FS 1 of the molding compound 112 to a top surface of the de-bonding layer 104 ).
- the first thickness Ta is substantially equal to a thickness of the semiconductor dies 108 A, 108 B.
- the second thickness Tb is greater than the first thickness Ta.
- the first thickness Ta ranges from 100 ⁇ m to 600 ⁇ m.
- the second thickness Tb may be greater than the first thickness Ta by 3 ⁇ m to 20 ⁇ m.
- a ratio of the first thickness Ta with respect to the second thickness Tb ranges from 0.833 to 0.995.
- Step S 108 is performed, and as shown in FIG. 2D , a redistribution structure 114 is formed on the front side FS of the semiconductor dies 108 A, 108 B and on the molding compound 112 .
- the redistribution structure 114 may include a plurality of dielectric layers 116 and a plurality of redistribution layers 118 .
- the dielectric layer 116 and the redistribution layers 118 are alternately stacked on the front side FS of the high-power device dies 108 and the molding compound 112 .
- a material of the dielectric layer 116 may include silicon oxide, silicon nitride, polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like.
- a material of the redistribution layers 118 may include copper, nickel, titanium, a combination thereof or the like.
- the redistribution structure 114 further includes a plurality of conductive vias 120 .
- a material of the conductive vias 120 is identical to the material of the redistribution layers 118 . Each of the conductive vias 120 penetrates through one of the dielectric layers 116 .
- the conductive vias 120 are physically connected to the conductive pads 110 of the semiconductor dies 108 A, 108 B and electrically connect the semiconductor dies 108 A, 108 B with the redistribution layers 118 . Rest of the conductive vias 120 are located between vertically adjacent redistribution layers 118 for electrically connecting the redistribution layers 118 .
- the opening AM in the adhesive pattern 102 a also functions as an alignment mark during the formation of the redistribution structure 114 .
- the opening AM can be used as an alignment mark when performing a lithography process for forming the conductive vias 120 .
- a via-to-pad overlay shift (the deviation distance relative to the predetermined desired location) regarding the conductive pads 110 and the corresponding conductive vias 120 can be reduced to 3 ⁇ m or less.
- each of the electrical connectors 122 may include a conductive pillar 122 a and a cap layer 122 b located on the conductive pillar 112 a .
- the conductive pillar 122 a is disposed within the opening of the topmost dielectric layer 116 and connected to the topmost redistribution layer 118 .
- a material of the conductive pillar 122 a may include copper, aluminum, gold, nickel, palladium, the like, or a combination thereof and may be formed by sputtering, printing, electro plating, electroless plating, CVD or the like.
- a material of the cap layer 122 b may include nickel, tin, tin-lead, gold, copper, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.
- the electrical connectors 122 are solder balls and/or bumps, such as controlled collapse chip connection (C 4 ), electroless nickel immersion Gold (ENIG), electroless nickel electroless palladium immersion gold technique (ENEPIG) formed bumps or the like.
- the bumps may include a conductive material such as solder, copper, or gold.
- the electrical connectors may be formed by suitable methods such as evaporation, electroplating, printing, solder transfer, ball placement or the like. In addition, a reflow may be performed in order to shape the material into the desired bump shapes.
- step S 110 is performed, and the carrier substrate 100 and the de-bonding layer 104 are removed.
- the de-bonding layer 104 is a LTHC layer or a thermal release layer, and the carrier substrate 100 is detached from the die attach film 106 a as the de-bonding layer 104 loses its adhesive property when exposed to light or heat. That is, the carrier substrate 100 and the de-bonding layer 104 are detached and separated from the die attach film 106 a , and then removed.
- the entire structure may be flipped over and attached to a tape 124 before or after the carrier substrate 100 and the de-bonding layer 104 are removed.
- step S 112 is performed, and the die attach film 106 a of the adhesive pattern 102 a is removed.
- the die attached film 106 is removed by performing a stripping process, an etching process and/or a cleaning process.
- the adhesive pattern 102 a is removed and the back side BS of the semiconductor dies 108 A, 108 B and the molding compound 112 are exposed.
- the back sides BS of the semiconductor dies 108 A, 108 B are coplanar and levelled with a back surface BS 1 A of the body portion 112 a of the molding compound 112 .
- the part 112 bb of the extended portion 112 b is protruded from the back surface BS 1 A of the body portion 112 a of the molding compound 112 .
- a singulation process such as a sawing process or a cutting process, is performed on the current structure.
- the singulated structure may contain one or more of the semiconductor dies, and may be referred as a single-die package structure or a multi-die package structure.
- step S 114 is performed, and a heat dissipation module 126 is formed on the molding compound 112 and over the back sides BS of the semiconductor dies 108 A, 108 B.
- the formation of the heat dissipation module 126 may include sequentially forming a thermal interfacial layer 128 and providing a lid 130 on the thermal interfacial layer 128 .
- the thermal interfacial layer 128 is formed over the semiconductor dies 108 A, 108 B and the molding compound 112 .
- the thermal interfacial layer 128 is in direct contact with the back side BS of the semiconductor dies 108 A, 108 B and in direct contact with the molding compound 112 .
- the lid 130 is provided on the thermal interfacial layer 128 , such that the thermal interfacial layer 128 is located between the semiconductor dies 108 A, 108 B and the lid 130 .
- the lid 130 is in direct contact with the back surface BS 1 B of the protruded part 112 bb , and the thermal interfacial layer 128 fills between the lid 130 , the semiconductor dies 108 A, 108 B and the body portion 112 a and surrounds the protruded part 112 bb of the extended portion 112 b .
- the extended portion 112 b of the molding compound 112 penetrates through the thermal interfacial layer 128 , and is in contact with the lid 130 .
- the thermal interfacial layer 128 may further extend to cover a sidewall of the molding compound 112 .
- an interface between the body portion 112 b and the thermal interfacial layer 128 of the heat dissipation module 126 is substantially parallel to or coplanar with the back side BS of the semiconductor dies 108 A, 108 B.
- a material of the thermal interfacial layer 128 may include a composite material containing polymer with inorganic material or metal oxide.
- a material of the lid 130 may include steel, copper, a combination thereof or the like.
- the redistribution structure 114 and the electrical connectors 122 are further mounted to a package substrate 132 , thus completing the semiconductor package 10 .
- the electrical connectors 122 are bonded to the package substrate 132 through a solder flux by performing a reflow process.
- the redistribution structure 114 and the electrical connectors 122 are located in between the semiconductor dies 108 A, 108 B and the package substrate 132 .
- the package substrate 132 may include a printed circuit board (PCB) or an organic package substrate.
- the organic package substrate may include a flexible organic package substrate, a core organic package substrate or a core-less organic package substrate.
- an underfill 134 is formed to fill a space between the redistribution structure 114 , the electrical connectors 122 and the package substrate 132 .
- the underfill 134 surrounds each of the electrical connectors 122 .
- the underfill 134 may further extend to a sidewall of the redistribution structure 114 .
- a material of the underfill 134 may include epoxy resin, silica rubber, a combination thereof or the like.
- the semiconductor package 10 according to some embodiments has been fabricated. With reference to FIG. 2G , a structure of the semiconductor package 10 will be discussed.
- the semiconductor package 10 includes the high-power device die(s) 108 , the redistribution structure 114 , the heat dissipation module 126 and the molding compound 112 .
- the high-power device die(s) e.g., the semiconductor dies 108 A, 108 B
- the redistribution structure 114 is disposed at the front side FS of the high-power device die(s) (e.g., the semiconductor dies 108 A, 108 B).
- the heat dissipation module 126 is disposed between the redistribution structure 114 and the back side BS of the high-power device die(s) (e.g., the semiconductor dies 108 A, 108 B).
- the molding compound 112 is disposed between the redistribution structure 114 and the heat dissipation module 126 , and surrounds the high-power device die(s) (e.g., the semiconductor dies 108 A, 108 B).
- the molding compound 112 has the body portion 112 a and the extended portion 112 b .
- the interface between the body portion 112 a and the heat dissipation module 126 is substantially parallel to the back side BS of the high-power device die(s) (e.g., the semiconductor dies 108 A, 108 B).
- the second thickness Tb of the extended portion 112 b is greater than the first thickness Ta of the body portion 112 a.
- the high-power device die(s) (e.g., the semiconductor dies 108 A, 108 B) is located in the body portion 112 a of the molding compound 112 .
- the shape of a top view of the extended portion 112 b of the molding compound 112 includes a cross shape, a circular shape, a polygonal shape or a combination thereof.
- the heat dissipation module 126 includes the thermal interfacial layer 128 and the lid 130 . The thermal interfacial layer 128 is indirect contact with the back side BS of the high-power device die(s) (e.g., the semiconductor dies 108 A, 108 B).
- the thermal interfacial layer 128 is disposed between the high-power device die(s) (e.g., the semiconductor dies 108 A, 108 B) and the lid 130 .
- the extended portion 112 b penetrates through the thermal interfacial layer 128 , and is in contact with the lid 130 .
- the semiconductor package 10 further includes the package substrate 132 and the underfill 134 .
- the package substrate 132 is bonded to the redistribution structure 114 , such that the redistribution structure 114 is located in between the high-power device die(s) (e.g., the semiconductor dies 108 A, 108 B) and the package substrate 132 .
- the underfill 134 fills a space between the redistribution structure 114 and the package substrate 132 .
- FIG. 3 is an exemplary flow chart showing the process steps of a manufacturing method of a semiconductor package 20 according to some embodiments of the present disclosure.
- FIG. 4A through FIG. 4G are schematic cross-sectional views illustrating intermediate structures and package structures at various stages according to the manufacturing method of the semiconductor package 20 shown in FIG. 3 .
- the manufacturing method of the semiconductor package 20 is similar with the manufacturing method of the semiconductor package 10 , only the difference therebetween will be discussed, the same or similar parts will not be repeated again.
- identical or similar components are denoted with the same or similar reference numerals.
- a formation method of the alignment pattern AM 1 may include forming a dielectric layer or a reflective layer on the carrier substrate 100 .
- a material of the dielectric layer may include silicon oxide, silicon nitride, a combination thereof or the like.
- a material of the reflective layer may include aluminum, silver, a composite material of copper, a combination thereof or the like.
- the dielectric layer or the reflective layer is patterned, to form the alignment pattern AM 1 .
- the de-bonding layer 104 is formed on the carrier substrate 100 before the alignment pattern AM 1 is formed.
- the carrier substrate 100 has a device region 100 a and a peripheral region 100 b .
- the peripheral region 100 b surrounds the device region 100 a .
- the alignment pattern AM 1 is formed in the peripheral region 100 b .
- at least a portion of the peripheral region 100 b may not be overlapped with a scribe line region, such that the alignment pattern AM 1 would at least partly remain in the semiconductor package after the singulation process is performed.
- the peripheral region 100 b is located in the scribe line region of the semiconductor package 20 , such that the alignment pattern AM 1 would be removed after a singulation process is performed.
- a material of the alignment pattern AM 1 may include a dielectric material, such as silicon oxide, silicon nitride, a combination thereof or the like. Similar to the opening AM shown in FIG. 2B , from a top view, the shape of a hollow portion of the alignment pattern AM 1 may be a cross shape. In alternative embodiments, from the top view, the shape of the hollow portion of the alignment pattern AM 1 may include a cross shape, a circular shape, a polygonal shape or a combination thereof. As such, the alignment pattern AM 1 can function as an alignment mark during subsequently performed steps.
- step S 202 is performed, and an adhesive layer 206 is formed on the carrier substrate 100 .
- the adhesive layer 206 is formed in the device region 100 a and the peripheral region 100 b , and covers the alignment pattern AM 1 . Due to a step height of the alignment pattern AM 1 , a height H 1 of the adhesive layer 206 in the peripheral region 100 b may be greater than a height H 2 of the adhesive layer 206 in the device region 100 a .
- the adhesive layer 206 has a recess R in the device region 100 a , and the recess R is located aside the alignment pattern AM 1 .
- an adhesive material layer having a uniform thickness throughout the carrier substrate 100 may be initially formed, and then a portion of the adhesive material layer may be removed, in order to form the adhesive layer 206 with the recess R.
- the adhesive layer 206 may be a die attach film.
- step S 204 is performed, and the at least one high-power device die is placed on the adhesive layer 206 .
- the semiconductor dies 108 A, 108 B are placed on the adhesive layer 206 .
- the semiconductor dies 108 are placed in the recess R of the adhesive layer 206 .
- the alignment pattern AM 1 can be used as an alignment mark when positioning each of the semiconductor dies 108 A, 108 B. As such, during the placement of the semiconductor dies 108 A, 108 B, the location shift of the placed semiconductor die(s) is reduced and the positioning accuracy can be improved.
- a die-to-die offset (the compensated distance relative to the predetermined desired location) regarding the deviated or shifted semiconductor die can be reduced to 3 ⁇ m or less.
- the alignment pattern AM 1 may be located beside the semiconductor dies 108 A, 108 B, or the alignment pattern AM 1 may be located beside and between the semiconductor dies 108 A, 108 B and equally spaced from the semiconductor dies 108 A, 108 B.
- step S 206 is performed, and a molding compound 212 is formed on the adhesive layer 206 .
- the molding compound 212 is formed in the device region 100 a and the peripheral region 100 b .
- the molding compound 212 surrounds each of the high-power device dies 108 , and fills up the recess R.
- the molding compound 212 exposes the front side FS of the semiconductor dies 108 A, 108 B.
- a front surface FS 3 of the molding compound 212 is coplanar with the front side FS of the semiconductor dies 108 A, 108 B.
- the molding compound 212 fills the recess R formed in the adhesive layer 206 , the molding compound 112 formed on the adhesive layer 206 fills up and extends into the recess R. Accordingly, the molding compound 212 has a body portion 212 a located right above the alignment pattern AM 1 and an extended portion 212 b extended into the recess R. The body portion 212 a is located beside the recess R, and spreads between the front surface FS 3 of the molding compound 212 and the adhesive layer 206 .
- the extended portion 202 b filled in the recess R surrounds each of the semiconductor dies 108 A, 108 B, and spreads between the front surface FS 3 of the molding compound 212 and the adhesive layer 206 .
- the high-power device dies 108 are located in the extended portion 212 b .
- a lower part 212 bb of the extended portion 212 b fitted within the recess R has a shape complementary to the shape of the recess R.
- the body portion 212 a has a first thickness Ta 1
- the extended portion 212 b has a second thickness Tb 1 .
- the second thickness Tb 1 is substantially equal to a thickness of the high-power device die 108 .
- the second thickness Tb 1 is greater than the first thickness Ta 1 .
- the second thickness Tb 1 ranges from 100 ⁇ m to 600 ⁇ m.
- the first thickness Ta 1 is less than the second thickness Tb 1 by 5 ⁇ m to 20 ⁇ m.
- a ratio of the first thickness Ta 1 with respect to the second thickness Tb 1 ranges from 0.8 to 0.992.
- Step 208 is performed, and the redistribution structure 114 is formed on the front side FS of the semiconductor dies 108 A, 108 B and on the molding compound 212 .
- the redistribution structure 114 covers the high-power device dies 108 and the molding compound 212 .
- the alignment pattern AM 1 also functions as an alignment mark when performing a lithography process for forming the conductive vias 120 of the redistribution structure 114 . Thereby, a via-to-pad overlay shift (the deviation distance relative to the predetermined desired location) regarding the conductive pads 110 and the corresponding conductive vias 120 can be reduced to 3 ⁇ m or less.
- the electrical connectors 122 are formed on the topmost dielectric layer 116 of the redistribution structure 114 , and are connected to the topmost redistribution layer 118 .
- step S 210 is performed, and the carrier substrate 100 and the de-bonding layer 104 are removed. As such, the adhesive layer 206 and the alignment pattern AM 1 are exposed. In some embodiments, the entire structure may be flipped over and attached to a tape 124 before or after the carrier substrate 100 and the de-bonding layer 104 are removed.
- step S 212 is performed, and the alignment pattern AM 1 and the adhesive layer 206 are removed.
- the alignment pattern AM 1 and the adhesive layer 206 are completely removed.
- the back side BS of the semiconductor dies 108 A, 108 B and a back surface BS 2 of the molding compound 212 opposite to the redistribution structure 114 are exposed.
- the back side BS of the semiconductor dies 108 A, 108 B is coplanar and levelled with a back surface BS 2 B of the part 212 bb of the extended portion 212 b .
- the back surface BS 2 B of the part 212 bb is protruded from a back surface BS 2 A of the body portion 212 a .
- a singulation process such as a sawing process or a cutting process, is performed on the current structure.
- the singulated structure may contain one or more of the semiconductor dies, and may be referred as a single-die package structure or a multi-die package structure.
- step S 214 is performed, and a heat dissipation module 226 is formed on the molding compound 212 and over the back sides BS of the semiconductor dies 108 A, 108 B.
- the formation of the heat dissipation module 226 may include sequentially forming a thermal interfacial layer 228 and providing the lid 130 .
- the thermal interfacial layer 228 is formed over the semiconductor dies 108 A, 108 B and the molding compound 212 .
- the thermal interfacial layer 228 is in direct contact with the back side BS of the semiconductor dies 108 A, 108 B and in direct contact with the molding compound 212 .
- the lid 130 is provided on the thermal interfacial layer 228 , such that the thermal interfacial layer 228 is located in between the semiconductor dies 108 A, 108 B and the lid 130 .
- the thermal interfacial layer 228 is in direct contact with the back surface BS 2 A of the body portion 212 a and the back surface BS 2 B of the protruded part 212 bb of the extended portion 212 b .
- the thermal interfacial layer 228 fills between the lid 130 , the semiconductor dies 108 A, 108 B and the body portion 212 a , and surrounds the protruded part 212 bb of the extended portion 212 b .
- the heat dissipation module 226 has a rib structure RS.
- the rib structure RS may be a portion of the thermal interfacial layer 228 .
- the rib structure RS and the thermal interfacial layer 228 are constituted of the same material.
- an interface between the thermal interfacial layer 228 and the rib structure RS may be absent.
- the rib structure RS protrudes from the thermal interfacial layer 228 toward the body portion 212 a of the molding compound 212 .
- the rib structure RS is indirect contact with the body portion 212 a of the molding compound 212 .
- the rib structure RS surrounds the protruding part 212 bb of the extended portion 212 b of the molding compound 212 .
- the redistribution structure 114 and the electrical connectors 122 are further mounted to the package substrate 132 , thus completing the semiconductor package 20 .
- the redistribution structure 114 and the electrical connectors 122 are located in between the semiconductor dies 108 A, 108 B and the package substrate 132 .
- an underfill 134 is formed to fill a space between the redistribution structure 114 and the package substrate 132 .
- the underfill 134 surrounds each of the electrical connectors 122 .
- the underfill 134 may further extend to a sidewall of the redistribution structure 114 .
- the semiconductor package 20 has been fabricated.
- the alignment pattern AM 1 has been removed in step S 212 , such that the alignment pattern AM 1 is absent in the final structure of the semiconductor package 20 .
- a location shift of the placed semiconductor die(s), a die-to-die offset regarding deviated or shifted semiconductor dies and a via-to-pad overlay shift of the conductive pads 110 and the corresponding conductive vias 120 can be reduced by virtue of the alignment pattern AM 1 during the formation of the semiconductor package 20 .
- FIG. 5 is a schematic cross-sectional view illustrating a semiconductor package 30 according to some embodiments of the present disclosure.
- the semiconductor package 30 is similar to the semiconductor package 20 as shown in FIG. 4G .
- a difference between the semiconductor package 30 with respect to the semiconductor package 20 lies in that a rib structure RS 1 in the semiconductor package 30 is not a portion of the thermal interfacial layer 228 .
- the rib structure RS 1 is located between the thermal interfacial layer 228 and the body portion 212 a of the molding compound 212 .
- the rib structure RS 1 and the thermal interfacial layer 228 of the heat dissipation module 226 are constituted of different materials. Thereby, an interface may exist between the rib structure RS 1 and the heat dissipation module 226 .
- the adhesive layer 206 and the alignment pattern AM 1 are partially removed in step S 212 (as shown in FIG. 4F ).
- a planarization process such as a CMP process or a grinding process, may be performed to partially remove the adhesive layer 206 and the alignment pattern AM 1 , till a surface S of the remaining portion of the alignment pattern AM 1 and a remaining portion of the adhesive layer 206 is coplanar and levelled with the back side BS of the semiconductor dies 108 A, 108 B.
- a portion of the adhesive layer 206 and a portion of the alignment pattern AM 1 may remain, and form the rib structure RS 1 .
- the alignment pattern AM 1 is constituted of a reflective material
- the adhesive layer 206 is constituted of an adhesive material.
- the rib structure RS 1 includes the reflective material and the adhesive material.
- the alignment pattern AM 1 may be completely removed in step S 212 (as shown in FIG. 4F ), while the adhesive layer 206 is partially removed.
- the surface S of the remaining portion of the adhesive layer 205 is coplanar and levelled with the back side BS of the semiconductor dies 108 A, 108 B. Accordingly, the alignment pattern AM 1 may be absent in the rib structure RS 1 and the final structure of the semiconductor package 30 .
- FIG. 6A through FIG. 6I are schematic cross-sectional views illustrating intermediate structures and package structures at various stages following a manufacturing method of semiconductor package 40 according to some embodiments of the present disclosure.
- the manufacturing method of the semiconductor package 40 is similar with the manufacturing method of the semiconductor package 20 , only the difference therebetween will be discussed, the same or similar parts will not be repeated again.
- identical or similar components are denoted with the same or similar reference numerals.
- an alignment pattern AM 2 is formed on the provided carrier substrate 100 .
- a formation method of the alignment pattern AM 2 includes forming a mask pattern MK on the carrier substrate 100 .
- the de-bonding layer 104 is formed on the carrier substrate 100 before the mask pattern MK is formed.
- the mask pattern MK includes a first mask pattern MK 1 and a second mask pattern MK 2 . The first mask pattern MK 1 and the second mask pattern MK 2 are sequentially stacked on the carrier substrate 100 .
- the first mask pattern MK 1 and the second mask pattern MK 2 may be constituted of a photoresist material.
- a material of the first mask pattern MK 1 may be identical to or different from a material of the second mask pattern MK 2 .
- a first opening P 1 is formed in the first mask pattern MK 1
- a second opening P 2 is formed in the second mask pattern MK 2 .
- the first opening P 1 is communicated with the second opening P 2 .
- the first opening P 1 and the second opening P 2 expose the de-bonding layer 104 .
- a width W 1 of the first opening P 1 is greater than a width W 2 of the second opening P 2 .
- a reflective layer RL is formed on the carrier substrate 100 .
- a first portion of the reflective layer RL covers a top surface of the second mask pattern MK 2 and a sidewall of the second opening P 2 (i.e., the sidewall of the second mask pattern MK 2 ).
- a second portion of the reflective layer RL is disposed on a bottom surface of the first opening P 1 that is exposed by the second mask pattern MK 2 .
- the reflective layer RL may not be disposed at the sidewall of the first opening P 1 .
- a material of the reflective layer RL may include aluminum, silver, a composite material of copper, a combination thereof or the like.
- a shape of the top view of the alignment pattern AM 2 may include a combination of a cross shape and a rectangular ring.
- the shape of the top view of the alignment pattern AM 2 may include a cross shape, a circular shape, a polygonal shape or a combination thereof. As such, the alignment pattern AM 2 can be served as an alignment mark during subsequently performed steps.
- step S 202 is performed, and an adhesive layer 306 is formed on the carrier substrate 100 .
- the adhesive layer 306 covers the alignment pattern AM 2 and the de-bonding layer 104 .
- the adhesive layer 306 has a planar top surface.
- step S 204 is performed, and the semiconductor dies 108 A, 108 B are placed on the adhesive layer 306 .
- the semiconductor dies 108 A, 108 B are placed aside the alignment pattern AM 2 .
- the alignment pattern AM 2 functions as an alignment mark when positioning each of the semiconductor dies 108 .
- a die-to-die offset (the compensated distance relative to the predetermined desired location) regarding the deviated or shifted semiconductor die can be reduced to 3 ⁇ m or less.
- step S 206 is performed, and a molding compound 312 is formed on the adhesive layer 306 .
- the molding compound 312 surrounds each of the semiconductor dies 108 , and exposes the front side FS of the semiconductor dies 108 .
- a front surface FS 4 of the molding compound 312 is coplanar and levelled with the front side FS of the high-power device dies 108 .
- a thickness of the molding compound 312 is uniform across its cover area.
- Step 208 is performed, and the redistribution structure 114 is formed on the front side FS of the semiconductor dies 108 A, 108 B.
- the redistribution structure 114 covers the semiconductor dies 108 A, 108 B and the molding compound 212 .
- the alignment pattern AM 2 also functions as an alignment mark during the formation of the redistribution structure 114 .
- the alignment pattern AM 2 can be used as an alignment mark when performing a lithography process for forming the conductive vias 120 . With the alignment mark(s), less misalignment for placing the semiconductor dies 108 A, 108 B and better alignment for forming the conductive via 120 over the conductive pads 110 of the semiconductor dies 108 A, 108 B are achieved.
- a via-to-pad overlay shift (the deviation distance relative to the predetermined desired location) regarding the conductive pads 110 and the corresponding conductive vias 120 can be reduced to 3 ⁇ m or less.
- the electrical connectors 122 are formed on the redistribution structure 114 .
- step S 210 is performed, and the carrier substrate 100 and the de-bonding layer 104 are removed. As such, the adhesive layer 306 and the alignment pattern AM 2 are exposed. In some embodiments, the entire structure may be flipped over and attached to a tape 124 before or after the carrier substrate 100 and the de-bonding layer 104 are removed.
- step S 212 is performed, and the alignment pattern AM 2 and the adhesive layer 306 are completely removed.
- the back side BS of the semiconductor dies 108 A, 108 B and a back surface BS 3 of the molding compound 312 opposite to the redistribution structure 114 are exposed.
- a singulation process such as a sawing process or a cutting process, is performed on the current structure.
- the singulated structure may contain one or more of the semiconductor dies, and may be referred as a single-die package structure or a multi-die package structure.
- step S 214 is performed, and the heat dissipation module 326 is formed over the back side BS of the semiconductor dies 108 A, 108 B.
- the formation of the heat dissipation module 326 may include sequentially forming a thermal interfacial layer 328 and providing the lid 130 .
- the thermal interfacial layer 328 is in direct contact with the back side BS of the high-power device dies 108 , and located in between the high-power device dies 108 and the lid 130 .
- the thermal interfacial layer 328 covers the back surface BS 3 of the molding compound 312 .
- a thickness of the thermal interfacial layer 328 is uniform across the back surface BS 3 of the molding compound 312 and the back side BS of the high-power device dies 108 .
- the redistribution structure 114 and the electrical connectors 122 are further mounted to the package substrate 132 .
- the redistribution structure 114 is located in between the high-power device dies 108 and the package substrate 132 .
- an underfill 134 is formed to fill a space between the redistribution structure 114 and the package substrate 132 .
- the underfill 134 surrounds each of the electrical connectors 122 .
- the semiconductor package 40 has been fabricated.
- the alignment pattern AM 2 has been removed in step S 212 , such that the alignment pattern AM 2 is absent in the final structure of the semiconductor package 40 .
- a location shift of the placed semiconductor die(s), a die-to-die offset regarding deviated or shifted semiconductor dies and a via-to-pad overlay shift of the conductive pads 110 and the corresponding conductive vias 120 can be reduced by virtue of the alignment pattern AM 2 during the formation of the semiconductor package 40 .
- an alignment mark is formed in or under an adhesive layer before high-power device dies are placed on the adhesive layer.
- the location shift of the placed high-power device die(s) can be reduced.
- a die-to-die offset regarding the deviated or shift high-power device dies can be reduced.
- a via-to-pad overlay shift regarding the conductive pads in the high-power device die(s) and the corresponding conductive vias in the redistribution structure can be reduced by virtue of the alignment mark as well.
- a reliability of electronic devices containing the semiconductor package according to embodiments of the present disclosure can be improved.
- at least a portion of the adhesive layer is removed, such that a heat dissipation module can be directly disposed at the back side of the high-power device dies.
- a heat path can be directly formed at the back side of the high-power device dies. Therefore, an efficient heat dissipation can be attained in the semiconductor package according to embodiments of the present disclosure.
- a semiconductor package includes at least one high-power device die, a redistribution structure, a heat dissipation module and a molding compound.
- the at least one high-power device die has a front side and a back side opposite to the front side.
- the redistribution structure is disposed at the front side of the at least one high-power device die.
- the heat dissipation module is in direct contact with the back side of the at least one high-power device die.
- the molding compound is disposed between the redistribution structure and the heat dissipation module and surrounding the at least one high-power device die.
- the molding compound has a body portion and an extended portion. An interface between the body portion and the heat dissipation module is substantially parallel to the back side of the at least one high-power device die. A thickness of the extended portion is greater than a thickness of the body portion.
- a manufacturing method of a semiconductor package includes the following steps: forming an adhesive layer on a carrier substrate; patterning the adhesive layer to form an adhesive pattern having an opening therein; placing at least one high-power device die on the adhesive pattern and aside the opening using the opening as an alignment mark, wherein the at least one high-power device die has a front side and a back side, the back side faces the adhesive pattern, and the front side opposite to the back side; forming a molding compound on the adhesive pattern and filling the opening, wherein the molding compound surrounds the at least one high-power device die and exposes the front side of the at least one high-power device die, and the molding compound has an extended portion in the opening of the adhesive pattern; forming a redistribution structure on the front side of the at least one high-power device die; removing the carrier substrate and the adhesive pattern; and forming a heat dissipation module at the back side of the at least one high-power device die, wherein the heat
- a manufacturing method of a semiconductor package includes the following steps: forming an alignment pattern on a carrier substrate; forming an adhesive layer on the carrier substrate, wherein the adhesive layer covers the alignment pattern; placing at least one high-power device die on the adhesive layer by using the alignment pattern as an alignment mark, wherein the at least one high-power device die has a front side and a back side, the back side faces the adhesive layer, and the front side opposite to the back side; forming a molding compound on the adhesive layer, wherein the molding compound surrounds the at least one high-power device die and exposes the front side of the at least one high-power device die; forming a redistribution structure on the front side of the at least one high-power device die; removing the carrier substrate, at least a portion of the adhesive layer and at least of the alignment pattern; and forming a heat dissipation module at the back side of the at least one high-power device die, wherein the heat dissipation module
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
- High-power device dies usually need effective heat dissipation paths. As electronic products are continuously miniaturized, heat dissipation of the packaged device die(s) has become an important issue for packaging technology. In addition, for multi-die packages, the arrangement of the dies and the corresponding connecting elements has impacts on the reliability of the packaged products.
- The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
-
FIG. 1 is an exemplary flow chart showing the process steps of a manufacturing method of semiconductor package according to some embodiments of the present disclosure. -
FIG. 2A throughFIG. 2G are schematic cross-sectional views illustrating intermediate structures and package structures at various stages according to the manufacturing method of semiconductor package shown inFIG. 1 . -
FIG. 2C ′ is a schematic top view of the intermediate structure shown inFIG. 2C . -
FIG. 2C ″ is a schematic top view illustrating an arrangement of semiconductor dies and an opening of the adhesive pattern according to some embodiments of the present disclosure. -
FIG. 3 is an exemplary flow chart showing the process steps of a manufacturing method of semiconductor package according to some embodiments of the present disclosure. -
FIG. 4A throughFIG. 4G are schematic cross-sectional views illustrating intermediate structures and package structures at various stages according to the manufacturing method of semiconductor package shown inFIG. 3 . -
FIG. 5 is a schematic cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure. -
FIG. 6A throughFIG. 6I are schematic cross-sectional views illustrating intermediate structures and package structures at various stages following a manufacturing method of semiconductor package according to some embodiments of the present disclosure. - The following disclosure provides many different embodiments or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
-
FIG. 1 is an exemplary flow chart showing the process steps of a manufacturing method of asemiconductor package 10 according to some embodiments of the present disclosure.FIG. 2A throughFIG. 2G are schematic cross-sectional views illustrating intermediate structures and package structures at various stages according to the manufacturing method of thesemiconductor package 10 according to some embodiments of the present disclosure. - Referring to
FIG. 1 andFIG. 2A , step S100 is performed, and anadhesive layer 102 is formed on a providedcarrier substrate 100. In some embodiments, thecarrier substrate 100 is a glass substrate. Theadhesive layer 102 may include ade-bonding layer 104 and a die attach film 106, which are sequentially formed on thecarrier substrate 100. For example, thede-bonding layer 104 may be a light-to-heat conversion (LTHC) layer or a thermal release layer. In some embodiments, the die attach film 106 is a photo-sensitive die attach film. For instance, a material of the die attach film 106 may include epoxy resin, phenol resin, acrylic rubber, silica filler, a combination thereof or the like. - Referring to
FIG. 1 andFIG. 2B , step S102 is performed, and theadhesive layer 102 is patterned. In some embodiments, the die attach film 106 of theadhesive layer 102 is patterned to form a dieattach pattern 106 a having an opening AM therein. In these embodiments, thedie attach pattern 106 a and thede-bonding layer 104 are collectively referred as anadhesive pattern 102 a. In some embodiments, the opening AM may be formed in a device region, such that the opening AM would not be cut off but still remain in the semiconductor package after the singulation process has been performed. In certain embodiments, the opening AM is located in a peripheral part of the device region, i.e., located beside the die-disposing central part of the device region but not located within the scribe line region, and spaced from the desired locations of the subsequently disposed die(s) with a distance. The region enclosed by a dash line inFIG. 2B shows an enlarged schematic top view of theadhesive pattern 102 a. In some embodiments, from the top view, the opening AM may be formed as a hollow cross or in a cross shape. A line width W of the cross-shaped opening AM may range from 10 μm to 100 μm. It is understood that the line width or the size of the opening may be tuned according to the material or thickness of the adhesive layer and/or the die attach film. In alternative embodiments, from the top view, the shape of the opening AM may include a cross shape, a circular shape, a polygonal shape or a combination thereof. As such, the opening AM can be served as an alignment mark during subsequently performed steps. It is understood that the shape(s), the pattern or the size of the alignment mark may be modified or adjusted according to the alignment requirements of the manufacturing processes. - In alternative embodiments, the opening AM may be formed in a scribe line region (not shown) of the
semiconductor package 10, such that the opening AM would be removed after a singulation process has been performed. - Referring to
FIG. 1 andFIG. 2C , step S104 is performed, and at least one high-power device die is placed on theadhesive pattern 102 a and aside the opening AM. In some embodiments, asemiconductor die 108A and asemiconductor die 108B are placed on theadhesive pattern 102 a. In some embodiments, the semiconductor die 108A includes a high bandwidth memory (HBM) chip. In some embodiments, the semiconductor die 108B includes a high bandwidth memory (HBM) chip. In some embodiments, the semiconductor die 108B includes a system chip, a memory chip or a processor chip. The opening AM in theadhesive pattern 102 a functions as an alignment mark when positioning each of the semiconductor dies 108A, 108B. As such, during the placement of the semiconductor dies 108A, 108B, the location shift of the placed semiconductor die(s) is reduced and the positioning accuracy can be improved. In some embodiments, a die-to-die offset (the compensated distance relative to the predetermined desired location) regarding the deviated or shifted semiconductor die can be reduced to 5 μm or less. Each of the semiconductor dies 108A, 108B has a plurality ofconductive pads 110, a front side FS and a back side BS opposite to the front side FS. The back side BS faces theadhesive pattern 102 a, and theconductive pads 110 located at the front side FS are at least partially exposed from the front side FS of the semiconductor dies 108A, 108B. In some embodiments, theconductive pads 110 may be protruded from the front side FS of the semiconductor dies 108A, 108B. -
FIG. 2C ′ is a schematic top view of the intermediate structure shown inFIG. 2C .FIG. 2C ″ is a schematic top view illustrating an arrangement of semiconductor dies 108A, 108B and an opening AM of theadhesive pattern 102 a according to some embodiments of the present disclosure. - Referring to
FIG. 2C ′, in some embodiments, the opening AM is located beside the semiconductor dies 108A, 108B, closer to the location of the semiconductor die 108A but farther from the location of the semiconductor die 108B. Referring toFIG. 2C ″, in alternative embodiments, the opening AM may be located beside and between the semiconductor dies 108A, 108B and equally spaced from the semiconductor dies 108A, 108B. - Referring to
FIG. 1 andFIG. 2D , step S106 may be performed, and amolding compound 112 is formed on theadhesive pattern 102 a, surrounding the semiconductor dies 108A, 108B and filling up the opening AM. In some embodiments, a molding compound material layer (not shown) is formed to cover and over-mold theadhesive structure 102 a and the semiconductor dies 108A, 108B, and then thinned to expose the front side FS of the semiconductor dies 108A, 108B, so as to form themolding compound 112. A material of themolding compound 112 includes an epoxy resin, polyimide, silica, a combination thereof or the like. For instance, a planarization process, such as a chemical mechanical polishing (CMP) process or a grinding process, may be performed for thinning the molding compound material layer and hence forming themolding compound 112. In some embodiments, a front surface FS1 of themolding compound 112 is coplanar with the front side FS of the semiconductor dies 108A, 108B. As the molding compound material fills the opening AM formed in theadhesive pattern 102 a, themolding compound 112 formed on theadhesive pattern 102 a fills up and extends into the opening AM. Accordingly, themolding compound 112 has abody portion 112 a located right above theadhesive pattern 102 a and anextended portion 112 b extended into the opening AM. Thebody portion 112 a spreads from the front surface FS1 of themolding compound 112 to a front surface FS2 of theadhesive pattern 102 a, and surrounds each of the semiconductor dies 108A, 108B. In other words, the semiconductor dies 108A, 108B are located in thebody portion 112 a of themolding compound 112. In some embodiments, theextended portion 112 b is located aside semiconductor dies 108A, 108B and spreads from the front surface FS1 of themolding compound 112 into the opening AM of theadhesive pattern 102 a. In some embodiments, alower part 112 bb of theextended portion 112 b fitted within the opening AM has a shape complementary to the shape of the opening AM. As thelower part 112 bb of theextended portion 112 b has a shape complementary to the shape of the opening AM, thepart 112 bb has a shape of a cross shape, a circular shape, a polygonal shape or a combination thereof. In some embodiments, the opening AM exposes thede-bonding layer 104, and theextended portion 112 b is in contact with thede-bonding layer 104. Thebody portion 112 a has a first thickness Ta (measuring from the front surface FS1 of themolding compound 112 to the front surface FS2 of theadhesive pattern 102 a), and theextended portion 112 b has a second thickness Tb (measuring from the front surface FS1 of themolding compound 112 to a top surface of the de-bonding layer 104). The first thickness Ta is substantially equal to a thickness of the semiconductor dies 108A, 108B. The second thickness Tb is greater than the first thickness Ta. For instance, the first thickness Ta ranges from 100 μm to 600 μm. The second thickness Tb may be greater than the first thickness Ta by 3 μm to 20 μm. In some embodiments, a ratio of the first thickness Ta with respect to the second thickness Tb ranges from 0.833 to 0.995. - Step S108 is performed, and as shown in
FIG. 2D , aredistribution structure 114 is formed on the front side FS of the semiconductor dies 108A, 108B and on themolding compound 112. Theredistribution structure 114 may include a plurality ofdielectric layers 116 and a plurality of redistribution layers 118. Thedielectric layer 116 and the redistribution layers 118 are alternately stacked on the front side FS of the high-power device dies 108 and themolding compound 112. In some embodiments, a material of thedielectric layer 116 may include silicon oxide, silicon nitride, polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. A material of the redistribution layers 118 may include copper, nickel, titanium, a combination thereof or the like. Theredistribution structure 114 further includes a plurality ofconductive vias 120. In some embodiments, a material of theconductive vias 120 is identical to the material of the redistribution layers 118. Each of theconductive vias 120 penetrates through one of the dielectric layers 116. Some of theconductive vias 120 are physically connected to theconductive pads 110 of the semiconductor dies 108A, 108B and electrically connect the semiconductor dies 108A, 108B with the redistribution layers 118. Rest of theconductive vias 120 are located between vertically adjacent redistribution layers 118 for electrically connecting the redistribution layers 118. In some embodiments, the opening AM in theadhesive pattern 102 a also functions as an alignment mark during the formation of theredistribution structure 114. For example, the opening AM can be used as an alignment mark when performing a lithography process for forming theconductive vias 120. With the alignment mark(s), less misalignment for placing the semiconductor dies 108A, 108B and better alignment for forming the conductive via 120 over theconductive pads 110 of the semiconductor dies 108A, 108B are achieved. Thereby, a via-to-pad overlay shift (the deviation distance relative to the predetermined desired location) regarding theconductive pads 110 and the correspondingconductive vias 120 can be reduced to 3 μm or less. - In addition, a plurality of
electrical connectors 122 are formed on theredistribution structure 114. Theelectrical connectors 122 are disposed on the topmostdielectric layer 116 and are connected to thetopmost redistribution layer 118, functioning as the electrical terminals for further electrical connection. In some embodiments, each of theelectrical connectors 122 may include aconductive pillar 122 a and acap layer 122 b located on theconductive pillar 112 a. Theconductive pillar 122 a is disposed within the opening of the topmostdielectric layer 116 and connected to thetopmost redistribution layer 118. In some embodiments, a material of theconductive pillar 122 a may include copper, aluminum, gold, nickel, palladium, the like, or a combination thereof and may be formed by sputtering, printing, electro plating, electroless plating, CVD or the like. A material of thecap layer 122 b may include nickel, tin, tin-lead, gold, copper, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process. In alternative embodiments, theelectrical connectors 122 are solder balls and/or bumps, such as controlled collapse chip connection (C4), electroless nickel immersion Gold (ENIG), electroless nickel electroless palladium immersion gold technique (ENEPIG) formed bumps or the like. In these embodiments, the bumps may include a conductive material such as solder, copper, or gold. The electrical connectors may be formed by suitable methods such as evaporation, electroplating, printing, solder transfer, ball placement or the like. In addition, a reflow may be performed in order to shape the material into the desired bump shapes. - Referring to
FIG. 1 andFIG. 2E , step S110 is performed, and thecarrier substrate 100 and thede-bonding layer 104 are removed. In some embodiments, thede-bonding layer 104 is a LTHC layer or a thermal release layer, and thecarrier substrate 100 is detached from the die attachfilm 106 a as thede-bonding layer 104 loses its adhesive property when exposed to light or heat. That is, thecarrier substrate 100 and thede-bonding layer 104 are detached and separated from the die attachfilm 106 a, and then removed. In some embodiments, the entire structure may be flipped over and attached to atape 124 before or after thecarrier substrate 100 and thede-bonding layer 104 are removed. - Referring to
FIG. 1 andFIG. 2F , step S112 is performed, and the die attachfilm 106 a of theadhesive pattern 102 a is removed. In some embodiments, the die attached film 106 is removed by performing a stripping process, an etching process and/or a cleaning process. After removing the die attachfilm 106 a, theadhesive pattern 102 a is removed and the back side BS of the semiconductor dies 108A, 108B and themolding compound 112 are exposed. In some embodiments, the back sides BS of the semiconductor dies 108A, 108B are coplanar and levelled with a back surface BS1A of thebody portion 112 a of themolding compound 112. In some embodiments, thepart 112 bb of theextended portion 112 b is protruded from the back surface BS1A of thebody portion 112 a of themolding compound 112. In some embodiments, a singulation process, such as a sawing process or a cutting process, is performed on the current structure. The singulated structure may contain one or more of the semiconductor dies, and may be referred as a single-die package structure or a multi-die package structure. - Referring to
FIG. 1 andFIG. 2G , step S114 is performed, and aheat dissipation module 126 is formed on themolding compound 112 and over the back sides BS of the semiconductor dies 108A, 108B. In some embodiments, the formation of theheat dissipation module 126 may include sequentially forming a thermalinterfacial layer 128 and providing alid 130 on the thermalinterfacial layer 128. The thermalinterfacial layer 128 is formed over the semiconductor dies 108A, 108B and themolding compound 112. In some embodiments, the thermalinterfacial layer 128 is in direct contact with the back side BS of the semiconductor dies 108A, 108B and in direct contact with themolding compound 112. Thelid 130 is provided on the thermalinterfacial layer 128, such that the thermalinterfacial layer 128 is located between the semiconductor dies 108A, 108B and thelid 130. In some embodiments, thelid 130 is in direct contact with the back surface BS1B of theprotruded part 112 bb, and the thermalinterfacial layer 128 fills between thelid 130, the semiconductor dies 108A, 108B and thebody portion 112 a and surrounds theprotruded part 112 bb of theextended portion 112 b. In another aspect, theextended portion 112 b of themolding compound 112 penetrates through the thermalinterfacial layer 128, and is in contact with thelid 130. In addition, in certain embodiments, the thermalinterfacial layer 128 may further extend to cover a sidewall of themolding compound 112. In some embodiments, an interface between thebody portion 112 b and the thermalinterfacial layer 128 of theheat dissipation module 126 is substantially parallel to or coplanar with the back side BS of the semiconductor dies 108A, 108B. In some embodiments, a material of the thermalinterfacial layer 128 may include a composite material containing polymer with inorganic material or metal oxide. A material of thelid 130 may include steel, copper, a combination thereof or the like. - In some embodiments, after the formation of the
heat dissipation module 126 and detaching thetape 124, theredistribution structure 114 and theelectrical connectors 122 are further mounted to apackage substrate 132, thus completing thesemiconductor package 10. In some embodiments, theelectrical connectors 122 are bonded to thepackage substrate 132 through a solder flux by performing a reflow process. As such, theredistribution structure 114 and theelectrical connectors 122 are located in between the semiconductor dies 108A, 108B and thepackage substrate 132. In some embodiments, thepackage substrate 132 may include a printed circuit board (PCB) or an organic package substrate. For example, the organic package substrate may include a flexible organic package substrate, a core organic package substrate or a core-less organic package substrate. In some embodiments, anunderfill 134 is formed to fill a space between theredistribution structure 114, theelectrical connectors 122 and thepackage substrate 132. In some embodiments, theunderfill 134 surrounds each of theelectrical connectors 122. In addition, theunderfill 134 may further extend to a sidewall of theredistribution structure 114. For instance, a material of theunderfill 134 may include epoxy resin, silica rubber, a combination thereof or the like. - So far, the
semiconductor package 10 according to some embodiments has been fabricated. With reference toFIG. 2G , a structure of thesemiconductor package 10 will be discussed. - According to some embodiments, the
semiconductor package 10 includes the high-power device die(s) 108, theredistribution structure 114, theheat dissipation module 126 and themolding compound 112. The high-power device die(s) (e.g., the semiconductor dies 108A, 108B) has the front side FS and the back side BS opposite to the front side FS. Theredistribution structure 114 is disposed at the front side FS of the high-power device die(s) (e.g., the semiconductor dies 108A, 108B). Theheat dissipation module 126 is disposed between theredistribution structure 114 and the back side BS of the high-power device die(s) (e.g., the semiconductor dies 108A, 108B). Themolding compound 112 is disposed between theredistribution structure 114 and theheat dissipation module 126, and surrounds the high-power device die(s) (e.g., the semiconductor dies 108A, 108B). Themolding compound 112 has thebody portion 112 a and theextended portion 112 b. The interface between thebody portion 112 a and theheat dissipation module 126 is substantially parallel to the back side BS of the high-power device die(s) (e.g., the semiconductor dies 108A, 108B). The second thickness Tb of theextended portion 112 b is greater than the first thickness Ta of thebody portion 112 a. - In some embodiments, the high-power device die(s) (e.g., the semiconductor dies 108A, 108B) is located in the
body portion 112 a of themolding compound 112. In some embodiments, the shape of a top view of theextended portion 112 b of themolding compound 112 includes a cross shape, a circular shape, a polygonal shape or a combination thereof. In some embodiments, theheat dissipation module 126 includes the thermalinterfacial layer 128 and thelid 130. The thermalinterfacial layer 128 is indirect contact with the back side BS of the high-power device die(s) (e.g., the semiconductor dies 108A, 108B). The thermalinterfacial layer 128 is disposed between the high-power device die(s) (e.g., the semiconductor dies 108A, 108B) and thelid 130. In some embodiments, theextended portion 112 b penetrates through the thermalinterfacial layer 128, and is in contact with thelid 130. In some embodiments, thesemiconductor package 10 further includes thepackage substrate 132 and theunderfill 134. Thepackage substrate 132 is bonded to theredistribution structure 114, such that theredistribution structure 114 is located in between the high-power device die(s) (e.g., the semiconductor dies 108A, 108B) and thepackage substrate 132. Theunderfill 134 fills a space between theredistribution structure 114 and thepackage substrate 132. -
FIG. 3 is an exemplary flow chart showing the process steps of a manufacturing method of asemiconductor package 20 according to some embodiments of the present disclosure.FIG. 4A throughFIG. 4G are schematic cross-sectional views illustrating intermediate structures and package structures at various stages according to the manufacturing method of thesemiconductor package 20 shown inFIG. 3 . The manufacturing method of thesemiconductor package 20 is similar with the manufacturing method of thesemiconductor package 10, only the difference therebetween will be discussed, the same or similar parts will not be repeated again. In addition, identical or similar components are denoted with the same or similar reference numerals. - Referring to
FIG. 3 andFIG. 4A , step S200 is performed, and an alignment pattern AM1 is formed on the providedcarrier substrate 100. In some embodiments, a formation method of the alignment pattern AM1 may include forming a dielectric layer or a reflective layer on thecarrier substrate 100. For instance, a material of the dielectric layer may include silicon oxide, silicon nitride, a combination thereof or the like. A material of the reflective layer may include aluminum, silver, a composite material of copper, a combination thereof or the like. Afterwards, the dielectric layer or the reflective layer is patterned, to form the alignment pattern AM1. In some embodiments, thede-bonding layer 104 is formed on thecarrier substrate 100 before the alignment pattern AM1 is formed. Thecarrier substrate 100 has adevice region 100 a and aperipheral region 100 b. In some embodiments, theperipheral region 100 b surrounds thedevice region 100 a. The alignment pattern AM1 is formed in theperipheral region 100 b. In some embodiments, at least a portion of theperipheral region 100 b may not be overlapped with a scribe line region, such that the alignment pattern AM1 would at least partly remain in the semiconductor package after the singulation process is performed. In alternative embodiments, theperipheral region 100 b is located in the scribe line region of thesemiconductor package 20, such that the alignment pattern AM1 would be removed after a singulation process is performed. In some embodiments, a material of the alignment pattern AM1 may include a dielectric material, such as silicon oxide, silicon nitride, a combination thereof or the like. Similar to the opening AM shown inFIG. 2B , from a top view, the shape of a hollow portion of the alignment pattern AM1 may be a cross shape. In alternative embodiments, from the top view, the shape of the hollow portion of the alignment pattern AM1 may include a cross shape, a circular shape, a polygonal shape or a combination thereof. As such, the alignment pattern AM1 can function as an alignment mark during subsequently performed steps. - Referring to
FIG. 3 andFIG. 4B , step S202 is performed, and anadhesive layer 206 is formed on thecarrier substrate 100. Theadhesive layer 206 is formed in thedevice region 100 a and theperipheral region 100 b, and covers the alignment pattern AM1. Due to a step height of the alignment pattern AM1, a height H1 of theadhesive layer 206 in theperipheral region 100 b may be greater than a height H2 of theadhesive layer 206 in thedevice region 100 a. In another aspect, theadhesive layer 206 has a recess R in thedevice region 100 a, and the recess R is located aside the alignment pattern AM1. In alternative embodiments, an adhesive material layer having a uniform thickness throughout thecarrier substrate 100 may be initially formed, and then a portion of the adhesive material layer may be removed, in order to form theadhesive layer 206 with the recess R. In some embodiments, theadhesive layer 206 may be a die attach film. - Referring to
FIG. 3 andFIG. 4C , step S204 is performed, and the at least one high-power device die is placed on theadhesive layer 206. In some embodiments, the semiconductor dies 108A, 108B are placed on theadhesive layer 206. In some embodiments, the semiconductor dies 108 are placed in the recess R of theadhesive layer 206. The alignment pattern AM1 can be used as an alignment mark when positioning each of the semiconductor dies 108A, 108B. As such, during the placement of the semiconductor dies 108A, 108B, the location shift of the placed semiconductor die(s) is reduced and the positioning accuracy can be improved. In some embodiments, a die-to-die offset (the compensated distance relative to the predetermined desired location) regarding the deviated or shifted semiconductor die can be reduced to 3 μm or less. Similar to the opening AM shown inFIG. 4C ′ andFIG. 4C ″, the alignment pattern AM1 may be located beside the semiconductor dies 108A, 108B, or the alignment pattern AM1 may be located beside and between the semiconductor dies 108A, 108B and equally spaced from the semiconductor dies 108A, 108B. - Referring to
FIG. 3 andFIG. 4D , step S206 is performed, and amolding compound 212 is formed on theadhesive layer 206. Themolding compound 212 is formed in thedevice region 100 a and theperipheral region 100 b. Themolding compound 212 surrounds each of the high-power device dies 108, and fills up the recess R. In addition, themolding compound 212 exposes the front side FS of the semiconductor dies 108A, 108B. In some embodiments, a front surface FS3 of themolding compound 212 is coplanar with the front side FS of the semiconductor dies 108A, 108B. In some embodiments, as themolding compound 212 fills the recess R formed in theadhesive layer 206, themolding compound 112 formed on theadhesive layer 206 fills up and extends into the recess R. Accordingly, themolding compound 212 has abody portion 212 a located right above the alignment pattern AM1 and anextended portion 212 b extended into the recess R. Thebody portion 212 a is located beside the recess R, and spreads between the front surface FS3 of themolding compound 212 and theadhesive layer 206. The extended portion 202 b filled in the recess R surrounds each of the semiconductor dies 108A, 108B, and spreads between the front surface FS3 of themolding compound 212 and theadhesive layer 206. In other words, the high-power device dies 108 are located in theextended portion 212 b. In some embodiments, alower part 212 bb of theextended portion 212 b fitted within the recess R has a shape complementary to the shape of the recess R. Thebody portion 212 a has a first thickness Ta1, and theextended portion 212 b has a second thickness Tb1. The second thickness Tb1 is substantially equal to a thickness of the high-power device die 108. The second thickness Tb1 is greater than the first thickness Ta1. For instance, the second thickness Tb1 ranges from 100 μm to 600 μm. The first thickness Ta1 is less than the second thickness Tb1 by 5 μm to 20 μm. In some embodiments, a ratio of the first thickness Ta1 with respect to the second thickness Tb1 ranges from 0.8 to 0.992. - Step 208 is performed, and the
redistribution structure 114 is formed on the front side FS of the semiconductor dies 108A, 108B and on themolding compound 212. Theredistribution structure 114 covers the high-power device dies 108 and themolding compound 212. In some embodiments, the alignment pattern AM1 also functions as an alignment mark when performing a lithography process for forming theconductive vias 120 of theredistribution structure 114. Thereby, a via-to-pad overlay shift (the deviation distance relative to the predetermined desired location) regarding theconductive pads 110 and the correspondingconductive vias 120 can be reduced to 3 μm or less. Furthermore, theelectrical connectors 122 are formed on the topmostdielectric layer 116 of theredistribution structure 114, and are connected to thetopmost redistribution layer 118. - Referring to
FIG. 3 andFIG. 4E , step S210 is performed, and thecarrier substrate 100 and thede-bonding layer 104 are removed. As such, theadhesive layer 206 and the alignment pattern AM1 are exposed. In some embodiments, the entire structure may be flipped over and attached to atape 124 before or after thecarrier substrate 100 and thede-bonding layer 104 are removed. - Referring to
FIG. 3 andFIG. 4F , step S212 is performed, and the alignment pattern AM1 and theadhesive layer 206 are removed. In some embodiments, the alignment pattern AM1 and theadhesive layer 206 are completely removed. As such, the back side BS of the semiconductor dies 108A, 108B and a back surface BS2 of themolding compound 212 opposite to theredistribution structure 114 are exposed. In some embodiments, the back side BS of the semiconductor dies 108A, 108B is coplanar and levelled with a back surface BS2B of thepart 212 bb of theextended portion 212 b. In some embodiments, the back surface BS2B of thepart 212 bb is protruded from a back surface BS2A of thebody portion 212 a. In some embodiments, a singulation process, such as a sawing process or a cutting process, is performed on the current structure. The singulated structure may contain one or more of the semiconductor dies, and may be referred as a single-die package structure or a multi-die package structure. - Referring to
FIG. 3 andFIG. 4G , step S214 is performed, and aheat dissipation module 226 is formed on themolding compound 212 and over the back sides BS of the semiconductor dies 108A, 108B. In some embodiments, the formation of theheat dissipation module 226 may include sequentially forming a thermalinterfacial layer 228 and providing thelid 130. The thermalinterfacial layer 228 is formed over the semiconductor dies 108A, 108B and themolding compound 212. In some embodiments, the thermalinterfacial layer 228 is in direct contact with the back side BS of the semiconductor dies 108A, 108B and in direct contact with themolding compound 212. Thelid 130 is provided on the thermalinterfacial layer 228, such that the thermalinterfacial layer 228 is located in between the semiconductor dies 108A, 108B and thelid 130. In some embodiments, the thermalinterfacial layer 228 is in direct contact with the back surface BS2A of thebody portion 212 a and the back surface BS2B of theprotruded part 212 bb of theextended portion 212 b. The thermalinterfacial layer 228 fills between thelid 130, the semiconductor dies 108A, 108B and thebody portion 212 a, and surrounds theprotruded part 212 bb of theextended portion 212 b. In some embodiments, theheat dissipation module 226 has a rib structure RS. In some embodiments, the rib structure RS may be a portion of the thermalinterfacial layer 228. In other words, the rib structure RS and the thermalinterfacial layer 228 are constituted of the same material. As such, an interface between the thermalinterfacial layer 228 and the rib structure RS may be absent. The rib structure RS protrudes from the thermalinterfacial layer 228 toward thebody portion 212 a of themolding compound 212. In some embodiments, the rib structure RS is indirect contact with thebody portion 212 a of themolding compound 212. In addition, the rib structure RS surrounds theprotruding part 212 bb of theextended portion 212 b of themolding compound 212. - In some embodiments, after the formation of the
heat dissipation module 226 and detaching thetape 124, theredistribution structure 114 and theelectrical connectors 122 are further mounted to thepackage substrate 132, thus completing thesemiconductor package 20. As such, theredistribution structure 114 and theelectrical connectors 122 are located in between the semiconductor dies 108A, 108B and thepackage substrate 132. In some embodiments, anunderfill 134 is formed to fill a space between theredistribution structure 114 and thepackage substrate 132. In some embodiments, theunderfill 134 surrounds each of theelectrical connectors 122. In addition, theunderfill 134 may further extend to a sidewall of theredistribution structure 114. - So far, the
semiconductor package 20 according to some embodiments has been fabricated. The alignment pattern AM1 has been removed in step S212, such that the alignment pattern AM1 is absent in the final structure of thesemiconductor package 20. Even though, a location shift of the placed semiconductor die(s), a die-to-die offset regarding deviated or shifted semiconductor dies and a via-to-pad overlay shift of theconductive pads 110 and the correspondingconductive vias 120 can be reduced by virtue of the alignment pattern AM1 during the formation of thesemiconductor package 20. -
FIG. 5 is a schematic cross-sectional view illustrating asemiconductor package 30 according to some embodiments of the present disclosure. - Referring to
FIG. 4G andFIG. 5 , thesemiconductor package 30 is similar to thesemiconductor package 20 as shown inFIG. 4G . A difference between thesemiconductor package 30 with respect to thesemiconductor package 20 lies in that a rib structure RS1 in thesemiconductor package 30 is not a portion of the thermalinterfacial layer 228. The rib structure RS1 is located between the thermalinterfacial layer 228 and thebody portion 212 a of themolding compound 212. In some embodiments, the rib structure RS1 and the thermalinterfacial layer 228 of theheat dissipation module 226 are constituted of different materials. Thereby, an interface may exist between the rib structure RS1 and theheat dissipation module 226. In these embodiments, theadhesive layer 206 and the alignment pattern AM1 are partially removed in step S212 (as shown inFIG. 4F ). In some embodiments, a planarization process, such as a CMP process or a grinding process, may be performed to partially remove theadhesive layer 206 and the alignment pattern AM1, till a surface S of the remaining portion of the alignment pattern AM1 and a remaining portion of theadhesive layer 206 is coplanar and levelled with the back side BS of the semiconductor dies 108A, 108B. As such, a portion of theadhesive layer 206 and a portion of the alignment pattern AM1 may remain, and form the rib structure RS1. In these embodiments, the alignment pattern AM1 is constituted of a reflective material, and theadhesive layer 206 is constituted of an adhesive material. As such, the rib structure RS1 includes the reflective material and the adhesive material. - In alternative embodiments, the alignment pattern AM1 may be completely removed in step S212 (as shown in
FIG. 4F ), while theadhesive layer 206 is partially removed. The surface S of the remaining portion of the adhesive layer 205 is coplanar and levelled with the back side BS of the semiconductor dies 108A, 108B. Accordingly, the alignment pattern AM1 may be absent in the rib structure RS1 and the final structure of thesemiconductor package 30. -
FIG. 6A throughFIG. 6I are schematic cross-sectional views illustrating intermediate structures and package structures at various stages following a manufacturing method ofsemiconductor package 40 according to some embodiments of the present disclosure. The manufacturing method of thesemiconductor package 40 is similar with the manufacturing method of thesemiconductor package 20, only the difference therebetween will be discussed, the same or similar parts will not be repeated again. In addition, identical or similar components are denoted with the same or similar reference numerals. - Referring to
FIG. 3 andFIG. 6A throughFIG. 6C , in step S200, an alignment pattern AM2 is formed on the providedcarrier substrate 100. As shown inFIG. 6A , a formation method of the alignment pattern AM2 includes forming a mask pattern MK on thecarrier substrate 100. In some embodiments, thede-bonding layer 104 is formed on thecarrier substrate 100 before the mask pattern MK is formed. In some embodiments, the mask pattern MK includes a first mask pattern MK1 and a second mask pattern MK2. The first mask pattern MK1 and the second mask pattern MK2 are sequentially stacked on thecarrier substrate 100. In some embodiments, the first mask pattern MK1 and the second mask pattern MK2 may be constituted of a photoresist material. A material of the first mask pattern MK1 may be identical to or different from a material of the second mask pattern MK2. A first opening P1 is formed in the first mask pattern MK1, and a second opening P2 is formed in the second mask pattern MK2. The first opening P1 is communicated with the second opening P2. The first opening P1 and the second opening P2 expose thede-bonding layer 104. A width W1 of the first opening P1 is greater than a width W2 of the second opening P2. - Referring to
FIG. 6B , a reflective layer RL is formed on thecarrier substrate 100. A first portion of the reflective layer RL covers a top surface of the second mask pattern MK2 and a sidewall of the second opening P2 (i.e., the sidewall of the second mask pattern MK2). A second portion of the reflective layer RL is disposed on a bottom surface of the first opening P1 that is exposed by the second mask pattern MK2. As the second opening P2 is narrower than the first opening P1 located under the second opening P2, a sidewall of the first opening P1 is covered by the second mask pattern MK2. Thereby, the reflective layer RL may not be disposed at the sidewall of the first opening P1. In addition, the second portion of the reflective layer RL on the bottom surface of the first opening P1 may separate from the first portion of the reflective layer RL formed on the top surface and the sidewall of the second mask pattern MK2. In some embodiments, a material of the reflective layer RL may include aluminum, silver, a composite material of copper, a combination thereof or the like. - Referring to
FIG. 6C , the mask pattern MK and the first portion of the reflective layer RL are removed. A remaining portion of the reflective layer RL (i.e., the second portion of the reflective layer RL) forms the alignment pattern AM2. The region enclosed by a dash line inFIG. 6C shows a schematic top view of the alignment pattern AM2 (i.e., the second portion of the reflective layer RL). In some embodiments, a shape of the top view of the alignment pattern AM2 may include a combination of a cross shape and a rectangular ring. In alternative embodiments, the shape of the top view of the alignment pattern AM2 may include a cross shape, a circular shape, a polygonal shape or a combination thereof. As such, the alignment pattern AM2 can be served as an alignment mark during subsequently performed steps. - Referring to
FIG. 3 andFIG. 6D , step S202 is performed, and anadhesive layer 306 is formed on thecarrier substrate 100. In some embodiments, theadhesive layer 306 covers the alignment pattern AM2 and thede-bonding layer 104. In some embodiments, theadhesive layer 306 has a planar top surface. - Referring to
FIG. 3 andFIG. 6E , step S204 is performed, and the semiconductor dies 108A, 108B are placed on theadhesive layer 306. The semiconductor dies 108A, 108B are placed aside the alignment pattern AM2. The alignment pattern AM2 functions as an alignment mark when positioning each of the semiconductor dies 108. As such, during the placement of the semiconductor dies 108A, 108B, the location shift of the placed semiconductor die(s) is reduced and the positioning accuracy can be improved. In some embodiments, a die-to-die offset (the compensated distance relative to the predetermined desired location) regarding the deviated or shifted semiconductor die can be reduced to 3 μm or less. - Referring to
FIG. 3 andFIG. 6F , step S206 is performed, and amolding compound 312 is formed on theadhesive layer 306. Themolding compound 312 surrounds each of the semiconductor dies 108, and exposes the front side FS of the semiconductor dies 108. In some embodiments, a front surface FS4 of themolding compound 312 is coplanar and levelled with the front side FS of the high-power device dies 108. In some embodiments, a thickness of themolding compound 312 is uniform across its cover area. - Step 208 is performed, and the
redistribution structure 114 is formed on the front side FS of the semiconductor dies 108A, 108B. Theredistribution structure 114 covers the semiconductor dies 108A, 108B and themolding compound 212. In some embodiments, the alignment pattern AM2 also functions as an alignment mark during the formation of theredistribution structure 114. For example, the alignment pattern AM2 can be used as an alignment mark when performing a lithography process for forming theconductive vias 120. With the alignment mark(s), less misalignment for placing the semiconductor dies 108A, 108B and better alignment for forming the conductive via 120 over theconductive pads 110 of the semiconductor dies 108A, 108B are achieved. Thereby, a via-to-pad overlay shift (the deviation distance relative to the predetermined desired location) regarding theconductive pads 110 and the correspondingconductive vias 120 can be reduced to 3 μm or less. In some embodiments, theelectrical connectors 122 are formed on theredistribution structure 114. - Referring to
FIG. 3 andFIG. 6G , step S210 is performed, and thecarrier substrate 100 and thede-bonding layer 104 are removed. As such, theadhesive layer 306 and the alignment pattern AM2 are exposed. In some embodiments, the entire structure may be flipped over and attached to atape 124 before or after thecarrier substrate 100 and thede-bonding layer 104 are removed. - Referring to
FIG. 3 andFIG. 6H , step S212 is performed, and the alignment pattern AM2 and theadhesive layer 306 are completely removed. As such, the back side BS of the semiconductor dies 108A, 108B and a back surface BS3 of themolding compound 312 opposite to theredistribution structure 114 are exposed. In some embodiments, a singulation process, such as a sawing process or a cutting process, is performed on the current structure. The singulated structure may contain one or more of the semiconductor dies, and may be referred as a single-die package structure or a multi-die package structure. - Referring to
FIG. 3 andFIG. 6I , step S214 is performed, and theheat dissipation module 326 is formed over the back side BS of the semiconductor dies 108A, 108B. In some embodiments, the formation of theheat dissipation module 326 may include sequentially forming a thermalinterfacial layer 328 and providing thelid 130. The thermalinterfacial layer 328 is in direct contact with the back side BS of the high-power device dies 108, and located in between the high-power device dies 108 and thelid 130. In addition, the thermalinterfacial layer 328 covers the back surface BS3 of themolding compound 312. In some embodiments, a thickness of the thermalinterfacial layer 328 is uniform across the back surface BS3 of themolding compound 312 and the back side BS of the high-power device dies 108. - In some embodiments, after the formation of the
heat dissipation module 326 and detaching thetape 124, theredistribution structure 114 and theelectrical connectors 122 are further mounted to thepackage substrate 132. As such, theredistribution structure 114 is located in between the high-power device dies 108 and thepackage substrate 132. In some embodiments, anunderfill 134 is formed to fill a space between theredistribution structure 114 and thepackage substrate 132. In some embodiments, theunderfill 134 surrounds each of theelectrical connectors 122. - So far, the
semiconductor package 40 according to some embodiments has been fabricated. The alignment pattern AM2 has been removed in step S212, such that the alignment pattern AM2 is absent in the final structure of thesemiconductor package 40. Even though, a location shift of the placed semiconductor die(s), a die-to-die offset regarding deviated or shifted semiconductor dies and a via-to-pad overlay shift of theconductive pads 110 and the correspondingconductive vias 120 can be reduced by virtue of the alignment pattern AM2 during the formation of thesemiconductor package 40. - As above, an alignment mark is formed in or under an adhesive layer before high-power device dies are placed on the adhesive layer. By using the alignment mark during the placement of the high-power device die(s), the location shift of the placed high-power device die(s) can be reduced. In addition, a die-to-die offset regarding the deviated or shift high-power device dies can be reduced. Moreover, when forming a redistribution structure at a front side of the high-power device die(s), a via-to-pad overlay shift regarding the conductive pads in the high-power device die(s) and the corresponding conductive vias in the redistribution structure can be reduced by virtue of the alignment mark as well. As a result, a reliability of electronic devices containing the semiconductor package according to embodiments of the present disclosure can be improved. Moreover, at least a portion of the adhesive layer is removed, such that a heat dissipation module can be directly disposed at the back side of the high-power device dies. As such, a heat path can be directly formed at the back side of the high-power device dies. Therefore, an efficient heat dissipation can be attained in the semiconductor package according to embodiments of the present disclosure.
- In some embodiments of the present disclosure, a semiconductor package is provided. The semiconductor package includes at least one high-power device die, a redistribution structure, a heat dissipation module and a molding compound. The at least one high-power device die has a front side and a back side opposite to the front side. The redistribution structure is disposed at the front side of the at least one high-power device die. The heat dissipation module is in direct contact with the back side of the at least one high-power device die. The molding compound is disposed between the redistribution structure and the heat dissipation module and surrounding the at least one high-power device die. The molding compound has a body portion and an extended portion. An interface between the body portion and the heat dissipation module is substantially parallel to the back side of the at least one high-power device die. A thickness of the extended portion is greater than a thickness of the body portion.
- In some embodiments of the present disclosure, a manufacturing method of a semiconductor package is provided. The manufacturing method of the semiconductor package includes the following steps: forming an adhesive layer on a carrier substrate; patterning the adhesive layer to form an adhesive pattern having an opening therein; placing at least one high-power device die on the adhesive pattern and aside the opening using the opening as an alignment mark, wherein the at least one high-power device die has a front side and a back side, the back side faces the adhesive pattern, and the front side opposite to the back side; forming a molding compound on the adhesive pattern and filling the opening, wherein the molding compound surrounds the at least one high-power device die and exposes the front side of the at least one high-power device die, and the molding compound has an extended portion in the opening of the adhesive pattern; forming a redistribution structure on the front side of the at least one high-power device die; removing the carrier substrate and the adhesive pattern; and forming a heat dissipation module at the back side of the at least one high-power device die, wherein the heat dissipation module is in direct contact with the back side of the at least one high-power device die.
- In some embodiments of the present disclosure, a manufacturing method of a semiconductor package is provided. The manufacturing method of the semiconductor package includes the following steps: forming an alignment pattern on a carrier substrate; forming an adhesive layer on the carrier substrate, wherein the adhesive layer covers the alignment pattern; placing at least one high-power device die on the adhesive layer by using the alignment pattern as an alignment mark, wherein the at least one high-power device die has a front side and a back side, the back side faces the adhesive layer, and the front side opposite to the back side; forming a molding compound on the adhesive layer, wherein the molding compound surrounds the at least one high-power device die and exposes the front side of the at least one high-power device die; forming a redistribution structure on the front side of the at least one high-power device die; removing the carrier substrate, at least a portion of the adhesive layer and at least of the alignment pattern; and forming a heat dissipation module at the back side of the at least one high-power device die, wherein the heat dissipation module is in direct contact with the back side of the at least one high-power device die.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/964,092 US10529593B2 (en) | 2018-04-27 | 2018-04-27 | Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package |
US16/734,421 US11121006B2 (en) | 2018-04-27 | 2020-01-06 | Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/964,092 US10529593B2 (en) | 2018-04-27 | 2018-04-27 | Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/734,421 Division US11121006B2 (en) | 2018-04-27 | 2020-01-06 | Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package |
Publications (2)
Publication Number | Publication Date |
---|---|
US20190333782A1 true US20190333782A1 (en) | 2019-10-31 |
US10529593B2 US10529593B2 (en) | 2020-01-07 |
Family
ID=68292791
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/964,092 Active US10529593B2 (en) | 2018-04-27 | 2018-04-27 | Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package |
US16/734,421 Active US11121006B2 (en) | 2018-04-27 | 2020-01-06 | Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/734,421 Active US11121006B2 (en) | 2018-04-27 | 2020-01-06 | Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package |
Country Status (1)
Country | Link |
---|---|
US (2) | US10529593B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190139900A1 (en) * | 2017-11-09 | 2019-05-09 | SK Hynix Inc. | Semiconductor packages including die over-shift indicating patterns |
US10804188B2 (en) * | 2018-09-07 | 2020-10-13 | Intel Corporation | Electronic device including a lateral trace |
US11152329B2 (en) * | 2019-03-11 | 2021-10-19 | Toshiba Memory Corporation | Method of separating bonded substrate, method of manufacturing semiconductor storage device, and substrate separation apparatus |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109346415B (en) * | 2018-09-20 | 2020-04-28 | 江苏长电科技股份有限公司 | Packaging method and packaging equipment for selectively packaging structure |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100510518B1 (en) * | 2003-01-30 | 2005-08-26 | 삼성전자주식회사 | Semiconductor device and packaging method of the semiconductor device |
TWI393223B (en) * | 2009-03-03 | 2013-04-11 | Advanced Semiconductor Eng | Semiconductor package structure and manufacturing method thereof |
TWI466259B (en) * | 2009-07-21 | 2014-12-21 | Advanced Semiconductor Eng | Semiconductor package, manufacturing method thereof and manufacturing method for chip-redistribution encapsulant |
TWI405306B (en) * | 2009-07-23 | 2013-08-11 | Advanced Semiconductor Eng | Semiconductor package, manufacturing method thereof and chip-redistribution encapsulant |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US8557631B2 (en) * | 2011-12-01 | 2013-10-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer wafer bonding method and apparatus |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
AT513047B1 (en) * | 2012-07-02 | 2014-01-15 | Austria Tech & System Tech | Method for embedding at least one component in a printed circuit board |
JP5521130B1 (en) * | 2012-08-30 | 2014-06-11 | パナソニック株式会社 | Electronic component package and manufacturing method thereof |
US8921994B2 (en) * | 2012-09-14 | 2014-12-30 | Freescale Semiconductor, Inc. | Thermally enhanced package with lid heat spreader |
US9159643B2 (en) * | 2012-09-14 | 2015-10-13 | Freescale Semiconductor, Inc. | Matrix lid heatspreader for flip chip package |
KR102018885B1 (en) * | 2012-12-20 | 2019-09-05 | 삼성전자주식회사 | Semiconductor devices having through vias and methods for fabricating the same |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US9960099B2 (en) * | 2013-11-11 | 2018-05-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thermally conductive molding compound structure for heat dissipation in semiconductor packages |
KR101542965B1 (en) * | 2013-12-30 | 2015-08-07 | 현대자동차 주식회사 | Method for junction of semiconductor substrate |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US10056267B2 (en) * | 2014-02-14 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
US10079224B2 (en) * | 2014-08-11 | 2018-09-18 | Massachusetts Institute Of Technology | Interconnect structures for assembly of semiconductor structures including at least one integrated circuit structure |
US10304675B2 (en) * | 2014-11-27 | 2019-05-28 | National Institute Of Advanced Industrial Science And Technology | System for integrating preceding steps and subsequent steps |
JP6691835B2 (en) * | 2016-06-17 | 2020-05-13 | 株式会社アムコー・テクノロジー・ジャパン | Method for manufacturing semiconductor package |
EP3333883A1 (en) * | 2016-12-08 | 2018-06-13 | IMEC vzw | A method for transferring and placing a semiconductor device on a substrate |
JP6596048B2 (en) * | 2017-09-05 | 2019-10-23 | シャープ株式会社 | Manufacturing method of substrate with alignment mark |
-
2018
- 2018-04-27 US US15/964,092 patent/US10529593B2/en active Active
-
2020
- 2020-01-06 US US16/734,421 patent/US11121006B2/en active Active
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190139900A1 (en) * | 2017-11-09 | 2019-05-09 | SK Hynix Inc. | Semiconductor packages including die over-shift indicating patterns |
US10692816B2 (en) * | 2017-11-09 | 2020-06-23 | SK Hynix Inc. | Semiconductor packages including die over-shift indicating patterns |
US11239177B2 (en) | 2017-11-09 | 2022-02-01 | SK Hynix Inc. | Semiconductor packages including die over-shift indicating patterns |
US10804188B2 (en) * | 2018-09-07 | 2020-10-13 | Intel Corporation | Electronic device including a lateral trace |
US11646254B2 (en) | 2018-09-07 | 2023-05-09 | Tahoe Research, Ltd. | Electronic device including a lateral trace |
US11152329B2 (en) * | 2019-03-11 | 2021-10-19 | Toshiba Memory Corporation | Method of separating bonded substrate, method of manufacturing semiconductor storage device, and substrate separation apparatus |
Also Published As
Publication number | Publication date |
---|---|
US20200144080A1 (en) | 2020-05-07 |
US10529593B2 (en) | 2020-01-07 |
US11121006B2 (en) | 2021-09-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11824040B2 (en) | Package component, electronic device and manufacturing method thereof | |
US11482508B2 (en) | Semiconductor package and manufacturing method thereof | |
US20240234372A1 (en) | Method of forming package structure | |
US11121006B2 (en) | Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package | |
US10283473B1 (en) | Package structure and manufacturing method thereof | |
US11410897B2 (en) | Semiconductor structure having a dielectric layer edge covering circuit carrier | |
US20220230969A1 (en) | Package structure and method of fabricating the same | |
US11450654B2 (en) | Package structure and method of fabricating the same | |
KR102415484B1 (en) | Package structure and method of fabricating the same | |
US11784106B2 (en) | Semiconductor package and manufacturing method thereof | |
KR20210084195A (en) | Fan-out packages and methods of forming the same | |
US11855060B2 (en) | Package structure and method of fabricating the same | |
US20240014120A1 (en) | Package structure and method of fabricating the same | |
US20230065884A1 (en) | Package structure and manufacturing method thereof | |
US12051639B2 (en) | Package structure and manufacturing method thereof | |
US20230282555A1 (en) | Package structure and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, PO-HAN;KUO, HUNG-JUI;HU, YU-HSIANG;REEL/FRAME:047293/0446 Effective date: 20180625 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |