US20190312139A1 - Avalanche robust ldmos - Google Patents
Avalanche robust ldmos Download PDFInfo
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- US20190312139A1 US20190312139A1 US15/945,588 US201815945588A US2019312139A1 US 20190312139 A1 US20190312139 A1 US 20190312139A1 US 201815945588 A US201815945588 A US 201815945588A US 2019312139 A1 US2019312139 A1 US 2019312139A1
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Definitions
- MOSFETs Metal-oxide field effect transistors
- the source region and the drain region are of a first conductivity type
- the body region is of a second conductivity type.
- the first conductivity type is n-type
- the second conductivity type is p-type. In other MOSFET devices, this relationship is reversed.
- MOSFET device When a MOSFET device is in an on state in response to an applied gate voltage, a channel region forms in the body region below the gate, and between the drain region and the source region. Current flows in the channel region. When the MOSFET device is in an off state, the channel region is not present, and thus current will not flow between the drain region and the source region.
- LDMOS Lateral diffusion MOSFETs
- LDD region is of the same conductivity type as the body region but is doped to a different concentration.
- the LDMOS may have an increased breakdown voltage as compared to a MOSFET, avalanche breakdown events can still occur if a reverse-bias voltage exceeds the breakdown voltage of the LDMOS.
- a semiconductor device includes a substrate and an active region.
- the active region includes a FET and a diode formed over the substrate.
- the FET includes one or more FET fingers formed in the active region, each FET finger having a FET source region, a FET drain region, and a lateral FET gate electrode.
- the diode includes one or more diode fingers formed in the active region, each diode finger having a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode.
- the one or more FET fingers of the FET are active fingers of the semiconductor device and the one or more diode fingers of the diode are dummy fingers of the semiconductor device.
- the diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.
- a semiconductor device includes a substrate and an active region formed over the substrate.
- the active region includes one or more active fingers and one or more diode fingers.
- Each active finger includes an active lateral gate electrode, two or more first active doped regions of a first conductivity type, and one or more second active doped regions doped of a second conductivity type.
- Each diode finger includes a diode lateral gate electrode, one or more first diode doped regions of the first conductivity type, and one or more second diode doped regions of the second conductivity type.
- Each active finger includes more regions doped to the first conductivity type than does the diode finger.
- the active finger includes the same number of regions doped to the second conductivity type as does the diode finger.
- the active lateral gate electrode is electrically isolated from the diode lateral gate electrode.
- the diode lateral gate electrode is electrically coupled to a diode region of the second diode doped regions.
- the one or more diode fingers are dummy fingers of the semiconductor device. The one or more diode fingers are configured to clamp a maximum voltage developed across two of the first active doped regions.
- a method for forming a semiconductor involves providing a substrate and forming an active region over the substrate.
- the active region includes one or more active fingers and one or more diode fingers.
- a FET is formed within one or more of the active fingers.
- the FET includes a FET source region, a FET drain region, and a lateral FET gate electrode.
- a diode is formed within one or more of the diode fingers.
- the diode includes a diode anode region, a diode cathode region, and a lateral diode gate electrode.
- the FET source region is electrically coupled to the diode anode region.
- the FET drain region is electrically coupled to the diode cathode region.
- the lateral diode gate electrode is laterally coupled to the diode anode region.
- the one or more diode fingers are dummy fingers of the semiconductor device.
- the lateral FET gate electrode is electrically isolated from the lateral diode gate electrode.
- the diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.
- FIG. 1 is a simplified orthoscopic diagram of a portion of a prior art multi-finger semiconductor device.
- FIG. 2 is a simplified orthoscopic diagram of a portion of a multi-finger semiconductor device, in accordance with some embodiments.
- FIG. 3 is a simplified cross-section diagram of an example LDMOS structure in an active finger of a multi-finger semiconductor device, in accordance with some embodiments.
- FIGS. 4-6 are simplified cross-section diagrams of example diode structures in a dummy finger of a multi-finger semiconductor device, in accordance with some embodiments.
- FIGS. 7-9 are simplified cross-section diagrams of multi-finger semiconductor devices, in accordance with some embodiments.
- FIGS. 10A-B are graphs of example experimental results measured using example embodiments disclosed herein.
- Avalanche breakdown can occur in an LDMOS device when a reverse-bias voltage developed across a source region and drain region of the LDMOS exceeds a breakdown voltage level of the LDMOS device.
- avalanche breakdown occurs, the LDMOS can be damaged or destroyed.
- One way to mitigate the risk of an avalanche breakdown event is to implement a reverse-biased diode in parallel with the LDMOS device.
- a cathode region of the diode is electrically coupled to the drain region of the LDMOS device, and an anode region of the diode is electrically coupled to the source region of the LDMOS device.
- the diode is configured to have a target (e.g., desired) diode breakdown voltage level that is less than a breakdown voltage that would cause an avalanche breakdown event to occur in the LDMOS device.
- a target diode breakdown voltage level that is less than a breakdown voltage that would cause an avalanche breakdown event to occur in the LDMOS device.
- the diode conducts a large amount of current. This current flow reduces or eliminates the reverse-bias voltage across the LDMOS device. Because the reverse-bias voltage across the LDMOS is reduced or eliminated the LDMOS is prevented from experiencing an avalanche breakdown event.
- one or more diodes are advantageously monolithically integrated with one or more LDMOS devices on a common substrate of a semiconductor device.
- the semiconductor device includes one or more active fingers and one or more dummy fingers (which are sometimes also referred to as termination fingers).
- the dummy fingers are fingers of a multi-finger semiconductor device that are adjacent to a terminating perimeter (e.g., an outside perimeter) of the semiconductor device.
- a dummy finger is a finger of a multi-finger semiconductor device having a control node (e.g., a gate electrode) that is not electrically coupled to corresponding control nodes (e.g., gate electrodes) of active fingers of the semiconductor device.
- the LDMOS devices are formed within one or more of the active fingers and diodes are formed in one or more of the dummy fingers. These diodes are electrically coupled to be in parallel with the LDMOS devices formed in one or more active fingers of the semiconductor device.
- the diode or diodes formed in the dummy fingers are configured to have a breakdown voltage level that is below a reverse-bias voltage level that would trigger an avalanche event in the LDMOS formed in the active fingers.
- the area of the semiconductor that would typically be wasted by the dummy fingers is advantageously repurposed as one or more diodes to extend and protect the life of the LDMOS formed in the active fingers.
- the dummy fingers are similar to the active fingers, a process flow to create the semiconductor device is advantageously simplified as compared to a process flow to monolithically integrate dissimilar semiconductor devices.
- FIG. 1 shows a simplified prior art orthoscopic diagram of a multi-finger semiconductor device 100 .
- the semiconductor device 100 generally includes two or more active fingers 102 and two or more dummy fingers 104 .
- An LDMOS device is formed in the active fingers 102 , as shown by alternating source regions S 2-3 , gate electrodes G 2-4 , and drain regions D 2-3 .
- a metallization layer (not shown) may be used to electrically couple corresponding regions of the active fingers 102 together as shown schematically. For example, a metallization layer may electrically couple each of the gate electrodes G 2-4 of the active fingers 102 together; another metallization layer may electrically couple each of the source regions S 2-3 of the active fingers 102 together, and so on.
- the dummy fingers 104 are typically positioned near an outside perimeter of the semiconductor device 100 to minimize peripheral effects of a process flow used to form the semiconductor device 100 .
- the dummy fingers 104 include alternating source S 1-n regions, gate electrodes G 1-n , and drain regions D 1-n . that are similar to corresponding regions of the active fingers 102 , with some exceptions. For example, regions of the dummy fingers 104 may not be electrically coupled to corresponding regions within the active fingers 102 (e.g., G 1 is typically electrically isolated from G 2 ).
- FIG. 2 shows a simplified orthoscopic diagram of a multi-finger semiconductor device 200 , in accordance with some embodiments. Some portions of the semiconductor device 200 understood by one of skill in the art to be present have been omitted from FIG. 2 for simplicity.
- the semiconductor device 200 generally includes two or more active fingers 202 and two or more dummy fingers 204 .
- the dummy fingers 204 are typically positioned near an outside perimeter of the semiconductor device 200 , though in some embodiments the dummy fingers 204 are interleaved between the active fingers 202 .
- a cross-section cutting line 203 through a portion of the active fingers 202 corresponds to a portion of an LDMOS shown and discussed with reference to FIG. 3 .
- a cross-section cutting line 205 through a portion of the dummy fingers 204 corresponds to a diode shown and discussed with reference to FIGS. 4-6 .
- An LDMOS device is formed in the active fingers 202 , as shown by alternating source regions S 2-3 , gate electrodes G 2-4 , and drain regions D 2-3 .
- metallization layers may be used to electrically couple corresponding regions of the active fingers 202 together as shown schematically.
- other metallization layers may be used to electrically couple regions of the dummy fingers 204 to each other and to regions of the active fingers 202 as shown schematically.
- only three LDMOS devices are shown in the active fingers 202 (e.g., as controlled by gate electrodes G 2 , G 3 , and G 4 ). However, in some embodiments the active fingers 202 include significantly more LDMOS devices.
- the active fingers 202 constitute a single LDMOS device.
- two or more independent LDMOS devices are formed in the active fingers 202 .
- a first LDMOS device and a second LDMOS device are implemented by a set of multiple interleaved fingers and are interconnected by a set of alternating electrically conducting paths.
- One or more regions of the dummy fingers 204 are modified to form gated diode(s).
- the diodes have alternating anode regions A 1-n , dummy gate electrodes G 1-n , and cathode regions C 1-n .
- Dummy gate electrodes G 1-n of each diode are electrically coupled to a respective anode region A 1-n of that diode to prevent a current conduction channel from forming in a body region of the diode.
- the dummy gate electrode is called a “dummy” gate electrode because it is not configured to receive a gate voltage.
- Diodes formed in the dummy fingers 204 are electrically coupled in parallel to the LDMOS formed in the active fingers 202 .
- the anode regions A 1-n formed in the dummy fingers 204 are electrically coupled to the source regions S 2-3 of the LDMOS formed in the active fingers 202 .
- the cathode regions C 1-n formed in the dummy fingers 204 are electrically coupled to the drain regions D 2-3 of the LDMOS formed in the active fingers 202 .
- a ratio of diodes to LDMOS devices is chosen based on desired performance, among other factors. In some embodiments, there are ten LDMOS devices for every one diode (a ratio of 10-1). In some embodiments, this ratio is 1-to-1, 1-2, 2-1, 2-2, 5-1, and so on. In some embodiments, this ratio is 20-1, 50-1, 100-1, so on. In some embodiments, the semiconductor device 200 is designed to have the smallest number of dummy fingers 204 possible while still meeting other design, process and/or performance criteria.
- surface area of the semiconductor device 200 that would typically be wasted by the dummy fingers 204 is advantageously repurposed as one or more diodes to extend and protect the life of the LDMOS formed in the active fingers 202 . That is, the diode or diodes formed in the dummy fingers 204 are configured to have a target breakdown voltage level that is below a reverse-bias voltage level that would trigger an avalanche event in the LDMOS formed in the active fingers 202 . Thus, diodes formed in the dummy fingers 204 advantageously reduce or eliminate the chances of an avalanche event occurring within the LDMOS formed in the active fingers 202 .
- a process flow to create the semiconductor device 200 is advantageously simplified as compared to a process flow to monolithically integrate dissimilar semiconductor devices, e.g., an LDMOS device and a separately formed reverse-biased diode in parallel with the LDMOS device.
- FIG. 3 is a simplified cross-section diagram, taken through the cutting line 203 of FIG. 2 , of an example LDMOS device 302 formed in the active fingers 202 , in accordance with some embodiments.
- the LDMOS 302 generally includes a substrate 310 , an optional buried insulator layer 312 (as indicated by dashed lines), and an active region 314 formed over the substrate 310 or over the buried insulator layer 312 .
- the active region 314 can be any of a doped portion of the bulk of a semiconductor wafer, a localized well formed in a larger doped portion of a semiconductor wager, an active layer of a semiconductor-on-insulator (SOI) wafer, and a localized well formed in an SOI wafer.
- SOI semiconductor-on-insulator
- the active region 314 is a thin film formed over the substrate 310 or over the buried insulator layer 312 .
- Some portions of the LDMOS 302 understood by one of skill in the art to be present have been omitted from FIG. 3 for simplicity.
- one or more metallization layers and interconnects are not shown, though are understood to be present.
- the active region 314 generally includes doped semiconductor regions of a first conductivity type and regions of a second conductivity type, formed by, example, by implanting impurities into the active region 314 .
- the regions of the first conductivity type can be formed by implanting one kind of dopant atom
- the regions of the second conductivity type can be formed by implanting another kind of dopant atom.
- the first conductivity type is n-type and the second conductivity type is p-type. In other embodiments, the first conductivity type is p-type and the second conductivity type is n-type.
- the regions of the first conductivity type include a source region 316 , a drain region 318 , an LDD region 320 , and a buried region 326 .
- the regions of the second conductivity type include a body region 322 , a source contact region 323 , and a buried well 324 .
- a silicide layer 330 on a lateral polysilicon gate electrode 328 forms a gate bus which is electrically coupled to a gate terminal (G) located in a third dimension.
- a shielding structure 336 is formed as a lateral extension of a conductive layer lining a source trench, shown on the left side of the LDMOS 302 , which is filled with top metal to form a source contact electrode 332 .
- the source contact electrode 332 is electrically coupled to a source terminal (S) located in a third dimension.
- Top metal also forms a drain contact electrode 334 which is electrically coupled to a drain terminal (D) located in a third dimension.
- a dielectric 338 electrically insulates portions of the active region 314 .
- a lateral distance 340 between an edge of the gate electrode 328 and the nearest edge of the drain region 318 is shown for reference with respect to FIGS. 4-5 .
- a lateral distance 352 between an edge of the buried well 324 and the nearest edge of the drain region 318 is shown for reference with respect to FIGS. 5-6 .
- the LDMOS 302 When sufficient gate voltage is applied to the gate electrode 328 , the LDMOS 302 is in an on state. In the on state, a conduction channel forms between the source region 316 and the drain region 318 and current flows in the conduction channel. Normally when no gate voltage is applied to the gate electrode 328 , the conduction channel is not formed, and the LDMOS 302 is in an off state. However, if a reverse-bias voltage that exceeds a breakdown voltage of the LDMOS 302 is applied across the source region 316 and the drain region 318 , an avalanche event can occur, whereby uncontrolled current flows between these regions regardless of whether a gate voltage is applied to the gate electrode 328 .
- FIG. 4 is a simplified cross-section diagram, taken through the cutting line 205 of FIG. 2 , of an example diode 404 formed in the dummy fingers 204 , in accordance with some embodiments.
- the diode 404 generally includes a substrate 410 , an optional buried insulator layer 412 , and an active region 414 formed over the substrate 410 or over the buried insulator layer 412 .
- Some portions of the diode 404 understood by one of skill in the art to be present have been omitted from FIG. 4 for simplicity. For example, metallization layers and other interconnects understood to be present are omitted from FIG. 4 .
- the substrate 410 and the substrate 310 of FIG. 3 are portions of the same substrate.
- the LDMOS 302 and the diode 404 are formed monolithically on the same substrate.
- the optional buried insulator layer 412 and the optional buried insulator layer 312 of FIG. 3 are portions of the same buried insulator layer.
- the active region 414 generally includes regions of the first conductivity type and regions of the second conductivity type in accordance with respective regions in the active region 314 described with reference to FIG. 3 .
- regions of the first conductivity type of the diode 404 have the same doping depth, concentration and lateral extent as corresponding regions of the LDMOS 302 .
- regions of the second conductivity type of the diode 404 have the same doping depth, concentration and lateral extent as corresponding regions of the LDMOS 302 .
- the regions of the first conductivity type include a cathode contact region 418 , an LDD region 420 , and a buried region 426 .
- the regions of the second conductivity type include a body region 422 , an anode contact region 423 , and a buried well 424 .
- a source region similar to the source region 316 of the LDMOS 302 , is omitted from the diode 404 . Omitting a source region advantageously creates an anode region comprised of the body region 422 , the buried well 424 , and the anode contact region 423 , each of these regions being of the second conductivity type.
- Top metal forms an anode contact electrode 432 which is electrically coupled to an anode terminal (A) located in a third dimension.
- Top metal also forms a cathode contact electrode 434 which is electrically coupled to a cathode terminal (C) located in a third dimension.
- the anode contact region 423 is electrically coupled to source contact region 323 of the LDMOS 302
- the cathode contact region 418 is electrically coupled to the drain region 318 of the LDMOS 302 (e.g., by top metal).
- a lateral gate electrode 428 with a silicide layer 430 is electrically coupled to the anode contact region 423 .
- the gate electrode 428 is electrically isolated from the gate electrode 328 of the LDMOS 302 .
- a dielectric 438 electrically insulates portions of the active region 414 .
- a target breakdown voltage (e.g., a desired breakdown voltage chosen at design time) of the diode 404 is configured to be less than a breakdown voltage of the LDMOS 302 .
- a lateral distance 440 between the gate electrode 428 and the nearest edge of the cathode contact region 418 is the same as the lateral distance 340 shown in FIG. 3 .
- a lateral distance 452 between the buried well 424 and the nearest edge of the cathode contact region 418 is the same as the lateral distance 352 shown in FIG. 3 .
- a target breakdown voltage of the diode 404 is reduced by forming the diode 404 such that a truncated shielding structure 436 does not overlap any portion of the gate electrode 428 (e.g., as compared to the lateral extent of the shielding structure 336 over the gate electrode 328 shown in FIG. 3 ).
- no portion of the truncated shielding structure 436 is included as part of the diode 404 (e.g., the shielding structure 436 is not formed as part of a process flow to form the diode 404 ). Removing or omitting the shielding structure 436 will cause the breakdown voltage of the diode 404 to decrease due to lack of carrier depletion previously provided by the shielding structure.
- the gate electrode 428 is electrically shorted to the anode contact region 423 by a metal. Electrically shorting the gate electrode 428 to the anode contact region 423 advantageously prevents a conduction channel from forming in the diode 404 , thereby reducing leakage current under high-frequency operation of the semiconductor device.
- a resistor 444 couples the gate electrode 428 to the anode contact region 423 . During an electrostatic discharge event, transient current through the resistor 444 will cause a voltage drop that inverts the region under the gate electrode 428 and forms a conduction channel.
- a trigger voltage of the diode 404 is advantageously lowered as compared to embodiments of the diode 404 where the gate electrode 428 is electrically shorted to the anode contact region 423 . Additionally, because a conduction channel is formed due to inversion, avalanche robustness of the diode 404 is advantageously increased.
- the diode 404 is electrically coupled in parallel to the LDMOS 302 as previously described. As such, a reverse-bias voltage applied across the drain region 318 and the source region 316 of the LDMOS 302 will also be present across the cathode contact region 418 and the anode contact region 423 of the diode 404 . If that reverse-bias voltage exceeds a breakdown voltage of the diode 404 , current will flow from the cathode contact region 418 to the anode contact region 423 . This flow of current will cause the reverse-bias voltage across the LDMOS 302 to be reduced or eliminated. Thus, an avalanche event is prevented from occurring within the LDMOS 302 , thereby protecting the LDMOS 302 from potential damage.
- FIG. 5 is a simplified cross-section diagram, taken through the cutting line 205 of FIG. 2 , of an example diode 504 formed in the dummy fingers 204 , in accordance with some embodiments.
- a target breakdown voltage of the diode 504 is modified as compared to the diode 404 by reducing a lateral distance 540 between a lateral gate electrode 528 and the nearest edge of a cathode contact region 518 .
- Other regions of the diode 504 are the same or similar to like numbered regions and features of the diode 404 .
- a body region 522 is the same or similar to the body region 422
- a buried well 524 is similar to the buried well 424
- a substrate 510 is similar to the substrate 410
- embodiments of electrical couplings and electrical isolations of the diode 504 are the same or similar to embodiments of electrical couplings and electrical isolations of the diode 404 .
- a lateral distance 552 between an edge of the buried well 524 and the nearest edge of the cathode contact region 518 is shown for reference with respect to FIG. 6 .
- the diode 504 generally includes a substrate 510 , an optional buried insulator layer 512 , and an active region 514 formed over the substrate 510 or over the buried insulator layer 512 . Some portions of the diode 504 understood by one of skill in the art to be present have been omitted from FIG. 5 for simplicity. For example, metallization layers and other interconnects understood to be present are omitted from FIG. 5 .
- the active region 514 generally includes regions of the first conductivity type and regions of the second conductivity type in accordance with respective regions in the active region 314 .
- regions of the first conductivity type of the diode 504 have the same doping depth and concentration as corresponding regions of the LDMOS 302 , but the lateral extents differ.
- regions of the second conductivity type of the diode 504 have the same doping depth and concentration as corresponding regions of the LDMOS 302 , but the lateral extents differ.
- the regions of the first conductivity type include a cathode contact region 518 , an LDD region 520 , and a buried region 526 .
- the regions of the second conductivity type include a body region 522 , an anode contact region 523 , and a buried well 524 .
- a source region similar to the source region 316 of the LDMOS 302 , is omitted from the diode 504 . Omitting the source region creates an anode region within the diode 504 .
- the anode region includes the anode contact region 523 , the body region 522 and the buried well 524 , each region being of the second conductivity type.
- Top metal forms an anode contact electrode 532 which is electrically coupled to an anode terminal (A) located in a third dimension.
- Top metal also forms a cathode contact electrode 534 which is electrically coupled to a cathode terminal (C) located in a third dimension.
- the anode contact region 523 is electrically coupled to the source contact region 323 of the LDMOS 302
- the cathode contact region 518 is electrically coupled to the drain region 318 of the LDMOS 302 (e.g., by top metal).
- a gate electrode 528 with a silicide layer 530 is electrically coupled to the anode contact region 523 either directly (e.g., by top metal), or through an optional resistor 544 which is the same or similar to the resistor 444 .
- the gate electrode 528 is electrically isolated from the gate electrode 328 of the LDMOS 302 .
- a dielectric 538 electrically insulates portions of the active region 514 .
- a shielding structure 536 overlaps (e.g., extends laterally over) the gate electrode 528 .
- the lateral extension of the shielding structure 536 would raise a target breakdown voltage of the diode 504 as compared to the diode 404 .
- the lateral distance 540 is reduced as compared to both the lateral distance 440 of diode 404 and the lateral distance 340 of the LDMOS 302 . This reduction in lateral distance reduces the target breakdown voltage of the diode 504 as compared to the diode 404 .
- the lateral distance 552 is reduced as compared to both the lateral distance 452 of the diode 404 and the lateral distance 352 of the LDMOS 302 .
- the lateral distance 540 and the lateral distance 552 can be chosen at design time such that a target breakdown voltage of the diode 504 is lower than a breakdown voltage of the LDMOS 302 .
- FIG. 6 is a simplified cross-section diagram, taken through the cutting line 205 of FIG. 2 , of an example diode 604 formed in the dummy fingers 204 , in accordance with some embodiments.
- a breakdown voltage of the diode 604 is modified as compared to the diode 504 by reducing a lateral distance 652 between a buried well 624 and the nearest edge of a cathode contact region 618 as compared to the lateral distance 552 of the diode 504 .
- Other regions of the diode 604 are the same or similar to like numbered regions and features of the diode 504 .
- a body region 622 is the same or similar to the body region 522
- a buried well 624 is similar to the buried well 524 (except with regards to a modified lateral extent of the buried well 624 )
- a substrate 610 is similar to the substrate 510 , and so on.
- embodiments of electrical couplings and electrical isolations of the diode 604 are the same or similar to embodiments of electrical couplings and electrical isolations of the diode 504 .
- the diode 604 generally includes a substrate 610 , an optional buried insulator layer 612 , and an active region 614 formed over the substrate 610 or over the buried insulator layer 612 . Some portions of the diode 604 understood by one of skill in the art to be present have been omitted from FIG. 6 for simplicity. For example, metallization layers and other interconnects understood to be present are omitted from FIG. 6 .
- the active region 614 generally includes regions of the first conductivity type and regions of the second conductivity type in accordance with respective regions in the active region 314 of the LDMOS 302 .
- regions of the first conductivity type of the diode 604 have the same doping depth and concentration as corresponding regions of the LDMOS 302 , but the lateral extents differ.
- regions of the second conductivity type of the diode 604 have the same doping depth and concentration as corresponding regions of the LDMOS 302 , but the lateral extents differ.
- the regions of the first conductivity type include a cathode contact region 618 , an LDD region 620 , and a buried region 626 .
- the regions of the second conductivity type include a body region 622 , an anode contact region 623 , and the buried well 624 .
- a source region is omitted from the diode 604 . Omitting a source region is omitted creates an anode region within the diode 604 .
- the anode region includes the anode contact region 623 , the body region 622 and the buried well 624 , each region being of the second conductivity type.
- Top metal forms an anode contact electrode 632 which is electrically coupled to an anode terminal (A) located in a third dimension.
- Top metal also forms a cathode contact electrode 634 which is electrically coupled to a cathode terminal (C) located in a third dimension.
- the anode contact region 623 is electrically coupled to source contact region 323 of the LDMOS 302
- the cathode contact region 618 is electrically coupled to the drain region 318 of the LDMOS 302 (e.g., by top metal).
- a lateral gate electrode 628 with a silicide layer 630 is electrically coupled to the anode contact region 623 either directly (e.g., by top metal), or through an optional resistor 644 which is the same or similar to the resistor 444 .
- the gate electrode 628 is electrically isolated from the gate electrode 328 of the LDMOS 302 .
- a dielectric 638 electrically insulates portions of the active region 614 .
- a shielding structure 636 extends laterally over the gate electrode 628 .
- a target breakdown voltage of the diode 604 is further modified from the target breakdown voltage of the diode 504 by the reduction of the lateral distance 652 as compared to the lateral distance 552 of the diode 504 .
- the lateral distance 652 can be designed such that a target breakdown voltage of the diode 604 is lower than a breakdown voltage of the LDMOS 302 .
- FIG. 7 shows a simplified orthoscopic diagram of a multi-finger semiconductor device 700 , in accordance with some embodiments.
- the semiconductor device 700 generally includes a substrate 710 , a buried insulator layer 712 , and an active region 714 .
- the active region 714 generally includes one or more active fingers 702 and one or more dummy fingers 704 .
- protective diodes are formed in the dummy fingers 704
- LDMOS devices are formed in the active fingers 702 .
- insulating barrier regions 746 electrically isolate the active fingers 702 from the dummy fingers 704 .
- the insulator barrier regions 746 are shallow trench isolation (STI) regions.
- STI shallow trench isolation
- the insulator barrier regions are deep trench isolation regions (DTI). Electrical connections in a third dimension shown schematically as a dashed line 762 electrically couple cathode regions (C) of the diodes to drain regions (D) of the LDMOS devices, and electrical connections in a third dimension shown schematically as a dashed line 764 electrically couple anode regions (A) of the diodes to source regions (S) of the LDMOS devices.
- DTI deep trench isolation regions
- FIG. 8 shows a simplified orthoscopic diagram of a multi-finger semiconductor device 800 , in accordance with some embodiments.
- the semiconductor device 800 generally includes a substrate 810 , a buried insulator layer 812 , and an active region 814 .
- the active region 814 generally includes one or more active fingers 802 and one or more dummy fingers 804 .
- protective diodes are formed in the dummy fingers 804
- LDMOS devices are formed in the active fingers 802 .
- insulating barrier regions 846 electrically isolate adjacent LDMOS devices formed in the active fingers 802 , as well as electrically isolate the active fingers 802 from the dummy fingers 804 .
- Electrical connections in a third dimension shown schematically as a dashed line 862 couple cathode regions (C) of the diodes to drain regions (D) of the LDMOS devices, and electrical connections in a third dimension shown schematically as a dashed line 864 electrically couple anode regions (A) of the diodes to source regions (S) of the LDMOS devices.
- FIG. 9 shows a simplified orthoscopic diagram of a multi-finger semiconductor device 900 , in accordance with some embodiments.
- the semiconductor device 900 generally includes a substrate 910 , a buried insulator layer 912 , and an active region 914 .
- the active region 914 generally includes one or more active fingers 902 interleaved with one or more dummy fingers 904 .
- protective diodes are formed in the dummy fingers 904
- LDMOS devices are formed in the active fingers 902 .
- insulating barrier regions 946 electrically isolate LDMOS devices formed in the active fingers 802 from adjacent diodes formed in the dummy fingers 904 .
- Electrical connections in a third dimension shown schematically as a dashed line 962 couple cathode regions (C) of the diodes to drain regions (D) of the LDMOS devices, and electrical connections in a third dimension shown schematically as a dashed line 964 electrically couple anode regions (A) of the diodes to source regions (S) of the LDMOS devices.
- FIGS. 10A-B are simplified graphs 1060 , 1070 of example experimental results measured using example embodiments disclosed herein.
- Lines 1062 and 1072 are measured transmission line pulse (TLP) curves generated using an LDMOS similar to the LDMOS 302 .
- Line 1064 is a TLP curve generated using a diode that is similar to the diode 504 with a direct electrical coupling of the gate electrode 428 to the anode contact region 423 and having a shielding structure similar to the shielding structure 336 .
- Line 1074 is a TLP curve generated using a diode similar to the diode 404 or 604 .
- a comparison of the line 1064 to the line 1062 shows a measured indication of ESD robustness of the diode 504 as being two times greater than a measured indication of ESD robustness of the LDMOS 302 .
- a comparison of line 1074 to line 1072 shows a measured indication of ESD robustness of the diode 404 or 604 (or other similar embodiments which match a breakdown voltage of the LDMOS 302 ) as being seven times greater than a measured indication of ESD robustness of the LDMOS 302 .
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Abstract
Description
- Metal-oxide field effect transistors (MOSFETs) generally include a gate electrode, a source region, a drain region, and a body region. The source region and the drain region are of a first conductivity type, and the body region is of a second conductivity type. In some MOSFET devices, the first conductivity type is n-type and the second conductivity type is p-type. In other MOSFET devices, this relationship is reversed. When a MOSFET device is in an on state in response to an applied gate voltage, a channel region forms in the body region below the gate, and between the drain region and the source region. Current flows in the channel region. When the MOSFET device is in an off state, the channel region is not present, and thus current will not flow between the drain region and the source region. However, if a reverse-bias voltage is applied across the drain region and the source region of the MOSFET that exceeds a breakdown voltage, a large uncontrolled current will flow between the source region and the drain region regardless of whether a voltage is applied to the gate electrode. As the reverse-bias voltage increases above the breakdown voltage, an avalanche breakdown event can occur. During the avalanche breakdown event, current through the MOSFET increases at an increasing rate and can quickly exceed a maximum current rating of the MOSFET. As a result, the MOSFET is often damaged or entirely destroyed.
- Lateral diffusion MOSFETs (LDMOS) are a class of MOSFETs that additionally include a lateral lightly doped drain (LDD) region to increase breakdown voltage of the semiconductor device as compared to the breakdown voltage of a typical MOSFET. The LDD region is of the same conductivity type as the body region but is doped to a different concentration. Though the LDMOS may have an increased breakdown voltage as compared to a MOSFET, avalanche breakdown events can still occur if a reverse-bias voltage exceeds the breakdown voltage of the LDMOS.
- In some embodiments, a semiconductor device includes a substrate and an active region. The active region includes a FET and a diode formed over the substrate. The FET includes one or more FET fingers formed in the active region, each FET finger having a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers formed in the active region, each diode finger having a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The one or more FET fingers of the FET are active fingers of the semiconductor device and the one or more diode fingers of the diode are dummy fingers of the semiconductor device. The diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.
- In some embodiments, a semiconductor device includes a substrate and an active region formed over the substrate. The active region includes one or more active fingers and one or more diode fingers. Each active finger includes an active lateral gate electrode, two or more first active doped regions of a first conductivity type, and one or more second active doped regions doped of a second conductivity type. Each diode finger includes a diode lateral gate electrode, one or more first diode doped regions of the first conductivity type, and one or more second diode doped regions of the second conductivity type. Each active finger includes more regions doped to the first conductivity type than does the diode finger. The active finger includes the same number of regions doped to the second conductivity type as does the diode finger. The active lateral gate electrode is electrically isolated from the diode lateral gate electrode. The diode lateral gate electrode is electrically coupled to a diode region of the second diode doped regions. The one or more diode fingers are dummy fingers of the semiconductor device. The one or more diode fingers are configured to clamp a maximum voltage developed across two of the first active doped regions.
- In some embodiments, a method for forming a semiconductor involves providing a substrate and forming an active region over the substrate. The active region includes one or more active fingers and one or more diode fingers. A FET is formed within one or more of the active fingers. The FET includes a FET source region, a FET drain region, and a lateral FET gate electrode. A diode is formed within one or more of the diode fingers. The diode includes a diode anode region, a diode cathode region, and a lateral diode gate electrode. The FET source region is electrically coupled to the diode anode region. The FET drain region is electrically coupled to the diode cathode region. The lateral diode gate electrode is laterally coupled to the diode anode region. The one or more diode fingers are dummy fingers of the semiconductor device. The lateral FET gate electrode is electrically isolated from the lateral diode gate electrode. The diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.
-
FIG. 1 is a simplified orthoscopic diagram of a portion of a prior art multi-finger semiconductor device. -
FIG. 2 is a simplified orthoscopic diagram of a portion of a multi-finger semiconductor device, in accordance with some embodiments. -
FIG. 3 is a simplified cross-section diagram of an example LDMOS structure in an active finger of a multi-finger semiconductor device, in accordance with some embodiments. -
FIGS. 4-6 are simplified cross-section diagrams of example diode structures in a dummy finger of a multi-finger semiconductor device, in accordance with some embodiments. -
FIGS. 7-9 are simplified cross-section diagrams of multi-finger semiconductor devices, in accordance with some embodiments. -
FIGS. 10A-B are graphs of example experimental results measured using example embodiments disclosed herein. - Avalanche breakdown can occur in an LDMOS device when a reverse-bias voltage developed across a source region and drain region of the LDMOS exceeds a breakdown voltage level of the LDMOS device. When avalanche breakdown occurs, the LDMOS can be damaged or destroyed. One way to mitigate the risk of an avalanche breakdown event is to implement a reverse-biased diode in parallel with the LDMOS device. In such embodiments, a cathode region of the diode is electrically coupled to the drain region of the LDMOS device, and an anode region of the diode is electrically coupled to the source region of the LDMOS device. The diode is configured to have a target (e.g., desired) diode breakdown voltage level that is less than a breakdown voltage that would cause an avalanche breakdown event to occur in the LDMOS device. When a reverse-bias voltage exceeds the diode's breakdown voltage, the diode conducts a large amount of current. This current flow reduces or eliminates the reverse-bias voltage across the LDMOS device. Because the reverse-bias voltage across the LDMOS is reduced or eliminated the LDMOS is prevented from experiencing an avalanche breakdown event.
- In example embodiments and methods described herein, one or more diodes are advantageously monolithically integrated with one or more LDMOS devices on a common substrate of a semiconductor device. The semiconductor device includes one or more active fingers and one or more dummy fingers (which are sometimes also referred to as termination fingers). In some embodiments, the dummy fingers are fingers of a multi-finger semiconductor device that are adjacent to a terminating perimeter (e.g., an outside perimeter) of the semiconductor device. In some embodiments, there are multiple fingers adjacent to the terminating perimeter of the semiconductor device that are configured to be dummy fingers. In some embodiments a dummy finger is a finger of a multi-finger semiconductor device having a control node (e.g., a gate electrode) that is not electrically coupled to corresponding control nodes (e.g., gate electrodes) of active fingers of the semiconductor device. In some embodiments, the LDMOS devices are formed within one or more of the active fingers and diodes are formed in one or more of the dummy fingers. These diodes are electrically coupled to be in parallel with the LDMOS devices formed in one or more active fingers of the semiconductor device. The diode or diodes formed in the dummy fingers are configured to have a breakdown voltage level that is below a reverse-bias voltage level that would trigger an avalanche event in the LDMOS formed in the active fingers. Thus, the area of the semiconductor that would typically be wasted by the dummy fingers is advantageously repurposed as one or more diodes to extend and protect the life of the LDMOS formed in the active fingers. Additionally, because the dummy fingers are similar to the active fingers, a process flow to create the semiconductor device is advantageously simplified as compared to a process flow to monolithically integrate dissimilar semiconductor devices.
-
FIG. 1 shows a simplified prior art orthoscopic diagram of amulti-finger semiconductor device 100. Thesemiconductor device 100 generally includes two or moreactive fingers 102 and two ormore dummy fingers 104. An LDMOS device is formed in theactive fingers 102, as shown by alternating source regions S2-3, gate electrodes G2-4, and drain regions D2-3. A metallization layer (not shown) may be used to electrically couple corresponding regions of theactive fingers 102 together as shown schematically. For example, a metallization layer may electrically couple each of the gate electrodes G2-4 of theactive fingers 102 together; another metallization layer may electrically couple each of the source regions S2-3 of theactive fingers 102 together, and so on. Thedummy fingers 104 are typically positioned near an outside perimeter of thesemiconductor device 100 to minimize peripheral effects of a process flow used to form thesemiconductor device 100. Thedummy fingers 104 include alternating source S1-n regions, gate electrodes G1-n, and drain regions D1-n. that are similar to corresponding regions of theactive fingers 102, with some exceptions. For example, regions of thedummy fingers 104 may not be electrically coupled to corresponding regions within the active fingers 102 (e.g., G1 is typically electrically isolated from G2). -
FIG. 2 shows a simplified orthoscopic diagram of amulti-finger semiconductor device 200, in accordance with some embodiments. Some portions of thesemiconductor device 200 understood by one of skill in the art to be present have been omitted fromFIG. 2 for simplicity. Thesemiconductor device 200 generally includes two or moreactive fingers 202 and two ormore dummy fingers 204. Thedummy fingers 204 are typically positioned near an outside perimeter of thesemiconductor device 200, though in some embodiments thedummy fingers 204 are interleaved between theactive fingers 202. Across-section cutting line 203 through a portion of theactive fingers 202 corresponds to a portion of an LDMOS shown and discussed with reference toFIG. 3 . Across-section cutting line 205 through a portion of thedummy fingers 204 corresponds to a diode shown and discussed with reference toFIGS. 4-6 . - An LDMOS device is formed in the
active fingers 202, as shown by alternating source regions S2-3, gate electrodes G2-4, and drain regions D2-3. As described with reference toFIG. 1 , metallization layers (not shown) may be used to electrically couple corresponding regions of theactive fingers 202 together as shown schematically. Additionally, other metallization layers (not shown) may be used to electrically couple regions of thedummy fingers 204 to each other and to regions of theactive fingers 202 as shown schematically. For simplicity, only three LDMOS devices are shown in the active fingers 202 (e.g., as controlled by gate electrodes G2, G3, and G4). However, in some embodiments theactive fingers 202 include significantly more LDMOS devices. In the example, theactive fingers 202 constitute a single LDMOS device. In other embodiments, two or more independent LDMOS devices are formed in theactive fingers 202. For example, in such embodiments a first LDMOS device and a second LDMOS device are implemented by a set of multiple interleaved fingers and are interconnected by a set of alternating electrically conducting paths. - One or more regions of the
dummy fingers 204 are modified to form gated diode(s). The diodes have alternating anode regions A1-n, dummy gate electrodes G1-n, and cathode regions C1-n. Dummy gate electrodes G1-n of each diode are electrically coupled to a respective anode region A1-n of that diode to prevent a current conduction channel from forming in a body region of the diode. The dummy gate electrode is called a “dummy” gate electrode because it is not configured to receive a gate voltage. Diodes formed in thedummy fingers 204 are electrically coupled in parallel to the LDMOS formed in theactive fingers 202. As shown, the anode regions A1-n formed in thedummy fingers 204 are electrically coupled to the source regions S2-3 of the LDMOS formed in theactive fingers 202. Likewise, the cathode regions C1-n formed in thedummy fingers 204 are electrically coupled to the drain regions D2-3 of the LDMOS formed in theactive fingers 202. A ratio of diodes to LDMOS devices is chosen based on desired performance, among other factors. In some embodiments, there are ten LDMOS devices for every one diode (a ratio of 10-1). In some embodiments, this ratio is 1-to-1, 1-2, 2-1, 2-2, 5-1, and so on. In some embodiments, this ratio is 20-1, 50-1, 100-1, so on. In some embodiments, thesemiconductor device 200 is designed to have the smallest number ofdummy fingers 204 possible while still meeting other design, process and/or performance criteria. - As shown, surface area of the
semiconductor device 200 that would typically be wasted by thedummy fingers 204 is advantageously repurposed as one or more diodes to extend and protect the life of the LDMOS formed in theactive fingers 202. That is, the diode or diodes formed in thedummy fingers 204 are configured to have a target breakdown voltage level that is below a reverse-bias voltage level that would trigger an avalanche event in the LDMOS formed in theactive fingers 202. Thus, diodes formed in thedummy fingers 204 advantageously reduce or eliminate the chances of an avalanche event occurring within the LDMOS formed in theactive fingers 202. Additionally, because thedummy fingers 204 are similar to theactive fingers 202, a process flow to create thesemiconductor device 200 is advantageously simplified as compared to a process flow to monolithically integrate dissimilar semiconductor devices, e.g., an LDMOS device and a separately formed reverse-biased diode in parallel with the LDMOS device. -
FIG. 3 is a simplified cross-section diagram, taken through thecutting line 203 ofFIG. 2 , of anexample LDMOS device 302 formed in theactive fingers 202, in accordance with some embodiments. TheLDMOS 302 generally includes asubstrate 310, an optional buried insulator layer 312 (as indicated by dashed lines), and anactive region 314 formed over thesubstrate 310 or over the buriedinsulator layer 312. Theactive region 314 can be any of a doped portion of the bulk of a semiconductor wafer, a localized well formed in a larger doped portion of a semiconductor wager, an active layer of a semiconductor-on-insulator (SOI) wafer, and a localized well formed in an SOI wafer. In the example shown, theactive region 314 is a thin film formed over thesubstrate 310 or over the buriedinsulator layer 312. Some portions of theLDMOS 302 understood by one of skill in the art to be present have been omitted fromFIG. 3 for simplicity. For example, one or more metallization layers and interconnects are not shown, though are understood to be present. Theactive region 314 generally includes doped semiconductor regions of a first conductivity type and regions of a second conductivity type, formed by, example, by implanting impurities into theactive region 314. For example, the regions of the first conductivity type can be formed by implanting one kind of dopant atom, and the regions of the second conductivity type can be formed by implanting another kind of dopant atom. In some embodiments the first conductivity type is n-type and the second conductivity type is p-type. In other embodiments, the first conductivity type is p-type and the second conductivity type is n-type. The regions of the first conductivity type include asource region 316, adrain region 318, anLDD region 320, and a buriedregion 326. The regions of the second conductivity type include abody region 322, asource contact region 323, and a buried well 324. Asilicide layer 330 on a lateralpolysilicon gate electrode 328 forms a gate bus which is electrically coupled to a gate terminal (G) located in a third dimension. Lateral is defined herein as being within a plane that is parallel to a top surface plane of thesubstrate 310. A shieldingstructure 336 is formed as a lateral extension of a conductive layer lining a source trench, shown on the left side of theLDMOS 302, which is filled with top metal to form asource contact electrode 332. Thesource contact electrode 332 is electrically coupled to a source terminal (S) located in a third dimension. Top metal also forms adrain contact electrode 334 which is electrically coupled to a drain terminal (D) located in a third dimension. A dielectric 338 electrically insulates portions of theactive region 314. Alateral distance 340 between an edge of thegate electrode 328 and the nearest edge of thedrain region 318 is shown for reference with respect toFIGS. 4-5 . Alateral distance 352 between an edge of the buried well 324 and the nearest edge of thedrain region 318 is shown for reference with respect toFIGS. 5-6 . - When sufficient gate voltage is applied to the
gate electrode 328, theLDMOS 302 is in an on state. In the on state, a conduction channel forms between thesource region 316 and thedrain region 318 and current flows in the conduction channel. Normally when no gate voltage is applied to thegate electrode 328, the conduction channel is not formed, and theLDMOS 302 is in an off state. However, if a reverse-bias voltage that exceeds a breakdown voltage of theLDMOS 302 is applied across thesource region 316 and thedrain region 318, an avalanche event can occur, whereby uncontrolled current flows between these regions regardless of whether a gate voltage is applied to thegate electrode 328. -
FIG. 4 is a simplified cross-section diagram, taken through thecutting line 205 ofFIG. 2 , of anexample diode 404 formed in thedummy fingers 204, in accordance with some embodiments. Thediode 404 generally includes asubstrate 410, an optionalburied insulator layer 412, and anactive region 414 formed over thesubstrate 410 or over the buriedinsulator layer 412. Some portions of thediode 404 understood by one of skill in the art to be present have been omitted fromFIG. 4 for simplicity. For example, metallization layers and other interconnects understood to be present are omitted fromFIG. 4 . In some embodiments, thesubstrate 410 and thesubstrate 310 ofFIG. 3 are portions of the same substrate. That is, in such embodiments, theLDMOS 302 and thediode 404 are formed monolithically on the same substrate. Similarly, in some embodiments, the optional buriedinsulator layer 412 and the optional buriedinsulator layer 312 ofFIG. 3 are portions of the same buried insulator layer. - The
active region 414 generally includes regions of the first conductivity type and regions of the second conductivity type in accordance with respective regions in theactive region 314 described with reference toFIG. 3 . In some embodiments, regions of the first conductivity type of thediode 404 have the same doping depth, concentration and lateral extent as corresponding regions of theLDMOS 302. Similarly, in some embodiments, regions of the second conductivity type of thediode 404 have the same doping depth, concentration and lateral extent as corresponding regions of theLDMOS 302. The regions of the first conductivity type include acathode contact region 418, anLDD region 420, and a buriedregion 426. The regions of the second conductivity type include abody region 422, ananode contact region 423, and a buried well 424. A source region, similar to thesource region 316 of theLDMOS 302, is omitted from thediode 404. Omitting a source region advantageously creates an anode region comprised of thebody region 422, the buried well 424, and theanode contact region 423, each of these regions being of the second conductivity type. Top metal forms ananode contact electrode 432 which is electrically coupled to an anode terminal (A) located in a third dimension. Top metal also forms acathode contact electrode 434 which is electrically coupled to a cathode terminal (C) located in a third dimension. Theanode contact region 423 is electrically coupled to sourcecontact region 323 of theLDMOS 302, and thecathode contact region 418 is electrically coupled to thedrain region 318 of the LDMOS 302 (e.g., by top metal). Alateral gate electrode 428 with asilicide layer 430 is electrically coupled to theanode contact region 423. Thegate electrode 428 is electrically isolated from thegate electrode 328 of theLDMOS 302. A dielectric 438 electrically insulates portions of theactive region 414. - By changing lateral distances between doped regions of the
diode 404, or by making other modifications that will be discussed, a target breakdown voltage (e.g., a desired breakdown voltage chosen at design time) of thediode 404 is configured to be less than a breakdown voltage of theLDMOS 302. For example, in the embodiment shown inFIG. 4 , alateral distance 440 between thegate electrode 428 and the nearest edge of thecathode contact region 418 is the same as thelateral distance 340 shown inFIG. 3 . Likewise, alateral distance 452 between the buried well 424 and the nearest edge of thecathode contact region 418 is the same as thelateral distance 352 shown inFIG. 3 . However, given the same lateral distances 440 and 452, a target breakdown voltage of thediode 404 is reduced by forming thediode 404 such that atruncated shielding structure 436 does not overlap any portion of the gate electrode 428 (e.g., as compared to the lateral extent of the shieldingstructure 336 over thegate electrode 328 shown inFIG. 3 ). In some embodiments, no portion of thetruncated shielding structure 436 is included as part of the diode 404 (e.g., the shieldingstructure 436 is not formed as part of a process flow to form the diode 404). Removing or omitting the shieldingstructure 436 will cause the breakdown voltage of thediode 404 to decrease due to lack of carrier depletion previously provided by the shielding structure. - In some embodiments, the
gate electrode 428 is electrically shorted to theanode contact region 423 by a metal. Electrically shorting thegate electrode 428 to theanode contact region 423 advantageously prevents a conduction channel from forming in thediode 404, thereby reducing leakage current under high-frequency operation of the semiconductor device. In other embodiments, aresistor 444 couples thegate electrode 428 to theanode contact region 423. During an electrostatic discharge event, transient current through theresistor 444 will cause a voltage drop that inverts the region under thegate electrode 428 and forms a conduction channel. By coupling thegate electrode 428 to theanode contact region 423 through theresistor 444, a trigger voltage of thediode 404 is advantageously lowered as compared to embodiments of thediode 404 where thegate electrode 428 is electrically shorted to theanode contact region 423. Additionally, because a conduction channel is formed due to inversion, avalanche robustness of thediode 404 is advantageously increased. - The
diode 404 is electrically coupled in parallel to theLDMOS 302 as previously described. As such, a reverse-bias voltage applied across thedrain region 318 and thesource region 316 of theLDMOS 302 will also be present across thecathode contact region 418 and theanode contact region 423 of thediode 404. If that reverse-bias voltage exceeds a breakdown voltage of thediode 404, current will flow from thecathode contact region 418 to theanode contact region 423. This flow of current will cause the reverse-bias voltage across theLDMOS 302 to be reduced or eliminated. Thus, an avalanche event is prevented from occurring within theLDMOS 302, thereby protecting theLDMOS 302 from potential damage. -
FIG. 5 is a simplified cross-section diagram, taken through thecutting line 205 ofFIG. 2 , of anexample diode 504 formed in thedummy fingers 204, in accordance with some embodiments. In the embodiment shown, a target breakdown voltage of thediode 504 is modified as compared to thediode 404 by reducing alateral distance 540 between alateral gate electrode 528 and the nearest edge of acathode contact region 518. Other regions of thediode 504 are the same or similar to like numbered regions and features of thediode 404. For example, abody region 522 is the same or similar to thebody region 422, a buried well 524 is similar to the buried well 424, asubstrate 510 is similar to thesubstrate 410, and so on Likewise, embodiments of electrical couplings and electrical isolations of thediode 504 are the same or similar to embodiments of electrical couplings and electrical isolations of thediode 404. Alateral distance 552 between an edge of the buried well 524 and the nearest edge of thecathode contact region 518 is shown for reference with respect toFIG. 6 . - The
diode 504 generally includes asubstrate 510, an optionalburied insulator layer 512, and anactive region 514 formed over thesubstrate 510 or over the buriedinsulator layer 512. Some portions of thediode 504 understood by one of skill in the art to be present have been omitted fromFIG. 5 for simplicity. For example, metallization layers and other interconnects understood to be present are omitted fromFIG. 5 . Theactive region 514 generally includes regions of the first conductivity type and regions of the second conductivity type in accordance with respective regions in theactive region 314. In some embodiments, regions of the first conductivity type of thediode 504 have the same doping depth and concentration as corresponding regions of theLDMOS 302, but the lateral extents differ. Similarly, in some embodiments, regions of the second conductivity type of thediode 504 have the same doping depth and concentration as corresponding regions of theLDMOS 302, but the lateral extents differ. The regions of the first conductivity type include acathode contact region 518, anLDD region 520, and a buriedregion 526. The regions of the second conductivity type include abody region 522, ananode contact region 523, and a buried well 524. A source region, similar to thesource region 316 of theLDMOS 302, is omitted from thediode 504. Omitting the source region creates an anode region within thediode 504. The anode region includes theanode contact region 523, thebody region 522 and the buried well 524, each region being of the second conductivity type. Top metal forms ananode contact electrode 532 which is electrically coupled to an anode terminal (A) located in a third dimension. Top metal also forms acathode contact electrode 534 which is electrically coupled to a cathode terminal (C) located in a third dimension. Theanode contact region 523 is electrically coupled to thesource contact region 323 of theLDMOS 302, and thecathode contact region 518 is electrically coupled to thedrain region 318 of the LDMOS 302 (e.g., by top metal). Agate electrode 528 with asilicide layer 530 is electrically coupled to theanode contact region 523 either directly (e.g., by top metal), or through anoptional resistor 544 which is the same or similar to theresistor 444. Thegate electrode 528 is electrically isolated from thegate electrode 328 of theLDMOS 302. A dielectric 538 electrically insulates portions of theactive region 514. A shieldingstructure 536 overlaps (e.g., extends laterally over) thegate electrode 528. With no other modifications, the lateral extension of the shieldingstructure 536 would raise a target breakdown voltage of thediode 504 as compared to thediode 404. However, in the embodiment shown, thelateral distance 540 is reduced as compared to both thelateral distance 440 ofdiode 404 and thelateral distance 340 of theLDMOS 302. This reduction in lateral distance reduces the target breakdown voltage of thediode 504 as compared to thediode 404. Additionally, thelateral distance 552 is reduced as compared to both thelateral distance 452 of thediode 404 and thelateral distance 352 of theLDMOS 302. This further reduces the breakdown voltage of thediode 504 as compared to thediode 404. Thelateral distance 540 and thelateral distance 552 can be chosen at design time such that a target breakdown voltage of thediode 504 is lower than a breakdown voltage of theLDMOS 302. -
FIG. 6 is a simplified cross-section diagram, taken through thecutting line 205 ofFIG. 2 , of anexample diode 604 formed in thedummy fingers 204, in accordance with some embodiments. In the embodiment shown, a breakdown voltage of thediode 604 is modified as compared to thediode 504 by reducing alateral distance 652 between a buried well 624 and the nearest edge of acathode contact region 618 as compared to thelateral distance 552 of thediode 504. Other regions of thediode 604 are the same or similar to like numbered regions and features of thediode 504. For example, abody region 622 is the same or similar to thebody region 522, a buried well 624 is similar to the buried well 524 (except with regards to a modified lateral extent of the buried well 624), asubstrate 610 is similar to thesubstrate 510, and so on. Likewise, embodiments of electrical couplings and electrical isolations of thediode 604 are the same or similar to embodiments of electrical couplings and electrical isolations of thediode 504. - The
diode 604 generally includes asubstrate 610, an optionalburied insulator layer 612, and anactive region 614 formed over thesubstrate 610 or over the buriedinsulator layer 612. Some portions of thediode 604 understood by one of skill in the art to be present have been omitted fromFIG. 6 for simplicity. For example, metallization layers and other interconnects understood to be present are omitted fromFIG. 6 . Theactive region 614 generally includes regions of the first conductivity type and regions of the second conductivity type in accordance with respective regions in theactive region 314 of theLDMOS 302. In some embodiments, regions of the first conductivity type of thediode 604 have the same doping depth and concentration as corresponding regions of theLDMOS 302, but the lateral extents differ. Similarly, in some embodiments, regions of the second conductivity type of thediode 604 have the same doping depth and concentration as corresponding regions of theLDMOS 302, but the lateral extents differ. The regions of the first conductivity type include acathode contact region 618, anLDD region 620, and a buriedregion 626. The regions of the second conductivity type include abody region 622, ananode contact region 623, and the buried well 624. A source region, similar to thesource region 316, is omitted from thediode 604. Omitting a source region is omitted creates an anode region within thediode 604. The anode region includes theanode contact region 623, thebody region 622 and the buried well 624, each region being of the second conductivity type. Top metal forms ananode contact electrode 632 which is electrically coupled to an anode terminal (A) located in a third dimension. Top metal also forms acathode contact electrode 634 which is electrically coupled to a cathode terminal (C) located in a third dimension. Theanode contact region 623 is electrically coupled to sourcecontact region 323 of theLDMOS 302, and thecathode contact region 618 is electrically coupled to thedrain region 318 of the LDMOS 302 (e.g., by top metal). Alateral gate electrode 628 with asilicide layer 630 is electrically coupled to theanode contact region 623 either directly (e.g., by top metal), or through anoptional resistor 644 which is the same or similar to theresistor 444. Thegate electrode 628 is electrically isolated from thegate electrode 328 of theLDMOS 302. A dielectric 638 electrically insulates portions of theactive region 614. A shieldingstructure 636 extends laterally over thegate electrode 628. A target breakdown voltage of thediode 604 is further modified from the target breakdown voltage of thediode 504 by the reduction of thelateral distance 652 as compared to thelateral distance 552 of thediode 504. Thelateral distance 652 can be designed such that a target breakdown voltage of thediode 604 is lower than a breakdown voltage of theLDMOS 302. -
FIG. 7 shows a simplified orthoscopic diagram of amulti-finger semiconductor device 700, in accordance with some embodiments. Thesemiconductor device 700 generally includes asubstrate 710, a buriedinsulator layer 712, and anactive region 714. Theactive region 714 generally includes one or moreactive fingers 702 and one ormore dummy fingers 704. As shown, protective diodes are formed in thedummy fingers 704, and LDMOS devices are formed in theactive fingers 702. In the embodiment shown, insulatingbarrier regions 746 electrically isolate theactive fingers 702 from thedummy fingers 704. In some embodiments, theinsulator barrier regions 746 are shallow trench isolation (STI) regions. In other embodiments, the insulator barrier regions are deep trench isolation regions (DTI). Electrical connections in a third dimension shown schematically as a dashedline 762 electrically couple cathode regions (C) of the diodes to drain regions (D) of the LDMOS devices, and electrical connections in a third dimension shown schematically as a dashedline 764 electrically couple anode regions (A) of the diodes to source regions (S) of the LDMOS devices. -
FIG. 8 shows a simplified orthoscopic diagram of amulti-finger semiconductor device 800, in accordance with some embodiments. Thesemiconductor device 800 generally includes asubstrate 810, a buriedinsulator layer 812, and anactive region 814. Theactive region 814 generally includes one or moreactive fingers 802 and one ormore dummy fingers 804. As shown, protective diodes are formed in thedummy fingers 804, and LDMOS devices are formed in theactive fingers 802. In the embodiment shown, insulatingbarrier regions 846 electrically isolate adjacent LDMOS devices formed in theactive fingers 802, as well as electrically isolate theactive fingers 802 from thedummy fingers 804. Electrical connections in a third dimension shown schematically as a dashedline 862 couple cathode regions (C) of the diodes to drain regions (D) of the LDMOS devices, and electrical connections in a third dimension shown schematically as a dashedline 864 electrically couple anode regions (A) of the diodes to source regions (S) of the LDMOS devices. -
FIG. 9 shows a simplified orthoscopic diagram of amulti-finger semiconductor device 900, in accordance with some embodiments. Thesemiconductor device 900 generally includes asubstrate 910, a buriedinsulator layer 912, and anactive region 914. Theactive region 914 generally includes one or moreactive fingers 902 interleaved with one ormore dummy fingers 904. As shown, protective diodes are formed in thedummy fingers 904, and LDMOS devices are formed in theactive fingers 902. In the embodiment shown, insulatingbarrier regions 946 electrically isolate LDMOS devices formed in theactive fingers 802 from adjacent diodes formed in thedummy fingers 904. Electrical connections in a third dimension shown schematically as a dashedline 962 couple cathode regions (C) of the diodes to drain regions (D) of the LDMOS devices, and electrical connections in a third dimension shown schematically as a dashedline 964 electrically couple anode regions (A) of the diodes to source regions (S) of the LDMOS devices. -
FIGS. 10A-B are simplifiedgraphs Lines LDMOS 302.Line 1064 is a TLP curve generated using a diode that is similar to thediode 504 with a direct electrical coupling of thegate electrode 428 to theanode contact region 423 and having a shielding structure similar to the shieldingstructure 336.Line 1074 is a TLP curve generated using a diode similar to thediode line 1064 to theline 1062 shows a measured indication of ESD robustness of thediode 504 as being two times greater than a measured indication of ESD robustness of theLDMOS 302. A comparison ofline 1074 toline 1072 shows a measured indication of ESD robustness of thediode 404 or 604 (or other similar embodiments which match a breakdown voltage of the LDMOS 302) as being seven times greater than a measured indication of ESD robustness of theLDMOS 302. - Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which have been illustrated in the accompanying figures. Each example has been provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, while the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only and is not intended to limit the invention.
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TW108106368A TWI810249B (en) | 2018-04-04 | 2019-02-25 | Avalanche robust ldmos |
CN201980019750.4A CN111868932A (en) | 2018-04-04 | 2019-03-22 | Avalanche robustness LDMOS |
PCT/IB2019/052355 WO2019193447A1 (en) | 2018-04-04 | 2019-03-22 | Avalanche robust ldmos |
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US6140678A (en) | 1995-06-02 | 2000-10-31 | Siliconix Incorporated | Trench-gated power MOSFET with protective diode |
US6794719B2 (en) | 2001-06-28 | 2004-09-21 | Koninklijke Philips Electronics N.V. | HV-SOI LDMOS device with integrated diode to improve reliability and avalanche ruggedness |
EP1402574A2 (en) * | 2001-07-05 | 2004-03-31 | Sarnoff Corporation | Electrostatic discharge (esd) protection device with simultaneous and distributed self-biasing for multi-finger turn-on |
US7719054B2 (en) | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
US7592673B2 (en) | 2006-03-31 | 2009-09-22 | Freescale Semiconductor, Inc. | ESD protection circuit with isolated diode element and method thereof |
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US8614480B2 (en) | 2011-07-05 | 2013-12-24 | Texas Instruments Incorporated | Power MOSFET with integrated gate resistor and diode-connected MOSFET |
US8994105B2 (en) * | 2012-07-31 | 2015-03-31 | Azure Silicon LLC | Power device integration on a common substrate |
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