US20190293866A1 - Test systems and methods for chips in wafer scale photonic systems - Google Patents
Test systems and methods for chips in wafer scale photonic systems Download PDFInfo
- Publication number
- US20190293866A1 US20190293866A1 US16/439,196 US201916439196A US2019293866A1 US 20190293866 A1 US20190293866 A1 US 20190293866A1 US 201916439196 A US201916439196 A US 201916439196A US 2019293866 A1 US2019293866 A1 US 2019293866A1
- Authority
- US
- United States
- Prior art keywords
- wafer
- chip
- test
- photonic
- coupler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
- G02B6/124—Geodesic lenses or integrated gratings
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/302—Contactless testing
- G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
- G01M11/00—Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
- G01M11/30—Testing of optical devices, constituted by fibre optics or optical waveguides
Definitions
- the invention relates to systems and methods for testing semiconductor devices in general and particularly to systems and methods that provide systems and methods for qualification tests for devices present on uncut wafers.
- a significant expense in the production of optical devices is test during manufacture.
- the devices are fabricated on a single wafer and usually need to be diced into many separate chips that are then tested individually. When manipulating the chips individually there is the possibility of damaging the chip. Some packaging may also be needed, such as wire bonding or fiber attach, before testing can occur. Testing discrete chips that need processing before evaluating for failure is a costly process.
- a preferred method is to test each system on wafer before dicing the wafer into individual chips.
- the invention features a qualification apparatus for a photonic chip on a substrate, comprising: a wafer having constructed thereon at least one photonic chip, the photonic chip comprising a circuit having an operating port configured to be used during normal operation of the photonic chip, the photonic chip configured to be separated from the wafer; the wafer having constructed thereon a test port comprising a grating coupler in optical communication with the circuit, the grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of the wafer, the grating coupler configured to be used during a qualification test of the photonic chip which is conducted prior to the photonic chip being separated from the wafer.
- the operating port comprises an edge coupler in optical communication with the circuit.
- the operating port comprises the grating coupler in optical communication with said circuit.
- the grating coupler in optical communication with the circuit is in optical communication with a second edge coupler by way of an optical waveguide, and the second edge coupler is in optical communication with the edge coupler of the photonic chip.
- the grating coupler is situated on a sacrificial region of the wafer, the sacrificial region configured to be mechanically separated from the photonic chip and discarded upon completion of the qualification test.
- the grating coupler in optical communication with the circuit is in optical communication with the circuit by way of an optical waveguide and a directional coupler.
- the grating coupler is situated on the photonic chip.
- the grating coupler is configured to be removed upon completion of the qualification test.
- the grating coupler is configured to be placed onto an adjacent chip.
- the grating coupler is configured to be removed upon completion of the qualification test.
- the invention relates to a method of manufacturing a qualification apparatus for a photonic chip on a substrate.
- the method comprises the steps of: fabricating on a substrate at least one photonic chip, the photonic chip comprising a circuit having an operating port configured to be used during normal operation of the photonic chip, the photonic chip configured to be separated from other photonic chips on the wafer; and fabricating on the wafer a test port comprising a grating coupler in optical communication with the circuit, the grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of the wafer, the grating coupler configured to be used during a qualification test of the photonic chip which is conducted prior to the photonic chip being separated from other photonic chips on the wafer.
- the invention relates to a method of operating a qualification apparatus for a photonic chip on a substrate.
- the method comprises the steps of: providing a qualification apparatus for a photonic chip on a substrate, comprising: a photonic chip constructed on the wafer, the photonic chip comprising a circuit having an operating port configured to be used during normal operation of the photonic chip, the photonic chip configured to be separated from other photonic chips on the wafer; and a test port constructed on the wafer, the test port comprising a grating coupler in optical communication with the circuit, the grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of the wafer, the grating coupler configured to be used during a qualification test of the photonic chip which is conducted prior to the photonic chip being separated from other photonic chips on the wafer; and applying an optical test signal to the test port, and providing the circuit in the photonic chip one or more required operating input signals; observing as a result a response signal from the circuit; and performing at
- the method of operating a qualification apparatus for a photonic chip further comprises the step of separating the photonic chip from other photonic chips on the wafer in the event that the response signal indicates that the photonic chip is acceptable.
- the method of operating a qualification apparatus for a photonic chip further comprises the step of removing the grating coupler upon completion of the qualification test.
- the method of operating a qualification apparatus for a photonic chip further comprises the step of placing the grating coupler onto an adjacent chip.
- the method of operating a qualification apparatus for a photonic chip on a substrate further comprises the step of removing the grating coupler upon completion of the qualification test.
- FIG. 1 is a drawing that illustrates one embodiment in which a chip having a circuit or a photonic device to be tested is present on a wafer.
- FIG. 2 is a drawing that illustrates another embodiment in which a chip having a circuit or a photonic device to be tested is present on a wafer.
- FIG. 3 is a diagram in plan view of a plurality of chips fabricated on a wafer.
- FIG. 4 is a first cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon.
- FIG. 5 is a second cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon.
- FIG. 6 is a cross sectional view through a second embodiment of a wafer having a plurality of chips fabricated thereon.
- FIG. 7 is a cross sectional view through a third embodiment of a wafer having a plurality of chips fabricated thereon.
- FIG. 8 is a cross sectional view through a fourth embodiment of a wafer having a plurality of chips fabricated thereon.
- FIG. 9 is a cross sectional view through a fourth embodiment of a wafer having a plurality of chips fabricated thereon.
- substrate is meant to include a silicon wafer, a silicon on insulator (SOI) wafer, a semiconductor wafer comprising material such as III-V compounds such as GaAs, InP and alloys of such III-V compounds, and wafers made of materials that are not semiconducting such as quartz and alumina.
- SOI silicon on insulator
- the systems and methods of the invention allow one to measure every chip fabricated on the substrate, decide which chips are good (e.g., pass a qualification test) and which are bad (e.g., fail at least one element of a qualification test), mark the ones that are bad, separate the individual chips (for example by dicing), readily identify the bad chips after the chips are separated, and optionally throw the bad chips away or destroy them, while keeping the good chips.
- an edge coupler is used to provide optical input and/or to receive optical output from photonic devices (or circuits) on a chip (e.g., to behave as an operating port for the photonic devices or circuits on the chip during normal operation).
- photonic devices or circuits
- the optical test circuit remains on the completed chip and may optionally be used as an input port after the chip is fabricated and separated from the other chips on the substrate.
- a chip 110 having a circuit 120 or a photonic device 120 to be tested is present on a wafer 100 .
- the chip 110 includes an edge coupler 130 that communicates with the circuit 120 by way of a waveguide 125 .
- a second optical coupler can be used to provide an optical connection for testing the device (e.g., to provide a temporary optical port that allows the device to be tested, and which can subsequently be removed, masked off, or put into an unused state).
- a sacrificial region 115 on the wafer 100 adjacent the chip 110 can be provided.
- a second edge coupler 140 can be used to couple to the edge coupler 130 of the circuit 120 of interest.
- This second edge coupler 140 can then be connected to a grating coupler 150 by way of an optical waveguide 180 in order to provide an interface for light that couples out of the plane of the chip.
- Dicing lanes 160 are provided so that the chip 110 and the sacrificial region 115 can be cut out of the wafer 100 if the chip 110 is found to be acceptable after the test.
- the sacrificial region 115 may be separated from the chip 110 and discarded.
- test signal can be applied from a source that does not have to have its optical propagation direction in the plane of the chip.
- a resulting optical signal that may be generated by the circuit can be observed without having to place an optical sensor or receiver in the plane of the chip.
- an optical test source and/or an optical sensor or receiver
- an optical test source can be used that is oriented at an angle to a surface of the chip, and that can be rastered over the surface of the chip, so that individual grating couplers 150 present on the chip (for example, one grating couple per circuit fabricated on the chip) can each be accessed in a convenient manner, quickly, and at reduced expense. In this manner, a plurality of circuits on the chip can be tested without having to dice or saw the chip, and the location of each circuit and whether it passed or failed a given test can be logged.
- the sacrificial grating coupler chip includes an optical circuit useful in testing, such as a phase modulator to test a coherent mixer or a photodetector for alignment.
- a wafer 200 has a chip 210 fabricated thereon.
- the chip 210 has not been cleaved or sawed from the wafer 200 .
- the chip 210 is in optical communication with an edge coupler 230 by way of waveguide 225 , which is the optical interface that is to be used with the chip 210 if the chip 210 passes the required tests and inspections, and is then cleaved or sawed out of the wafer 200 .
- a test interface comprising a grating coupler 250 in optical communication with a directional coupler 270 by way of a waveguide 280 can be provided as a convenient optical connection to allow the circuit 210 to be tested.
- the grating coupler 250 provides the same advantages as are provided by the grating coupler 150 shown in FIG. 1 .
- wafer-scale test of edge coupled systems can be enabled by using a grating coupler 250 that is fed into the main optical path 225 using a directional coupler 270 .
- a directional coupler 270 As directional couplers are optically symmetric, a small tap is used so that little power is lost from the main optical circuit.
- a second tap can be used to measure an optical output of the circuit. Electrical outputs can be probed such that the electrical systems in the circuit can be tested in some way before dicing. After dicing and facet preparation, the testing structures are still present in the circuit, but provide minimal loss for the circuit operation.
- the testing interface e.g., a grating coupler and/or a second edge coupler
- the testing interface can be removed in a variety of ways. If polishing is the approach used for facet preparation, the extra area or the test grating coupler 150 , 250 can simply be polished away. If the facet is etched, the second set of edge couplers could exist on the other side of the etch trench, or the etch could proceed after circuit test. If the wafer is cleaved or sawed, the couplers could sit on opposite sides of the cleave (or saw) line. In some embodiments, such as illustrated in FIG.
- the optical connection provided by the grating coupler 250 can simply be ignored if the chip on which the circuit 210 is fabricated is housed or used in such a way that the grating coupler 250 is masked off or otherwise is rendered optically inaccessible.
- the grating coupler 250 may be left in place without being masked off, but the waveguide 280 is cut or removed, so that the grating coupler 250 is no longer in optical communication with the directional coupler 270 .
- wafer-scale test of edge coupled systems can be enabled by using a grating coupler that is fed into the main optical path using a directional coupler.
- a directional coupler As directional couplers are optically symmetric, a small tap is used so that little power is lost from the main optical circuit.
- a second tap can be used to measure an optical output of the circuit. Electrical outputs can be probed such that most systems can be tested in some way before dicing. After dicing and facet preparation, the testing structures are still present in the circuit, but provide minimal loss for the circuit operation.
- the gap between the edge couplers can be in the range of 50 to 100 ⁇ m. Due to the significant distance, the edge couplers can be designed to have large mode fields to minimize the optical divergence to just a few degrees.
- the etched facets are angled, so that one can deflect the optical beam of the edge coupler of the optical circuit in one direction or another.
- the second edge coupler can be designed to be higher or lower in the back end to match the location where the optical beam will hit. Further, the second edge couple may be configured such that the optical output propagates at an angle opposite the first edge coupler so that the two modes will overlap for minimal optical loss.
- FIG. 3 is a diagram in plan view of a plurality of chips 310 , 310 ′, 310 ′′, 310 ′′′ fabricated on a wafer 300 .
- each chip includes an edge coupler 320 connected by an optical waveguide to a circuit 320 , and a grating coupler 340 connected to a second edge coupler 350 .
- chip 310 ′ can be tested using the grating coupler and the second edge coupler present on adjacent chip 310 .
- additional grating couplers and second edge couplers can be provided in areas that do not carry circuits, such as in area 305 to allow testing of the circuits present on chips that are at the periphery of the wafer 300 .
- Dicing lanes 360 are illustrated to indicate how the chips may be separated from each other, with the test structures (the grating coupler and the second edge coupler) for the adjacent chip remaining after dicing.
- a dicing lane 370 (shown in a dotted line) may be used to remove the test structures so that the diced chip includes only the first edge coupler and the circuit, but not the test structures for a chip that is no long present after dicing.
- the chips that pass the qualification test and the chips that fail the qualification test are differentiated, for example by marking the chips that have failed at least one element of the qualification test, so that they can be separated from the good chips after the dicing operation.
- FIG. 4 is a first cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon.
- an edge coupler 400 that is part of the test structure and an edge coupler 420 that is connected to a circuit are present.
- the test edge coupler 400 is constructed so that it is quite close to the edge coupler 420 during testing so that optical communication between edge coupler 400 and edge coupler 420 will be good. However, during etching or dicing for separating chips, some of edge coupler 400 will be lost, while none of edge couple 420 will be removed or damaged.
- FIG. 5 is a second cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon.
- FIG. 5 which is a diagram similar to FIG. 4 but after etching has occurred, one sees that part of edge coupler 400 is gone, but the edge coupler 420 is intact.
- FIG. 6 is a cross sectional view through a second embodiment of a wafer having a plurality of chips fabricated thereon.
- an edge coupler 620 connected to a circuit on a chip (not shown) communicates with another edge coupler 600 as illustrated by the propagating light 610 that propagates across an etch trench.
- FIG. 7 is a cross sectional view through a third embodiment 700 of a wafer having a plurality of chips fabricated thereon.
- an edge coupler 730 connected to a circuit on a chip communicates with another edge coupler 700 as illustrated by the propagating light 720 that propagates across an etch trench at an angle.
- Propagating light 720 is situated at an angle to a direction of propagation in edge coupler 730 in order to accommodate edge coupler 710 , which is shown at a different height than edge coupler 730 .
- FIG. 8 is a cross sectional view through a fourth embodiment 800 of a wafer having a plurality of chips fabricated thereon.
- an edge coupler 840 connected to a circuit on a chip communicates with a grating coupler 810 as illustrated by the propagating light 830 that propagates across an etch trench at an angle.
- Propagating light 830 is situated at an angle to a direction of propagation in edge coupler 840 in order to accommodate grating coupler 810 , which is shown at a different height than edge coupler 840 .
- propagating light 820 from the grating coupler 810 to the edge coupler 840 .
- FIG. 9 is a cross sectional view through a fourth embodiment 900 of a wafer having a plurality of chips fabricated thereon.
- a first grating coupler 940 connected to a circuit on a chip communicates with a second grating coupler 910 as illustrated by the propagating light 930 that propagates across an etch trench at an angle.
- Propagating light 930 is situated at an angle to a direction of propagation in grating coupler 940 in order to accommodate grating coupler 910 , which is shown at a different height than grating coupler 940 .
- propagating light 920 from the grating coupler 910 to the grating coupler 940 .
- grating coupled taps can be used to observe signals from an actual system such as a coherent transceiver, so as to allow testing of the actual edge facet that will be used and will be coupled to an optical fiber.
- optical communication channel is intended to denote a single optical channel, such as light that can carry information using a specific carrier wavelength in a wavelength division multiplexed (WDM) system.
- WDM wavelength division multiplexed
- optical carrier is intended to denote a medium or a structure through which any number of optical signals including WDM signals can propagate, which by way of example can include gases such as air, a void such as a vacuum or extraterrestrial space, and structures such as optical fibers and optical waveguides.
Abstract
Description
- The invention relates to systems and methods for testing semiconductor devices in general and particularly to systems and methods that provide systems and methods for qualification tests for devices present on uncut wafers.
- A significant expense in the production of optical devices is test during manufacture. The devices are fabricated on a single wafer and usually need to be diced into many separate chips that are then tested individually. When manipulating the chips individually there is the possibility of damaging the chip. Some packaging may also be needed, such as wire bonding or fiber attach, before testing can occur. Testing discrete chips that need processing before evaluating for failure is a costly process. A preferred method is to test each system on wafer before dicing the wafer into individual chips.
- There is a need for improved systems and methods for qualifying photonic chips.
- According to one aspect, the invention features a qualification apparatus for a photonic chip on a substrate, comprising: a wafer having constructed thereon at least one photonic chip, the photonic chip comprising a circuit having an operating port configured to be used during normal operation of the photonic chip, the photonic chip configured to be separated from the wafer; the wafer having constructed thereon a test port comprising a grating coupler in optical communication with the circuit, the grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of the wafer, the grating coupler configured to be used during a qualification test of the photonic chip which is conducted prior to the photonic chip being separated from the wafer.
- In one embodiment, the operating port comprises an edge coupler in optical communication with the circuit.
- In another embodiment, the operating port comprises the grating coupler in optical communication with said circuit.
- In another embodiment, the grating coupler in optical communication with the circuit is in optical communication with a second edge coupler by way of an optical waveguide, and the second edge coupler is in optical communication with the edge coupler of the photonic chip.
- In yet another embodiment, the grating coupler is situated on a sacrificial region of the wafer, the sacrificial region configured to be mechanically separated from the photonic chip and discarded upon completion of the qualification test.
- In still another embodiment, the grating coupler in optical communication with the circuit is in optical communication with the circuit by way of an optical waveguide and a directional coupler.
- In a further embodiment, the grating coupler is situated on the photonic chip.
- In yet a further embodiment, the grating coupler is configured to be removed upon completion of the qualification test.
- In an additional embodiment, the grating coupler is configured to be placed onto an adjacent chip.
- In one more embodiment, the grating coupler is configured to be removed upon completion of the qualification test.
- According to another aspect, the invention relates to a method of manufacturing a qualification apparatus for a photonic chip on a substrate. The method comprises the steps of: fabricating on a substrate at least one photonic chip, the photonic chip comprising a circuit having an operating port configured to be used during normal operation of the photonic chip, the photonic chip configured to be separated from other photonic chips on the wafer; and fabricating on the wafer a test port comprising a grating coupler in optical communication with the circuit, the grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of the wafer, the grating coupler configured to be used during a qualification test of the photonic chip which is conducted prior to the photonic chip being separated from other photonic chips on the wafer.
- According to another aspect, the invention relates to a method of operating a qualification apparatus for a photonic chip on a substrate. The method comprises the steps of: providing a qualification apparatus for a photonic chip on a substrate, comprising: a photonic chip constructed on the wafer, the photonic chip comprising a circuit having an operating port configured to be used during normal operation of the photonic chip, the photonic chip configured to be separated from other photonic chips on the wafer; and a test port constructed on the wafer, the test port comprising a grating coupler in optical communication with the circuit, the grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of the wafer, the grating coupler configured to be used during a qualification test of the photonic chip which is conducted prior to the photonic chip being separated from other photonic chips on the wafer; and applying an optical test signal to the test port, and providing the circuit in the photonic chip one or more required operating input signals; observing as a result a response signal from the circuit; and performing at least one of recording the result, transmitting the result to a data handling system, or to displaying the result to a user.
- In one embodiment, the method of operating a qualification apparatus for a photonic chip further comprises the step of separating the photonic chip from other photonic chips on the wafer in the event that the response signal indicates that the photonic chip is acceptable.
- In another embodiment, the method of operating a qualification apparatus for a photonic chip further comprises the step of removing the grating coupler upon completion of the qualification test.
- In yet another embodiment, the method of operating a qualification apparatus for a photonic chip further comprises the step of placing the grating coupler onto an adjacent chip.
- In still another embodiment, the method of operating a qualification apparatus for a photonic chip on a substrate further comprises the step of removing the grating coupler upon completion of the qualification test.
- The foregoing and other objects, aspects, features, and advantages of the invention will become more apparent from the following description and from the claims.
- The objects and features of the invention can be better understood with reference to the drawings described below, and the claims. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the drawings, like numerals are used to indicate like parts throughout the various views.
-
FIG. 1 is a drawing that illustrates one embodiment in which a chip having a circuit or a photonic device to be tested is present on a wafer. -
FIG. 2 is a drawing that illustrates another embodiment in which a chip having a circuit or a photonic device to be tested is present on a wafer. -
FIG. 3 is a diagram in plan view of a plurality of chips fabricated on a wafer. -
FIG. 4 is a first cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon. -
FIG. 5 is a second cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon. -
FIG. 6 is a cross sectional view through a second embodiment of a wafer having a plurality of chips fabricated thereon. -
FIG. 7 is a cross sectional view through a third embodiment of a wafer having a plurality of chips fabricated thereon. -
FIG. 8 is a cross sectional view through a fourth embodiment of a wafer having a plurality of chips fabricated thereon. -
FIG. 9 is a cross sectional view through a fourth embodiment of a wafer having a plurality of chips fabricated thereon. - A list of acronyms and their usual meanings in the present document (unless otherwise explicitly stated to denote a different thing) are presented below.
-
- AMR Adabatic Micro-Ring
- APD Avalanche Photodetector
- ARM Anti-Reflection Microstructure
- ASE Amplified Spontaneous Emission
- BER Bit Error Rate
- BOX Buried Oxide
- CMOS Complementary Metal-Oxide-Semiconductor
- CMP Chemical-Mechanical Planarization
- DBR Distributed Bragg Reflector
- DC (optics) Directional Coupler
- DC (electronics) Direct Current
- DCA Digital Communication Analyzer
- DRC Design Rule Checking
- DUT Device Under Test
- ECL External Cavity Laser
- FDTD Finite Difference Time Domain
- FOM Figure of Merit
- FSR Free Spectral Range
- FWHM Full Width at Half Maximum
- GaAs Gallium Arsenide
- InP Indium Phosphide
- LiNO3 Lithium Niobate
- LIV Light intensity(L)-Current(I)-Voltage(V)
- MFD Mode Field Diameter
- MPW Multi Project Wafer
- NRZ Non-Return to Zero
- PIC Photonic Integrated Circuits
- PRBS Pseudo Random Bit Sequence
- PDFA Praseodymium-Doped-Fiber-Amplifier
- PSO Particle Swarm Optimization
- Q Quality factor
-
-
- QD Quantum Dot
- RSOA Reflective Semiconductor Optical Amplifier
- SOI Silicon on Insulator
- SEM Scanning Electron Microscope
- SMSR Single-Mode Suppression Ratio
- TEC Thermal Electric Cooler
- WDM Wavelength Division Multiplexing
- As used herein the term “substrate” is meant to include a silicon wafer, a silicon on insulator (SOI) wafer, a semiconductor wafer comprising material such as III-V compounds such as GaAs, InP and alloys of such III-V compounds, and wafers made of materials that are not semiconducting such as quartz and alumina.
- We describe systems and methods for wafer scale qualification of photonic systems that would otherwise need to be diced and processed before component qualification can occur. In brief, the systems and methods of the invention allow one to measure every chip fabricated on the substrate, decide which chips are good (e.g., pass a qualification test) and which are bad (e.g., fail at least one element of a qualification test), mark the ones that are bad, separate the individual chips (for example by dicing), readily identify the bad chips after the chips are separated, and optionally throw the bad chips away or destroy them, while keeping the good chips. In some embodiments, an edge coupler is used to provide optical input and/or to receive optical output from photonic devices (or circuits) on a chip (e.g., to behave as an operating port for the photonic devices or circuits on the chip during normal operation). In order to not introduce extra loss, it is desirable to keep the optical path of the final circuit unchanged as compared to the optical path of a test circuit. In some embodiments, the optical test circuit remains on the completed chip and may optionally be used as an input port after the chip is fabricated and separated from the other chips on the substrate.
- As illustrated in the embodiment shown in
FIG. 1 , achip 110 having acircuit 120 or aphotonic device 120 to be tested is present on awafer 100. Thechip 110 includes anedge coupler 130 that communicates with thecircuit 120 by way of awaveguide 125. - As illustrated in the embodiment shown in
FIG. 1 , a second optical coupler can be used to provide an optical connection for testing the device (e.g., to provide a temporary optical port that allows the device to be tested, and which can subsequently be removed, masked off, or put into an unused state). As shown in the embodiment ofFIG. 1 , asacrificial region 115 on thewafer 100 adjacent thechip 110 can be provided. In the sacrificial region 115 asecond edge coupler 140 can be used to couple to theedge coupler 130 of thecircuit 120 of interest. Thissecond edge coupler 140 can then be connected to agrating coupler 150 by way of anoptical waveguide 180 in order to provide an interface for light that couples out of the plane of the chip. Dicinglanes 160 are provided so that thechip 110 and thesacrificial region 115 can be cut out of thewafer 100 if thechip 110 is found to be acceptable after the test. Thesacrificial region 115 may be separated from thechip 110 and discarded. - One advantage of using a grating coupler is that the test signal can be applied from a source that does not have to have its optical propagation direction in the plane of the chip. In addition, a resulting optical signal that may be generated by the circuit can be observed without having to place an optical sensor or receiver in the plane of the chip. For example, an optical test source (and/or an optical sensor or receiver) can be used that is oriented at an angle to a surface of the chip, and that can be rastered over the surface of the chip, so that individual
grating couplers 150 present on the chip (for example, one grating couple per circuit fabricated on the chip) can each be accessed in a convenient manner, quickly, and at reduced expense. In this manner, a plurality of circuits on the chip can be tested without having to dice or saw the chip, and the location of each circuit and whether it passed or failed a given test can be logged. - In some embodiments, the sacrificial grating coupler chip includes an optical circuit useful in testing, such as a phase modulator to test a coherent mixer or a photodetector for alignment.
- As illustrated in another embodiment shown in
FIG. 2 , awafer 200 has achip 210 fabricated thereon. Thechip 210 has not been cleaved or sawed from thewafer 200. Thechip 210 is in optical communication with anedge coupler 230 by way ofwaveguide 225, which is the optical interface that is to be used with thechip 210 if thechip 210 passes the required tests and inspections, and is then cleaved or sawed out of thewafer 200. - As illustrated in the embodiment shown in
FIG. 2 , a test interface comprising agrating coupler 250 in optical communication with adirectional coupler 270 by way of awaveguide 280 can be provided as a convenient optical connection to allow thecircuit 210 to be tested. Once again, thegrating coupler 250 provides the same advantages as are provided by thegrating coupler 150 shown inFIG. 1 . - In the embodiment of
FIG. 2 , wafer-scale test of edge coupled systems can be enabled by using agrating coupler 250 that is fed into the mainoptical path 225 using adirectional coupler 270. As directional couplers are optically symmetric, a small tap is used so that little power is lost from the main optical circuit. A second tap can be used to measure an optical output of the circuit. Electrical outputs can be probed such that the electrical systems in the circuit can be tested in some way before dicing. After dicing and facet preparation, the testing structures are still present in the circuit, but provide minimal loss for the circuit operation. - After testing is completed, and depending on the method of facet fabrication, the testing interface (e.g., a grating coupler and/or a second edge coupler) can be removed in a variety of ways. If polishing is the approach used for facet preparation, the extra area or the
test grating coupler FIG. 2 , the optical connection provided by thegrating coupler 250 can simply be ignored if the chip on which thecircuit 210 is fabricated is housed or used in such a way that thegrating coupler 250 is masked off or otherwise is rendered optically inaccessible. In some alternative embodiments, thegrating coupler 250 may be left in place without being masked off, but thewaveguide 280 is cut or removed, so that thegrating coupler 250 is no longer in optical communication with thedirectional coupler 270. - In the embodiment of
FIG. 2 , wafer-scale test of edge coupled systems can be enabled by using a grating coupler that is fed into the main optical path using a directional coupler. As directional couplers are optically symmetric, a small tap is used so that little power is lost from the main optical circuit. A second tap can be used to measure an optical output of the circuit. Electrical outputs can be probed such that most systems can be tested in some way before dicing. After dicing and facet preparation, the testing structures are still present in the circuit, but provide minimal loss for the circuit operation. - In some embodiments, the gap between the edge couplers can be in the range of 50 to 100 μm. Due to the significant distance, the edge couplers can be designed to have large mode fields to minimize the optical divergence to just a few degrees.
- In a further embodiment, the etched facets are angled, so that one can deflect the optical beam of the edge coupler of the optical circuit in one direction or another. The second edge coupler can be designed to be higher or lower in the back end to match the location where the optical beam will hit. Further, the second edge couple may be configured such that the optical output propagates at an angle opposite the first edge coupler so that the two modes will overlap for minimal optical loss.
-
FIG. 3 is a diagram in plan view of a plurality ofchips wafer 300. InFIG. 3 , each chip includes anedge coupler 320 connected by an optical waveguide to acircuit 320, and agrating coupler 340 connected to asecond edge coupler 350. As should be apparent from the forgoing discussion,chip 310′ can be tested using the grating coupler and the second edge coupler present onadjacent chip 310. For chips at the periphery of the wafer, additional grating couplers and second edge couplers (not shown) can be provided in areas that do not carry circuits, such as inarea 305 to allow testing of the circuits present on chips that are at the periphery of thewafer 300. Dicinglanes 360 are illustrated to indicate how the chips may be separated from each other, with the test structures (the grating coupler and the second edge coupler) for the adjacent chip remaining after dicing. In another embodiment, a dicing lane 370 (shown in a dotted line) may be used to remove the test structures so that the diced chip includes only the first edge coupler and the circuit, but not the test structures for a chip that is no long present after dicing. During testing, the chips that pass the qualification test and the chips that fail the qualification test are differentiated, for example by marking the chips that have failed at least one element of the qualification test, so that they can be separated from the good chips after the dicing operation. -
FIG. 4 is a first cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon. As shown inFIG. 4 anedge coupler 400 that is part of the test structure and anedge coupler 420 that is connected to a circuit are present. Aregion 410 that can be used to etch to separate chips on a wafer, or that can be a dicing lane, is illustrated. Thetest edge coupler 400 is constructed so that it is quite close to theedge coupler 420 during testing so that optical communication betweenedge coupler 400 andedge coupler 420 will be good. However, during etching or dicing for separating chips, some ofedge coupler 400 will be lost, while none ofedge couple 420 will be removed or damaged. -
FIG. 5 is a second cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon. InFIG. 5 , which is a diagram similar toFIG. 4 but after etching has occurred, one sees that part ofedge coupler 400 is gone, but theedge coupler 420 is intact. -
FIG. 6 is a cross sectional view through a second embodiment of a wafer having a plurality of chips fabricated thereon. In the embodiment ofFIG. 6 , anedge coupler 620 connected to a circuit on a chip (not shown) communicates with anotheredge coupler 600 as illustrated by the propagating light 610 that propagates across an etch trench. -
FIG. 7 is a cross sectional view through athird embodiment 700 of a wafer having a plurality of chips fabricated thereon. In the embodiment ofFIG. 7 , anedge coupler 730 connected to a circuit on a chip (not shown) communicates with anotheredge coupler 700 as illustrated by the propagating light 720 that propagates across an etch trench at an angle. Propagating light 720 is situated at an angle to a direction of propagation inedge coupler 730 in order to accommodateedge coupler 710, which is shown at a different height thanedge coupler 730. -
FIG. 8 is a cross sectional view through afourth embodiment 800 of a wafer having a plurality of chips fabricated thereon. In the embodiment ofFIG. 8 , anedge coupler 840 connected to a circuit on a chip (not shown) communicates with agrating coupler 810 as illustrated by the propagating light 830 that propagates across an etch trench at an angle. Propagating light 830 is situated at an angle to a direction of propagation inedge coupler 840 in order to accommodategrating coupler 810, which is shown at a different height thanedge coupler 840. Also shown is propagating light 820 from thegrating coupler 810 to theedge coupler 840. -
FIG. 9 is a cross sectional view through afourth embodiment 900 of a wafer having a plurality of chips fabricated thereon. In the embodiment ofFIG. 9 , a firstgrating coupler 940 connected to a circuit on a chip (not shown) communicates with a secondgrating coupler 910 as illustrated by the propagating light 930 that propagates across an etch trench at an angle. Propagating light 930 is situated at an angle to a direction of propagation ingrating coupler 940 in order to accommodategrating coupler 910, which is shown at a different height than gratingcoupler 940. Also shown is propagating light 920 from thegrating coupler 910 to thegrating coupler 940. - Various additional embodiments and features can be used with the systems and methods of the invention.
- One can use on-chip photodiodes as monitors for edge couplers, using either taps or the structure shown in
FIG. 1 andFIG. 2 . - In some embodiments, one can use a plurality of coupler structures in sequence in order to characterize system losses.
- In some embodiments, one can use couplers facing one another across a wafer-scale etched trench, in order to directly characterize coupling losses.
- In some embodiments, grating coupled taps can be used to observe signals from an actual system such as a coherent transceiver, so as to allow testing of the actual edge facet that will be used and will be coupled to an optical fiber.
- In some embodiments, one can provide lithographically designed in-plane lenses on one or two axes in combination with the chip.
- In some embodiments, one may integrate polarization controllers and rotators with these structures.
- In some embodiments, one may integrate additional electro-optical circuitry in the test structure to aid in the qualification of the chips, such as an on-chip phase modulator.
- In some embodiments, one may integrate large photodiodes across the trench from the optical circuit's edge couplers, so as to monitor parameters such as insertion loss.
- Methods of designing and fabricating devices having elements similar to those described herein are described in one or more of U.S. Pat. Nos. 7,200,308, 7,339,724, 7,424,192, 7,480,434, 7,643,714, 7,760,970, 7,894,696, 8,031,985, 8,067,724, 8,098,965, 8,203,115, 8,237,102, 8,258,476, 8,270,778, 8,280,211, 8,311,374, 8,340,486, 8,380,016, 8,390,922, 8,798,406, and 8,818,141, each of which documents is hereby incorporated by reference herein in its entirety.
- Methods of testing photonic devices having elements similar to those described herein, and various kinds of test apparatus, are described in one or more of U.S. Pat. Nos. 7,200,308, 7,339,724, 7,424,192, 7,480,434, 7,643,714, 7,760,970, 7,894,696, 8,031,985, 8,067,724, 8,098,965, 8,203,115, 8,237,102, 8,258,476, 8,270,778, 8,280,211, 8,311,374, 8,340,486, 8,380,016, 8,390,922, 8,798,406, and 8,818,141, each of which documents is hereby incorporated by reference herein in its entirety.
- As used herein, the term “optical communication channel” is intended to denote a single optical channel, such as light that can carry information using a specific carrier wavelength in a wavelength division multiplexed (WDM) system.
- As used herein, the term “optical carrier” is intended to denote a medium or a structure through which any number of optical signals including WDM signals can propagate, which by way of example can include gases such as air, a void such as a vacuum or extraterrestrial space, and structures such as optical fibers and optical waveguides.
- Although the theoretical description given herein is thought to be correct, the operation of the devices described and claimed herein does not depend upon the accuracy or validity of the theoretical description. That is, later theoretical developments that may explain the observed results on a basis different from the theory presented herein will not detract from the inventions described herein.
- Any patent, patent application, patent application publication, journal article, book, published paper, or other publicly available material identified in the specification is hereby incorporated by reference herein in its entirety. Any material, or portion thereof, that is said to be incorporated by reference herein, but which conflicts with existing definitions, statements, or other disclosure material explicitly set forth herein is only incorporated to the extent that no conflict arises between that incorporated material and the present disclosure material. In the event of a conflict, the conflict is to be resolved in favor of the present disclosure as the preferred disclosure.
- While the present invention has been particularly shown and described with reference to the preferred mode as illustrated in the drawing, it will be understood by one skilled in the art that various changes in detail may be affected therein without departing from the spirit and scope of the invention as defined by the claims.
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/439,196 US20190293866A1 (en) | 2015-09-21 | 2019-06-12 | Test systems and methods for chips in wafer scale photonic systems |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/860,537 US10359567B2 (en) | 2015-09-21 | 2015-09-21 | Test systems and methods for chips in wafer scale photonic systems |
US16/439,196 US20190293866A1 (en) | 2015-09-21 | 2019-06-12 | Test systems and methods for chips in wafer scale photonic systems |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/860,537 Continuation US10359567B2 (en) | 2015-09-21 | 2015-09-21 | Test systems and methods for chips in wafer scale photonic systems |
Publications (1)
Publication Number | Publication Date |
---|---|
US20190293866A1 true US20190293866A1 (en) | 2019-09-26 |
Family
ID=57113724
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/860,537 Active 2035-11-28 US10359567B2 (en) | 2015-09-21 | 2015-09-21 | Test systems and methods for chips in wafer scale photonic systems |
US16/439,196 Abandoned US20190293866A1 (en) | 2015-09-21 | 2019-06-12 | Test systems and methods for chips in wafer scale photonic systems |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/860,537 Active 2035-11-28 US10359567B2 (en) | 2015-09-21 | 2015-09-21 | Test systems and methods for chips in wafer scale photonic systems |
Country Status (2)
Country | Link |
---|---|
US (2) | US10359567B2 (en) |
WO (1) | WO2017053308A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113325513A (en) * | 2020-02-28 | 2021-08-31 | 富士通光器件株式会社 | Optical device and method of testing optical device |
US20210270697A1 (en) * | 2020-03-02 | 2021-09-02 | Fujitsu Optical Components Limited | Optical device and optical device testing method |
US20220283366A1 (en) * | 2019-08-23 | 2022-09-08 | Nippon Telegraph And Telephone Corporation | Optical Circuit |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10012798B2 (en) * | 2016-06-30 | 2018-07-03 | International Business Machines Corporation | Sacrificial coupler for testing V-grooved integrated circuits |
US10042131B1 (en) * | 2017-04-05 | 2018-08-07 | Xilinx, Inc. | Architecture for silicon photonics enabling wafer probe and test |
US10145758B2 (en) * | 2017-04-28 | 2018-12-04 | Cisco Technology, Inc. | Wafer level optical probing structures for silicon photonics |
DE112018004026A5 (en) | 2017-08-07 | 2020-05-28 | Jenoptik Optical Systems Gmbh | LOCAL TOLERANCE SENSITIVE CONTACTING MODULE FOR CONTACTING OPTOELECTRONIC CHIPS |
JP6823571B2 (en) * | 2017-09-05 | 2021-02-03 | 日本電信電話株式会社 | Optical circuit |
JP2019207305A (en) * | 2018-05-29 | 2019-12-05 | 日本電信電話株式会社 | Optical inspection circuit |
JP7192255B2 (en) | 2018-05-31 | 2022-12-20 | 富士通オプティカルコンポーネンツ株式会社 | Optical device, optical module using same, and test method for optical device |
JP7103042B2 (en) * | 2018-08-03 | 2022-07-20 | 富士通オプティカルコンポーネンツ株式会社 | Optical devices, optical transceiver modules, and methods for manufacturing optical devices |
JP7107094B2 (en) | 2018-08-23 | 2022-07-27 | 富士通オプティカルコンポーネンツ株式会社 | Optical device and optical transceiver module |
US11163120B2 (en) * | 2018-11-16 | 2021-11-02 | Ayar Labs, Inc. | Fiber attach enabled wafer level fanout |
TWI672480B (en) * | 2018-12-03 | 2019-09-21 | 財團法人工業技術研究院 | Optical measurement apparatus and method |
JP7296835B2 (en) * | 2019-09-19 | 2023-06-23 | 株式会社ディスコ | WAFER PROCESSING METHOD AND CHIP MEASURING DEVICE |
TWI717047B (en) | 2019-10-04 | 2021-01-21 | 財團法人工業技術研究院 | Test device and heterogeneously integrated structure |
US11694935B2 (en) * | 2019-10-25 | 2023-07-04 | Ayar Labs, Inc. | Systems and methods for wafer-level photonic testing |
US11143821B1 (en) * | 2020-03-24 | 2021-10-12 | Mitsubishi Electric Research Laboratories, Inc. | Integrated grating coupler system |
CN112180505B (en) * | 2020-10-22 | 2022-08-16 | 武汉光谷信息光电子创新中心有限公司 | Photoelectric integrated chip |
US20220196732A1 (en) * | 2020-12-22 | 2022-06-23 | Intel Corporation | Active optical plug to optically or electrically test a photonics package |
CN112800715B (en) * | 2021-01-14 | 2021-09-24 | 国家数字交换系统工程技术研究中心 | Software definition on-chip system, data interaction method and system architecture |
CN113009624A (en) * | 2021-02-19 | 2021-06-22 | 中国科学院微电子研究所 | Optical device test structure and manufacturing method thereof |
US11788929B1 (en) * | 2022-09-29 | 2023-10-17 | Aeva, Inc. | Techniques for wafer level die testing using sacrificial structures |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030223672A1 (en) * | 2002-03-08 | 2003-12-04 | Joyner Charles H. | Insertion loss reduction, passivation and/or planarization and in-wafer testing of integrated optical components in photonic integrated circuits (PICs) |
US20120104389A1 (en) * | 2009-04-01 | 2012-05-03 | Neil David Whitbread | Sacrificial waveguide test structures |
US20150147042A1 (en) * | 2013-11-25 | 2015-05-28 | Panasonic Intellectual Property Management Co., Ltd. | Imaging apparatus and imaging method |
US20160109659A1 (en) * | 2014-10-15 | 2016-04-21 | Huawei Technologies Co., Ltd. | Stacked Photonic Chip Coupler for SOI Chip-Fiber Coupling |
US9459177B1 (en) * | 2015-05-15 | 2016-10-04 | Alcatel Lucent | Wafer-level testing of optical circuit devices |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4117854B2 (en) * | 1997-06-20 | 2008-07-16 | シャープ株式会社 | Waveguide type optical integrated circuit device and manufacturing method thereof |
US7283694B2 (en) * | 2001-10-09 | 2007-10-16 | Infinera Corporation | Transmitter photonic integrated circuits (TxPIC) and optical transport networks employing TxPICs |
US7378861B1 (en) | 2003-04-07 | 2008-05-27 | Luxtera, Inc. | Optical alignment loops for the wafer-level testing of optical and optoelectronic chips |
CA2558483C (en) | 2004-03-08 | 2015-01-06 | Sioptical, Inc. | Wafer-level opto-electronic testing apparatus and method |
US7424192B2 (en) | 2005-06-28 | 2008-09-09 | California Institute Of Technology | Frequency conversion with nonlinear optical polymers and high index contrast waveguides |
US7643714B2 (en) | 2005-06-28 | 2010-01-05 | California Institute Of Technology | Nanophotonic devices in silicon |
US7339724B2 (en) | 2005-06-28 | 2008-03-04 | California Institute Of Technology | Bremsstrahlung laser (“blaser”) |
US7200308B2 (en) | 2005-06-28 | 2007-04-03 | California Institute Of Technology | Frequency conversion with nonlinear optical polymers and high index contrast waveguides |
US7894696B2 (en) | 2005-06-28 | 2011-02-22 | California Institute Of Technology | Integrated optical modulator |
US7480434B2 (en) | 2006-07-25 | 2009-01-20 | California Institute Of Technology | Low loss terahertz waveguides, and terahertz generation with nonlinear optical systems |
US7760970B2 (en) | 2007-10-11 | 2010-07-20 | California Institute Of Technology | Single photon absorption all-optical modulator in silicon |
WO2009134506A2 (en) | 2008-02-07 | 2009-11-05 | University Of Washington | Enhanced silicon all-optical modulator |
US8067724B2 (en) | 2008-02-07 | 2011-11-29 | University Of Washington | All-optical integrated photonic clock having a delay line for providing gate signal to a gate waveguide |
US8031985B2 (en) | 2008-02-07 | 2011-10-04 | University Of Washington | Optical XOR logic gate |
US20090297094A1 (en) | 2008-03-05 | 2009-12-03 | University Of Washington | All-optical modulation and sdwitching with patterned optically absorbing polymers |
US8311374B2 (en) | 2008-07-29 | 2012-11-13 | University Of Washington | Beam generation and steering with integrated optical circuits for light detection and ranging |
US8390922B1 (en) | 2008-07-29 | 2013-03-05 | University Of Washington | Phase matching for difference frequency generation and nonlinear optical conversion for planar waveguides via vertical coupling |
US8258476B1 (en) | 2008-07-29 | 2012-09-04 | University Of Washington | Radiation detection using a nonlinear phase shift mechanism |
US8203115B2 (en) | 2008-07-29 | 2012-06-19 | University Of Washington | Method of performing hyperspectral imaging with photonic integrated circuits |
US8280211B1 (en) | 2009-01-16 | 2012-10-02 | University Of Washington | All-optical high bandwidth sampling device based on a third-order optical nonlinearity |
US8380016B1 (en) | 2009-06-09 | 2013-02-19 | University Of Washington Through Its Center For Commercialization | Geometries for electrooptic modulation with χ2 materials in silicon waveguides |
US8340486B1 (en) | 2009-06-09 | 2012-12-25 | University Of Washington | Effective χ2 on the basis of electric biasing of χ3 materials |
US8818141B1 (en) | 2010-06-25 | 2014-08-26 | University Of Washington | Transmission line driven slot waveguide mach-zehnder interferometers |
US8625942B2 (en) * | 2011-03-30 | 2014-01-07 | Intel Corporation | Efficient silicon-on-insulator grating coupler |
US9236958B2 (en) * | 2012-08-10 | 2016-01-12 | Skorpios Technologies, Inc. | Method and system for performing testing of photonic devices |
JP2014071318A (en) | 2012-09-28 | 2014-04-21 | Oki Electric Ind Co Ltd | Optical element and usage method of the same, and optical integrated circuit and inspection method of the same |
US10222294B2 (en) * | 2015-03-31 | 2019-03-05 | Mellanox Technologies Silicon Photonics Inc. | Wafer level testing of optical devices |
-
2015
- 2015-09-21 US US14/860,537 patent/US10359567B2/en active Active
-
2016
- 2016-09-20 WO PCT/US2016/052684 patent/WO2017053308A1/en active Application Filing
-
2019
- 2019-06-12 US US16/439,196 patent/US20190293866A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030223672A1 (en) * | 2002-03-08 | 2003-12-04 | Joyner Charles H. | Insertion loss reduction, passivation and/or planarization and in-wafer testing of integrated optical components in photonic integrated circuits (PICs) |
US20120104389A1 (en) * | 2009-04-01 | 2012-05-03 | Neil David Whitbread | Sacrificial waveguide test structures |
US20150147024A1 (en) * | 2009-04-01 | 2015-05-28 | Oclaro Technology Ltd | Sacrificial Waveguide Test Structures |
US20150147042A1 (en) * | 2013-11-25 | 2015-05-28 | Panasonic Intellectual Property Management Co., Ltd. | Imaging apparatus and imaging method |
US20160109659A1 (en) * | 2014-10-15 | 2016-04-21 | Huawei Technologies Co., Ltd. | Stacked Photonic Chip Coupler for SOI Chip-Fiber Coupling |
US9459177B1 (en) * | 2015-05-15 | 2016-10-04 | Alcatel Lucent | Wafer-level testing of optical circuit devices |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220283366A1 (en) * | 2019-08-23 | 2022-09-08 | Nippon Telegraph And Telephone Corporation | Optical Circuit |
CN113325513A (en) * | 2020-02-28 | 2021-08-31 | 富士通光器件株式会社 | Optical device and method of testing optical device |
US11604116B2 (en) | 2020-02-28 | 2023-03-14 | Fujitsu Optical Components Limited | Optical device having terrace for mounting optical chip component and method of testing optical device having terrace for mounting optical chip component |
JP7467985B2 (en) | 2020-02-28 | 2024-04-16 | 富士通オプティカルコンポーネンツ株式会社 | Optical device and optical device test method |
US20210270697A1 (en) * | 2020-03-02 | 2021-09-02 | Fujitsu Optical Components Limited | Optical device and optical device testing method |
US11719598B2 (en) * | 2020-03-02 | 2023-08-08 | Fujitsu Optical Components Limited | Optical device for measuring power of test light and optical device testing method |
Also Published As
Publication number | Publication date |
---|---|
US10359567B2 (en) | 2019-07-23 |
WO2017053308A1 (en) | 2017-03-30 |
US20170082799A1 (en) | 2017-03-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20190293866A1 (en) | Test systems and methods for chips in wafer scale photonic systems | |
US10826267B2 (en) | Surface coupled systems | |
US10042131B1 (en) | Architecture for silicon photonics enabling wafer probe and test | |
US10205302B2 (en) | Quantum dot SOA-silicon external cavity multi-wavelength laser | |
US9479286B2 (en) | Optically interconnected chip, method of testing the same, and optical receiver | |
US10243328B2 (en) | Semiconductor laser | |
US9470844B1 (en) | Low loss high extinction ratio on-chip polarizer | |
US20200033533A1 (en) | On-wafer testing of photonic chips | |
KR20130133009A (en) | Efficient silicon-on-insulator grating coupler | |
US20160377814A1 (en) | Optimized 2x2 3db multi-mode interference coupler | |
US20230343655A1 (en) | Systems and Methods for Wafer-Level Photonic Testing | |
US20190379476A1 (en) | Broadband high-speed wavelength-division multiplexed receiver using multiple photodetectors per channel | |
JP2005222048A (en) | Active/passive monolithically integrated channel filtering polarization splitter | |
WO2016138506A2 (en) | Multi-wavelength laser | |
US20160231581A1 (en) | Multiple Laser Optical Assembly | |
JP7451376B2 (en) | Loss monitoring in photonic circuit manufacturing | |
TWI773248B (en) | Semiconductor structures and methods of forming the same | |
US20230376818A1 (en) | High Density Fiber Optic Packaging for Cryogenic Applications | |
US20220035100A1 (en) | Optical Circuit and Optical Connection Structure | |
Yang | Hybrid laser integration for silicon photonics platform |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: CORIANT ADVANCED TECHNOLOGY, LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NOVACK, ARI;STRESHINSKY, MATTHEW AKIO;HOCHBERG, MICHAEL J;SIGNING DATES FROM 20150918 TO 20150921;REEL/FRAME:049448/0963 Owner name: ELENION TECHNOLOGIES, LLC, NEW YORK Free format text: CHANGE OF NAME;ASSIGNOR:CORIANT ADVANCED TECHNOLOGIES LLC;REEL/FRAME:049453/0440 Effective date: 20161116 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: NOKIA SOLUTIONS AND NETWORKS OY, FINLAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ELENION TECHNOLOGIES LLC;REEL/FRAME:058708/0603 Effective date: 20200910 |