US20190235338A1 - Active matrix substrate, display panel, and display device provided with same - Google Patents
Active matrix substrate, display panel, and display device provided with same Download PDFInfo
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- US20190235338A1 US20190235338A1 US16/334,772 US201716334772A US2019235338A1 US 20190235338 A1 US20190235338 A1 US 20190235338A1 US 201716334772 A US201716334772 A US 201716334772A US 2019235338 A1 US2019235338 A1 US 2019235338A1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
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- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136263—Line defects
Definitions
- the present disclosure relates to an active matrix substrate, a display panel, and a display device provided with the same, and particularly relates to altering the size of an active matrix substrate and a display panel including the same.
- a short circuit may occur near the dividing line. This short circuit then causes a display defect in the display panel after the size alteration.
- the present disclosure takes the aforementioned problem into consideration, and an objective thereof is to realize an active matrix substrate with which regions where a short circuit may have occurred due to dividing can be isolated from a display region.
- an active matrix substrate is a configuration including: a plurality of source lines including a plurality of first source lines that transmit a first source signal from a ⁇ Y direction toward a +Y direction; and a plurality of gate lines that intersect the plurality of first source lines only at a plurality of first intersections, and transmit a gate signal from a ⁇ X direction toward a +X direction, in the gate lines, gate line detour sections being provided corresponding to each of the first intersections, and each of the gate line detour sections having: a first start section in which the corresponding gate line is bent toward the +Y direction or the ⁇ Y direction from a first start position that is in the ⁇ X direction relative to the corresponding first intersection; and first straddling sections in which the corresponding gate line straddles a first straight line that passes through a +X direction end of the corresponding first intersection and extends in the +Y direction and the ⁇ Y direction.
- an effect is demonstrated in which regions where a short circuit may have occurred due to dividing can be isolated from a display region.
- FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device according to several embodiments of the present disclosure.
- FIG. 2 is a top view depicting a schematic configuration of an active matrix substrate according to several embodiments of the present disclosure.
- FIG. 3( a ) is a top view depicting a schematic configuration of dividing lines along which a display panel is divided
- FIG. 3( b ) is a perspective view depicting a schematic configuration of the vicinity of the dividing lines of the display panel after having been mechanically divided, according to several embodiments of the present disclosure.
- FIG. 4 is a top view depicting a schematic configuration of wiring near a laser scanning line of an active matrix substrate according to one embodiment of the present disclosure.
- FIG. 5 is a top view depicting a schematic configuration of an active matrix substrate according to one embodiment of the present disclosure.
- FIG. 6 is a top view depicting a schematic configuration of an active matrix substrate, for depicting one working example of gate line detour sections and source line detour sections according to one embodiment of the present disclosure.
- FIG. 7 is a top view depicting a schematic configuration of the active matrix substrate, in a case where a boundary section at the ⁇ X direction side of a laser light irradiated region L superposes a source line, in the working example depicted in FIG. 6 .
- FIG. 8 is a top view depicting a schematic configuration of an active matrix substrate, for depicting one working example of gate line detour sections and source line detour sections according to one embodiment of the present disclosure.
- FIG. 9 is a top view depicting a schematic configuration of an active matrix substrate, for depicting one working example of gate line detour sections and source line detour sections according to one embodiment of the present disclosure.
- FIG. 10 is a top view depicting a schematic arrangement of gate line detour sections and source line detour sections in an active matrix substrate according to one embodiment of the present disclosure.
- FIG. 11 is a top view depicting a schematic configuration of (a) one working example and (b) another working example of a liquid crystal display device according to one embodiment of the present disclosure.
- FIG. 12 is a top view depicting the relationship between the shape of a dividing line and the arrangement of a gate driver, in a liquid crystal display device according to one embodiment of the present disclosure.
- FIG. 13 is a top view depicting a schematic configuration of a dividing line according to one embodiment of the present disclosure.
- FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device 1 according to the present embodiment.
- the liquid crystal display device 1 (display device) is provided with a display panel 2 , a source driver 3 , a gate driver 11 (gate driving circuit), a display control circuit 4 , and a power source 5 .
- the display panel 2 is provided with an active matrix substrate 20 a , an opposite substrate 20 b , and a liquid crystal layer (not depicted) held between the active matrix substrate 20 a and the opposite substrate 20 b .
- a polarizer is provided at the lower surface side ( ⁇ Z side) of the active matrix substrate 20 a and the upper surface side (+Z side) of the opposite substrate 20 b .
- a black matrix, three color filters of red (R), green (G), and blue (B), and a common electrode (none depicted) are formed on the opposite substrate 20 b.
- the active matrix substrate 20 a is electrically connected to the source driver 3 and the gate driver 11 , which are formed on a flexible substrate.
- the display control circuit 4 is electrically connected to the display panel 2 , the source driver 3 , the gate driver 11 , and the power source 5 .
- the display control circuit 4 outputs control signals to the source driver 3 and the gate driver 11 .
- the control signals include a reset signal, a clock signal, a source signal, and the like for displaying images on the display panel 2 .
- the power source 5 is electrically connected to the display panel 2 , the source driver 3 , and the display control circuit 4 , and supplies power source voltage signals to each thereof.
- FIG. 2 is a top view depicting a schematic configuration of the active matrix substrate 20 a.
- the active matrix substrate 20 a includes an insulating substrate 2 a such as a glass substrate, and N gate lines 13 G, N auxiliary capacitance lines 13 CS, and M source lines 15 S that are formed on the insulating substrate 2 a (N and M are natural numbers that are greater than or equal to 2).
- the N gate lines 13 G are formed to be substantially parallel at substantially equal intervals from one end ( ⁇ X direction end) of the insulating substrate 2 a to the other end (+X direction end) in the X axis direction.
- the N auxiliary capacitance lines 13 CS are also similarly formed to be substantially parallel at substantially equal intervals from one end ( ⁇ X direction end) of the insulating substrate 2 a to the other end (+X direction end).
- the M source lines 15 S (first source lines and second source lines) are formed to be substantially parallel at substantially equal intervals from one end ( ⁇ Y direction end) of the insulating substrate 2 a to the other end (+Y direction end) in the Y axis direction so as to intersect the N gate lines 13 G and the N auxiliary capacitance lines 13 CS.
- the N gate lines 13 G are electrically connected to the gate driver 11 , and transmit gate signals generated by the gate driver 11 from the ⁇ X direction toward the +X direction.
- the N auxiliary capacitance lines 13 CS also similarly transmit auxiliary capacitance voltages (auxiliary capacitance signals) from the ⁇ X direction toward the +X direction.
- the M source lines 15 S are electrically connected to the source driver 3 , and transmit source signals (first source signals and second source signals) generated by the source driver 3 from the ⁇ Y direction toward the +Y direction.
- the X axis and the Y axis are substantially orthogonal.
- Each region enclosed by the gate lines 13 G and the source lines 15 S is a pixel region, and, although not depicted in FIG. 2 , one pixel electrode and one switching element (first switching element) are formed in each pixel region.
- Each pixel electrode corresponds to any color of the color filters, and is connected to a gate line 13 G and a source line 15 S via a switching element.
- the switching elements are thin film transistors (TFTs), for example, and the gate electrodes of the TFTs are arranged on the insulating substrate 2 a similar to the gate lines 13 G and are connected to the corresponding gate lines 13 G.
- the source electrodes and the drain electrodes of the TFTs are arranged on a gate insulating film similar to the source lines 15 S being arranged on an insulating film, and are connected to the corresponding source lines 15 S and pixel electrodes.
- one auxiliary capacitance line 13 CS is provided with respect to one gate line 13 G, and the gate lines 13 G and the auxiliary capacitance lines 13 CS are arranged in an alternating manner. There is no restriction thereto, and a plurality of auxiliary capacitance lines 13 CS may be provided with respect to one gate line 13 G.
- FIG. 3 is a drawing for describing the dividing of the display panel 2 according to dividing lines 25 .
- FIG. 3( a ) is a top view depicting a schematic configuration of the dividing lines 25 along which the display panel 2 is divided.
- the dividing lines 25 include an active matrix substrate dividing line 25 a along which the active matrix substrate 20 a is mechanically divided, an opposite substrate dividing line 25 b along which the opposite substrate 20 b is mechanically divided, and a laser scanning line 25 c along which the gate lines 13 G and the auxiliary capacitance lines 13 CS (and also the source lines 15 S in some cases) on the active matrix substrate 20 a are divided.
- the active matrix substrate dividing line 25 a , the opposite substrate dividing line 25 b , and the laser scanning line 25 c are substantially parallel with each other in the Y axis direction.
- the opposite substrate dividing line 25 b is positioned at the side near the gate driver 11 ( ⁇ X side), seen from the active matrix substrate dividing line 25 a . It is preferable for the gap between the active matrix substrate dividing line 25 a and the opposite substrate dividing line 25 b to be 0.5 mm to 2 mm, although this depends on the extent to which the mechanical dividing of the active matrix substrate 20 a affects the gate lines 13 G and the auxiliary capacitance lines 13 CS. Furthermore, the laser scanning line 25 c is positioned between the active matrix substrate dividing line 25 a and the opposite substrate dividing line 25 b.
- a region 41 at the side ( ⁇ X side) nearer the gate driver 11 than the opposite substrate dividing line 25 b active matrix substrate 20 a becomes a display region 41 .
- a region 42 at the side (+X side) further from the gate driver 11 than the active matrix substrate dividing line 25 a becomes a non-display region 42 .
- a region 43 that is electrically isolated from the display region 41 due to laser scanning along the laser scanning line 25 c becomes an isolated region 43 .
- the isolated region 43 includes regions where a short circuit may occur due to mechanical dividing along the active matrix substrate dividing line 25 a . Therefore, the display region 41 is isolated from the regions where a short circuit may have occurred, due to the laser scanning along the laser scanning line 25 c . Consequently, it is preferable for the laser scanning line 25 c to be sufficiently separated from the active matrix substrate dividing line 25 a so that the isolated region 43 includes all regions where a short circuit may have occurred.
- the laser light that is radiated along the laser scanning line 25 c it is preferable for the laser light that is radiated along the laser scanning line 25 c to be away from the source lines 15 S so that the gate lines 13 G do not short circuit to the source lines 15 S, with consideration being given to the width of the source lines 15 S and width of the laser light.
- FIG. 3( b ) is a perspective view depicting a schematic configuration of the vicinity of the dividing lines 25 of the display panel 2 after having been mechanically divided.
- the source lines 15 S are depicted as solid lines
- the gate lines 13 G are depicted as one-dot chain lines
- the auxiliary capacitance lines 13 CS are depicted as two-dot chain lines.
- a process for dividing the display panel 2 will be described with reference to FIG. 3( b ) .
- the active matrix substrate 20 a is mechanically divided along the active matrix substrate dividing line 25 a .
- the gate lines 13 G and the auxiliary capacitance lines 13 CS are also divided together with the insulating substrate 2 a .
- the gate lines 13 G and the auxiliary capacitance lines 13 CS near the active matrix substrate dividing line 25 a may have short-circuited or may short-circuit during use of the display panel 2 since a mechanical external force is applied.
- the opposite substrate 20 b is likewise mechanically divided along the opposite substrate dividing line 25 b . It should be noted that the dividing of the active matrix substrate 20 a and the dividing of the opposite substrate 20 b may be carried out one after the other or may be carried out at the same time.
- a liquid crystal layer 30 that is exposed on the active matrix substrate 20 a within the non-display region 42 is then removed.
- Wiring (gate lines 13 G, auxiliary capacitance lines 13 CS, and source lines 15 S) on the insulating substrate 2 a within the non-display region 42 is thereby exposed. Due to this exposure, it becomes easy to radiate a scanning laser in the next step.
- a laser is scanned on the surface of the active matrix substrate 20 a along the laser scanning line 25 c . Due to the laser scanning, wiring (gate lines 13 G, auxiliary capacitance lines 13 CS, and source lines 15 S) within the laser irradiated region is evaporated and removed. As a result, wiring at the side nearer the active matrix substrate dividing line 25 a than the laser irradiated region (+X direction) is isolated from wiring at the side nearer the gate driver 11 ( ⁇ X direction).
- the liquid crystal layer 30 within the display region 41 held between the active matrix substrate 20 a and the opposite substrate 20 b is sealed with a sealing material (in a case where the liquid crystal layer 30 is lacking, a liquid crystal composition that forms the liquid crystal layer 30 is injected prior to the sealing).
- FIG. 4 is a top view depicting a schematic configuration of wiring near the laser scanning line 25 c of the active matrix substrate 20 a . It should be noted that, in FIG. 4 , the insulating substrate 2 a , pixel electrodes, insulating layers, and the like are omitted in order to aid understanding of the schematic structure of the wiring.
- Switching elements T for applying source signals in accordance with gate signals to the pixel electrodes are provided on the active matrix substrate 20 a .
- the switching elements T are thin film transistors (TFTs), for example, and are provided corresponding to intersections between the gate lines 13 G and the source lines 15 S.
- the gate lines 13 G, the auxiliary capacitance lines 13 CS, and the source lines 15 S are laminated with an insulating layer interposed, and therefore, due to the melting, the gate lines 13 G and the source lines 15 S may short-circuit at the intersections between the gate lines 13 G and the source lines 15 S. Similarly, due to the melting, the auxiliary capacitance lines 13 CS and the source lines 15 S may short-circuit at intersections between the auxiliary capacitance lines 13 CS and the source lines 15 S.
- the gate line 13 G of an n th row (n being a natural number greater than or equal to 1 and less than or equal to N ⁇ 1) from the source driver 3 and the source line 15 S of an m th column (m being a natural number greater than or equal to 1 and less than or equal to M ⁇ 1) from the gate driver 11 intersect
- the gate line 13 G and the source line 15 S may short-circuit at the intersection C G,n,m . Therefore, it is necessary for the laser light irradiated region L to satisfy the relationship of expression (1) below.
- X S,m is the X coordinate of the center line of the source line 15 S of the m th column from the gate driver 11 ,
- X L is the X coordinate of the center line of the irradiated region L
- d S is the width of the source line 15 S
- r is the width of the laser light radiated along the laser scanning line 25 c and the width of the irradiated region L.
- the gate line 13 G and the source line 15 S may short-circuit at the intersection C G,n,m .
- position tolerance which is the difference between the X coordinate of the center line of the irradiated region L and the X coordinate of the laser scanning line 25 c , it is necessary for the position tolerance for the radiation of laser light along the laser scanning line 25 c to be less than ⁇ (p ⁇ d S )/2, and is preferably even smaller. Furthermore, it is preferable for the laser scanning line 25 c to be away from the source lines 15 S.
- the isolated region 43 that includes regions where a short circuit may occur is electrically isolated from the display region 41 due to laser light being radiated along the laser scanning line 25 c . Therefore, short-circuiting caused by the dividing has no bearing on the display region 41 , and display defects caused by short-circuiting due to the dividing are not generated therein.
- FIGS. 1, 5, 6, and 7 Another embodiment of the present disclosure is as follows when described on the basis of FIGS. 1, 5, 6, and 7 . It should be noted that, for convenience of the description, members having the same functions as the members described in the aforementioned embodiment are denoted by the same reference signs and descriptions thereof are omitted.
- FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device according to the present embodiment.
- a liquid crystal display device 1 is provided with a display panel 2 , a source driver 3 , a gate driver 11 , a display control circuit 4 , and a power source 5 .
- the display panel 2 is provided with an active matrix substrate 20 a , an opposite substrate 20 b , and a liquid crystal layer (not depicted) held between these substrates.
- FIG. 5 is a top view depicting a schematic configuration of the active matrix substrate 20 a.
- the active matrix substrate 20 a includes an insulating substrate 2 a such as a glass substrate, and N gate lines 13 G, N auxiliary capacitance lines 13 CS, and M source lines 15 S that are formed on the insulating substrate 2 a (N and M are natural numbers that are greater than or equal to 2).
- gate line detour sections 50 G are provided in each gate line 13 G and source line detour sections 50 S (source line first detour sections) are provided in each source line 15 S, as in FIGS. 6 and 7 , although not depicted in FIG. 5 .
- the gate line detour sections 50 G are provided corresponding to intersections between the gate lines 13 G and the source lines 15 S.
- the gate line detour sections 50 G are portions formed in such a way that the gate lines 13 G detour so that (i) gate lines 13 G extending from the ⁇ X direction end of the active matrix substrate 20 a prior to passing through corresponding intersections are divided at the irradiated region L in a case where the laser light irradiated region L satisfies the relationship of expression (2), and so that (ii) intersections where the gate lines 13 G intersect (themselves or other wiring, including being superposed in parallel) are not newly made (in other words, are not increased). This is because, in a case where there is an increase in intersections in the gate lines 13 G, those intersections may short-circuit when the boundary sections of the irradiated region L superpose those intersections.
- the source line detour sections 50 S are provided corresponding to the gate line detour sections 50 G.
- the source line detour sections 50 S are portions formed in such a way that the source lines 15 S avoid the corresponding gate line detour sections 50 G so that intersections where the source lines 15 S intersect (themselves or other wiring) are not newly made.
- the gate line detour sections 50 G do not cause an increase in intersections, as previously mentioned. Therefore, the gate lines 13 G intersect the source lines 15 S only at intersections (first intersections) where the gate line detour sections 50 G are provided in a corresponding manner. Furthermore, the gate lines 13 G do not intersect themselves and do not intersect other adjacent gate lines 13 G. As a result, the gate lines 13 G start detouring with the gate lines 13 G bending from a start position (first start position) between a corresponding intersection and another intersection adjacent at the ⁇ X direction side to the corresponding intersection (in the ⁇ X direction relative to the corresponding intersection), toward the ⁇ Y direction or the +Y direction.
- the gate lines 13 G stop detouring, the gate lines 13 G return from the ⁇ Y direction or the +Y direction to an end position (first end position) between the corresponding intersection and the start position (in the ⁇ X direction relative to the corresponding intersection, and in the +X direction relative to the start position).
- the gate lines 13 G having finished detouring then bend toward the +X direction and pass through the corresponding intersection.
- the gate line detour sections 50 G are divided at the irradiated region L in a case where the laser light irradiated region L satisfies the relationship of expression (2). Therefore, the gate lines 13 G of the gate line detour sections 50 G straddle both a straight line (first straight line) that passes through the +X direction end of the corresponding intersection and extends in the Y axis direction (+Y direction and ⁇ Y direction) and a straight line that passes through the ⁇ X direction end and extends in the Y axis direction.
- the gate line detour sections 50 G start from a start position that is in the ⁇ X direction relative to the corresponding intersection and finish at an end position that is in the ⁇ X direction relative to the corresponding intersection, and therefore the gate lines 13 G of the gate line detour sections 50 G also straddle a straight line that passes through the ⁇ X direction end when straddling a straight line that passes through the +X direction end.
- gate signals that are supplied from the gate driver 11 to the gate lines 13 G reach the immediately preceding intersection C G,n,m ⁇ 1 , are then interrupted at the gate line detour sections 50 G, and do not reach the intersection C G,n,m , which may have short-circuited.
- the gate line detour sections 50 G include: (i) a start section 51 G (first start section) in which the gate line 13 G is drawn out in the +Y direction or the ⁇ Y direction from a start position that is in the ⁇ X direction relative to the corresponding intersection; (ii) straddling sections 52 G (first straddling sections) in which the gate line 13 G straddles a straight line that passes through the +X direction end of the corresponding intersection and extends in the Y axis direction; and (iii) an end section 53 G (first end section) in which the gate line 13 G returns from an end position that is in the ⁇ X direction relative to the corresponding intersection and in the +X direction relative to the start position.
- the gate line 13 G electrically connects: (i) between the end position of the gate line detour section 50 G and the corresponding intersection by means of a portion of the gate line 13 G that is not the gate line detour section 50 G; (ii) between the start position of the gate line detour section 50 G and another intersection adjacent at the ⁇ X direction side to the corresponding intersection by means of a portion of the gate line 13 G that is not the gate line detour section 50 G; and (iii) between the start position and the end position of the same gate line detour section 50 G by means of only a portion of the gate line 13 G that is the gate line detour section 50 G. It is preferable for the gate lines 13 G of the gate line detour sections 50 G and the source lines 15 S of the source line detour sections 50 S to be formed so as to pass through positions that are different from the switching elements T in order to avoid the switching elements T.
- FIG. 6 is a top view depicting a schematic configuration of the active matrix substrate 20 a , for depicting one working example of the gate line detour sections 50 G and the source line detour sections 50 S in the present embodiment.
- FIG. 6 a working example in which the gate lines 13 G are bent in a linear and simple manner to thereby form the gate line detour sections 50 G, and the source lines 15 S are bent in a linear and simple manner to thereby form the source line detour sections 50 S.
- the examples depicted in FIGS. 6 to 10 are for deepening understanding of the gate line detour sections 50 G and the source line detour sections 50 S, and do not restrict the present disclosure.
- the gate line detour sections 50 G and the source line detour sections 50 S may be formed in any complex manner so as to branch in a curved manner, bend a large number of times, and so forth.
- M is a natural number that is greater than or equal to 2
- m is a natural number that is greater than or equal to 1 and less than or equal to M ⁇ 1
- N is a natural number that is greater than or equal to 2
- n is a natural number that is greater than or equal to 1 and less than or equal to N ⁇ 1.
- the widths of the switching elements T in the X axis direction and the Y axis direction are taken as T X and T Y .
- a gate line 13 G of the 0th row and a source line 15 S of the 0 th column do not actually exist, for convenience, it is assumed that the gate line 13 G of the 0th row extends along the ⁇ Y side end of the active matrix substrate and the source line 15 S of the 0 th column extends along the ⁇ X side end of the active matrix substrate.
- the magnitude relationship of the X coordinates and the magnitude relationship of the Y coordinates will be examined with regard to the intersection C G,n,m where the source line 15 S of the m th column from the gate driver 11 and the gate line 13 G of the n th row from the source driver 3 intersect, the gate line detour section 50 G of the gate line 13 G corresponding to the intersection C G,n,m , and the source line detour section 50 S of the source line 15 S corresponding to the gate line detour section 50 G.
- X coordinates or Y coordinates of center lines of the gate line 13 G are respectively Y G,n , X G,m (1) , Y G,n (1) , X G,m (2) , Y G,n (2) , and X G,m (3) , and
- X coordinates or Y coordinates of center lines of the source line 15 S are respectively X S,m , Y S,n (1) , X S,m (1) , and Y S,n (2) .
- the width d G of the gate lines 13 G and the width d S of the source lines 15 S are taken into consideration, it is derived based on the relationship of expression (3) that the gate line detour sections 50 G and the source line detour sections 50 S satisfy the relationships of expressions (5-1) to (5-6) below. Similarly, it is derived based on the relationship of expression (4) that the relationships of expressions (6-1) to (6-5) below are satisfied.
- FIG. 7 is a top view depicting a schematic configuration in a case where the laser light irradiated region L satisfies the relationship of expression (2), in the working example depicted in FIG. 6 .
- a gate line 13 G is divided between the intersection C G,n,m ⁇ 1 and reaching the intersection C G,n,m , specifically, in the gate line detour section 50 G corresponding to the intersection C G,n,m , and more specifically, in the straddling sections 52 G of that gate line detour section 50 G.
- the source line detour section 50 S corresponding to the gate line detour section 50 G in which the gate line 13 G is divided is also divided.
- the isolated region 43 that includes regions where a short circuit may have occurred due to the mechanical dividing of the display panel 2 can be electrically isolated from the display region 41 by radiating laser light along the laser scanning line 25 c . Therefore, an effect is demonstrated in that short circuits and display defects caused by the short circuits are reliably removed from the display region 41 of the display panel 2 after having been divided.
- the laser light irradiated region L satisfies the relationship of expression (2)
- the intersection C G,n,m which may short-circuit, is electrically isolated from the display region 41 ( FIG. 3 ). Therefore, the laser light irradiated region L may not satisfy the relationship of expression (1). Consequently, it is possible for the laser scanning line 25 c to be near or superposing a source line 15 S. Furthermore, the position tolerance of the laser light may be greater than ⁇ (p ⁇ d S )/2.
- the laser light irradiated region L may not satisfy the relationship of expression (1), it is possible to more easily realize a display panel in which display defects do not occur due to short circuits caused by dividing.
- FIGS. 1, 2, and 8 Another embodiment of the present disclosure is as follows when described on the basis of FIGS. 1, 2, and 8 . It should be noted that, for convenience of the description, members having the same functions as the members described in the aforementioned embodiment are denoted by the same reference signs and descriptions thereof are omitted.
- FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device according to the present embodiment.
- a liquid crystal display device 1 is provided with a display panel 2 , a source driver 3 , a gate driver 11 , a display control circuit 4 , and a power source 5 .
- the display panel 2 is provided with an active matrix substrate 20 a , an opposite substrate 20 b , and a liquid crystal layer (not depicted) held between these substrates.
- FIG. 2 is a top view depicting a schematic configuration of the active matrix substrate 20 a.
- the active matrix substrate 20 a includes an insulating substrate 2 a such as a glass substrate, and N gate lines 13 G, N auxiliary capacitance lines 13 CS, and M source lines 15 S formed on the insulating substrate 2 a.
- the active matrix substrate 20 a includes the auxiliary capacitance lines 13 CS.
- gate line detour sections 50 G and source line detour sections 50 S are provided. Also, due to the presence of the auxiliary capacitance lines 13 CS, which are wiring other than the gate lines 13 G and the source lines 15 S, the gate line detour sections 50 G and the source line detour sections 50 S are formed so as to not intersect the auxiliary capacitance lines 13 CS.
- FIG. 8 is a top view depicting a schematic configuration of the active matrix substrate 20 a , for depicting one working example of the gate line detour sections 50 G and the source line detour sections 50 S in the present embodiment.
- the gate line 13 G of the n th row from the source driver 3 and the source line 15 S of the m th column from the gate driver 11 are bent in a similar manner to the aforementioned embodiment 2. Furthermore, in FIG. 8 , the auxiliary capacitance line 13 CS of the n th row from the source driver 3 extends in the +X direction at Y CS,n .
- the gate line detour section 50 G corresponding to the intersection C G,n,m and the source line detour section 50 S corresponding to that gate line detour section 50 G satisfy the relationship of the aforementioned expression (3) and the relationship of expression (7) or (8) below.
- the expressions (7) and (8) are conditional expressions with which the gate line detour section 50 G and the source line detour section 50 S are classified so as to not intersect the auxiliary capacitance line 13 CS.
- Expression (7) is established in a case where Y S,n (1) where the source line 15 S of the m th column turns in the +X direction is in a position ( ⁇ Y side) that is nearer to the source driver 3 than the auxiliary capacitance line 13 CS of the n th row.
- expression (8) is established in a case where Y S,n (1) where the source line 15 S of the m th column turns in the +X direction is in a position (+Y side) that is further from the source driver 3 than the auxiliary capacitance line 13 CS of the n th row.
- the width do of the gate lines 13 G, the width d S of the source lines 15 S, and the width d CS of the auxiliary capacitance lines 13 CS are taken into consideration, it is derived based on the relationship of expression (3) that the gate line detour sections 50 G and the source line detour sections 50 S satisfy the relationships of the aforementioned expressions (5-1) to (5-6).
- the relationship of expression (7) is satisfied, it is derived based on the relationship of expression (7) that the relationships of expressions (9-1) and (9-2) below and the aforementioned expressions (6-3) to (6-5) are satisfied.
- the relationship of expression (8) is satisfied, it is derived based on the relationship of expression (8) that the relationships of expression (10) below and the aforementioned expressions (6-2) to (6-5) are satisfied.
- the gate line 13 G is divided in the gate line detour section 50 G corresponding to the intersection C G,n,m .
- the isolated region 43 that includes regions where a short circuit may have occurred due to the mechanical dividing of the display panel 2 can be electrically isolated from the display region 41 by radiating laser light along the laser scanning line 25 c . Therefore, an effect is demonstrated in that short circuits and display defects caused by the short circuits are reliably removed from the display region 41 of the display panel 2 after having been divided.
- the laser light irradiated region L in a case where the laser light irradiated region L satisfies the relationship of expression (2), the intersection C G,n,m , which may short-circuit, is electrically isolated from the display region 41 ( FIG. 3 ). Therefore, the laser light irradiated region L may not satisfy the relationship of expression (1).
- FIGS. 1, 2, and 9 Another embodiment of the present disclosure is as follows when described on the basis of FIGS. 1, 2, and 9 . It should be noted that, for convenience of the description, members having the same functions as the members described in the aforementioned embodiment are denoted by the same reference signs and descriptions thereof are omitted.
- FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device according to the present embodiment.
- a liquid crystal display device 1 is provided with a display panel 2 , a source driver 3 , a gate driver 11 , a display control circuit 4 , and a power source 5 .
- the display panel 2 is provided with an active matrix substrate 20 a , an opposite substrate 20 b , and a liquid crystal layer (not depicted) held between these substrates.
- FIG. 2 is a top view depicting a schematic configuration of the active matrix substrate 20 a.
- the active matrix substrate 20 a includes an insulating substrate 2 a such as a glass substrate, and N gate lines 13 G, N auxiliary capacitance lines 13 CS, and M source lines 15 S formed on the insulating substrate 2 a.
- the active matrix substrate 20 a includes the auxiliary capacitance lines 13 CS.
- gate line detour sections 50 G and source line detour sections 50 S (source line first detour sections) corresponding to the gate line detour section 50 G are provided.
- auxiliary capacitance line detour sections 50 CS are provided in each auxiliary capacitance line 13 CS, and source line detour sections 50 S (source line second detour sections) corresponding to the auxiliary capacitance line detour sections 50 CS are provided in each source line 15 S.
- the auxiliary capacitance line detour sections 50 CS are provided corresponding to intersections between the auxiliary capacitance lines 13 CS and the source lines 15 S, similar to the gate line detour sections 50 G being provided corresponding to intersections between the gate lines 13 G and the source lines 15 S.
- the auxiliary capacitance line detour sections 50 CS are portions formed in such a way that the auxiliary capacitance lines 13 CS detour so that (i) auxiliary capacitance lines 13 CS extending from the ⁇ X direction end of the active matrix substrate 20 a prior to passing through corresponding intersections are divided at the irradiated region L in a case where the laser light irradiated region L satisfies the relationship of expression (2), and so that (ii) intersections where the auxiliary capacitance lines 13 CS intersect (themselves or other wiring) are not newly made (in other words, are not increased).
- the source line detour sections 50 S are provided corresponding to the gate line detour sections 50 G, and are also provided corresponding to the auxiliary capacitance line detour sections 50 CS.
- the source line detour sections 50 S corresponding to the auxiliary capacitance line detour sections 50 CS are portions formed in such a way that the source lines 15 S avoid the corresponding auxiliary capacitance line detour sections 50 CS so that intersections where the source lines 15 S intersect (themselves or other wiring) are not newly made.
- the gate line detour sections 50 G do not cause an increase in intersections, as previously mentioned. Therefore, the gate lines 13 G intersect the source lines 15 S only at intersections (first intersections) where the gate line detour sections 50 G are provided in a corresponding manner. Furthermore, the gate lines 13 G do not intersect themselves and do not intersect adjacent auxiliary capacitance lines 13 CS.
- the auxiliary capacitance line detour sections 50 CS do not cause an increase in intersections, as previously mentioned. Therefore, the auxiliary capacitance lines 13 CS intersect the source lines 15 S only at intersections (second intersections) where the auxiliary capacitance line detour sections 50 CS are provided in a corresponding manner. Furthermore, the auxiliary capacitance lines 13 CS do not intersect themselves and do not intersect adjacent gate lines 13 G.
- the auxiliary capacitance lines 13 CS start detouring with the auxiliary capacitance lines 13 CS bending from a start position (second start position) between a corresponding intersection and another intersection adjacent at the ⁇ X direction side to the corresponding intersection (in the ⁇ X direction relative to the corresponding intersection), toward the ⁇ Y direction or the +Y direction.
- the auxiliary capacitance lines 13 CS stop detouring the auxiliary capacitance lines 13 CS return from the ⁇ Y direction or the +Y direction to an end position (second end position) between the corresponding intersection and the start position (in the ⁇ X direction relative to the corresponding intersection, and in the +X direction relative to the start position).
- the auxiliary capacitance lines 13 CS having finished detouring then bend toward the +X direction and pass through the corresponding intersection.
- the auxiliary capacitance line detour sections 50 CS are divided at the irradiated region L in a case where the laser light irradiated region L satisfies the relationship of expression (2). Therefore, the auxiliary capacitance lines 13 CS of the auxiliary capacitance line detour sections 50 CS straddle both a straight line (second straight line) that passes through the +X direction end of the corresponding intersection and extends in the Y axis direction (+Y direction and ⁇ Y direction) and a straight line that passes through the ⁇ X direction end and extends in the Y axis direction.
- the auxiliary capacitance line detour sections 50 CS start from a start position that is in the ⁇ X direction relative to the corresponding intersection, and finish at an end position that is in the ⁇ X direction relative to the corresponding intersection, and therefore the auxiliary capacitance lines 13 CS of the auxiliary capacitance line detour sections 50 CS also straddle a straight line that passes through the ⁇ X direction end when straddling a straight line that passes through the +X direction end.
- auxiliary capacitance signals transmitted by the auxiliary capacitance lines 13 CS reach the immediately preceding intersection C CS,n,m ⁇ 1 , are then interrupted at the auxiliary capacitance line detour sections 50 CS, and do not reach the intersection C CS,n,m , which may have short-circuited.
- the auxiliary capacitance line detour sections 50 CS include: (i) a start section 51 CS (second start section) in which the auxiliary capacitance line 13 CS is drawn out in the +Y direction or the ⁇ Y direction from a start position that is in the ⁇ X direction relative to the corresponding intersection; (ii) straddling sections 52 CS (second straddling sections) in which the auxiliary capacitance line 13 CS straddles a straight line that passes through the +X direction end of the corresponding intersection and extends in the Y axis direction; and (iii) an end section 53 CS (second end section) in which the auxiliary capacitance line 13 CS returns from an end position that is in the ⁇ X direction relative to the corresponding intersection and in the +X direction relative to the start position.
- the auxiliary capacitance line 13 CS electrically connects: (i) between the end position of the auxiliary capacitance line detour section 50 CS and the corresponding intersection by means of a portion of the auxiliary capacitance line 13 CS that is not the auxiliary capacitance line detour section 50 CS; (ii) between the start position of the auxiliary capacitance line detour section 50 CS and another intersection adjacent at the ⁇ X direction side to the corresponding intersection by means of a portion of the auxiliary capacitance line 13 CS that is not the auxiliary capacitance line detour section 50 CS; and (iii) between the start position and end position of the same auxiliary capacitance line detour section 50 CS by means of only a portion of the auxiliary capacitance line 13 CS that is the auxiliary capacitance line detour section 50 CS.
- auxiliary capacitance lines 13 CS of the auxiliary capacitance line detour sections 50 CS and the source lines 15 S of the source line detour sections 50 S are formed so as to pass through positions that are different from the switching elements T in order to avoid the switching elements T.
- FIG. 9 is a top view depicting a schematic configuration of the active matrix substrate 20 a , for depicting one working example of the gate line detour sections 50 G and the source line detour sections 50 S in the present embodiment.
- the gate line 13 G of the n th row from the source driver 3 is bent in a similar manner to the aforementioned embodiment 2.
- the source line 15 S of the m th column from the gate driver 11 is bent in a similar manner to the aforementioned embodiment 2, and, in addition,
- X coordinates or Y coordinates of center lines of the auxiliary capacitance line 13 CS are respectively Y CS,n , X CS,m (1) , Y CS,n (1) , X CS,n (2) , Y CS,n (2) , and X CS,m (3) , and
- X coordinates or Y coordinates of center lines of the source line 15 S are respectively Y S,n (3) , X S,m (2) , and Y S,n (4) .
- the isolated region 43 that includes regions where a short circuit may have occurred due to the mechanical dividing of the display panel 2 can be electrically isolated from the display region 41 by radiating laser light along the laser scanning line 25 c . Therefore, an effect is demonstrated in that short circuits and display defects caused by the short circuits are reliably removed from the display region 41 of the display panel 2 after having been divided.
- the intersection C G,n,m which may short-circuit, is electrically isolated from the display region 41 ( FIG. 3 ). Therefore, the laser light irradiated region L may not satisfy the relationship of expression (1).
- the intersection C CS,n,m between an auxiliary capacitance line 13 CS and a source line 15 S is also likewise electrically isolated from the display region 41 .
- FIGS. 1, 2, and 10 Another embodiment of the present disclosure is as follows when described on the basis of FIGS. 1, 2, and 10 . It should be noted that, for convenience of the description, members having the same functions as the members described in the aforementioned embodiment are denoted by the same reference signs and descriptions thereof are omitted.
- FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device according to the present embodiment.
- a liquid crystal display device 1 is provided with a display panel 2 , a source driver 3 , a gate driver 11 , a display control circuit 4 , and a power source 5 .
- the display panel 2 is provided with an active matrix substrate 20 a , an opposite substrate 20 b , and a liquid crystal layer (not depicted) held between these substrates.
- FIG. 2 is a top view depicting a schematic configuration of the active matrix substrate 20 a.
- the active matrix substrate 20 a includes an insulating substrate 2 a such as a glass substrate, and N gate lines 13 G, N auxiliary capacitance lines 13 CS, and M source lines 15 S formed on the insulating substrate 2 a.
- the active matrix substrate 20 a includes the auxiliary capacitance lines 13 CS.
- FIG. 10 is a top view depicting a schematic arrangement of the gate line detour sections 50 G and the source line detour sections 50 S in the active matrix substrate 20 a of the present embodiment.
- red pixel electrodes 17 R for displaying image information for red are provided with respect to the source line 15 S of the 3k ⁇ 2th column.
- blue pixel electrodes 17 B for displaying image information for blue are provided with respect to the source line 15 S of the 3k ⁇ 1th column.
- the gate line detour sections 50 G and the source line detour sections 50 S were provided corresponding to all intersections between the gate lines 13 G and the source lines 15 S so that the boundary section at the ⁇ X side of the laser scanning line 25 c may overlap with any of the source lines 15 S in the first to M th columns.
- the gate line detour sections 50 G and the source line detour sections 50 S are provided only for intersections corresponding to the green pixel electrodes 17 G from among the intersections between the gate lines 13 G and the source lines 15 S.
- the gate line detour sections 50 G and the source line detour sections 50 S are provided once every three pixels in the present embodiment, in contrast to being provided once every single pixel in the aforementioned embodiment 3. Therefore, the ratio of the area taken up by the gate line detour sections 50 G and the source line detour sections 50 S with respect to the display region 41 decreases to approximately 1 ⁇ 3 in the present embodiment in comparison to embodiment 3. Consequently, it is possible to suppress a decrease in the aperture ratio caused by the gate line detour sections 50 G and the source line detour sections 50 S.
- the gate line detour sections 50 G and the source line detour sections 50 S may have a small area, and to have a shape that is bent in a simple manner as in the examples depicted in FIGS. 6 to 10 , for example. It should be noted that the gate line detour sections 50 G and the source line detour sections 50 S may be provided once every two pixels, twice every three pixels, or once every four or more pixels.
- the active matrix substrate 20 a in the present embodiment includes: (i) K source lines 15 S (first source lines) that transmit source signals for a green component (first source signals) from the ⁇ Y direction toward the +Y direction; (ii) N gate lines 13 G that intersect the source lines 15 S that transmit the source signals for the green component, only at intersections (first intersections) where the gate line detour sections 50 G are provided in a corresponding manner, and transmit gate signals from the ⁇ X direction toward the +X direction; (iii) N auxiliary capacitance lines 13 CS that intersect at intersections (second intersections) with the source lines 15 S that transmit the source signals for the green component, and transmit auxiliary capacitance signals from the ⁇ X direction toward the +X direction; and (iv) 2K source lines 15 S (second source lines) that transmit source signals for a red component and a blue component (second source signals) from the ⁇ Y direction toward the +Y direction, intersect at intersections (third intersections) with the gate lines 13 G, and intersect at intersections (fourth
- source signals (first source signals) transmitted by source lines 15 S (first source lines) that pass through intersections (first intersections) with gate lines 13 G on which the gate line detour sections 50 G are provided indicate image information for green.
- Source signals (first source signals) transmitted by source lines 15 S (second source lines) that pass through intersections (third intersections) with gate lines 13 G on which the gate line detour sections 50 G are not provided indicate image information for green and for red, a different color from green.
- the laser light position tolerance was ⁇ (p ⁇ d S )/2. Consequently, by providing the gate line detour sections 50 G for intersections through which some source lines 15 S from among the plurality of source lines 15 S pass, the laser light position tolerance can be increased.
- the isolated region 43 that includes regions where a short circuit may have occurred due to the mechanical dividing of the display panel 2 can be electrically isolated from the display region 41 by radiating laser light along the laser scanning line 25 c . Therefore, an effect is demonstrated in that short circuits and display defects caused by the short circuits are reliably removed from the display region 41 of the display panel 2 after having been divided.
- the laser light position tolerance can be increased. Furthermore, it is possible to suppress a decrease in the aperture ratio of the display panel 2 caused by the gate line detour sections 50 G and the source line detour sections 50 S.
- FIGS. 11, 12, and 13 Another embodiment of the present disclosure is as follows when described on the basis of FIGS. 11, 12, and 13 . It should be noted that, for convenience of the description, members having the same functions as the members described in the aforementioned embodiment are denoted by the same reference signs and descriptions thereof are omitted.
- FIGS. 11( a ) and ( b ) are top views depicting schematic configurations of different working examples of a liquid crystal display device 1 according to the present embodiment.
- the liquid crystal display device 1 is provided with a display panel 2 , a source driver 3 , a gate driver 11 , a display control circuit 4 , and a power source 5 .
- the display panel 2 is provided with an active matrix substrate 20 a , an opposite substrate 20 b , and a liquid crystal layer (not depicted) held between these substrates.
- the active matrix substrate 20 a includes an insulating substrate 2 a , N gate lines 13 G, N auxiliary capacitance lines 13 CS, and M source lines 15 S, with gate line detour sections 50 G being provided in the gate lines 13 G, and source line detour sections 50 S being provided in the source lines 15 S.
- a gate driver 11 or part of the gate driver 11 is formed inside pixel regions, which are regions in which a pixel electrode is arranged corresponding to a gate line 13 G and a source line 15 S.
- the gate driver 11 (i) is connected to at least some wiring including a gate line 13 G, (ii) controls the potential of the wiring including the gate line 13 G in accordance with a control signal supplied from outside a display region that includes the pixel regions defined by the gate lines 13 G and the source lines 15 S, and (iii) includes a plurality of switching elements (second switching elements) at least some of which are formed in the pixel regions.
- PTL 3 is cited herein for reference.
- the dividing lines 25 along which the display panel 2 is divided can be altered to lines having various shapes. Consequently, in addition to altering the size of the display panel 2 , it becomes possible to alter the shape of the display panel 2 to various shapes such as those in FIGS. 11( a ) and ( b ) . It should be noted that the scope of the present disclosure is not restricted hereto, and the technique in which at least part of the gate driver 11 is formed inside the pixel regions may be combined with any of the aforementioned embodiments 1, 2, 4, and 5.
- the gate line detour sections 50 G and the source line detour sections 50 S are defined on the basis of the transmission directions of gate signals and source signals and the positions of intersections between the gate line 13 G and the source line 15 S. Consequently, as in FIG. 11 , in a case where the gate driver 11 is provided inside the display region 41 , and in a case where the gate driver 11 is provided in plurality, the X axis direction is set so that gate signals are transmitted from the ⁇ X direction toward the +X direction. Specifically, the direction going away from each gate driver 11 is taken as the +X direction and the direction coming toward each gate driver 11 is taken as the ⁇ X direction.
- FIGS. 12( a ) and ( b ) are top views depicting the relationship between the shape of the dividing lines 25 and the arrangement of the gate drivers 11 , in the liquid crystal display device 1 device according to the present embodiment.
- the gate drivers 11 are provided with one at the left and one at the right, on the active matrix substrate 20 a provided in the display panel 2 .
- the gate lines 13 G that pass within a region 44 are divided according to the dividing lines 25 and are not connected to the gate drivers 11 . Therefore, within the region 44 , gate signals are not transmitted and therefore images are not displayed.
- one gate driver 11 is provided in the center of the active matrix substrate 20 a provided in the display panel 2 .
- gate lines 13 G that pass within the region 44 are connected to the gate driver 11 at the upper side of the display panel 2 . Therefore, within the region 44 , gate signals are transmitted and images are displayed.
- the gate drivers 11 are arranged so as to conform to the shape of the dividing lines 25 , or the shape of the dividing lines 25 is set so as to conform to the arrangement of the gate drivers 11 .
- the gate drivers 11 are arranged and/or the shape of the dividing lines 25 is set so that both gate signals and source signals are transmitted to all pixels included within the display region 41 after having been divided, so that each gate line 13 G included within the divided display region 41 is connected to the gate drivers 11 , and so that each source line 15 S included within the divided display region 41 is connected to the source driver 3 .
- the longest length in the Y axis direction of the gate drivers 11 included in the display region 41 of the panel 2 after having been divided and the longest length in the Y axis direction of the display region 41 match each other. This is because (i) the gate drivers 11 are divided according to the dividing lines 25 together with the active matrix substrate 20 a and therefore the gate drivers 11 are never longer than the display region 41 , and (ii) in a case where the gate drivers 11 are shorter than the longest length of the display region 41 , a region where display is not possible is formed, such as the region 44 of FIG. 12( a ) .
- FIG. 13 is a top view depicting a schematic configuration of the dividing lines 25 according to the present embodiment.
- the gap between the active matrix substrate dividing line 25 a and the opposite substrate dividing line 25 b is preferable for the gap between the active matrix substrate dividing line 25 a and the opposite substrate dividing line 25 b to be 0.5 mm to 2 mm.
- the laser scanning line 25 c is set so as to have a stepped form along a grid formed by the gate lines 13 G and the source lines 15 S, at an outer side along the active matrix substrate dividing line 25 a.
- An active matrix substrate ( 20 a ) is a configuration including: a plurality of source lines ( 15 S) including a plurality of first source lines that transmit a first source signal from a ⁇ Y direction toward a +Y direction; and a plurality of gate lines ( 13 G) that intersect the plurality of first source lines only at a plurality of first intersections, and transmit a gate signal from a ⁇ X direction toward a +X direction, in the gate lines, gate line detour sections ( 50 G) being provided corresponding to each of the first intersections, and each of the gate line detour sections having: a first start section ( 51 G) in which the corresponding gate line is bent toward the +Y direction or the ⁇ Y direction from a first start position (X G,m (1) with reference to FIGS.
- the boundary section in a case where a boundary section at the ⁇ X direction side between an irradiated region, where laser light is radiated onto the active matrix substrate for the gate lines to be divided, and a non-irradiated region superposes a first intersection, the boundary section also superposes the first straddling sections of the gate line detour section corresponding to the first intersection. Therefore, the gate lines are invariably divided at the first straddling sections and/or between the first straddling sections of the corresponding gate line detour section, and therefore, in a case where a boundary section superposes a first intersection, the corresponding gate line detour section is divided.
- a first intersection that may have short-circuited due to superposing a boundary section between an irradiated region and a non-irradiated region is isolated from intersections (including first intersections) between gate lines and source lines that are in the ⁇ X direction relative to the first intersection.
- gate lines intersect first source lines only at first intersections, and the gate line detour sections start from a first start position that is in the ⁇ X direction relative to a first intersection, and straddle a first straight line that passes through the +X direction end of the first intersection. Consequently, the gate line detour sections straddle the first straight line from the ⁇ X direction toward the +X direction, and thereafter straddle the first straight line so as to return from the +X direction toward the ⁇ X direction.
- An active matrix substrate ( 20 a ) according to aspect 2 of the present disclosure may be a configuration in which, in the aforementioned aspect 1, source line first detour sections ( 50 S) in which the first source lines detour around the gate line detour sections ( 50 G) are provided in the first source lines ( 15 S).
- the first source lines detour in such a way as to not superpose the gate line detour sections. Therefore, it is possible for the gate lines to intersect the first source lines only at the first intersections.
- An active matrix substrate ( 20 a ) according to aspect 3 of the present disclosure may be a configuration in which, in the aforementioned aspect 2, the gate lines ( 13 G) of the gate line detour sections ( 50 G) and the first source lines ( 15 S) of the source line first detour sections ( 50 S) pass through positions that are different from a plurality of first switching elements (T) that correspond to the first intersections.
- the gate lines of the gate line detour sections and the first source lines of the source line first detour sections pass through positions that are different from the first switching elements. Therefore, it becomes possible for the gate line detour sections and the source line first detour sections to not superpose the first switching elements.
- An active matrix substrate ( 20 a ) according to aspect 4 of the present disclosure may be a configuration in which, in any one aspect of the aforementioned aspects 1 to 3, each of the gate line detour sections ( 50 G) has a first end section ( 53 G) in which the corresponding gate line ( 13 G) returns to a first end position (X G,m (3) with reference to FIGS. 6 and 8 ) that is in the ⁇ X direction relative to the corresponding first intersection (C G,n,m with reference to FIGS. 6 and 8 ) and in the +X direction relative to the first start position (X G,m (1) with reference to FIGS. 6 and 8 ), and each of the gate lines connects between the first intersections and the corresponding first end positions, and connects between the corresponding first end positions and the corresponding first start positions by means of only the gate line detour sections.
- a first end position and a first start position corresponding to the same first intersection are connected by means of only the corresponding gate line detour section. Consequently, when a gate line detour section is divided, the corresponding first intersection is isolated from other first intersections that are in the ⁇ X direction.
- An active matrix substrate ( 20 a ) according to aspect 5 of the present disclosure may be a configuration that, in any one aspect of the aforementioned aspects 1 to 4, further includes a plurality of auxiliary capacitance lines ( 13 CS) that intersect the plurality of first source lines ( 15 S) only at a plurality of second intersections, and transmit an auxiliary capacitance signal from the ⁇ X direction toward the +X direction.
- An active matrix substrate ( 20 a ) according to aspect 6 of the present disclosure may be a configuration in which, in the aforementioned aspect 5, in the auxiliary capacitance lines ( 13 CS), auxiliary capacitance line detour sections ( 50 CS) are provided corresponding to each of the second intersections, and each of the auxiliary capacitance line detour sections has: a second start section in which the corresponding auxiliary capacitance line is bent toward the +Y direction or the ⁇ Y direction from a second start position (X CS,m (1) with reference to FIG. 9 ) that is in the ⁇ X direction relative to the corresponding second intersection (C CS,n,m with reference to FIG.
- the boundary section in a case where a boundary section at the ⁇ X direction side between an irradiated region, where laser light is radiated onto the active matrix substrate, and a non-irradiated region superposes a second intersection, the boundary section also superposes the second straddling sections of the auxiliary capacitance line detour section corresponding to the second intersection. Therefore, the auxiliary capacitance lines are invariably divided at the second straddling sections and/or between the second straddling sections of the corresponding auxiliary capacitance line detour section, and therefore, in a case where a boundary section superposes a second intersection, the corresponding auxiliary capacitance line detour section is divided.
- a second intersection that may have short-circuited due to superposing a boundary section between an irradiated region and a non-irradiated region is isolated from intersections (including second intersections) between auxiliary capacitance lines and source lines that are in the ⁇ X direction relative to the second intersection.
- An active matrix substrate ( 20 a ) according to aspect 7 of the present disclosure may be a configuration in which, in the aforementioned aspect 6, source line second detour sections ( 50 G) in which the first source lines detour around the auxiliary capacitance line detour sections ( 50 CS) are provided in the first source lines ( 15 S).
- the first source lines detour in such a way as to not superpose the auxiliary capacitance line detour sections. Therefore, it is possible for the auxiliary capacitance lines to intersect the first source lines only at the second intersections.
- An active matrix substrate ( 20 a ) according to aspect 8 of the present disclosure may be a configuration in which, in the aforementioned aspect 7, the auxiliary capacitance lines ( 13 CS) of the auxiliary capacitance line detour sections ( 50 CS) and the first source lines ( 15 S) of the source line second detour sections ( 50 S) pass through positions that are different from the plurality of first switching elements (T) that correspond to the first intersections.
- the auxiliary capacitance lines of the auxiliary capacitance line detour sections and the first source lines of the source line second detour sections pass through positions that are different from the first switching elements. Therefore, it becomes possible for the auxiliary capacitance line detour sections and the source line second detour sections to not superpose the first switching elements.
- An active matrix substrate ( 20 a ) according to aspect 9 of the present disclosure may be a configuration in which, in any one aspect of the aforementioned aspects 6 to 8, each of the auxiliary capacitance line detour sections ( 50 CS) has a second end section ( 53 CS) in which the corresponding auxiliary capacitance line returns to a second end position (X CS,m (3) with reference to FIG. 9 ) that is in the ⁇ X direction relative to the corresponding second intersection (C CS,n,m with reference to FIG. 9 ) and in the +X direction relative to the second start position (X CS,m (1) with reference to FIG. 9 ), and each of the auxiliary capacitance lines connects between the second intersections and the corresponding second end positions, and connects between the corresponding second end positions and the corresponding second start positions by means of only the auxiliary capacitance line detour sections.
- a second end position and a second start position corresponding to the same second intersection are connected by means of only the corresponding auxiliary capacitance line detour section. Consequently, when an auxiliary capacitance line detour section is divided, the corresponding second intersection is isolated from other second intersections that are in the ⁇ X direction.
- An active matrix substrate according to aspect 10 of the present disclosure may be a configuration in which, in any one aspect of the aforementioned aspects 1 to 9, the plurality of source lines further include a plurality of second source lines that transmit a second source signal from the ⁇ Y direction toward the +Y direction, and intersect the plurality of gate lines only at third intersections.
- gate line detour sections corresponding to the third intersections may not be provided in the gate lines.
- An active matrix substrate may be a configuration in which, in any one aspect of the aforementioned aspects 5 to 9, the plurality of source lines further include a plurality of second source lines that transmit a second source signal from the ⁇ Y direction toward the +Y direction, intersect the plurality of gate lines only at third intersections, and intersect the plurality of auxiliary capacitance lines only at fourth intersections.
- gate line detour sections corresponding to the third intersections may not be provided in the gate lines.
- An active matrix substrate ( 20 a ) according to aspect 12 of the present disclosure may be a configuration in which, in the aforementioned aspect 10 or 11, the second source signal (image information for red and image information for blue) indicates image information for a color that is different from the first source signal (image information for green).
- An active matrix substrate ( 20 a ) according to aspect 13 of the present disclosure may be a configuration that, in any one aspect of the aforementioned aspects 1 to 12, further includes a gate driving circuit (gate driver 11 ) that supplies the gate signal to at least some of the plurality of gate lines ( 13 G), and has a plurality of second switching elements, at least some of the plurality of second switching elements being formed in pixel regions defined by the plurality of source lines and the plurality of gate lines.
- gate driver 11 that supplies the gate signal to at least some of the plurality of gate lines ( 13 G), and has a plurality of second switching elements, at least some of the plurality of second switching elements being formed in pixel regions defined by the plurality of source lines and the plurality of gate lines.
- An active matrix substrate ( 20 a ) according to aspect 14 of the present disclosure may be a configuration in which, in any one aspect of the aforementioned aspects 1 to 13, the +X and ⁇ X directions and the +Y and ⁇ Y directions are mutually orthogonal.
- a display panel ( 2 ) according to aspect 15 of the present disclosure is a configuration provided with: the active matrix substrate ( 20 a ) according to any one of the aforementioned aspects 1 to 14; an opposite substrate ( 20 b ); and a liquid crystal layer held between the active matrix substrate and the opposite substrate.
- a display device is a configuration provided with the display panel according to the aforementioned aspect 15.
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Abstract
Description
- The present disclosure relates to an active matrix substrate, a display panel, and a display device provided with the same, and particularly relates to altering the size of an active matrix substrate and a display panel including the same.
- In display panels such as liquid crystal displays and electronic flat panel displays, there is a demand for altering the size of the display panel.
- However, when a display panel provided with an active matrix substrate is mechanically divided in order to alter the size, a short circuit may occur near the dividing line. This short circuit then causes a display defect in the display panel after the size alteration.
- In the invention described in
PTL 1, in order to prevent a display defect caused by this short circuit, it is disclosed that short circuits are detected and repaired after a liquid crystal display has been divided. - In the invention described in
PTL 2, as a method for dividing wiring or electrodes on a substrate without dividing the substrate itself, a method is disclosed in which laser light is scanned on the substrate and the material of the wiring or electrodes in a laser light irradiated region is evaporated. - PTL 1: Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2013-532304 (published on Aug. 15, 2013)
- PTL 2: Japanese Unexamined Patent Application Publication No. 10-186392 (published on Jul. 14, 1998)
- PTL 3: International Publication No. WO2014/069529 (published on May 8, 2014)
- In the invention described in the
aforementioned PTL 1, short circuits are detected and repaired after a display panel has been divided, and a display region of the divided display panel is connected to the portions where the short circuits have been repaired. Therefore, there is a problem in that if a repaired short circuit reoccurs, a display defect reoccurs in the display panel. - The present disclosure takes the aforementioned problem into consideration, and an objective thereof is to realize an active matrix substrate with which regions where a short circuit may have occurred due to dividing can be isolated from a display region.
- In order to solve the aforementioned problem, an active matrix substrate according to one aspect of the present disclosure is a configuration including: a plurality of source lines including a plurality of first source lines that transmit a first source signal from a −Y direction toward a +Y direction; and a plurality of gate lines that intersect the plurality of first source lines only at a plurality of first intersections, and transmit a gate signal from a −X direction toward a +X direction, in the gate lines, gate line detour sections being provided corresponding to each of the first intersections, and each of the gate line detour sections having: a first start section in which the corresponding gate line is bent toward the +Y direction or the −Y direction from a first start position that is in the −X direction relative to the corresponding first intersection; and first straddling sections in which the corresponding gate line straddles a first straight line that passes through a +X direction end of the corresponding first intersection and extends in the +Y direction and the −Y direction.
- According to one aspect of the present disclosure, an effect is demonstrated in which regions where a short circuit may have occurred due to dividing can be isolated from a display region.
-
FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device according to several embodiments of the present disclosure. -
FIG. 2 is a top view depicting a schematic configuration of an active matrix substrate according to several embodiments of the present disclosure. -
FIG. 3(a) is a top view depicting a schematic configuration of dividing lines along which a display panel is divided, andFIG. 3(b) is a perspective view depicting a schematic configuration of the vicinity of the dividing lines of the display panel after having been mechanically divided, according to several embodiments of the present disclosure. -
FIG. 4 is a top view depicting a schematic configuration of wiring near a laser scanning line of an active matrix substrate according to one embodiment of the present disclosure. -
FIG. 5 is a top view depicting a schematic configuration of an active matrix substrate according to one embodiment of the present disclosure. -
FIG. 6 is a top view depicting a schematic configuration of an active matrix substrate, for depicting one working example of gate line detour sections and source line detour sections according to one embodiment of the present disclosure. -
FIG. 7 is a top view depicting a schematic configuration of the active matrix substrate, in a case where a boundary section at the −X direction side of a laser light irradiated region L superposes a source line, in the working example depicted inFIG. 6 . -
FIG. 8 is a top view depicting a schematic configuration of an active matrix substrate, for depicting one working example of gate line detour sections and source line detour sections according to one embodiment of the present disclosure. -
FIG. 9 is a top view depicting a schematic configuration of an active matrix substrate, for depicting one working example of gate line detour sections and source line detour sections according to one embodiment of the present disclosure. -
FIG. 10 is a top view depicting a schematic arrangement of gate line detour sections and source line detour sections in an active matrix substrate according to one embodiment of the present disclosure. -
FIG. 11 is a top view depicting a schematic configuration of (a) one working example and (b) another working example of a liquid crystal display device according to one embodiment of the present disclosure. -
FIG. 12 is a top view depicting the relationship between the shape of a dividing line and the arrangement of a gate driver, in a liquid crystal display device according to one embodiment of the present disclosure. -
FIG. 13 is a top view depicting a schematic configuration of a dividing line according to one embodiment of the present disclosure. - Hereinafter, one embodiment of the present disclosure will be described in detail with reference to
FIGS. 1, 2, 3 , and 4. -
FIG. 1 is a top view depicting a schematic configuration of a liquidcrystal display device 1 according to the present embodiment. - The liquid crystal display device 1 (display device) is provided with a
display panel 2, asource driver 3, a gate driver 11 (gate driving circuit), adisplay control circuit 4, and apower source 5. Thedisplay panel 2 is provided with anactive matrix substrate 20 a, anopposite substrate 20 b, and a liquid crystal layer (not depicted) held between theactive matrix substrate 20 a and theopposite substrate 20 b. Although not depicted inFIG. 1 , a polarizer is provided at the lower surface side (−Z side) of theactive matrix substrate 20 a and the upper surface side (+Z side) of theopposite substrate 20 b. A black matrix, three color filters of red (R), green (G), and blue (B), and a common electrode (none depicted) are formed on theopposite substrate 20 b. - As depicted in
FIG. 1 , theactive matrix substrate 20 a is electrically connected to thesource driver 3 and thegate driver 11, which are formed on a flexible substrate. Thedisplay control circuit 4 is electrically connected to thedisplay panel 2, thesource driver 3, thegate driver 11, and thepower source 5. Thedisplay control circuit 4 outputs control signals to thesource driver 3 and thegate driver 11. The control signals include a reset signal, a clock signal, a source signal, and the like for displaying images on thedisplay panel 2. Thepower source 5 is electrically connected to thedisplay panel 2, thesource driver 3, and thedisplay control circuit 4, and supplies power source voltage signals to each thereof. -
FIG. 2 is a top view depicting a schematic configuration of theactive matrix substrate 20 a. - The
active matrix substrate 20 a includes aninsulating substrate 2 a such as a glass substrate, andN gate lines 13G, N auxiliary capacitance lines 13CS, andM source lines 15S that are formed on theinsulating substrate 2 a (N and M are natural numbers that are greater than or equal to 2). - The
N gate lines 13G are formed to be substantially parallel at substantially equal intervals from one end (−X direction end) of theinsulating substrate 2 a to the other end (+X direction end) in the X axis direction. The N auxiliary capacitance lines 13CS are also similarly formed to be substantially parallel at substantially equal intervals from one end (−X direction end) of theinsulating substrate 2 a to the other end (+X direction end). Furthermore, theM source lines 15S (first source lines and second source lines) are formed to be substantially parallel at substantially equal intervals from one end (−Y direction end) of theinsulating substrate 2 a to the other end (+Y direction end) in the Y axis direction so as to intersect theN gate lines 13G and the N auxiliary capacitance lines 13CS. - The
N gate lines 13G are electrically connected to thegate driver 11, and transmit gate signals generated by thegate driver 11 from the −X direction toward the +X direction. The N auxiliary capacitance lines 13CS also similarly transmit auxiliary capacitance voltages (auxiliary capacitance signals) from the −X direction toward the +X direction. TheM source lines 15S are electrically connected to thesource driver 3, and transmit source signals (first source signals and second source signals) generated by thesource driver 3 from the −Y direction toward the +Y direction. The X axis and the Y axis are substantially orthogonal. - Each region enclosed by the
gate lines 13G and thesource lines 15S is a pixel region, and, although not depicted inFIG. 2 , one pixel electrode and one switching element (first switching element) are formed in each pixel region. Each pixel electrode corresponds to any color of the color filters, and is connected to agate line 13G and asource line 15S via a switching element. The switching elements are thin film transistors (TFTs), for example, and the gate electrodes of the TFTs are arranged on theinsulating substrate 2 a similar to thegate lines 13G and are connected to thecorresponding gate lines 13G. Furthermore, the source electrodes and the drain electrodes of the TFTs are arranged on a gate insulating film similar to thesource lines 15S being arranged on an insulating film, and are connected to thecorresponding source lines 15S and pixel electrodes. - In
FIG. 2 , one auxiliary capacitance line 13CS is provided with respect to onegate line 13G, and thegate lines 13G and the auxiliary capacitance lines 13CS are arranged in an alternating manner. There is no restriction thereto, and a plurality of auxiliary capacitance lines 13CS may be provided with respect to onegate line 13G. -
FIG. 3 is a drawing for describing the dividing of thedisplay panel 2 according to dividinglines 25. -
FIG. 3(a) is a top view depicting a schematic configuration of thedividing lines 25 along which thedisplay panel 2 is divided. - The
dividing lines 25 include an active matrixsubstrate dividing line 25 a along which theactive matrix substrate 20 a is mechanically divided, an oppositesubstrate dividing line 25 b along which theopposite substrate 20 b is mechanically divided, and alaser scanning line 25 c along which thegate lines 13G and the auxiliary capacitance lines 13CS (and also the source lines 15S in some cases) on theactive matrix substrate 20 a are divided. - The active matrix
substrate dividing line 25 a, the oppositesubstrate dividing line 25 b, and thelaser scanning line 25 c are substantially parallel with each other in the Y axis direction. The oppositesubstrate dividing line 25 b is positioned at the side near the gate driver 11 (−X side), seen from the active matrixsubstrate dividing line 25 a. It is preferable for the gap between the active matrixsubstrate dividing line 25 a and the oppositesubstrate dividing line 25 b to be 0.5 mm to 2 mm, although this depends on the extent to which the mechanical dividing of theactive matrix substrate 20 a affects thegate lines 13G and the auxiliary capacitance lines 13CS. Furthermore, thelaser scanning line 25 c is positioned between the active matrixsubstrate dividing line 25 a and the oppositesubstrate dividing line 25 b. - In the
display panel 2 after having been divided along thedividing lines 25, aregion 41 at the side (−X side) nearer thegate driver 11 than the oppositesubstrate dividing line 25 bactive matrix substrate 20 a becomes adisplay region 41. Furthermore, aregion 42 at the side (+X side) further from thegate driver 11 than the active matrixsubstrate dividing line 25 a becomes anon-display region 42. Furthermore, from within thenon-display region 42, aregion 43 that is electrically isolated from thedisplay region 41 due to laser scanning along thelaser scanning line 25 c becomes anisolated region 43. - The
isolated region 43 includes regions where a short circuit may occur due to mechanical dividing along the active matrixsubstrate dividing line 25 a. Therefore, thedisplay region 41 is isolated from the regions where a short circuit may have occurred, due to the laser scanning along thelaser scanning line 25 c. Consequently, it is preferable for thelaser scanning line 25 c to be sufficiently separated from the active matrixsubstrate dividing line 25 a so that theisolated region 43 includes all regions where a short circuit may have occurred. Furthermore, in the present embodiment, although described in detail later, it is preferable for the laser light that is radiated along thelaser scanning line 25 c to be away from thesource lines 15S so that thegate lines 13G do not short circuit to the source lines 15S, with consideration being given to the width of the source lines 15S and width of the laser light. -
FIG. 3(b) is a perspective view depicting a schematic configuration of the vicinity of thedividing lines 25 of thedisplay panel 2 after having been mechanically divided. InFIG. 3(b) , thesource lines 15S are depicted as solid lines, thegate lines 13G are depicted as one-dot chain lines, and the auxiliary capacitance lines 13CS are depicted as two-dot chain lines. Hereinafter, a process for dividing thedisplay panel 2 will be described with reference toFIG. 3(b) . - First, the
active matrix substrate 20 a is mechanically divided along the active matrixsubstrate dividing line 25 a. At such time, thegate lines 13G and the auxiliary capacitance lines 13CS are also divided together with the insulatingsubstrate 2 a. The gate lines 13G and the auxiliary capacitance lines 13CS near the active matrixsubstrate dividing line 25 a may have short-circuited or may short-circuit during use of thedisplay panel 2 since a mechanical external force is applied. - Next, the
opposite substrate 20 b is likewise mechanically divided along the oppositesubstrate dividing line 25 b. It should be noted that the dividing of theactive matrix substrate 20 a and the dividing of theopposite substrate 20 b may be carried out one after the other or may be carried out at the same time. - A
liquid crystal layer 30 that is exposed on theactive matrix substrate 20 a within thenon-display region 42 is then removed. Wiring (gate lines 13G, auxiliary capacitance lines 13CS, andsource lines 15S) on the insulatingsubstrate 2 a within thenon-display region 42 is thereby exposed. Due to this exposure, it becomes easy to radiate a scanning laser in the next step. - Next, a laser is scanned on the surface of the
active matrix substrate 20 a along thelaser scanning line 25 c. Due to the laser scanning, wiring (gate lines 13G, auxiliary capacitance lines 13CS, andsource lines 15S) within the laser irradiated region is evaporated and removed. As a result, wiring at the side nearer the active matrixsubstrate dividing line 25 a than the laser irradiated region (+X direction) is isolated from wiring at the side nearer the gate driver 11 (−X direction). - After carrying out dividing such as the aforementioned, the
liquid crystal layer 30 within thedisplay region 41 held between theactive matrix substrate 20 a and theopposite substrate 20 b is sealed with a sealing material (in a case where theliquid crystal layer 30 is lacking, a liquid crystal composition that forms theliquid crystal layer 30 is injected prior to the sealing). -
FIG. 4 is a top view depicting a schematic configuration of wiring near thelaser scanning line 25 c of theactive matrix substrate 20 a. It should be noted that, inFIG. 4 , the insulatingsubstrate 2 a, pixel electrodes, insulating layers, and the like are omitted in order to aid understanding of the schematic structure of the wiring. - Switching elements T (first switching elements) for applying source signals in accordance with gate signals to the pixel electrodes are provided on the
active matrix substrate 20 a. The switching elements T are thin film transistors (TFTs), for example, and are provided corresponding to intersections between thegate lines 13G and the source lines 15S. - As depicted in
FIG. 4 , when laser light having a width r is radiated along thelaser scanning line 25 c, an irradiated region L having the width r along thelaser scanning line 25 c is generated, and the portion of the wiring (gate lines 13G, auxiliary capacitance lines 13CS, andsource lines 15S) inside the irradiated region L is evaporated and removed. Meanwhile, at the boundary sections between the irradiated region L and non-irradiated regions, the material forming the wiring melts and remains without evaporating. The gate lines 13G, the auxiliary capacitance lines 13CS, and the source lines 15S are laminated with an insulating layer interposed, and therefore, due to the melting, thegate lines 13G and the source lines 15S may short-circuit at the intersections between thegate lines 13G and the source lines 15S. Similarly, due to the melting, the auxiliary capacitance lines 13CS and the source lines 15S may short-circuit at intersections between the auxiliary capacitance lines 13CS and the source lines 15S. Therefore, in a case where the boundary section nearer the gate driver 11 (−X side) out of the boundary sections between the irradiated region L and the non-irradiated regions superposes an intersection CG,n,m where thegate line 13G of an nth row (n being a natural number greater than or equal to 1 and less than or equal to N−1) from thesource driver 3 and thesource line 15S of an mth column (m being a natural number greater than or equal to 1 and less than or equal to M−1) from thegate driver 11 intersect, thegate line 13G and thesource line 15S may short-circuit at the intersection CG,n,m. Therefore, it is necessary for the laser light irradiated region L to satisfy the relationship of expression (1) below. -
X S,m +d S/2<X L −r/2<X S,m+1 −d S/2 (1) - In which,
- XS,m is the X coordinate of the center line of the
source line 15S of the mth column from thegate driver 11, - XL is the X coordinate of the center line of the irradiated region L,
- dS is the width of the
source line 15S, and - r is the width of the laser light radiated along the
laser scanning line 25 c and the width of the irradiated region L. - Furthermore, conversely, in a case where the laser light irradiated region L does not satisfy the relationship of expression (1), in other words, in a case where the relationship of expression (2) below is satisfied, the
gate line 13G and thesource line 15S may short-circuit at the intersection CG,n,m. -
X S,m −d S/2≤X L −r/2≤X S,m +d S/2 (2) - Also, p=XS,m+1−XS,m when a sub-pixel pitch is taken as p, and therefore the laser light position tolerance is ±(p−dS)/2.
- Consequently, with regard to position tolerance, which is the difference between the X coordinate of the center line of the irradiated region L and the X coordinate of the
laser scanning line 25 c, it is necessary for the position tolerance for the radiation of laser light along thelaser scanning line 25 c to be less than ±(p−dS)/2, and is preferably even smaller. Furthermore, it is preferable for thelaser scanning line 25 c to be away from the source lines 15S. - In the invention described in the
aforementioned PTL 1, there is a problem in that there is a possibility of a repaired short circuit reoccurring during the use, operation lifetime, and so forth of a display panel, and of a weak portion that has not short-circuited then short-circuiting immediately after the display panel is divided. With respect to this problem, in the invention described in theaforementioned PTL 1, additional stress testing is carried out, and weak portions that may short-circuit during use, the operation lifetime, and so forth are exposed. - However, in the dividing of the
display panel 2 including theactive matrix substrate 20 a according to the present embodiment of the present disclosure, theisolated region 43 that includes regions where a short circuit may occur is electrically isolated from thedisplay region 41 due to laser light being radiated along thelaser scanning line 25 c. Therefore, short-circuiting caused by the dividing has no bearing on thedisplay region 41, and display defects caused by short-circuiting due to the dividing are not generated therein. - Another embodiment of the present disclosure is as follows when described on the basis of
FIGS. 1, 5, 6, and 7 . It should be noted that, for convenience of the description, members having the same functions as the members described in the aforementioned embodiment are denoted by the same reference signs and descriptions thereof are omitted. -
FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device according to the present embodiment. - A liquid
crystal display device 1 is provided with adisplay panel 2, asource driver 3, agate driver 11, adisplay control circuit 4, and apower source 5. Thedisplay panel 2 is provided with anactive matrix substrate 20 a, anopposite substrate 20 b, and a liquid crystal layer (not depicted) held between these substrates. -
FIG. 5 is a top view depicting a schematic configuration of theactive matrix substrate 20 a. - The
active matrix substrate 20 a includes an insulatingsubstrate 2 a such as a glass substrate, andN gate lines 13G, N auxiliary capacitance lines 13CS, and M source lines 15S that are formed on the insulatingsubstrate 2 a (N and M are natural numbers that are greater than or equal to 2). - In the present embodiment, different from the
aforementioned embodiment 1, gateline detour sections 50G are provided in eachgate line 13G and sourceline detour sections 50S (source line first detour sections) are provided in eachsource line 15S, as inFIGS. 6 and 7 , although not depicted inFIG. 5 . - The gate
line detour sections 50G are provided corresponding to intersections between thegate lines 13G and the source lines 15S. The gateline detour sections 50G are portions formed in such a way that thegate lines 13G detour so that (i)gate lines 13G extending from the −X direction end of theactive matrix substrate 20 a prior to passing through corresponding intersections are divided at the irradiated region L in a case where the laser light irradiated region L satisfies the relationship of expression (2), and so that (ii) intersections where thegate lines 13G intersect (themselves or other wiring, including being superposed in parallel) are not newly made (in other words, are not increased). This is because, in a case where there is an increase in intersections in thegate lines 13G, those intersections may short-circuit when the boundary sections of the irradiated region L superpose those intersections. - The source
line detour sections 50S are provided corresponding to the gateline detour sections 50G. The sourceline detour sections 50S are portions formed in such a way that the source lines 15S avoid the corresponding gateline detour sections 50G so that intersections where the source lines 15S intersect (themselves or other wiring) are not newly made. - The gate
line detour sections 50G do not cause an increase in intersections, as previously mentioned. Therefore, thegate lines 13G intersect the source lines 15S only at intersections (first intersections) where the gateline detour sections 50G are provided in a corresponding manner. Furthermore, thegate lines 13G do not intersect themselves and do not intersect otheradjacent gate lines 13G. As a result, thegate lines 13G start detouring with thegate lines 13G bending from a start position (first start position) between a corresponding intersection and another intersection adjacent at the −X direction side to the corresponding intersection (in the −X direction relative to the corresponding intersection), toward the −Y direction or the +Y direction. Similarly, when thegate lines 13G stop detouring, thegate lines 13G return from the −Y direction or the +Y direction to an end position (first end position) between the corresponding intersection and the start position (in the −X direction relative to the corresponding intersection, and in the +X direction relative to the start position). Thegate lines 13G having finished detouring then bend toward the +X direction and pass through the corresponding intersection. - The gate
line detour sections 50G are divided at the irradiated region L in a case where the laser light irradiated region L satisfies the relationship of expression (2). Therefore, thegate lines 13G of the gateline detour sections 50G straddle both a straight line (first straight line) that passes through the +X direction end of the corresponding intersection and extends in the Y axis direction (+Y direction and −Y direction) and a straight line that passes through the −X direction end and extends in the Y axis direction. However, as previously mentioned, the gateline detour sections 50G start from a start position that is in the −X direction relative to the corresponding intersection and finish at an end position that is in the −X direction relative to the corresponding intersection, and therefore thegate lines 13G of the gateline detour sections 50G also straddle a straight line that passes through the −X direction end when straddling a straight line that passes through the +X direction end. - Due to such gate
line detour sections 50G, with reference toFIGS. 4 and 7 in a case where the laser light irradiated region L satisfies the relationship of expression (2), gate signals that are supplied from thegate driver 11 to thegate lines 13G reach the immediately preceding intersection CG,n,m−1, are then interrupted at the gateline detour sections 50G, and do not reach the intersection CG,n,m, which may have short-circuited. - Consequently, with reference to
FIG. 6 , the gateline detour sections 50G include: (i) astart section 51G (first start section) in which thegate line 13G is drawn out in the +Y direction or the −Y direction from a start position that is in the −X direction relative to the corresponding intersection; (ii) straddlingsections 52G (first straddling sections) in which thegate line 13G straddles a straight line that passes through the +X direction end of the corresponding intersection and extends in the Y axis direction; and (iii) anend section 53G (first end section) in which thegate line 13G returns from an end position that is in the −X direction relative to the corresponding intersection and in the +X direction relative to the start position. Thegate line 13G electrically connects: (i) between the end position of the gateline detour section 50G and the corresponding intersection by means of a portion of thegate line 13G that is not the gateline detour section 50G; (ii) between the start position of the gateline detour section 50G and another intersection adjacent at the −X direction side to the corresponding intersection by means of a portion of thegate line 13G that is not the gateline detour section 50G; and (iii) between the start position and the end position of the same gateline detour section 50G by means of only a portion of thegate line 13G that is the gateline detour section 50G. It is preferable for thegate lines 13G of the gateline detour sections 50G and the source lines 15S of the sourceline detour sections 50S to be formed so as to pass through positions that are different from the switching elements T in order to avoid the switching elements T. -
FIG. 6 is a top view depicting a schematic configuration of theactive matrix substrate 20 a, for depicting one working example of the gateline detour sections 50G and the sourceline detour sections 50S in the present embodiment. - Hereinafter, a detailed description will be given with reference to
FIG. 6 of a working example in which thegate lines 13G are bent in a linear and simple manner to thereby form the gateline detour sections 50G, and the source lines 15S are bent in a linear and simple manner to thereby form the sourceline detour sections 50S. However, the examples depicted inFIGS. 6 to 10 are for deepening understanding of the gateline detour sections 50G and the sourceline detour sections 50S, and do not restrict the present disclosure. The gateline detour sections 50G and the sourceline detour sections 50S may be formed in any complex manner so as to branch in a curved manner, bend a large number of times, and so forth. - Hereinafter, M is a natural number that is greater than or equal to 2, m is a natural number that is greater than or equal to 1 and less than or equal to M− 1, N is a natural number that is greater than or equal to 2, and n is a natural number that is greater than or equal to 1 and less than or equal to
N− 1. Furthermore, the widths of the switching elements T in the X axis direction and the Y axis direction are taken as TX and TY. Furthermore, although agate line 13G of the 0th row and asource line 15S of the 0th column do not actually exist, for convenience, it is assumed that thegate line 13G of the 0th row extends along the −Y side end of the active matrix substrate and thesource line 15S of the 0th column extends along the −X side end of the active matrix substrate. - Hereinafter, the magnitude relationship of the X coordinates and the magnitude relationship of the Y coordinates will be examined with regard to the intersection CG,n,m where the
source line 15S of the mth column from thegate driver 11 and thegate line 13G of the nth row from thesource driver 3 intersect, the gateline detour section 50G of thegate line 13G corresponding to the intersection CG,n,m, and the sourceline detour section 50S of thesource line 15S corresponding to the gateline detour section 50G. - In
FIG. 6 , thegate line 13G of the nth row from thesource driver 3 - passes through the intersection CG,n,m−1 in the +X direction,
- turns in the −Y direction at XG,m (1),
- turns in the +X direction at YG,n (1),
- turns in the +Y direction at XG,m (2),
- turns in the −X direction at YG,n (2),
- turns in the +Y direction at XG,m (3),
- turns in the +X direction at YG,n, and
- passes through the intersection CG,n,m in the +X direction.
- In
FIG. 6 , thesource line 15S of the mth column from thegate driver 11 - passes through the intersection CG,n−1,m in the +Y direction,
- turns in the +X direction at YS,n (1),
- turns in the +Y direction at XS,m (1),
- turns in the −X direction at YS,n (2),
- turns in the +Y direction at XS,m, and
- passes through the intersection CG,n,m in the +Y direction.
- It should be noted that
- the coordinates of the central point of the intersection CG,n,m are (XS,m, YG,n),
- the coordinates of the central point of the intersection CG,n−1,m are (XS,m, YG,n−1),
- the coordinates of the central point of the intersection CG,n,m−1 are (XS,m−1, YG,n),
- X coordinates or Y coordinates of center lines of the
gate line 13G are respectively YG,n, XG,m (1), YG,n (1), XG,m (2), YG,n (2), and XG,m (3), and - X coordinates or Y coordinates of center lines of the
source line 15S are respectively XS,m, YS,n (1), XS,m (1), and YS,n (2). - Then, on the basis of (i) the positional relationship of the
start section 51G, the straddlingsections 52G, and theend section 53G provided in the gateline detour sections 50G to each other, with respect to the intersection CG,n,m, the intersection CG,n−1,m, and the intersection CG,n,m−1, and it being preferable for (ii) the sourceline detour sections 50S to be provided so as to avoid the gateline detour sections 50G and (iii) thegate lines 13G of the gateline detour sections 50G and the source lines 15S of the sourceline detour sections 50S to not superpose the switching elements T, if a width dG of thegate lines 13G and a width dS of the source lines 15S are not taken into consideration, the gateline detour section 50G corresponding to the intersection CG,n,m and the sourceline detour section 50S corresponding to that gateline detour section 50G satisfy the relationships of expression (3) and expression (4) below. -
X S,m−1 +T X <X G,m (1) <X G,m (3) <X S,m <X G,m (2) <X S,m (1) <X G,m+1 (1) (3) -
Y G,n−1 <Y S,n (1) <Y G,n (1) <Y G,n (2) <Y S,n (2) <Y G,n −T Y (4) - In addition, if the width dG of the
gate lines 13G and the width dS of the source lines 15S are taken into consideration, it is derived based on the relationship of expression (3) that the gateline detour sections 50G and the sourceline detour sections 50S satisfy the relationships of expressions (5-1) to (5-6) below. Similarly, it is derived based on the relationship of expression (4) that the relationships of expressions (6-1) to (6-5) below are satisfied. -
X S,m−1 +d S/2+T X +d G/2<X G,m (1) (5-1) -
X G,n (1) +d G <X G,m (3) (5-2) -
X G,m (3) +d G/2+d S/2<X S,m (5-3) -
X S,m +d S/2+d G/2<X G,m (2) (5-4) -
X G,m (2) +d G/2+d S/2<X S,m (1) (5-5) -
X S,m (1) +d S/2+d G/2<X G,m+1 (1) (5-6) -
Y G,n−1 +d G/2+d S/2<Y S,n (1) (6-1) -
Y S,n (1) +d S/2+d G/2<Y G,n (1) (6-2) -
Y G,n (1) +d G <Y G,n (2) (6-3) -
Y G,n (2) +d G/2+d S/2<Y S,n (2) (6-4) -
Y S,n (2) +d S/2+d G/2<Y G,n −T Y (6-5) -
FIG. 7 is a top view depicting a schematic configuration in a case where the laser light irradiated region L satisfies the relationship of expression (2), in the working example depicted inFIG. 6 . - As depicted in
FIG. 7 , in a case where the laser light irradiated region L satisfies the relationship of expression (2), agate line 13G is divided between the intersection CG,n,m−1 and reaching the intersection CG,n,m, specifically, in the gateline detour section 50G corresponding to the intersection CG,n,m, and more specifically, in the straddlingsections 52G of that gateline detour section 50G. At the same time, the sourceline detour section 50S corresponding to the gateline detour section 50G in which thegate line 13G is divided is also divided. Consequently, a gate signal transmitted from the −X direction toward the +X direction by thegate line 13G of the nth row reaches the intersection CG,n,m−1, is then interrupted at the gateline detour section 50G corresponding to the intersection CG,n,m, and does not reach the intersection CG,n,m. - According to the present embodiment, the
isolated region 43 that includes regions where a short circuit may have occurred due to the mechanical dividing of thedisplay panel 2 can be electrically isolated from thedisplay region 41 by radiating laser light along thelaser scanning line 25 c. Therefore, an effect is demonstrated in that short circuits and display defects caused by the short circuits are reliably removed from thedisplay region 41 of thedisplay panel 2 after having been divided. - In addition, as depicted in
FIG. 7 , different from theaforementioned embodiment 1, according to the present embodiment, in a case where the laser light irradiated region L satisfies the relationship of expression (2), the intersection CG,n,m, which may short-circuit, is electrically isolated from the display region 41 (FIG. 3 ). Therefore, the laser light irradiated region L may not satisfy the relationship of expression (1). Consequently, it is possible for thelaser scanning line 25 c to be near or superposing asource line 15S. Furthermore, the position tolerance of the laser light may be greater than ±(p−dS)/2. - In this way, since the laser light irradiated region L may not satisfy the relationship of expression (1), it is possible to more easily realize a display panel in which display defects do not occur due to short circuits caused by dividing.
- Another embodiment of the present disclosure is as follows when described on the basis of
FIGS. 1, 2, and 8 . It should be noted that, for convenience of the description, members having the same functions as the members described in the aforementioned embodiment are denoted by the same reference signs and descriptions thereof are omitted. -
FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device according to the present embodiment. - A liquid
crystal display device 1 is provided with adisplay panel 2, asource driver 3, agate driver 11, adisplay control circuit 4, and apower source 5. Thedisplay panel 2 is provided with anactive matrix substrate 20 a, anopposite substrate 20 b, and a liquid crystal layer (not depicted) held between these substrates. -
FIG. 2 is a top view depicting a schematic configuration of theactive matrix substrate 20 a. - The
active matrix substrate 20 a includes an insulatingsubstrate 2 a such as a glass substrate, andN gate lines 13G, N auxiliary capacitance lines 13CS, andM source lines 15S formed on the insulatingsubstrate 2 a. - In the present embodiment, different from the
aforementioned embodiment 2 but similar to theaforementioned embodiment 1, theactive matrix substrate 20 a includes the auxiliary capacitance lines 13CS. - In the present embodiment, similar to the
aforementioned embodiment 2, gateline detour sections 50G and sourceline detour sections 50S are provided. Also, due to the presence of the auxiliary capacitance lines 13CS, which are wiring other than thegate lines 13G and the source lines 15S, the gateline detour sections 50G and the sourceline detour sections 50S are formed so as to not intersect the auxiliary capacitance lines 13CS. -
FIG. 8 is a top view depicting a schematic configuration of theactive matrix substrate 20 a, for depicting one working example of the gateline detour sections 50G and the sourceline detour sections 50S in the present embodiment. - In
FIG. 8 , thegate line 13G of the nth row from thesource driver 3 and thesource line 15S of the mth column from thegate driver 11 are bent in a similar manner to theaforementioned embodiment 2. Furthermore, inFIG. 8 , the auxiliary capacitance line 13CS of the nth row from thesource driver 3 extends in the +X direction at YCS,n. Consequently, similar to theaforementioned embodiment 2, if the width dG of thegate lines 13G, the width dS of the source lines 15S, and a width dCS of the auxiliary capacitance lines 13CS are not taken into consideration, the gateline detour section 50G corresponding to the intersection CG,n,m and the sourceline detour section 50S corresponding to that gateline detour section 50G satisfy the relationship of the aforementioned expression (3) and the relationship of expression (7) or (8) below. -
Y G,n−1 <Y S,n (1) <Y CS,n <Y G,n (1) <Y G,n (2) <Y S,n (2) <Y G,n −T Y (7) -
Y G,n−1 <Y CS,n <Y S,n (1) <Y G,n (1) <Y G,n (2) <Y S,n (2) <Y G,n −T Y (8) - The expressions (7) and (8) are conditional expressions with which the gate
line detour section 50G and the sourceline detour section 50S are classified so as to not intersect the auxiliary capacitance line 13CS. Expression (7) is established in a case where YS,n (1) where thesource line 15S of the mth column turns in the +X direction is in a position (−Y side) that is nearer to thesource driver 3 than the auxiliary capacitance line 13CS of the nth row. Furthermore, expression (8) is established in a case where YS,n (1) where thesource line 15S of the mth column turns in the +X direction is in a position (+Y side) that is further from thesource driver 3 than the auxiliary capacitance line 13CS of the nth row. - In addition, if the width do of the
gate lines 13G, the width dS of the source lines 15S, and the width dCS of the auxiliary capacitance lines 13CS are taken into consideration, it is derived based on the relationship of expression (3) that the gateline detour sections 50G and the sourceline detour sections 50S satisfy the relationships of the aforementioned expressions (5-1) to (5-6). Similarly, in a case where the relationship of expression (7) is satisfied, it is derived based on the relationship of expression (7) that the relationships of expressions (9-1) and (9-2) below and the aforementioned expressions (6-3) to (6-5) are satisfied. Furthermore, in a case where the relationship of expression (8) is satisfied, it is derived based on the relationship of expression (8) that the relationships of expression (10) below and the aforementioned expressions (6-2) to (6-5) are satisfied. -
Y G,n−1 +d G/2+d S/2<Y S,n (1) <Y CS,n −d S/2−d CS/2 (9-1) -
Y CS,n +d CS/2+d G/2<Y G,n (1) (9-2) -
Y CS,n +d CS/2+d S/2<Y S,n (1) (10) - Also in the working example depicted in
FIG. 8 , similar to the working examples depicted inFIGS. 6 and 7 , in a case where the laser light irradiated region L satisfies the relationship of expression (2), thegate line 13G, specifically, is divided in the gateline detour section 50G corresponding to the intersection CG,n,m. - According to the present embodiment, the
isolated region 43 that includes regions where a short circuit may have occurred due to the mechanical dividing of thedisplay panel 2 can be electrically isolated from thedisplay region 41 by radiating laser light along thelaser scanning line 25 c. Therefore, an effect is demonstrated in that short circuits and display defects caused by the short circuits are reliably removed from thedisplay region 41 of thedisplay panel 2 after having been divided. - In addition, similar to the
aforementioned embodiment 2, according to the present embodiment, in a case where the laser light irradiated region L satisfies the relationship of expression (2), the intersection CG,n,m, which may short-circuit, is electrically isolated from the display region 41 (FIG. 3 ). Therefore, the laser light irradiated region L may not satisfy the relationship of expression (1). - Another embodiment of the present disclosure is as follows when described on the basis of
FIGS. 1, 2, and 9 . It should be noted that, for convenience of the description, members having the same functions as the members described in the aforementioned embodiment are denoted by the same reference signs and descriptions thereof are omitted. -
FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device according to the present embodiment. - A liquid
crystal display device 1 is provided with adisplay panel 2, asource driver 3, agate driver 11, adisplay control circuit 4, and apower source 5. Thedisplay panel 2 is provided with anactive matrix substrate 20 a, anopposite substrate 20 b, and a liquid crystal layer (not depicted) held between these substrates. -
FIG. 2 is a top view depicting a schematic configuration of theactive matrix substrate 20 a. - The
active matrix substrate 20 a includes an insulatingsubstrate 2 a such as a glass substrate, andN gate lines 13G, N auxiliary capacitance lines 13CS, andM source lines 15S formed on the insulatingsubstrate 2 a. - In the present embodiment, similar to the
aforementioned embodiments active matrix substrate 20 a includes the auxiliary capacitance lines 13CS. - In the present embodiment, similar to the
aforementioned embodiments line detour sections 50G and sourceline detour sections 50S (source line first detour sections) corresponding to the gateline detour section 50G are provided. In addition, in the present embodiment, auxiliary capacitance line detour sections 50CS are provided in each auxiliary capacitance line 13CS, and sourceline detour sections 50S (source line second detour sections) corresponding to the auxiliary capacitance line detour sections 50CS are provided in eachsource line 15S. - The auxiliary capacitance line detour sections 50CS are provided corresponding to intersections between the auxiliary capacitance lines 13CS and the source lines 15S, similar to the gate
line detour sections 50G being provided corresponding to intersections between thegate lines 13G and the source lines 15S. The auxiliary capacitance line detour sections 50CS are portions formed in such a way that the auxiliary capacitance lines 13CS detour so that (i) auxiliary capacitance lines 13CS extending from the −X direction end of theactive matrix substrate 20 a prior to passing through corresponding intersections are divided at the irradiated region L in a case where the laser light irradiated region L satisfies the relationship of expression (2), and so that (ii) intersections where the auxiliary capacitance lines 13CS intersect (themselves or other wiring) are not newly made (in other words, are not increased). - The source
line detour sections 50S are provided corresponding to the gateline detour sections 50G, and are also provided corresponding to the auxiliary capacitance line detour sections 50CS. The sourceline detour sections 50S corresponding to the auxiliary capacitance line detour sections 50CS are portions formed in such a way that the source lines 15S avoid the corresponding auxiliary capacitance line detour sections 50CS so that intersections where the source lines 15S intersect (themselves or other wiring) are not newly made. - The gate
line detour sections 50G do not cause an increase in intersections, as previously mentioned. Therefore, thegate lines 13G intersect the source lines 15S only at intersections (first intersections) where the gateline detour sections 50G are provided in a corresponding manner. Furthermore, thegate lines 13G do not intersect themselves and do not intersect adjacent auxiliary capacitance lines 13CS. - The auxiliary capacitance line detour sections 50CS do not cause an increase in intersections, as previously mentioned. Therefore, the auxiliary capacitance lines 13CS intersect the source lines 15S only at intersections (second intersections) where the auxiliary capacitance line detour sections 50CS are provided in a corresponding manner. Furthermore, the auxiliary capacitance lines 13CS do not intersect themselves and do not intersect
adjacent gate lines 13G. As a result, the auxiliary capacitance lines 13CS start detouring with the auxiliary capacitance lines 13CS bending from a start position (second start position) between a corresponding intersection and another intersection adjacent at the −X direction side to the corresponding intersection (in the −X direction relative to the corresponding intersection), toward the −Y direction or the +Y direction. Similarly, when the auxiliary capacitance lines 13CS stop detouring, the auxiliary capacitance lines 13CS return from the −Y direction or the +Y direction to an end position (second end position) between the corresponding intersection and the start position (in the −X direction relative to the corresponding intersection, and in the +X direction relative to the start position). The auxiliary capacitance lines 13CS having finished detouring then bend toward the +X direction and pass through the corresponding intersection. - The auxiliary capacitance line detour sections 50CS are divided at the irradiated region L in a case where the laser light irradiated region L satisfies the relationship of expression (2). Therefore, the auxiliary capacitance lines 13CS of the auxiliary capacitance line detour sections 50CS straddle both a straight line (second straight line) that passes through the +X direction end of the corresponding intersection and extends in the Y axis direction (+Y direction and −Y direction) and a straight line that passes through the −X direction end and extends in the Y axis direction. However, as previously mentioned, the auxiliary capacitance line detour sections 50CS start from a start position that is in the −X direction relative to the corresponding intersection, and finish at an end position that is in the −X direction relative to the corresponding intersection, and therefore the auxiliary capacitance lines 13CS of the auxiliary capacitance line detour sections 50CS also straddle a straight line that passes through the −X direction end when straddling a straight line that passes through the +X direction end.
- Due to the auxiliary capacitance line detour sections 50CS, with reference to
FIGS. 4 and 9 in a case where the laser light irradiated region L satisfies the relationship of expression (2), auxiliary capacitance signals transmitted by the auxiliary capacitance lines 13CS reach the immediately preceding intersection CCS,n,m−1, are then interrupted at the auxiliary capacitance line detour sections 50CS, and do not reach the intersection CCS,n,m, which may have short-circuited. - Consequently, with reference to
FIG. 9 , the auxiliary capacitance line detour sections 50CS include: (i) a start section 51CS (second start section) in which the auxiliary capacitance line 13CS is drawn out in the +Y direction or the −Y direction from a start position that is in the −X direction relative to the corresponding intersection; (ii) straddling sections 52CS (second straddling sections) in which the auxiliary capacitance line 13CS straddles a straight line that passes through the +X direction end of the corresponding intersection and extends in the Y axis direction; and (iii) an end section 53CS (second end section) in which the auxiliary capacitance line 13CS returns from an end position that is in the −X direction relative to the corresponding intersection and in the +X direction relative to the start position. The auxiliary capacitance line 13CS electrically connects: (i) between the end position of the auxiliary capacitance line detour section 50CS and the corresponding intersection by means of a portion of the auxiliary capacitance line 13CS that is not the auxiliary capacitance line detour section 50CS; (ii) between the start position of the auxiliary capacitance line detour section 50CS and another intersection adjacent at the −X direction side to the corresponding intersection by means of a portion of the auxiliary capacitance line 13CS that is not the auxiliary capacitance line detour section 50CS; and (iii) between the start position and end position of the same auxiliary capacitance line detour section 50CS by means of only a portion of the auxiliary capacitance line 13CS that is the auxiliary capacitance line detour section 50CS. It is preferable for the auxiliary capacitance lines 13CS of the auxiliary capacitance line detour sections 50CS and the source lines 15S of the sourceline detour sections 50S to be formed so as to pass through positions that are different from the switching elements T in order to avoid the switching elements T. -
FIG. 9 is a top view depicting a schematic configuration of theactive matrix substrate 20 a, for depicting one working example of the gateline detour sections 50G and the sourceline detour sections 50S in the present embodiment. - In
FIG. 9 , thegate line 13G of the nth row from thesource driver 3 is bent in a similar manner to theaforementioned embodiment 2. - In
FIG. 9 , thesource line 15S of the mth column from thegate driver 11 is bent in a similar manner to theaforementioned embodiment 2, and, in addition, - turns in the +X direction at YS,n (3),
- turns in the +Y direction at XS,m (1),
- turns in the −X direction at YS,n (4),
- turns in the +Y direction at XS,m, and
- passes through the intersection CCS,n,m.
- In
FIG. 9 , the auxiliary capacitance line 13CS of the nth row from thesource driver 3 - passes through the intersection CCS,n,m−1 in the +X direction,
- turns in the −Y direction at XCS,m (1),
- turns in the +X direction at YCS,n (1),
- turns in the +Y direction at XCS,m (2),
- turns in the −X direction at YCS,n (2),
- turns in the +Y direction at XCS,m (3),
- turns in the +X direction at YCS,n, and
- passes through the intersection CCS,n,m, in the +X direction.
- It should be noted that
- the central coordinates of the intersection CCS,n,m are (XCS,m, YCS,n),
- the central coordinates of the intersection CCS,n,m−1 are (XCS,m−1, YCS,n),
- X coordinates or Y coordinates of center lines of the auxiliary capacitance line 13CS are respectively YCS,n, XCS,m (1), YCS,n (1), XCS,n (2), YCS,n (2), and XCS,m (3), and
- X coordinates or Y coordinates of center lines of the
source line 15S are respectively YS,n (3), XS,m (2), and YS,n (4). - Then, on the basis of (i) the positional relationship of the start section 51G, the straddling sections 52G, and the end section 53G provided in the gate line detour sections 50G to each other, with respect to the intersection CG,n,m, the intersection CCS,n,m, and the intersection CG,n,m−1, (ii) the positional relationship of the start section 51CS, the straddling sections 52CS, and the end section 53CS provided in the auxiliary capacitance line detour sections 50CS to each other, with respect to the intersection CCS,n,m, the intersection CG,n−1,m, and the intersection CCS,n,m−1, and it being preferable for (iii) the source line detour sections 50S to be provided so as to avoid the gate line detour sections 50G and the auxiliary capacitance line detour sections 50CS, and (iv) the gate lines 13G of the gate line detour sections 50G, the source lines 15S of the source line detour sections 50S, and the auxiliary capacitance lines 13CS of the auxiliary capacitance line detour sections 50CS to not superpose the switching elements T, if the width dc of the gate lines 13G, the width dS of the source lines 15S, and the width dCS of the auxiliary capacitance lines 13CS are not taken into consideration, the gate line detour section 50G corresponding to the intersection CG,n,m, the auxiliary capacitance line detour section 50CS corresponding to the intersection CCS,n,m, and the source line detour section 50S corresponding to that gate line detour section 50G and auxiliary capacitance line detour section 50CS satisfy the relationships of expression (3) and expressions (11) and (12) below.
-
X S,m−1 +T X <X CS,m (1) <X CS,m (3) <X S,m <X CS,m (2) <X S,m (1) <X CS,m+1 (1) (11) -
Y G,n−1 <Y S,n (3) <Y CS,n (1) <Y CS,n (2) <Y S,n (4) <Y CS,n <Y S,n (1) <Y G,n (1) <Y G,n (2) <Y S,n (2) <Y G,n −T Y (12) - In addition, if the width do of the
gate line 13G, the width dS of thesource line 15S, and the width dCS of the auxiliary capacitance line 13CS are taken into consideration, a relationship satisfied by the gateline detour section 50G, the auxiliary capacitance line detour section 50CS, and the sourceline detour section 50S is derived with reference toFIG. 9 from the aforementioned expressions (3), (11), and (12). This derivation is similar to the derivation of expressions (5-1) to (5-6) from expression (3) and the derivation of expressions (6-1) to (6-5) from expression (4) in theaforementioned embodiment 2, is obvious to a person skilled in the art, and is therefore omitted. - According to the present embodiment, the
isolated region 43 that includes regions where a short circuit may have occurred due to the mechanical dividing of thedisplay panel 2 can be electrically isolated from thedisplay region 41 by radiating laser light along thelaser scanning line 25 c. Therefore, an effect is demonstrated in that short circuits and display defects caused by the short circuits are reliably removed from thedisplay region 41 of thedisplay panel 2 after having been divided. - In addition, similar to the
aforementioned embodiment 2, according to the present embodiment, in a case where the laser light irradiated region L satisfies the relationship of expression (2), the intersection CG,n,m, which may short-circuit, is electrically isolated from the display region 41 (FIG. 3 ). Therefore, the laser light irradiated region L may not satisfy the relationship of expression (1). In addition, according to the present embodiment, the intersection CCS,n,m between an auxiliary capacitance line 13CS and asource line 15S is also likewise electrically isolated from thedisplay region 41. - Another embodiment of the present disclosure is as follows when described on the basis of
FIGS. 1, 2, and 10 . It should be noted that, for convenience of the description, members having the same functions as the members described in the aforementioned embodiment are denoted by the same reference signs and descriptions thereof are omitted. -
FIG. 1 is a top view depicting a schematic configuration of a liquid crystal display device according to the present embodiment. - A liquid
crystal display device 1 is provided with adisplay panel 2, asource driver 3, agate driver 11, adisplay control circuit 4, and apower source 5. Thedisplay panel 2 is provided with anactive matrix substrate 20 a, anopposite substrate 20 b, and a liquid crystal layer (not depicted) held between these substrates. -
FIG. 2 is a top view depicting a schematic configuration of theactive matrix substrate 20 a. - The
active matrix substrate 20 a includes an insulatingsubstrate 2 a such as a glass substrate, andN gate lines 13G, N auxiliary capacitance lines 13CS, andM source lines 15S formed on the insulatingsubstrate 2 a. - In the present embodiment, similar to the
aforementioned embodiments active matrix substrate 20 a includes the auxiliary capacitance lines 13CS. -
FIG. 10 is a top view depicting a schematic arrangement of the gateline detour sections 50G and the sourceline detour sections 50S in theactive matrix substrate 20 a of the present embodiment. - In the
active matrix substrate 20 a,red pixel electrodes 17R for displaying image information for red are provided with respect to thesource line 15S of the 3k−2th column. Furthermore, blue pixel electrodes 17B for displaying image information for blue are provided with respect to thesource line 15S of the 3k−1th column. Furthermore,green pixel electrodes 17G for displaying image information for green are provided with respect to thesource line 15S of the 3kth column (M=3K, and k is a natural number that is greater than or equal to 1 and less than or equal to K−1). - In the
aforementioned embodiment 3, the gateline detour sections 50G and the sourceline detour sections 50S were provided corresponding to all intersections between thegate lines 13G and thesource lines 15S so that the boundary section at the −X side of thelaser scanning line 25 c may overlap with any of the source lines 15S in the first to Mth columns. However, in the present embodiment, the gateline detour sections 50G and the sourceline detour sections 50S are provided only for intersections corresponding to thegreen pixel electrodes 17G from among the intersections between thegate lines 13G and the source lines 15S. - In this way, the gate
line detour sections 50G and the sourceline detour sections 50S are provided once every three pixels in the present embodiment, in contrast to being provided once every single pixel in theaforementioned embodiment 3. Therefore, the ratio of the area taken up by the gateline detour sections 50G and the sourceline detour sections 50S with respect to thedisplay region 41 decreases to approximately ⅓ in the present embodiment in comparison toembodiment 3. Consequently, it is possible to suppress a decrease in the aperture ratio caused by the gateline detour sections 50G and the sourceline detour sections 50S. Furthermore, in order to suppress this decrease in the aperture ratio, it is preferable for the gateline detour sections 50G and the sourceline detour sections 50S to have a small area, and to have a shape that is bent in a simple manner as in the examples depicted inFIGS. 6 to 10 , for example. It should be noted that the gateline detour sections 50G and the sourceline detour sections 50S may be provided once every two pixels, twice every three pixels, or once every four or more pixels. - The
active matrix substrate 20 a in the present embodiment includes: (i)K source lines 15S (first source lines) that transmit source signals for a green component (first source signals) from the −Y direction toward the +Y direction; (ii)N gate lines 13G that intersect the source lines 15S that transmit the source signals for the green component, only at intersections (first intersections) where the gateline detour sections 50G are provided in a corresponding manner, and transmit gate signals from the −X direction toward the +X direction; (iii) N auxiliary capacitance lines 13CS that intersect at intersections (second intersections) with the source lines 15S that transmit the source signals for the green component, and transmit auxiliary capacitance signals from the −X direction toward the +X direction; and (iv)2K source lines 15S (second source lines) that transmit source signals for a red component and a blue component (second source signals) from the −Y direction toward the +Y direction, intersect at intersections (third intersections) with thegate lines 13G, and intersect at intersections (fourth intersections) with the auxiliary capacitance lines 13CS. In addition, source signals (first source signals) transmitted bysource lines 15S (first source lines) that pass through intersections (first intersections) withgate lines 13G on which the gateline detour sections 50G are provided indicate image information for green. Source signals (first source signals) transmitted bysource lines 15S (second source lines) that pass through intersections (third intersections) withgate lines 13G on which the gateline detour sections 50G are not provided indicate image information for green and for red, a different color from green. - With reference to
FIG. 10 , in a case where the laser light irradiated region L satisfies the relationship of expression (2) with regard tosource lines 15S that transmit source signals for a green component, intersections that may short-circuit are electrically isolated from the display region 41 (FIG. 3 ). However, in a case where the laser light irradiated region L satisfies the relationship of expression (2) with regard tosource lines 15S that transmit source signals for a red component and a blue component, intersections that may short-circuit are not electrically isolated from thedisplay region 41. Consequently, it is necessary for the laser light irradiated region L to satisfy the relationship of expression (13) or (14) below derived on the basis of expression (1). -
X S,3k−2 +d S/2<X L −r/2<X S,3k −d S/2 (13) -
X S,3k +d S/2<X L −r/2<X S,3k+1 −d S/2 (14) - Derived from expression (13), in the present embodiment, the pitch of a sub-pixel is, from p, 2p=XS,3k−XS,3k−2, and therefore the laser light position tolerance is ±(2p−dS)/2. In contrast, in
embodiment 1 in which the gateline detour sections 50G are not provided, the laser light position tolerance was ±(p−dS)/2. Consequently, by providing the gateline detour sections 50G for intersections through which somesource lines 15S from among the plurality ofsource lines 15S pass, the laser light position tolerance can be increased. - According to the present embodiment, the
isolated region 43 that includes regions where a short circuit may have occurred due to the mechanical dividing of thedisplay panel 2 can be electrically isolated from thedisplay region 41 by radiating laser light along thelaser scanning line 25 c. Therefore, an effect is demonstrated in that short circuits and display defects caused by the short circuits are reliably removed from thedisplay region 41 of thedisplay panel 2 after having been divided. - In addition, by providing the gate
line detour sections 50G for intersections through which somesource lines 15S from among the plurality ofsource lines 15S pass, the laser light position tolerance can be increased. Furthermore, it is possible to suppress a decrease in the aperture ratio of thedisplay panel 2 caused by the gateline detour sections 50G and the sourceline detour sections 50S. - Another embodiment of the present disclosure is as follows when described on the basis of
FIGS. 11, 12, and 13 . It should be noted that, for convenience of the description, members having the same functions as the members described in the aforementioned embodiment are denoted by the same reference signs and descriptions thereof are omitted. -
FIGS. 11(a) and (b) are top views depicting schematic configurations of different working examples of a liquidcrystal display device 1 according to the present embodiment. - The liquid
crystal display device 1 is provided with adisplay panel 2, asource driver 3, agate driver 11, adisplay control circuit 4, and apower source 5. Thedisplay panel 2 is provided with anactive matrix substrate 20 a, anopposite substrate 20 b, and a liquid crystal layer (not depicted) held between these substrates. - In the present embodiment, similar to the
aforementioned embodiment 3, theactive matrix substrate 20 a includes an insulatingsubstrate 2 a,N gate lines 13G, N auxiliary capacitance lines 13CS, and M source lines 15S, with gateline detour sections 50G being provided in thegate lines 13G, and sourceline detour sections 50S being provided in the source lines 15S. - In the present embodiment, different from the
aforementioned embodiments 1 to 5, agate driver 11 or part of thegate driver 11 is formed inside pixel regions, which are regions in which a pixel electrode is arranged corresponding to agate line 13G and asource line 15S. - This kind of technique in which at least part of the
gate driver 11 is formed within pixel regions defined bysource lines 15S andgate lines 13G is described in PTL 3 (International Publication No. WO2014/069529), for example. According to the technique described inPTL 3, the gate driver 11 (i) is connected to at least some wiring including agate line 13G, (ii) controls the potential of the wiring including thegate line 13G in accordance with a control signal supplied from outside a display region that includes the pixel regions defined by thegate lines 13G and the source lines 15S, and (iii) includes a plurality of switching elements (second switching elements) at least some of which are formed in the pixel regions.PTL 3 is cited herein for reference. - Due to at least part of the
gate driver 11 being provided inside the pixel regions, thedividing lines 25 along which thedisplay panel 2 is divided can be altered to lines having various shapes. Consequently, in addition to altering the size of thedisplay panel 2, it becomes possible to alter the shape of thedisplay panel 2 to various shapes such as those inFIGS. 11(a) and (b) . It should be noted that the scope of the present disclosure is not restricted hereto, and the technique in which at least part of thegate driver 11 is formed inside the pixel regions may be combined with any of theaforementioned embodiments - As described with reference to
FIG. 6 in theaforementioned embodiments line detour sections 50G and the sourceline detour sections 50S are defined on the basis of the transmission directions of gate signals and source signals and the positions of intersections between thegate line 13G and thesource line 15S. Consequently, as inFIG. 11 , in a case where thegate driver 11 is provided inside thedisplay region 41, and in a case where thegate driver 11 is provided in plurality, the X axis direction is set so that gate signals are transmitted from the −X direction toward the +X direction. Specifically, the direction going away from eachgate driver 11 is taken as the +X direction and the direction coming toward eachgate driver 11 is taken as the −X direction. -
FIGS. 12(a) and (b) are top views depicting the relationship between the shape of thedividing lines 25 and the arrangement of thegate drivers 11, in the liquidcrystal display device 1 device according to the present embodiment. - When reference is made to
FIG. 12(a) , thegate drivers 11 are provided with one at the left and one at the right, on theactive matrix substrate 20 a provided in thedisplay panel 2. In thedisplay panel 2 divided according to thedividing lines 25 depicted inFIG. 12(a) ,gate lines 13G that pass within aregion 44 are divided according to thedividing lines 25 and are not connected to thegate drivers 11. Therefore, within theregion 44, gate signals are not transmitted and therefore images are not displayed. - However, when reference is made to
FIG. 12(b) , onegate driver 11 is provided in the center of theactive matrix substrate 20 a provided in thedisplay panel 2. In thedisplay panel 2 divided according to thedividing lines 25 depicted inFIG. 12(b) ,gate lines 13G that pass within theregion 44 are connected to thegate driver 11 at the upper side of thedisplay panel 2. Therefore, within theregion 44, gate signals are transmitted and images are displayed. - Consequently, when reference is made to
FIGS. 12(a) and (b) in comparison, thegate drivers 11 are arranged so as to conform to the shape of thedividing lines 25, or the shape of thedividing lines 25 is set so as to conform to the arrangement of thegate drivers 11. Specifically, thegate drivers 11 are arranged and/or the shape of thedividing lines 25 is set so that both gate signals and source signals are transmitted to all pixels included within thedisplay region 41 after having been divided, so that eachgate line 13G included within the divideddisplay region 41 is connected to thegate drivers 11, and so that eachsource line 15S included within the divideddisplay region 41 is connected to thesource driver 3. - At such time, the longest length in the Y axis direction of the
gate drivers 11 included in thedisplay region 41 of thepanel 2 after having been divided and the longest length in the Y axis direction of thedisplay region 41 match each other. This is because (i) thegate drivers 11 are divided according to thedividing lines 25 together with theactive matrix substrate 20 a and therefore thegate drivers 11 are never longer than thedisplay region 41, and (ii) in a case where thegate drivers 11 are shorter than the longest length of thedisplay region 41, a region where display is not possible is formed, such as theregion 44 ofFIG. 12(a) . -
FIG. 13 is a top view depicting a schematic configuration of thedividing lines 25 according to the present embodiment. - In the case where the
dividing lines 25 were straight lines as inFIG. 3 , and also in the case of not being straight lines as inFIG. 13 , it is preferable for the gap between the active matrixsubstrate dividing line 25 a and the oppositesubstrate dividing line 25 b to be 0.5 mm to 2 mm. Furthermore, as inFIG. 13 , in a case where the active matrixsubstrate dividing line 25 a and the oppositesubstrate dividing line 25 b are curves, thelaser scanning line 25 c is set so as to have a stepped form along a grid formed by thegate lines 13G and the source lines 15S, at an outer side along the active matrixsubstrate dividing line 25 a. - An active matrix substrate (20 a) according to
aspect 1 of the present disclosure is a configuration including: a plurality of source lines (15S) including a plurality of first source lines that transmit a first source signal from a −Y direction toward a +Y direction; and a plurality of gate lines (13G) that intersect the plurality of first source lines only at a plurality of first intersections, and transmit a gate signal from a −X direction toward a +X direction, in the gate lines, gate line detour sections (50G) being provided corresponding to each of the first intersections, and each of the gate line detour sections having: a first start section (51G) in which the corresponding gate line is bent toward the +Y direction or the −Y direction from a first start position (XG,m (1) with reference toFIGS. 6 and 8 ) that is in the −X direction relative to the corresponding first intersection (CG,n,m with reference toFIGS. 6 and 8 ); and first straddling sections (52G) in which the corresponding gate line straddles a first straight line that passes through a +X direction end (XS,m+dS/2 with reference toFIGS. 6 and 8 ) of the corresponding first intersection and extends in the +Y direction and the −Y direction. - According to the aforementioned configuration, in a case where a boundary section at the −X direction side between an irradiated region, where laser light is radiated onto the active matrix substrate for the gate lines to be divided, and a non-irradiated region superposes a first intersection, the boundary section also superposes the first straddling sections of the gate line detour section corresponding to the first intersection. Therefore, the gate lines are invariably divided at the first straddling sections and/or between the first straddling sections of the corresponding gate line detour section, and therefore, in a case where a boundary section superposes a first intersection, the corresponding gate line detour section is divided. Consequently, a first intersection that may have short-circuited due to superposing a boundary section between an irradiated region and a non-irradiated region is isolated from intersections (including first intersections) between gate lines and source lines that are in the −X direction relative to the first intersection.
- Consequently, in a display panel provided with an active matrix substrate having the aforementioned configuration, with laser scanning that is carried out once, (i) regions where a short circuit may have occurred due to mechanical dividing and (ii) first intersections where a short circuit may have occurred due to the radiation of a laser in the laser scanning can be isolated from a display region. Therefore, it is permissible for the first intersections to short-circuit due to the radiation of a laser. Furthermore, as a result, laser scanning can be carried out so as to pass through positions near the first intersections, and the position tolerance of the laser scanning may be increased.
- According to the aforementioned configuration, gate lines intersect first source lines only at first intersections, and the gate line detour sections start from a first start position that is in the −X direction relative to a first intersection, and straddle a first straight line that passes through the +X direction end of the first intersection. Consequently, the gate line detour sections straddle the first straight line from the −X direction toward the +X direction, and thereafter straddle the first straight line so as to return from the +X direction toward the −X direction.
- An active matrix substrate (20 a) according to
aspect 2 of the present disclosure may be a configuration in which, in theaforementioned aspect 1, source line first detour sections (50S) in which the first source lines detour around the gate line detour sections (50G) are provided in the first source lines (15S). - According to the aforementioned configuration, the first source lines detour in such a way as to not superpose the gate line detour sections. Therefore, it is possible for the gate lines to intersect the first source lines only at the first intersections.
- An active matrix substrate (20 a) according to
aspect 3 of the present disclosure may be a configuration in which, in theaforementioned aspect 2, the gate lines (13G) of the gate line detour sections (50G) and the first source lines (15S) of the source line first detour sections (50S) pass through positions that are different from a plurality of first switching elements (T) that correspond to the first intersections. - According to the aforementioned configuration, the gate lines of the gate line detour sections and the first source lines of the source line first detour sections pass through positions that are different from the first switching elements. Therefore, it becomes possible for the gate line detour sections and the source line first detour sections to not superpose the first switching elements.
- An active matrix substrate (20 a) according to
aspect 4 of the present disclosure may be a configuration in which, in any one aspect of theaforementioned aspects 1 to 3, each of the gate line detour sections (50G) has a first end section (53G) in which the corresponding gate line (13G) returns to a first end position (XG,m (3) with reference toFIGS. 6 and 8 ) that is in the −X direction relative to the corresponding first intersection (CG,n,m with reference toFIGS. 6 and 8 ) and in the +X direction relative to the first start position (XG,m (1) with reference toFIGS. 6 and 8 ), and each of the gate lines connects between the first intersections and the corresponding first end positions, and connects between the corresponding first end positions and the corresponding first start positions by means of only the gate line detour sections. - According to the aforementioned configuration, a first end position and a first start position corresponding to the same first intersection are connected by means of only the corresponding gate line detour section. Consequently, when a gate line detour section is divided, the corresponding first intersection is isolated from other first intersections that are in the −X direction.
- An active matrix substrate (20 a) according to
aspect 5 of the present disclosure may be a configuration that, in any one aspect of theaforementioned aspects 1 to 4, further includes a plurality of auxiliary capacitance lines (13CS) that intersect the plurality of first source lines (15S) only at a plurality of second intersections, and transmit an auxiliary capacitance signal from the −X direction toward the +X direction. - An active matrix substrate (20 a) according to aspect 6 of the present disclosure may be a configuration in which, in the
aforementioned aspect 5, in the auxiliary capacitance lines (13CS), auxiliary capacitance line detour sections (50CS) are provided corresponding to each of the second intersections, and each of the auxiliary capacitance line detour sections has: a second start section in which the corresponding auxiliary capacitance line is bent toward the +Y direction or the −Y direction from a second start position (XCS,m (1) with reference toFIG. 9 ) that is in the −X direction relative to the corresponding second intersection (CCS,n,m with reference toFIG. 9 ); and second straddling sections (52CS) in which the corresponding auxiliary capacitance line straddles a second straight line that passes through a +X direction end (XS,m+dS/2 with reference toFIG. 9 ) of the corresponding second intersection and extends in the +Y direction and the −Y direction. - According to the aforementioned configuration, in a case where a boundary section at the −X direction side between an irradiated region, where laser light is radiated onto the active matrix substrate, and a non-irradiated region superposes a second intersection, the boundary section also superposes the second straddling sections of the auxiliary capacitance line detour section corresponding to the second intersection. Therefore, the auxiliary capacitance lines are invariably divided at the second straddling sections and/or between the second straddling sections of the corresponding auxiliary capacitance line detour section, and therefore, in a case where a boundary section superposes a second intersection, the corresponding auxiliary capacitance line detour section is divided. Consequently, a second intersection that may have short-circuited due to superposing a boundary section between an irradiated region and a non-irradiated region is isolated from intersections (including second intersections) between auxiliary capacitance lines and source lines that are in the −X direction relative to the second intersection.
- An active matrix substrate (20 a) according to aspect 7 of the present disclosure may be a configuration in which, in the aforementioned aspect 6, source line second detour sections (50G) in which the first source lines detour around the auxiliary capacitance line detour sections (50CS) are provided in the first source lines (15S).
- According to the aforementioned configuration, the first source lines detour in such a way as to not superpose the auxiliary capacitance line detour sections. Therefore, it is possible for the auxiliary capacitance lines to intersect the first source lines only at the second intersections.
- An active matrix substrate (20 a) according to
aspect 8 of the present disclosure may be a configuration in which, in the aforementioned aspect 7, the auxiliary capacitance lines (13CS) of the auxiliary capacitance line detour sections (50CS) and the first source lines (15S) of the source line second detour sections (50S) pass through positions that are different from the plurality of first switching elements (T) that correspond to the first intersections. - According to the aforementioned configuration, the auxiliary capacitance lines of the auxiliary capacitance line detour sections and the first source lines of the source line second detour sections pass through positions that are different from the first switching elements. Therefore, it becomes possible for the auxiliary capacitance line detour sections and the source line second detour sections to not superpose the first switching elements.
- An active matrix substrate (20 a) according to aspect 9 of the present disclosure may be a configuration in which, in any one aspect of the aforementioned aspects 6 to 8, each of the auxiliary capacitance line detour sections (50CS) has a second end section (53CS) in which the corresponding auxiliary capacitance line returns to a second end position (XCS,m (3) with reference to
FIG. 9 ) that is in the −X direction relative to the corresponding second intersection (CCS,n,m with reference toFIG. 9 ) and in the +X direction relative to the second start position (XCS,m (1) with reference toFIG. 9 ), and each of the auxiliary capacitance lines connects between the second intersections and the corresponding second end positions, and connects between the corresponding second end positions and the corresponding second start positions by means of only the auxiliary capacitance line detour sections. - According to the aforementioned configuration, a second end position and a second start position corresponding to the same second intersection are connected by means of only the corresponding auxiliary capacitance line detour section. Consequently, when an auxiliary capacitance line detour section is divided, the corresponding second intersection is isolated from other second intersections that are in the −X direction.
- An active matrix substrate according to aspect 10 of the present disclosure may be a configuration in which, in any one aspect of the
aforementioned aspects 1 to 9, the plurality of source lines further include a plurality of second source lines that transmit a second source signal from the −Y direction toward the +Y direction, and intersect the plurality of gate lines only at third intersections. - According to the aforementioned configuration, gate line detour sections corresponding to the third intersections may not be provided in the gate lines. Thus, it is possible to suppress the area taken up by the gate line detour sections with respect to pixel regions defined by the plurality of source lines and the plurality of gate lines, and it is possible to suppress a decrease in the aperture ratio caused by the gate line detour sections.
- An active matrix substrate according to
aspect 11 of the present disclosure may be a configuration in which, in any one aspect of theaforementioned aspects 5 to 9, the plurality of source lines further include a plurality of second source lines that transmit a second source signal from the −Y direction toward the +Y direction, intersect the plurality of gate lines only at third intersections, and intersect the plurality of auxiliary capacitance lines only at fourth intersections. - According to the aforementioned configuration, gate line detour sections corresponding to the third intersections may not be provided in the gate lines. Thus, it is possible to suppress the area taken up by the gate line detour sections with respect to pixel regions defined by the plurality of source lines and the plurality of gate lines, and it is possible to suppress a decrease in the aperture ratio caused by the gate line detour sections.
- An active matrix substrate (20 a) according to
aspect 12 of the present disclosure may be a configuration in which, in theaforementioned aspect 10 or 11, the second source signal (image information for red and image information for blue) indicates image information for a color that is different from the first source signal (image information for green). - An active matrix substrate (20 a) according to aspect 13 of the present disclosure may be a configuration that, in any one aspect of the
aforementioned aspects 1 to 12, further includes a gate driving circuit (gate driver 11) that supplies the gate signal to at least some of the plurality of gate lines (13G), and has a plurality of second switching elements, at least some of the plurality of second switching elements being formed in pixel regions defined by the plurality of source lines and the plurality of gate lines. - According to the aforementioned configuration, in addition to altering the size of the active matrix substrate, it becomes possible to also alter the shape.
- An active matrix substrate (20 a) according to aspect 14 of the present disclosure may be a configuration in which, in any one aspect of the
aforementioned aspects 1 to 13, the +X and −X directions and the +Y and −Y directions are mutually orthogonal. - A display panel (2) according to
aspect 15 of the present disclosure is a configuration provided with: the active matrix substrate (20 a) according to any one of theaforementioned aspects 1 to 14; an opposite substrate (20 b); and a liquid crystal layer held between the active matrix substrate and the opposite substrate. - According to the aforementioned configuration, it is possible to realize a display panel provided with an active matrix substrate according to an embodiment of the present disclosure.
- A display device according to aspect 16 of the present disclosure is a configuration provided with the display panel according to the
aforementioned aspect 15. - According to the aforementioned configuration, it is possible to realize a display panel provided with a display panel according to an embodiment of the present disclosure.
- The present invention is not restricted to the aforementioned embodiments, various alterations are possible within the scope indicated in the claims, and embodiments obtained by appropriately combining the technical means disclosed in each of the different embodiments are also included within the technical scope of the present invention. In addition, novel technical features can be formed by combining the technical means disclosed in each of the embodiments.
-
-
- 1 Liquid crystal display device (display device)
- 2 Display panel
- 11 Gate driver (gate driving circuit)
- 13CS Auxiliary capacitance line
- 13G Gate line
- 15S Source line (first source line, second source line)
- 20 a Active matrix substrate
- 20 b Opposite substrate
- 30 Liquid crystal layer
- 50CS Auxiliary capacitance line detour section
- 50G Gate line detour section
- 50S Source line detour section (source line first detour section, source line second detour section)
- 51CS Start section (second start section)
- 51G Start section (first start section)
- 52CS Straddling section (second straddling section)
- 52G Straddling section (first straddling section)
- 53CS End section (second end section)
- 53G End section (first end section)
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PCT/JP2017/034284 WO2018062035A1 (en) | 2016-09-29 | 2017-09-22 | Active matrix substrate, display panel, and display device provided with same |
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- 2017-09-22 US US16/334,772 patent/US10578941B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20200005696A1 (en) * | 2018-06-28 | 2020-01-02 | Au Optronics Corporation | Display device |
US10692414B2 (en) * | 2018-06-28 | 2020-06-23 | Au Optronics Corporation | Display device |
Also Published As
Publication number | Publication date |
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CN109791746A (en) | 2019-05-21 |
WO2018062035A1 (en) | 2018-04-05 |
CN109791746B (en) | 2021-06-08 |
US10578941B2 (en) | 2020-03-03 |
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