US20190228834A1 - Semiconductor systems - Google Patents
Semiconductor systems Download PDFInfo
- Publication number
- US20190228834A1 US20190228834A1 US16/370,439 US201916370439A US2019228834A1 US 20190228834 A1 US20190228834 A1 US 20190228834A1 US 201916370439 A US201916370439 A US 201916370439A US 2019228834 A1 US2019228834 A1 US 2019228834A1
- Authority
- US
- United States
- Prior art keywords
- data
- failure
- test
- signal
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
Definitions
- Embodiments of the present disclosure may generally relate to semiconductor systems, and more particularly to semiconductor systems including semiconductor devices configured for correcting data errors.
- error codes which are capable of detecting the occurrence of errors may be generated and transmitted with the data to guarantee the reliability of data transmission.
- the error codes may include an error detection code (EDC) which is capable of detecting errors and an error correction code (ECC) which is capable of correcting the errors by itself.
- EDC error detection code
- ECC error correction code
- a semiconductor system may be provided.
- the semiconductor system may include a first semiconductor device and a second semiconductor device.
- the first semiconductor device may be configured to output a test command, a test address, test input data, and an error correction control signal.
- the first semiconductor device may be configured to classify failure groups of test output data and may be configured to generate a failure row address and a failure column address that may include position information on the failure groups.
- the second semiconductor device may be configured to perform an error correction operation of internal data selected by the test address to output the corrected internal data as the test output data based on a test enablement signal and the error correction control signal.
- the second semiconductor device may be configured to replace a memory area in which the failure groups of the test output data are stored with a redundancy area according to a row address and a column address generated from the failure row address and the failure column address.
- a semiconductor system may be provided.
- the semiconductor system may include a first semiconductor device and a second semiconductor device.
- the first semiconductor device may be configured to output a test command, a test address, test input data, and an error correction control signal.
- the first semiconductor device may be configured to set priorities of failure groups of test output data.
- the second semiconductor device may be configured to perform an error correction operation of internal data selected by the test address to output the corrected internal data as the test output data based on a test enablement signal and the error correction control signal.
- the second semiconductor device may be configured to replace a memory area in which the failure groups of the test output data are stored with a redundancy area according to the priorities of the failure groups.
- a semiconductor system may be provided.
- the semiconductor system may include a first semiconductor device that may be configured to classify failure groups of data including erroneous bits and replace a memory area in which the failure groups are stored with a redundancy area according to priorities of the failed groups.
- FIG. 1 is a block diagram illustrating a configuration of a semiconductor system according to an embodiment of the present disclosure.
- FIG. 2 is a block diagram illustrating a configuration of a first semiconductor device included in the semiconductor system of FIG. 1 .
- FIG. 3 is a block diagram illustrating a configuration of a second semiconductor device included in the semiconductor system of FIG. 1 .
- FIG. 4 is a block diagram illustrating a configuration of an erroneous data classification circuit included in the second semiconductor device of FIG. 3 .
- FIGS. 5 and 6 are schematic views illustrating first to fourth failure groups set in a semiconductor system according to an embodiment of the present disclosure.
- FIG. 7 is a block diagram illustrating a configuration of a repair control circuit included in the second semiconductor device of FIG. 3 .
- FIG. 8 is a block diagram illustrating a configuration of a third semiconductor device included in the semiconductor system of FIG. 1 .
- FIG. 9 is a block diagram illustrating a configuration of an error correction circuit included in the third semiconductor of FIG. 8 .
- FIG. 10 is a block diagram illustrating a configuration of a memory circuit included in the third semiconductor of FIG. 8 .
- FIG. 11 is a block diagram illustrating a configuration of an electronic system employing the semiconductor system described with reference to FIGS. 1 to 10 .
- FIG. 12 is a block diagram illustrating a configuration of an electronic system employing the semiconductor system described with reference to FIGS. 1 to 10 .
- a semiconductor system may include a first semiconductor device 1 , a second semiconductor device 2 , and a third semiconductor device 3 .
- the first semiconductor device 1 may output a test enablement signal TEN, a command CMD, a row address RADD, and a column address CADD.
- the first semiconductor device 1 may receive or output data DATA ⁇ 1 : 64 >.
- the first semiconductor device 1 may change a combination of the row address RADD corresponding to a failure row address F_RADD ⁇ 1 :N> and a combination of the column address CADD corresponding to a failure column address F_CADD ⁇ 1 :N> and may output the row address RADD and the column address CADD with the combination changes.
- the command CMD is illustrated with a single signal line, the command CMD may be set to include a plurality of bits and may be transmitted through signal lines that transmit at least one group of addresses, commands, and data.
- each of the row address RADD and the column address CADD is illustrated with a single signal line, each of the row address RADD and the column address CADD may be set to include a plurality of bits and may be transmitted through signal lines that transmit at least one group of addresses, commands, and data.
- the data DATA ⁇ 1 : 64 > may be transmitted through signal lines that transmit at least one group of addresses, commands and data.
- the number of bits of the data DATA ⁇ 1 : 64 > may be set to be different according to the embodiments.
- the test enablement signal TEN may be enabled to perform a test for classifying failure groups of test output data TDOUT ⁇ 1 : 64 >.
- the second semiconductor device 2 may output a test command TCMD, a test address TADD, a test input data TDIN ⁇ 1 : 64 >, and an error correction control signal ECC_CON.
- the test address TADD may be set to include a plurality of bits which are sequentially counted.
- the second semiconductor device 2 may classify the failure groups of the test output data TDOUT ⁇ 1 : 64 >.
- the second semiconductor device 2 may generate the failure row address F_RADD ⁇ 1 :N> and the failure column address F_CADD ⁇ 1 :N> that include position information on the failure groups of the test output data TDOUT ⁇ 1 : 64 >.
- the error correction control signal ECC_CON may be enabled to perform an error correction operation for correcting errors of internal data (ID ⁇ 1 : 64 > of FIG. 8 ).
- the third semiconductor device 3 may perform the error correction operation of the internal data (ID ⁇ 1 : 64 > of FIG. 8 ) selected according to the test address TADD to output the corrected internal data as the test output data TDOUT ⁇ 1 : 64 >, in response to the test enablement signal TEN and the error correction control signal ECC_CON.
- the third semiconductor device 3 may replace an area in which a failure group of the test output data TDOUT ⁇ 1 : 64 > is stored according to the row address RADD and the column address CADD generated from the failure row address F_RADD ⁇ 1 :N> and the failure column address F_CADD ⁇ 1 :N> with a redundancy area (a row redundancy area 352 and a column redundancy area 353 of FIG. 10 ).
- the third semiconductor device 3 may receive or output the data DATA ⁇ 1 : 64 > according to the row address RADD and the column address CADD in response to the command CMD and the error correction control signal ECC_CON.
- the first semiconductor device 1 may include a fuse circuit 11 , a control circuit 12 , and a data processing circuit 13 .
- the fuse circuit 11 may include a plurality of fuses.
- the fuse circuit 11 may program the plurality of fuses to generate a programmed row address P_RADD ⁇ 1 :N> and a programmed column address P_CADD ⁇ 1 :N> according to the failure row address F_RADD ⁇ 1 :N> and the failure column address F_CADD ⁇ 1 :N>.
- the fuse circuit 11 may be realized using a general fuse array circuit in which a plurality of fuses are arrayed.
- the control circuit 12 may output the command CMD, the row address RADD, the column address CADD, and the test enablement signal TEN. If an area selected by the row address RADD is identical to an area selected by the programmed row address P_RADD ⁇ 1 :N>, the control circuit 12 may change a combination of the row address RADD and may output the row address RADD having the changed combination. If an area selected by the column address CADD is identical to an area selected by the programmed column address P_CADD ⁇ 1 :N>, the control circuit 12 may change a combination of the column address CADD and may output the column address CADD having the changed combination. The control circuit 12 may interrupt the output of the command CMD, the row address RADD, and the column address CADD if the test enablement signal TEN is enabled.
- the data processing circuit 13 may receive an external data EXD ⁇ 1 : 64 > to output the data DATA ⁇ 1 : 64 > during a write operation.
- the data processing circuit 13 may receive the data DATA ⁇ 1 : 64 > to output the external data EXD ⁇ 1 : 64 > during a read operation.
- the second semiconductor device 2 may include a test control circuit 21 , an erroneous data classification circuit 22 , and a repair control circuit 23 .
- the test control circuit 21 may output the test command TCMD, the test address TADD, the test input data TDIN ⁇ 1 : 64 >, and the error correction control signal ECC_CON in response to a test information signal JTAG provided by an external device.
- the test information signal JTAG is illustrated with a single signal line, the test information signal JTAG may be set to include a plurality of bits.
- the test information signal JTAG may include information for generating the test command TCMD, the test address TADD, the test input data TDIN ⁇ 1 : 64 >, and the error correction control signal ECC_CON.
- the test command TCMD is illustrated with a single signal line, the test command TCMD may be set to include a plurality of bits.
- the test address TADD is illustrated with a single signal line, the test address TADD may be set to include a plurality of bits.
- the number of bits of the test input data TDIN ⁇ 1 : 64 > may be set to be different according to the embodiments.
- the erroneous data classification circuit 22 may classify the failure groups of the test output data TDOUT ⁇ 1 : 64 >.
- the erroneous data classification circuit 22 may generate first to third failure group information signals FCLS 1 ⁇ 1 :N>, FCLS 2 ⁇ 1 :N>, and FCLS 3 ⁇ 1 :N> from the test address TADD including position information on the failure groups of the test output data TDOUT ⁇ 1 : 64 >.
- the first failure group information signal FCLS 1 ⁇ 1 :N> may include the position information on the first failure group having a first priority.
- the second failure group information signal FCLS 2 ⁇ 1 :N> may include the position information on the second failure group having a second priority.
- the third failure group information signal FCLS 3 ⁇ 1 :N> may include the position information on the third failure group having a third priority.
- the repair control circuit 23 may output the first to third failure group information signals FCLS 1 ⁇ 1 :N>, FCLS 2 ⁇ 1 :N>, and FCLS 3 ⁇ 1 :N> as the failure row address F_RADD ⁇ 1 :N> and the failure column address F_CADD ⁇ 1 :N> in response to a redundancy use information signal RDI.
- the redundancy use information signal RDI may include information on the availability of the redundancy area (the row redundancy area 352 and the column redundancy area 353 of FIG. 10 ).
- the redundancy use information signal RDI may be enabled if the redundancy area (the row redundancy area 352 and the column redundancy area 353 of FIG. 10 ) has a replaceable area.
- the erroneous data classification circuit 22 may include a comparison circuit 221 , a selection signal generation circuit 222 , a selection and transmission (selection/transmission) circuit 223 , a first storage circuit 224 , and a second storage circuit 225 .
- the comparison circuit 221 may compare logic levels of the test output data TDOUT ⁇ 1 : 64 > with logic levels of reference data REFD ⁇ 1 : 64 > to generate a failure comparison signal F_CMP ⁇ 1 : 64 >.
- the comparison circuit 221 may compare logic levels of the corresponding bits of the test output data TDOUT ⁇ 1 : 64 > and the reference data REFD ⁇ 1 : 64 > to generate the failure comparison signal F_CMP ⁇ 1 : 64 >.
- the comparison circuit 221 may generate the failure comparison signal F_CMP ⁇ 1 > which is enabled to have a logic “high” level if a logic level of the test output datum TDOUT ⁇ 1 > is different from a logic level of the reference datum REFD ⁇ 1 >.
- the failure comparison signal F_CMP ⁇ 1 : 64 > may be generated to include information on the number of bit pairs having different logic levels among the pairs of the corresponding bits of the test output data TDOUT ⁇ 1 : 64 > and the reference data REFD ⁇ 1 : 64 >.
- the reference data REFD ⁇ 1 : 64 > may be set to have the same level combination as the test input data TDIN ⁇ 1 : 64 >.
- the selection signal generation circuit 222 may generate a selection signal SEL in response to the failure comparison signal F_CMP ⁇ 1 : 64 >.
- the selection signal generation circuit 222 may generate the selection signal SEL which is enabled if any one bit of the failure comparison signal F_CMP ⁇ 1 : 64 > is enabled.
- the selection/transmission circuit 223 may output the failure comparison signal F_CMP ⁇ 1 : 64 > as a first failure transmission signal F_TS 1 ⁇ 1 : 64 > or a second failure transmission signal F_TS 2 ⁇ 1 : 64 > in response to the selection signal SEL.
- the selection/transmission circuit 223 may output the failure comparison signal F_CMP ⁇ 1 : 64 > as the first failure transmission signal F_TS 1 ⁇ 1 : 64 > if the selection signal SEL is enabled.
- the selection/transmission circuit 223 may output the failure comparison signal F_CMP ⁇ 1 : 64 > as the second failure transmission signal F_TS 2 ⁇ 1 : 64 > if the selection signal SEL is disabled.
- the first storage circuit 224 may detect the number of bits which are enabled among the bits of the first failure transmission signal F_TS 1 ⁇ 1 : 64 >.
- the first storage circuit 224 may synthesize the test address TADD and the first failure transmission signal F_TS 1 ⁇ 1 : 64 > to generate the first to third failure group information signals FCLS 1 ⁇ 1 :N>, FCLS 2 ⁇ 1 :N> and FCLS 3 ⁇ 1 :N> according to the detection result of the number of the bits which are enabled among the bits of the first failure transmission signal F_TS 1 ⁇ 1 : 64 >.
- the first failure group information signal FCLS 1 ⁇ 1 :N> may include position information of a memory area ( 351 of FIG.
- the second failure group information signal FCLS 2 ⁇ 1 :N> may include position information of the memory area ( 351 of FIG. 10 ) storing the second failure group and position information of erroneous bits of the test output data TDOUT ⁇ 1 : 64 >.
- the third failure group information signal FCLS 3 ⁇ 1 :N> may include position information of the memory area ( 351 of FIG. 10 ) storing the third failure group and position information of erroneous bits of the test output data TDOUT ⁇ 1 : 64 >.
- the second storage circuit 225 may synthesize the test address TADD and the second failure transmission signal F_TS 2 ⁇ 1 : 64 > to generate a fourth failure group information signal FCLS 4 ⁇ 1 :N>.
- the fourth failure group information signal FCLS 4 ⁇ 1 :N> may include position information of the memory area ( 351 of FIG. 10 ) storing the fourth failure group and position information of erroneous bits of the test output data TDOUT ⁇ 1 : 64 >.
- a method of setting the first to fourth failure groups of the test output data TDOUT ⁇ 1 : 64 > will be described hereinafter with reference to FIGS. 5 and 6 .
- ECC_OFF means the internal data (ID ⁇ 1 : 64 > of FIG. 8 ) before the error correction operation of the internal data (ID ⁇ 1 : 64 > of FIG. 8 ) is performed
- ECC_ON means the test output data TDOUT ⁇ 1 : 64 > generated after the error correction operation of the internal data (ID ⁇ 1 : 64 > of FIG. 8 ) is performed.
- the first failure group of the test output data TDOUT ⁇ 1 : 64 > may be set to have failed bits which are not corrected by the error correction operation when the internal data ID ⁇ 1 : 64 > have at least two failed bits. That is, the first failure group of the test output data TDOUT ⁇ 1 : 64 > may be set to have the second, third, and fourth bits ID ⁇ 2 : 4 > of the internal data ID ⁇ 1 : 64 >.
- the third failure group of the test output data TDOUT ⁇ 1 : 64 > may be set to have a single bit which is corrected by the error correction operation when the internal data ID ⁇ 1 : 64 > have at least two failed bits. That is, the third failure group of the test output data TDOUT ⁇ 1 : 64 > may be set to have the first bit ID ⁇ 1 > of the internal data ID ⁇ 1 : 64 >.
- the fourth failure group of the test output data TDOUT ⁇ 1 : 64 > may be set to have a failed bit whose logic level is inverted by the error correction operation when the internal data ID ⁇ 1 : 64 > have at least two failed bits. That is, the fourth failure group of the test output data TDOUT ⁇ 1 : 64 > may be set to have the last bit, for example, the sixty fourth bit ID ⁇ 64 > of the internal data ID ⁇ 1 : 64 >.
- the second failure group of the test output data TDOUT ⁇ 1 : 64 > may be set to have a single bit which is corrected by the error correction operation when the internal data ID ⁇ 1 : 64 > have a single failed bit. Accordingly, the second failure group of the test output data TDOUT ⁇ 1 : 64 > may be set to have the first bit ID ⁇ 1 > of the internal data ID ⁇ 1 : 64 >.
- the repair control circuit 23 may include a flag signal generation circuit 231 and a failure address generation circuit 232 .
- the flag signal generation circuit 231 may generate a flag signal RFLAG which is enabled in response to the redundancy use information signal RDI.
- the flag signal generation circuit 231 may generate the flag signal RFLAG which is enabled in response to the redundancy use information signal RDI if the redundancy area (the row redundancy area 352 and the column redundancy area 353 of FIG. 10 ) has a replaceable area.
- the failure address generation circuit 232 may output the first to third failure group information signals FCLS 1 ⁇ 1 :N>, FCLS 2 ⁇ 1 :N>, and FCLS 3 ⁇ 1 :N> as the failure row address F_RADD ⁇ 1 :N> and the failure column address F_CADD ⁇ 1 :N> in response to the flag signal RFLAG.
- the failure address generation circuit 232 may generate the failure row address F_RADD ⁇ 1 :N> and the failure column address F_CADD ⁇ 1 :N> from the first failure group information signal FCLS 1 ⁇ 1 :N> if the flag signal RFLAG is enabled.
- the failure address generation circuit 232 may generate the failure row address F_RADD ⁇ 1 :N> and the failure column address F_CADD ⁇ 1 :N> from the second failure group information signal FCLS 2 ⁇ 1 :N> if the flag signal RFLAG is enabled.
- the failure address generation circuit 232 may generate the failure roar address F_RADD ⁇ 1 :N> and the failure column address F_CADD ⁇ 1 :N> from the third failure group information signal FCLS 3 ⁇ 1 :N> if the flag signal RFLAG is enabled.
- the third semiconductor device 3 may include an input and output (input/output) (I/O) circuit 31 , an internal command generation circuit 32 , an enablement signal generation circuit 33 , an error correction circuit 34 , and a memory circuit 35 .
- I/O input and output
- the I/O circuit 31 may include an input buffer 311 and an output buffer 312 .
- the input buffer 311 may output the test input data TDIN ⁇ 1 : 64 > or the data DATA ⁇ 1 : 64 > as input data DIN ⁇ 1 : 64 > in response to the test enablement signal TEN.
- the input buffer 311 may output the test input data TDIN ⁇ 1 : 64 > as the input data DIN ⁇ 1 : 64 > if the test enablement signal TEN is enabled.
- the input buffer 311 may drive the input data DIN ⁇ 1 : 64 > in response to the test input data TDIN ⁇ 1 : 64 > if the test enablement signal TEN is enabled.
- the input buffer 311 may output the data DATA ⁇ 1 : 64 > as the input data DIN ⁇ 1 : 64 > if the test enablement signal TEN is disabled.
- the input buffer 311 may drive the input data DIN ⁇ 1 : 64 > in response to the data DATA ⁇ 1 : 64 > if the test enablement signal TEN is disabled.
- the output buffer 312 may transmit output data DOUT ⁇ 1 : 64 > as the test output data TDOUT ⁇ 1 : 64 > or the data DATA ⁇ 1 : 64 > in response to the test enablement signal TEN.
- the output buffer 312 may output the output data DOUT ⁇ 1 : 64 > as the test output data TDOUT ⁇ 1 : 64 > if the test enablement signal TEN is enabled.
- the output buffer 312 may drive the test output data TDOUT ⁇ 1 : 64 > in response to the output data DOUT ⁇ 1 : 64 > if the test enablement signal TEN is enabled.
- the output buffer 312 may output the output data DOUT ⁇ 1 : 64 > as the data DATA ⁇ 1 : 64 > if the test enablement signal TEN is disabled.
- the output buffer 312 may drive the data DATA ⁇ 1 : 64 > in response to the output data DOUT ⁇ 1 : 64 > if the test enablement signal TEN is disabled.
- the internal command generation circuit 32 may decode the test command TCMD or the command CMD to generate an internal command ICMD, in response to the test enablement signal TEN.
- the internal command generation circuit 32 may decode the test command TCMD to generate the internal command ICMD if the test enablement signal TEN is enabled.
- the internal command generation circuit 32 may decode the command CMD to generate the internal command ICMD if the test enablement signal TEN is disabled.
- the internal command ICMD may be a command for controlling an internal operation (e.g., a write operation or a read operation) of the third semiconductor device 3 .
- the enablement signal generation circuit 33 may generate an enablement signal EN which is enabled in response to the internal command ICMD if a failure detection signal F_DET is enabled.
- the enablement signal generation circuit 33 may generate the enablement signal EN which is disabled in response to the internal command ICMD if the failure detection signal F_DET is disabled.
- the error correction circuit 34 may generate an internal codeword ICDW including error information on the input data DIN ⁇ 1 : 64 >, may detect erroneous data of the internal data ID ⁇ 1 : 64 > to generate the failure detection signal F_DET, and may perform the error correction operation of the internal data ID ⁇ 1 : 64 > to generate the output data DOUT ⁇ 1 : 64 > according to the error correction control signal ECC_CON.
- the error correction circuit 34 may generate the internal codeword ICDW including error information on the input data DIN ⁇ 1 : 64 > during the write operation.
- the error correction circuit 34 may detect erroneous data of the internal data ID ⁇ 1 : 64 > to generate the failure detection signal F_DET during the read operation.
- the error correction circuit 34 may perform the error correction operation of the internal data ID ⁇ 1 : 64 > to generate the output data DOUT ⁇ 1 : 64 > during the read operation.
- the memory circuit 35 may store the input data DIN ⁇ 1 : 64 >as the internal data ID ⁇ 1 : 64 > according to the test address TADD or the row and column addresses RADD and CADD during the write operation.
- the memory circuit 35 may store the input data DIN ⁇ 1 : 64 > corresponding to the internal data ID ⁇ 1 : 64 > into the memory area ( 351 of FIG. 10 ) thereof according to the test address TADD which is sequentially counted, during a write operation for test.
- the memory circuit 35 may store the internal codeword ICDW during the write operation for test.
- the memory circuit 35 may store the input data DIN ⁇ 1 : 64 > as the internal data ID ⁇ 1 : 64 > according to the row and column addresses RADD and CADD during a normal write operation.
- the memory circuit 35 may store the internal codeword ICDW during the normal write operation.
- the memory circuit 35 may output the internal data ID ⁇ 1 : 64 > stored therein according to the test address TADD or the row and column addresses RADD and CADD during the read operation.
- the memory circuit 35 may output the internal data ID ⁇ 1 : 64 > stored in the memory area ( 351 of FIG. 10 ) according to the test address TADD which is sequentially counted during a read operation for test.
- the memory circuit 35 may output the internal data ID ⁇ 1 : 64 > stored in the memory area ( 351 of FIG. 10 ) according to the row and column addresses RADD and CADD during a normal read operation.
- the memory circuit 35 may be realized to include both of an area for storing the input data DIN ⁇ 1 : 64 > and an area for storing the internal codeword ICDW.
- the error correction circuit 34 may include a codeword generation circuit 341 , a comparison code generation circuit 342 , a syndrome generation circuit 343 , and a data correction circuit 344 .
- the codeword generation circuit 341 may generate the internal codeword ICDW including error information on the input data DIN ⁇ 1 : 64 >, The codeword generation circuit 341 may generate the internal codeword ICDW including error information on the input data DIN ⁇ 1 : 64 > during the write operation.
- the comparison code generation circuit 342 may generate a comparison code CPCD including error information on the internal data ID ⁇ 1 : 64 >.
- the comparison code generation circuit 342 may generate the comparison code CPCD including error information on the internal data ID ⁇ 1 : 64 > during the read operation.
- the syndrome generation circuit 343 may compare the internal codeword ICDW with the comparison code CPCD to generate a syndrome signal SYN and may generate the failure detection signal F_DET which is enabled if the syndrome signal SYN is generated.
- the syndrome generation circuit 343 may compare the internal codeword ICDW with the comparison code CPCD to generate the syndrome signal SYN during the read operation and may generate the failure detection signal F_DET which is enabled if the syndrome signal SYN is generated.
- the syndrome signal SYN may include position information of erroneous bits (i.e., failed bits) among the bits included in the internal data ID ⁇ 1 : 64 >.
- the data correction circuit 344 may correct erroneous data of the internal data ID ⁇ 1 : 64 > to output the corrected internal data as the output data DOUT ⁇ 1 : 64 > according to the syndrome signal SYN, in response to the error correction control signal ECC_CON.
- the data correction circuit 344 may correct erroneous data of the internal data ID ⁇ 1 : 64 > to output the corrected internal data as the output data DOUT ⁇ 1 : 64 > according to the syndrome signal SYN, in response to the error correction control signal ECC_CON during the read operation.
- the data correction circuit 344 may correct erroneous data of the internal data ID ⁇ 1 : 64 > to output the corrected internal data as the output data DOUT ⁇ 1 : 64 > according to the syndrome signal SYN, if the error correction control signal ECC_CON is enabled during the read operation.
- the data correction circuit 344 may output the internal data ID ⁇ 1 : 64 > as the output data DOUT ⁇ 1 : 64 > without correcting erroneous data of the internal data ID ⁇ 1 : 64 >, in response to the error correction control signal ECC_CON.
- the data correction circuit 344 may output the internal data ID ⁇ 1 : 64 > as the output data DOUT ⁇ 1 : 64 > without correcting erroneous data of the internal data ID ⁇ 1 : 64 >, in response to the error correction control signal ECC_CON during the read operation.
- the data correction circuit 344 may output the internal data ID ⁇ 1 : 64 > as the output data DOUT ⁇ 1 : 64 > without correcting erroneous data of the internal data ID ⁇ 1 : 64 >, if the error correction control signal ECC_CON is disabled during the read operation.
- the error correction circuit 34 described above may include in part a general error correction code (ECC) circuit using an error detection code (EDC) and an error correction code (ECC).
- ECC error correction code
- the memory circuit 35 may include the memory area 351 , the row redundancy area 352 , and the column redundancy area 353 .
- the memory area 351 may store the input data DIN ⁇ 1 : 64 > into an area selected by the test address TADD sequentially counted and may output the stored input data DIN ⁇ 1 : 64 > as the internal data ID ⁇ 1 : 64 >.
- the memory area 351 may store the input data DIN ⁇ 1 : 64 > into an area selected by the row and column addresses RADD and CADD and may output the stored input data DIN ⁇ 1 : 64 > as the internal data ID ⁇ 1 : 64 >.
- the memory area 351 may store the input data DIN ⁇ 1 : 64 > into an area selected by the test address TADD during the write operation for test.
- the memory area 351 may store the internal codeword ICDW during the write operation for test.
- the memory area 351 may output the input data DIN ⁇ 1 : 64 > stored in an area selected by the test address TADD as the internal data ID ⁇ 1 : 64 > during the read operation for test.
- the memory area 351 may store the input data DIN ⁇ 1 : 64 > into an area selected by the row and column addresses RADD and CADD during the normal write operation.
- the memory area 351 may store the internal codeword ICDW during the normal write operation.
- the memory area 351 may output the input data DIN ⁇ 1 : 64 > stored in an area selected by the row and column addresses RADD and CADD as the internal data ID ⁇ 1 : 64 > during the normal read operation.
- the row redundancy area 352 may replace the memory area 351 having the failure group according to the row address RADD to store the input data DIN ⁇ 1 : 64 > into the row redundancy area 352 and may output the stored input data DIN ⁇ 1 : 64 > as the internal data ID ⁇ 1 : 64 >.
- the row redundancy area 352 may replace the memory area 351 having the failure group according to the row address RADD to store the input data DIN ⁇ 1 : 64 > into the row redundancy area 352 during the write operation.
- the row redundancy area 352 may output the stored input data DIN ⁇ 1 : 64 > as the internal data ID ⁇ 1 : 64 > according to the row address RADD during the read operation.
- the column redundancy area 353 may replace the memory area 351 having the failure group according to the column address CADD to store the input data DIN ⁇ 1 : 64 > into the column redundancy area 353 and may output the stored input data DIN ⁇ 1 : 64 > as the internal data ID ⁇ 1 : 64 >.
- the column redundancy area 353 may replace the memory area 351 having the failure group according to the column address CADD to store the input data DIN ⁇ 1 : 64 > into the column redundancy area 353 during the write operation.
- the column redundancy area 353 may output the stored input data DIN ⁇ 1 : 64 > as the internal data ID ⁇ 1 : 64 > according to the column address CADD during the read operation.
- the first row area R 1 of the memory area 351 may be replaced with the row redundancy area 352 to store the input data DIN ⁇ 1 : 64 > into the row redundancy area 352 and the input data DIN ⁇ 1 : 64 > stored in the row redundancy area 352 may be outputted as the internal data ID ⁇ 1 : 64 >.
- the second row area R 2 of the memory area 351 may be replaced with the row redundancy area 352 to store the input data DIN ⁇ 1 : 64 > into the row redundancy area 352 and the input data DIN ⁇ 1 : 64 > stored in the row redundancy area 352 may be outputted as the internal data ID ⁇ 1 : 64 >.
- the first column area C 1 of the memory area 351 may be replaced with the column redundancy area 353 to store the input data DIN ⁇ 1 : 64 > into the column redundancy area 353 and the input data DIN ⁇ 1 : 64 > stored in the column redundancy area 353 may be outputted as the internal data ID ⁇ 1 : 64 >.
- the second and third column areas C 2 and C 3 may be replaced with the column redundancy area 353 to store the input data DIN ⁇ 1 : 64 > into the column redundancy area 353 and the input data DIN ⁇ 1 : 64 > stored in the column redundancy area 353 may be outputted as the internal data ID ⁇ 1 : 64 >.
- the fourth column area C 4 may be replaced with the column redundancy area 353 to store the input data DIN ⁇ 1 : 64 > into the column redundancy area 353 and the input data DIN ⁇ 1 : 64 > stored in the column redundancy area 353 may be outputted as the internal data ID ⁇ 1 : 64 >.
- the memory area 351 in which the first failure groups (indicated by the symbol “ ⁇ ”) are stored may be replaced with the row redundancy area 352 and the column redundancy area 353 by the first priority
- the memory area 351 in which the second failure groups (indicated by the symbol “ ⁇ ”) are stored may be replaced with the row redundancy area 352 and the column redundancy area 353 by the second priority
- the memory area 351 in which the third failure groups (indicated by the symbol “ ⁇ ”) are stored may be replaced with the row redundancy area 352 and the column redundancy area 353 by the third priority.
- an area “A” including the third failure groups may not be replaced with any of the row redundancy area 352 and the column redundancy area 353 .
- an area “B” including the second failure group may not be replaced with any of the row redundancy area 352 and the column redundancy area 353 .
- a semiconductor system may classify failure groups of data including erroneous bits and may replace a memory area in which the failure groups are stored with a redundancy area according to priorities of the failure groups. As a result, the fabrication yield of the semiconductor systems may be improved.
- an electronic system 1000 may include a data storage circuit 1001 , a memory controller 1002 , a buffer memory 1003 , and an input/output (I/O) interface 1004 .
- I/O input/output
- the data storage circuit 1001 may store data which are outputted from the memory controller 1002 or may read and output the stored data to the memory controller 1002 , according to a control signal generated from the memory controller 1002 .
- the data storage circuit 1001 may include the third semiconductor device 3 illustrated in FIG. 1 .
- the data storage circuit 1001 may include a nonvolatile memory that can retain their stored data even when its power supply is interrupted.
- the nonvolatile memory may be a flash memory such as a NOR-type flash memory or a NAND-type flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), or the like.
- the memory controller 1002 may receive a command outputted from an external device (e.g., a host device) through the I/O interface 1004 and may decode the command outputted from the host device to control an operation for inputting data into the data storage circuit 1001 or the buffer memory 1003 or for outputting the data stored in the data storage circuit 1001 or the buffer memory 1003 .
- the memory controller 1002 may include the first and second semiconductor devices 1 and 2 illustrated in FIG. 1 .
- FIG. 11 illustrates the memory controller 1002 with a single block, the memory controller 1002 may include one controller for controlling the data storage circuit 1001 comprised of a nonvolatile memory and another controller for controlling the buffer memory 1003 comprised of a volatile memory.
- the buffer memory 1003 may temporarily store the data which are processed by the memory controller 1002 . That is, the buffer memory 1003 may temporarily store the data which are outputted from or to be inputted to the data storage circuit 1001 .
- the buffer memory 1003 may store the data, which are outputted from the memory controller 1002 , according to a control signal.
- the buffer memory 1003 may read and output the stored data to the memory controller 1002 .
- the buffer memory 1003 may include a volatile memory such as a dynamic random access memory (DRAM), a mobile DRAM, or a static random access memory (SRAM).
- DRAM dynamic random access memory
- SRAM static random access memory
- the I/O interface 1004 may physically and electrically connect the memory controller 1002 to the external device (i.e., the host).
- the memory controller 1002 may receive control signals and data supplied from the external device (i.e., the host) through the I/O interface 1004 and may output the data generated from the memory controller 1002 to the external device (i.e., the host) through the I/O interface 1004 . That is, the electronic system 1000 may communicate with the host through the I/O interface 1004 .
- the I/O interface 1004 may include any one of various interface protocols such as a universal serial bus (USB) drive, a multi-media card (MMC), a peripheral component interconnect-express (PCI-E), a serial attached SCSI (SAS), a serial AT attachment (SATA), a parallel AT attachment (PATA), a small computer system interface (SCSI), an enhanced small device interface (ESDI) and an integrated drive electronics (IDE).
- USB universal serial bus
- MMC multi-media card
- PCI-E peripheral component interconnect-express
- SAS serial attached SCSI
- SATA serial AT attachment
- PATA parallel AT attachment
- SCSI small computer system interface
- ESDI enhanced small device interface
- IDE integrated drive electronics
- the electronic system 1000 may be used as an auxiliary storage device of the host or an external storage device.
- the electronic system 1000 may include a solid state disk (SSD), a USB drive, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multi-media card (MMC), an embedded multi-media card (eMMC), a compact flash (CF) card, or the like.
- SSD solid state disk
- SD secure digital
- mSD mini secure digital
- micro SD micro secure digital
- SDHC secure digital high capacity
- SM smart media
- MMC multi-media card
- eMMC embedded multi-media card
- CF compact flash
- an electronic system 2000 may include a host 2001 , a memory controller 2002 , and a data storage circuit 2003 .
- the host 2001 may output a request signal and data to the memory controller 2002 to access to the data storage circuit 2003 .
- the memory controller 2002 may supply the data, a data strobe signal, a command, addresses, and a clock signal to the data storage circuit 2003 in response to the request signal, and the data storage circuit 2003 may execute a write operation or a read operation in response to the command.
- the host 2001 may transmit the data to the memory controller 2002 to store the data into the data storage circuit 2003 .
- the host 2001 may receive the data outputted from the data storage circuit 2003 through the memory controller 2002 .
- the host 2001 may include a circuit that corrects errors of the data using an error correction code (ECC) scheme.
- ECC error correction code
- the memory controller 2002 may act as an interface that connects the host 2001 to the data storage circuit 2003 for communication between the host 2001 and the data storage circuit 2003 .
- the memory controller 2002 may receive the request signal and the data outputted from the host 2001 and may generate and supply the data, the data strobe signal, the command, the addresses and the clock signal to the data storage circuit 2003 in order to control operations of the data storage circuit 2003 .
- the memory controller 2002 may supply the data outputted from the data storage circuit 2003 to the host 2001 .
- the memory controller 2002 may include the first and second semiconductor devices 1 and 2 illustrated in FIG. 1 .
- the data storage circuit 2003 may include a plurality of memories.
- the data storage circuit 2003 may receive the data, the data strobe signal, the command, the addresses, and the clock signal from the memory controller 2002 to execute the write operation or the read operation.
- Each of the memories included in the data storage circuit 2003 may include a circuit that corrects the errors of the data using an error correction code (ECC) scheme.
- ECC error correction code
- the data storage circuit 2003 may include the third semiconductor device 3 illustrated in FIG. 1 .
- the electronic system 2000 may be realized to selectively operate any one of the ECC circuits included in the host 2001 and the data storage circuit 2003 .
- the electronic system 2000 may be realized to simultaneously operate all of the ECC circuits included in the host 2001 and the data storage circuit 2003 .
- the host 2001 and the memory controller 2002 may be realized in a single chip according to the embodiments.
- the memory controller 2002 and the data storage circuit 2003 may be realized in a single chip according to the embodiments.
Abstract
Description
- The present application is a divisional application of U.S. patent application Ser. No. 15/819,411, filed on Nov. 21, 2017, and claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2017-0071601, filed on Jun. 8, 2017, which is incorporated herein by reference in its entirety.
- Embodiments of the present disclosure may generally relate to semiconductor systems, and more particularly to semiconductor systems including semiconductor devices configured for correcting data errors.
- With regards to the fabrication of semiconductor devices, attempts to increase integration density in the semiconductor devices have typically resulted in the increase of failed memory cells. This may lead to lowering the fabrication yield of the semiconductor devices. Even though each semiconductor device has, for example, only a single defective memory cell, the semiconductor device still cannot be supplied to customers due to the single defective memory cell.
- A lot of effort has gone into improving the fabrication yield of highly integrated semiconductor devices. For example, various techniques for repairing addresses of failed memory cells with redundancy memory cells have been proposed to improve the fabrication yield of the highly integrated semiconductor devices.
- Whenever data is transmitted in semiconductor devices, error codes which are capable of detecting the occurrence of errors may be generated and transmitted with the data to guarantee the reliability of data transmission. The error codes may include an error detection code (EDC) which is capable of detecting errors and an error correction code (ECC) which is capable of correcting the errors by itself.
- According to an embodiment, a semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a test command, a test address, test input data, and an error correction control signal. The first semiconductor device may be configured to classify failure groups of test output data and may be configured to generate a failure row address and a failure column address that may include position information on the failure groups. The second semiconductor device may be configured to perform an error correction operation of internal data selected by the test address to output the corrected internal data as the test output data based on a test enablement signal and the error correction control signal. The second semiconductor device may be configured to replace a memory area in which the failure groups of the test output data are stored with a redundancy area according to a row address and a column address generated from the failure row address and the failure column address.
- According to an embodiment, a semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a test command, a test address, test input data, and an error correction control signal. The first semiconductor device may be configured to set priorities of failure groups of test output data. The second semiconductor device may be configured to perform an error correction operation of internal data selected by the test address to output the corrected internal data as the test output data based on a test enablement signal and the error correction control signal. The second semiconductor device may be configured to replace a memory area in which the failure groups of the test output data are stored with a redundancy area according to the priorities of the failure groups.
- According to an embodiment, a semiconductor system may be provided. The semiconductor system may include a first semiconductor device that may be configured to classify failure groups of data including erroneous bits and replace a memory area in which the failure groups are stored with a redundancy area according to priorities of the failed groups.
-
FIG. 1 is a block diagram illustrating a configuration of a semiconductor system according to an embodiment of the present disclosure. -
FIG. 2 is a block diagram illustrating a configuration of a first semiconductor device included in the semiconductor system ofFIG. 1 . -
FIG. 3 is a block diagram illustrating a configuration of a second semiconductor device included in the semiconductor system ofFIG. 1 . -
FIG. 4 is a block diagram illustrating a configuration of an erroneous data classification circuit included in the second semiconductor device ofFIG. 3 . -
FIGS. 5 and 6 are schematic views illustrating first to fourth failure groups set in a semiconductor system according to an embodiment of the present disclosure. -
FIG. 7 is a block diagram illustrating a configuration of a repair control circuit included in the second semiconductor device ofFIG. 3 . -
FIG. 8 is a block diagram illustrating a configuration of a third semiconductor device included in the semiconductor system ofFIG. 1 . -
FIG. 9 is a block diagram illustrating a configuration of an error correction circuit included in the third semiconductor ofFIG. 8 . -
FIG. 10 is a block diagram illustrating a configuration of a memory circuit included in the third semiconductor ofFIG. 8 . -
FIG. 11 is a block diagram illustrating a configuration of an electronic system employing the semiconductor system described with reference toFIGS. 1 to 10 . -
FIG. 12 is a block diagram illustrating a configuration of an electronic system employing the semiconductor system described with reference toFIGS. 1 to 10 . - Various embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.
- Referring to
FIG. 1 , a semiconductor system according to an embodiment may include afirst semiconductor device 1, asecond semiconductor device 2, and athird semiconductor device 3. - The
first semiconductor device 1 may output a test enablement signal TEN, a command CMD, a row address RADD, and a column address CADD. Thefirst semiconductor device 1 may receive or output data DATA<1:64>. Thefirst semiconductor device 1 may change a combination of the row address RADD corresponding to a failure row address F_RADD<1:N> and a combination of the column address CADD corresponding to a failure column address F_CADD<1:N> and may output the row address RADD and the column address CADD with the combination changes. Although the command CMD is illustrated with a single signal line, the command CMD may be set to include a plurality of bits and may be transmitted through signal lines that transmit at least one group of addresses, commands, and data. Although each of the row address RADD and the column address CADD is illustrated with a single signal line, each of the row address RADD and the column address CADD may be set to include a plurality of bits and may be transmitted through signal lines that transmit at least one group of addresses, commands, and data. The data DATA<1:64> may be transmitted through signal lines that transmit at least one group of addresses, commands and data. The number of bits of the data DATA<1:64> may be set to be different according to the embodiments. The test enablement signal TEN may be enabled to perform a test for classifying failure groups of test output data TDOUT<1:64>. - The
second semiconductor device 2 may output a test command TCMD, a test address TADD, a test input data TDIN<1:64>, and an error correction control signal ECC_CON. The test address TADD may be set to include a plurality of bits which are sequentially counted. Thesecond semiconductor device 2 may classify the failure groups of the test output data TDOUT<1:64>. Thesecond semiconductor device 2 may generate the failure row address F_RADD<1:N> and the failure column address F_CADD<1:N> that include position information on the failure groups of the test output data TDOUT<1:64>. The error correction control signal ECC_CON may be enabled to perform an error correction operation for correcting errors of internal data (ID<1:64> ofFIG. 8 ). - The
third semiconductor device 3 may perform the error correction operation of the internal data (ID<1:64> ofFIG. 8 ) selected according to the test address TADD to output the corrected internal data as the test output data TDOUT<1:64>, in response to the test enablement signal TEN and the error correction control signal ECC_CON. Thethird semiconductor device 3 may replace an area in which a failure group of the test output data TDOUT<1:64> is stored according to the row address RADD and the column address CADD generated from the failure row address F_RADD<1:N> and the failure column address F_CADD<1:N> with a redundancy area (arow redundancy area 352 and acolumn redundancy area 353 ofFIG. 10 ). Thethird semiconductor device 3 may receive or output the data DATA<1:64> according to the row address RADD and the column address CADD in response to the command CMD and the error correction control signal ECC_CON. - Referring to
FIG. 2 , thefirst semiconductor device 1 may include afuse circuit 11, acontrol circuit 12, and adata processing circuit 13. - The
fuse circuit 11 may include a plurality of fuses. Thefuse circuit 11 may program the plurality of fuses to generate a programmed row address P_RADD<1:N> and a programmed column address P_CADD<1:N> according to the failure row address F_RADD<1:N> and the failure column address F_CADD<1:N>. Thefuse circuit 11 may be realized using a general fuse array circuit in which a plurality of fuses are arrayed. - The
control circuit 12 may output the command CMD, the row address RADD, the column address CADD, and the test enablement signal TEN. If an area selected by the row address RADD is identical to an area selected by the programmed row address P_RADD<1:N>, thecontrol circuit 12 may change a combination of the row address RADD and may output the row address RADD having the changed combination. If an area selected by the column address CADD is identical to an area selected by the programmed column address P_CADD<1:N>, thecontrol circuit 12 may change a combination of the column address CADD and may output the column address CADD having the changed combination. Thecontrol circuit 12 may interrupt the output of the command CMD, the row address RADD, and the column address CADD if the test enablement signal TEN is enabled. - The
data processing circuit 13 may receive an external data EXD<1:64> to output the data DATA<1:64> during a write operation. Thedata processing circuit 13 may receive the data DATA<1:64> to output the external data EXD<1:64> during a read operation. - Referring to
FIG. 3 , thesecond semiconductor device 2 may include atest control circuit 21, an erroneousdata classification circuit 22, and arepair control circuit 23. - The
test control circuit 21 may output the test command TCMD, the test address TADD, the test input data TDIN<1:64>, and the error correction control signal ECC_CON in response to a test information signal JTAG provided by an external device. Although the test information signal JTAG is illustrated with a single signal line, the test information signal JTAG may be set to include a plurality of bits. The test information signal JTAG may include information for generating the test command TCMD, the test address TADD, the test input data TDIN<1:64>, and the error correction control signal ECC_CON. Although the test command TCMD is illustrated with a single signal line, the test command TCMD may be set to include a plurality of bits. Although the test address TADD is illustrated with a single signal line, the test address TADD may be set to include a plurality of bits. The number of bits of the test input data TDIN<1:64> may be set to be different according to the embodiments. - The erroneous
data classification circuit 22 may classify the failure groups of the test output data TDOUT<1:64>. The erroneousdata classification circuit 22 may generate first to third failure group information signals FCLS1<1:N>, FCLS2<1:N>, and FCLS3<1:N> from the test address TADD including position information on the failure groups of the test output data TDOUT<1:64>. The first failure group information signal FCLS1<1:N> may include the position information on the first failure group having a first priority. The second failure group information signal FCLS2<1:N> may include the position information on the second failure group having a second priority. The third failure group information signal FCLS3<1:N> may include the position information on the third failure group having a third priority. - The
repair control circuit 23 may output the first to third failure group information signals FCLS1<1:N>, FCLS2<1:N>, and FCLS3<1:N> as the failure row address F_RADD<1:N> and the failure column address F_CADD<1:N> in response to a redundancy use information signal RDI. The redundancy use information signal RDI may include information on the availability of the redundancy area (therow redundancy area 352 and thecolumn redundancy area 353 ofFIG. 10 ). The redundancy use information signal RDI may be enabled if the redundancy area (therow redundancy area 352 and thecolumn redundancy area 353 ofFIG. 10 ) has a replaceable area. - Referring to
FIG. 4 , the erroneousdata classification circuit 22 may include acomparison circuit 221, a selectionsignal generation circuit 222, a selection and transmission (selection/transmission)circuit 223, afirst storage circuit 224, and asecond storage circuit 225. - The
comparison circuit 221 may compare logic levels of the test output data TDOUT<1:64> with logic levels of reference data REFD<1:64> to generate a failure comparison signal F_CMP<1:64>. Thecomparison circuit 221 may compare logic levels of the corresponding bits of the test output data TDOUT<1:64> and the reference data REFD<1:64> to generate the failure comparison signal F_CMP<1:64>. For example, thecomparison circuit 221 may generate the failure comparison signal F_CMP<1> which is enabled to have a logic “high” level if a logic level of the test output datum TDOUT<1> is different from a logic level of the reference datum REFD<1>. That is, the failure comparison signal F_CMP<1:64> may be generated to include information on the number of bit pairs having different logic levels among the pairs of the corresponding bits of the test output data TDOUT<1:64> and the reference data REFD<1:64>. The reference data REFD<1:64> may be set to have the same level combination as the test input data TDIN<1:64>. - The selection
signal generation circuit 222 may generate a selection signal SEL in response to the failure comparison signal F_CMP<1:64>. The selectionsignal generation circuit 222 may generate the selection signal SEL which is enabled if any one bit of the failure comparison signal F_CMP<1:64> is enabled. - The selection/
transmission circuit 223 may output the failure comparison signal F_CMP<1:64> as a first failure transmission signal F_TS1<1:64> or a second failure transmission signal F_TS2<1:64> in response to the selection signal SEL. The selection/transmission circuit 223 may output the failure comparison signal F_CMP<1:64> as the first failure transmission signal F_TS1<1:64> if the selection signal SEL is enabled. The selection/transmission circuit 223 may output the failure comparison signal F_CMP<1:64> as the second failure transmission signal F_TS2<1:64> if the selection signal SEL is disabled. - The
first storage circuit 224 may detect the number of bits which are enabled among the bits of the first failure transmission signal F_TS1<1:64>. Thefirst storage circuit 224 may synthesize the test address TADD and the first failure transmission signal F_TS1<1:64> to generate the first to third failure group information signals FCLS1<1:N>, FCLS2<1:N> and FCLS3<1:N> according to the detection result of the number of the bits which are enabled among the bits of the first failure transmission signal F_TS1<1:64>. The first failure group information signal FCLS1<1:N> may include position information of a memory area (351 ofFIG. 10 ) storing the first failure group and position information of erroneous bits of the test output data TDOUT<1:64>. The second failure group information signal FCLS2<1:N> may include position information of the memory area (351 ofFIG. 10 ) storing the second failure group and position information of erroneous bits of the test output data TDOUT<1:64>. The third failure group information signal FCLS3<1:N> may include position information of the memory area (351 ofFIG. 10 ) storing the third failure group and position information of erroneous bits of the test output data TDOUT<1:64>. - The
second storage circuit 225 may synthesize the test address TADD and the second failure transmission signal F_TS2<1:64> to generate a fourth failure group information signal FCLS4<1:N>. The fourth failure group information signal FCLS4<1:N> may include position information of the memory area (351 ofFIG. 10 ) storing the fourth failure group and position information of erroneous bits of the test output data TDOUT<1:64>. - A method of setting the first to fourth failure groups of the test output data TDOUT<1:64> will be described hereinafter with reference to
FIGS. 5 and 6 . - In
FIGS. 5 and 6 , “ECC_OFF” means the internal data (ID<1:64> ofFIG. 8 ) before the error correction operation of the internal data (ID<1:64> ofFIG. 8 ) is performed, and “ECC_ON” means the test output data TDOUT<1:64> generated after the error correction operation of the internal data (ID<1:64> ofFIG. 8 ) is performed. - First, an example in which the first to fourth bits ID<1:4> of the internal data ID<1:64> have erroneous data (i.e., failed data “F”) before the error correction operation will be described with reference to
FIG. 5 . - The first failure group of the test output data TDOUT<1:64> may be set to have failed bits which are not corrected by the error correction operation when the internal data ID<1:64> have at least two failed bits. That is, the first failure group of the test output data TDOUT<1:64> may be set to have the second, third, and fourth bits ID<2:4> of the internal data ID<1:64>.
- The third failure group of the test output data TDOUT<1:64> may be set to have a single bit which is corrected by the error correction operation when the internal data ID<1:64> have at least two failed bits. That is, the third failure group of the test output data TDOUT<1:64> may be set to have the first bit ID<1> of the internal data ID<1:64>.
- The fourth failure group of the test output data TDOUT<1:64> may be set to have a failed bit whose logic level is inverted by the error correction operation when the internal data ID<1:64> have at least two failed bits. That is, the fourth failure group of the test output data TDOUT<1:64> may be set to have the last bit, for example, the sixty fourth bit ID<64> of the internal data ID<1:64>.
- Next, an example in which the first bit ID<1> of the internal data ID<1:64> has an erroneous datum (i.e., a failed datum “F”) before the error correction operation will be described with reference to
FIG. 6 . - The second failure group of the test output data TDOUT<1:64> may be set to have a single bit which is corrected by the error correction operation when the internal data ID<1:64> have a single failed bit. Accordingly, the second failure group of the test output data TDOUT<1:64> may be set to have the first bit ID<1> of the internal data ID<1:64>.
- Referring to
FIG. 7 , therepair control circuit 23 may include a flagsignal generation circuit 231 and a failureaddress generation circuit 232. - The flag
signal generation circuit 231 may generate a flag signal RFLAG which is enabled in response to the redundancy use information signal RDI. The flagsignal generation circuit 231 may generate the flag signal RFLAG which is enabled in response to the redundancy use information signal RDI if the redundancy area (therow redundancy area 352 and thecolumn redundancy area 353 ofFIG. 10 ) has a replaceable area. - The failure
address generation circuit 232 may output the first to third failure group information signals FCLS1<1:N>, FCLS2<1:N>, and FCLS3<1:N> as the failure row address F_RADD<1:N> and the failure column address F_CADD<1:N> in response to the flag signal RFLAG. The failureaddress generation circuit 232 may generate the failure row address F_RADD<1:N> and the failure column address F_CADD<1:N> from the first failure group information signal FCLS1<1:N> if the flag signal RFLAG is enabled. The failureaddress generation circuit 232 may generate the failure row address F_RADD<1:N> and the failure column address F_CADD<1:N> from the second failure group information signal FCLS2<1:N> if the flag signal RFLAG is enabled. The failureaddress generation circuit 232 may generate the failure roar address F_RADD<1:N> and the failure column address F_CADD<1:N> from the third failure group information signal FCLS3<1:N> if the flag signal RFLAG is enabled. - Referring to
FIG. 8 , thethird semiconductor device 3 may include an input and output (input/output) (I/O)circuit 31, an internalcommand generation circuit 32, an enablementsignal generation circuit 33, anerror correction circuit 34, and amemory circuit 35. - The I/
O circuit 31 may include aninput buffer 311 and anoutput buffer 312. - The
input buffer 311 may output the test input data TDIN<1:64> or the data DATA<1:64> as input data DIN<1:64> in response to the test enablement signal TEN. Theinput buffer 311 may output the test input data TDIN<1:64> as the input data DIN<1:64> if the test enablement signal TEN is enabled. Theinput buffer 311 may drive the input data DIN<1:64> in response to the test input data TDIN<1:64> if the test enablement signal TEN is enabled. Theinput buffer 311 may output the data DATA<1:64> as the input data DIN<1:64> if the test enablement signal TEN is disabled. Theinput buffer 311 may drive the input data DIN<1:64> in response to the data DATA<1:64> if the test enablement signal TEN is disabled. - The
output buffer 312 may transmit output data DOUT<1:64> as the test output data TDOUT<1:64> or the data DATA<1:64> in response to the test enablement signal TEN. Theoutput buffer 312 may output the output data DOUT<1:64> as the test output data TDOUT<1:64> if the test enablement signal TEN is enabled. Theoutput buffer 312 may drive the test output data TDOUT<1:64> in response to the output data DOUT<1:64> if the test enablement signal TEN is enabled. Theoutput buffer 312 may output the output data DOUT<1:64> as the data DATA<1:64> if the test enablement signal TEN is disabled. Theoutput buffer 312 may drive the data DATA<1:64> in response to the output data DOUT<1:64> if the test enablement signal TEN is disabled. - The internal
command generation circuit 32 may decode the test command TCMD or the command CMD to generate an internal command ICMD, in response to the test enablement signal TEN. The internalcommand generation circuit 32 may decode the test command TCMD to generate the internal command ICMD if the test enablement signal TEN is enabled. The internalcommand generation circuit 32 may decode the command CMD to generate the internal command ICMD if the test enablement signal TEN is disabled. The internal command ICMD may be a command for controlling an internal operation (e.g., a write operation or a read operation) of thethird semiconductor device 3. - The enablement
signal generation circuit 33 may generate an enablement signal EN which is enabled in response to the internal command ICMD if a failure detection signal F_DET is enabled. The enablementsignal generation circuit 33 may generate the enablement signal EN which is disabled in response to the internal command ICMD if the failure detection signal F_DET is disabled. - The
error correction circuit 34 may generate an internal codeword ICDW including error information on the input data DIN<1:64>, may detect erroneous data of the internal data ID<1:64> to generate the failure detection signal F_DET, and may perform the error correction operation of the internal data ID<1:64> to generate the output data DOUT<1:64> according to the error correction control signal ECC_CON. Theerror correction circuit 34 may generate the internal codeword ICDW including error information on the input data DIN<1:64> during the write operation. Theerror correction circuit 34 may detect erroneous data of the internal data ID<1:64> to generate the failure detection signal F_DET during the read operation. Theerror correction circuit 34 may perform the error correction operation of the internal data ID<1:64> to generate the output data DOUT<1:64> during the read operation. - The
memory circuit 35 may store the input data DIN<1:64>as the internal data ID<1:64> according to the test address TADD or the row and column addresses RADD and CADD during the write operation. Thememory circuit 35 may store the input data DIN<1:64> corresponding to the internal data ID<1:64> into the memory area (351 ofFIG. 10 ) thereof according to the test address TADD which is sequentially counted, during a write operation for test. Thememory circuit 35 may store the internal codeword ICDW during the write operation for test. Thememory circuit 35 may store the input data DIN<1:64> as the internal data ID<1:64> according to the row and column addresses RADD and CADD during a normal write operation. Thememory circuit 35 may store the internal codeword ICDW during the normal write operation. Thememory circuit 35 may output the internal data ID<1:64> stored therein according to the test address TADD or the row and column addresses RADD and CADD during the read operation. Thememory circuit 35 may output the internal data ID<1:64> stored in the memory area (351 ofFIG. 10 ) according to the test address TADD which is sequentially counted during a read operation for test. Thememory circuit 35 may output the internal data ID<1:64> stored in the memory area (351 ofFIG. 10 ) according to the row and column addresses RADD and CADD during a normal read operation. Thememory circuit 35 may be realized to include both of an area for storing the input data DIN<1:64> and an area for storing the internal codeword ICDW. - Referring to
FIG. 9 , theerror correction circuit 34 may include acodeword generation circuit 341, a comparisoncode generation circuit 342, asyndrome generation circuit 343, and adata correction circuit 344. - The
codeword generation circuit 341 may generate the internal codeword ICDW including error information on the input data DIN<1:64>, Thecodeword generation circuit 341 may generate the internal codeword ICDW including error information on the input data DIN<1:64> during the write operation. - The comparison
code generation circuit 342 may generate a comparison code CPCD including error information on the internal data ID<1:64>. The comparisoncode generation circuit 342 may generate the comparison code CPCD including error information on the internal data ID<1:64> during the read operation. - The
syndrome generation circuit 343 may compare the internal codeword ICDW with the comparison code CPCD to generate a syndrome signal SYN and may generate the failure detection signal F_DET which is enabled if the syndrome signal SYN is generated. Thesyndrome generation circuit 343 may compare the internal codeword ICDW with the comparison code CPCD to generate the syndrome signal SYN during the read operation and may generate the failure detection signal F_DET which is enabled if the syndrome signal SYN is generated. The syndrome signal SYN may include position information of erroneous bits (i.e., failed bits) among the bits included in the internal data ID<1:64>. - The
data correction circuit 344 may correct erroneous data of the internal data ID<1:64> to output the corrected internal data as the output data DOUT<1:64> according to the syndrome signal SYN, in response to the error correction control signal ECC_CON. Thedata correction circuit 344 may correct erroneous data of the internal data ID<1:64> to output the corrected internal data as the output data DOUT<1:64> according to the syndrome signal SYN, in response to the error correction control signal ECC_CON during the read operation. Thedata correction circuit 344 may correct erroneous data of the internal data ID<1:64> to output the corrected internal data as the output data DOUT<1:64> according to the syndrome signal SYN, if the error correction control signal ECC_CON is enabled during the read operation. Thedata correction circuit 344 may output the internal data ID<1:64> as the output data DOUT<1:64> without correcting erroneous data of the internal data ID<1:64>, in response to the error correction control signal ECC_CON. Thedata correction circuit 344 may output the internal data ID<1:64> as the output data DOUT<1:64> without correcting erroneous data of the internal data ID<1:64>, in response to the error correction control signal ECC_CON during the read operation. Thedata correction circuit 344 may output the internal data ID<1:64> as the output data DOUT<1:64> without correcting erroneous data of the internal data ID<1:64>, if the error correction control signal ECC_CON is disabled during the read operation. - The
error correction circuit 34 described above may include in part a general error correction code (ECC) circuit using an error detection code (EDC) and an error correction code (ECC). - Referring to
FIG. 10 , thememory circuit 35 may include thememory area 351, therow redundancy area 352, and thecolumn redundancy area 353. - The
memory area 351 may store the input data DIN<1:64> into an area selected by the test address TADD sequentially counted and may output the stored input data DIN<1:64> as the internal data ID<1:64>. Thememory area 351 may store the input data DIN<1:64> into an area selected by the row and column addresses RADD and CADD and may output the stored input data DIN<1:64> as the internal data ID<1:64>. Thememory area 351 may store the input data DIN<1:64> into an area selected by the test address TADD during the write operation for test. Thememory area 351 may store the internal codeword ICDW during the write operation for test. Thememory area 351 may output the input data DIN<1:64> stored in an area selected by the test address TADD as the internal data ID<1:64> during the read operation for test. Thememory area 351 may store the input data DIN<1:64> into an area selected by the row and column addresses RADD and CADD during the normal write operation. Thememory area 351 may store the internal codeword ICDW during the normal write operation. Thememory area 351 may output the input data DIN<1:64> stored in an area selected by the row and column addresses RADD and CADD as the internal data ID<1:64> during the normal read operation. - The
row redundancy area 352 may replace thememory area 351 having the failure group according to the row address RADD to store the input data DIN<1:64> into therow redundancy area 352 and may output the stored input data DIN<1:64> as the internal data ID<1:64>. Therow redundancy area 352 may replace thememory area 351 having the failure group according to the row address RADD to store the input data DIN<1:64> into therow redundancy area 352 during the write operation. Therow redundancy area 352 may output the stored input data DIN<1:64> as the internal data ID<1:64> according to the row address RADD during the read operation. - The
column redundancy area 353 may replace thememory area 351 having the failure group according to the column address CADD to store the input data DIN<1:64> into thecolumn redundancy area 353 and may output the stored input data DIN<1:64> as the internal data ID<1:64>. Thecolumn redundancy area 353 may replace thememory area 351 having the failure group according to the column address CADD to store the input data DIN<1:64> into thecolumn redundancy area 353 during the write operation. Thecolumn redundancy area 353 may output the stored input data DIN<1:64> as the internal data ID<1:64> according to the column address CADD during the read operation. - An operation of replacing the
memory area 351 in which the first to third failure groups of the test output data TDOUT<1:64> are stored with therow redundancy area 352 and thecolumn redundancy area 353 will be described hereinafter with reference toFIG. 10 . - If a row address RADD<1:N> for selecting a first row area R1 including first failure groups (indicated by a symbol “×”) is inputted to the
memory circuit 35, the first row area R1 of thememory area 351 may be replaced with therow redundancy area 352 to store the input data DIN<1:64> into therow redundancy area 352 and the input data DIN<1:64> stored in therow redundancy area 352 may be outputted as the internal data ID<1:64>. - If the row address RADD<1:N> for selecting a second row area R2 including second failure groups (indicated by a symbol “Δ”) is inputted to the
memory circuit 35, the second row area R2 of thememory area 351 may be replaced with therow redundancy area 352 to store the input data DIN<1:64> into therow redundancy area 352 and the input data DIN<1:64> stored in therow redundancy area 352 may be outputted as the internal data ID<1:64>. - If a column address CADD<1:N> for selecting a first column area Cl including the second failure groups (indicated by the symbol “Δ”) is inputted to the
memory circuit 35, the first column area C1 of thememory area 351 may be replaced with thecolumn redundancy area 353 to store the input data DIN<1:64> into thecolumn redundancy area 353 and the input data DIN<1:64> stored in thecolumn redundancy area 353 may be outputted as the internal data ID<1:64>. - If the column address CADD<1:N> for selecting a second column area C2 and a third column area C3 including the first failure groups (indicated by the symbol “×”) is inputted to the
memory circuit 35, the second and third column areas C2 and C3 may be replaced with thecolumn redundancy area 353 to store the input data DIN<1:64> into thecolumn redundancy area 353 and the input data DIN<1:64> stored in thecolumn redundancy area 353 may be outputted as the internal data ID<1:64>. - If the column address CADD<1:N> for selecting a fourth column area C4 including third failure groups (indicated by a symbol “⋄”) is inputted to the
memory circuit 35, the fourth column area C4 may be replaced with thecolumn redundancy area 353 to store the input data DIN<1:64> into thecolumn redundancy area 353 and the input data DIN<1:64> stored in thecolumn redundancy area 353 may be outputted as the internal data ID<1:64>. - The
memory area 351 in which the first failure groups (indicated by the symbol “×”) are stored may be replaced with therow redundancy area 352 and thecolumn redundancy area 353 by the first priority, thememory area 351 in which the second failure groups (indicated by the symbol “Δ”) are stored may be replaced with therow redundancy area 352 and thecolumn redundancy area 353 by the second priority, and thememory area 351 in which the third failure groups (indicated by the symbol “⋄”) are stored may be replaced with therow redundancy area 352 and thecolumn redundancy area 353 by the third priority. - If entire portions of the
row redundancy area 352 and thecolumn redundancy area 353 are used to replace defective portions (i.e., the failure groups) of thememory area 351 so that no replaceable redundancy area remains in therow redundancy area 352 and thecolumn redundancy area 353, an area “A” including the third failure groups (indicated by the symbol “⋄”) may not be replaced with any of therow redundancy area 352 and thecolumn redundancy area 353. In addition, if entire portions of therow redundancy area 352 and thecolumn redundancy area 353 are used to replace defective portions (i.e., the failure groups) of thememory area 351 so that no replaceable redundancy area remains in therow redundancy area 352 and thecolumn redundancy area 353, an area “B” including the second failure group (indicated by the symbol “L”) may not be replaced with any of therow redundancy area 352 and thecolumn redundancy area 353. - As described above, a semiconductor system according to an embodiment may classify failure groups of data including erroneous bits and may replace a memory area in which the failure groups are stored with a redundancy area according to priorities of the failure groups. As a result, the fabrication yield of the semiconductor systems may be improved.
- The semiconductor devices or the semiconductor system described with reference to
FIGS. 1 to 10 may be applied to an electronic system that includes a memory system, a graphic system, a computing system, a mobile system, or the like. For example, as illustrated inFIG. 11 , anelectronic system 1000 according an embodiment may include adata storage circuit 1001, amemory controller 1002, abuffer memory 1003, and an input/output (I/O)interface 1004. - The
data storage circuit 1001 may store data which are outputted from thememory controller 1002 or may read and output the stored data to thememory controller 1002, according to a control signal generated from thememory controller 1002. Thedata storage circuit 1001 may include thethird semiconductor device 3 illustrated inFIG. 1 . Meanwhile, thedata storage circuit 1001 may include a nonvolatile memory that can retain their stored data even when its power supply is interrupted. The nonvolatile memory may be a flash memory such as a NOR-type flash memory or a NAND-type flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), or the like. - The
memory controller 1002 may receive a command outputted from an external device (e.g., a host device) through the I/O interface 1004 and may decode the command outputted from the host device to control an operation for inputting data into thedata storage circuit 1001 or thebuffer memory 1003 or for outputting the data stored in thedata storage circuit 1001 or thebuffer memory 1003. Thememory controller 1002 may include the first andsecond semiconductor devices FIG. 1 . AlthoughFIG. 11 illustrates thememory controller 1002 with a single block, thememory controller 1002 may include one controller for controlling thedata storage circuit 1001 comprised of a nonvolatile memory and another controller for controlling thebuffer memory 1003 comprised of a volatile memory. - The
buffer memory 1003 may temporarily store the data which are processed by thememory controller 1002. That is, thebuffer memory 1003 may temporarily store the data which are outputted from or to be inputted to thedata storage circuit 1001. Thebuffer memory 1003 may store the data, which are outputted from thememory controller 1002, according to a control signal. Thebuffer memory 1003 may read and output the stored data to thememory controller 1002. Thebuffer memory 1003 may include a volatile memory such as a dynamic random access memory (DRAM), a mobile DRAM, or a static random access memory (SRAM). - The I/
O interface 1004 may physically and electrically connect thememory controller 1002 to the external device (i.e., the host). Thus, thememory controller 1002 may receive control signals and data supplied from the external device (i.e., the host) through the I/O interface 1004 and may output the data generated from thememory controller 1002 to the external device (i.e., the host) through the I/O interface 1004. That is, theelectronic system 1000 may communicate with the host through the I/O interface 1004. The I/O interface 1004 may include any one of various interface protocols such as a universal serial bus (USB) drive, a multi-media card (MMC), a peripheral component interconnect-express (PCI-E), a serial attached SCSI (SAS), a serial AT attachment (SATA), a parallel AT attachment (PATA), a small computer system interface (SCSI), an enhanced small device interface (ESDI) and an integrated drive electronics (IDE). - The
electronic system 1000 may be used as an auxiliary storage device of the host or an external storage device. Theelectronic system 1000 may include a solid state disk (SSD), a USB drive, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multi-media card (MMC), an embedded multi-media card (eMMC), a compact flash (CF) card, or the like. - Referring to
FIG. 12 , anelectronic system 2000 according an embodiment may include ahost 2001, amemory controller 2002, and adata storage circuit 2003. - The
host 2001 may output a request signal and data to thememory controller 2002 to access to thedata storage circuit 2003. Thememory controller 2002 may supply the data, a data strobe signal, a command, addresses, and a clock signal to thedata storage circuit 2003 in response to the request signal, and thedata storage circuit 2003 may execute a write operation or a read operation in response to the command. Thehost 2001 may transmit the data to thememory controller 2002 to store the data into thedata storage circuit 2003. In addition, thehost 2001 may receive the data outputted from thedata storage circuit 2003 through thememory controller 2002. Thehost 2001 may include a circuit that corrects errors of the data using an error correction code (ECC) scheme. - The
memory controller 2002 may act as an interface that connects thehost 2001 to thedata storage circuit 2003 for communication between thehost 2001 and thedata storage circuit 2003. Thememory controller 2002 may receive the request signal and the data outputted from thehost 2001 and may generate and supply the data, the data strobe signal, the command, the addresses and the clock signal to thedata storage circuit 2003 in order to control operations of thedata storage circuit 2003. In addition, thememory controller 2002 may supply the data outputted from thedata storage circuit 2003 to thehost 2001. Thememory controller 2002 may include the first andsecond semiconductor devices FIG. 1 . - The
data storage circuit 2003 may include a plurality of memories. Thedata storage circuit 2003 may receive the data, the data strobe signal, the command, the addresses, and the clock signal from thememory controller 2002 to execute the write operation or the read operation. Each of the memories included in thedata storage circuit 2003 may include a circuit that corrects the errors of the data using an error correction code (ECC) scheme. Thedata storage circuit 2003 may include thethird semiconductor device 3 illustrated inFIG. 1 . - In some embodiments, the
electronic system 2000 may be realized to selectively operate any one of the ECC circuits included in thehost 2001 and thedata storage circuit 2003. Alternatively, theelectronic system 2000 may be realized to simultaneously operate all of the ECC circuits included in thehost 2001 and thedata storage circuit 2003. Thehost 2001 and thememory controller 2002 may be realized in a single chip according to the embodiments. Thememory controller 2002 and thedata storage circuit 2003 may be realized in a single chip according to the embodiments.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/370,439 US20190228834A1 (en) | 2017-06-08 | 2019-03-29 | Semiconductor systems |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170071601A KR20180134120A (en) | 2017-06-08 | 2017-06-08 | Semiconductor system |
KR10-2017-0071601 | 2017-06-08 | ||
US15/819,411 US10290361B2 (en) | 2017-06-08 | 2017-11-21 | Semiconductor systems |
US16/370,439 US20190228834A1 (en) | 2017-06-08 | 2019-03-29 | Semiconductor systems |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/819,411 Division US10290361B2 (en) | 2017-06-08 | 2017-11-21 | Semiconductor systems |
Publications (1)
Publication Number | Publication Date |
---|---|
US20190228834A1 true US20190228834A1 (en) | 2019-07-25 |
Family
ID=64562687
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/819,411 Active US10290361B2 (en) | 2017-06-08 | 2017-11-21 | Semiconductor systems |
US16/370,327 Active US10811116B2 (en) | 2017-06-08 | 2019-03-29 | Semiconductor systems |
US16/370,439 Abandoned US20190228834A1 (en) | 2017-06-08 | 2019-03-29 | Semiconductor systems |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/819,411 Active US10290361B2 (en) | 2017-06-08 | 2017-11-21 | Semiconductor systems |
US16/370,327 Active US10811116B2 (en) | 2017-06-08 | 2019-03-29 | Semiconductor systems |
Country Status (2)
Country | Link |
---|---|
US (3) | US10290361B2 (en) |
KR (1) | KR20180134120A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10825543B2 (en) * | 2018-07-25 | 2020-11-03 | International Business Machines Corporation | Locating failures in memory with redundancy |
KR20210113841A (en) * | 2020-03-09 | 2021-09-17 | 에스케이하이닉스 주식회사 | Repair circuit and memory device including the same |
TWI794967B (en) * | 2021-09-10 | 2023-03-01 | 臺灣發展軟體科技股份有限公司 | Data processing circuit and fault repair method |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4493075A (en) * | 1982-05-17 | 1985-01-08 | National Semiconductor Corporation | Self repairing bulk memory |
JPH1074396A (en) * | 1996-08-30 | 1998-03-17 | Nec Corp | Semiconductor storage device |
KR100354437B1 (en) * | 2000-01-28 | 2002-09-28 | 삼성전자 주식회사 | An integrated circuit semiconductor device having built-in self-repair circuit for embedded memory and a method for repairing the memory |
US7237172B2 (en) * | 2002-12-24 | 2007-06-26 | Micron Technology, Inc. | Error detection and correction in a CAM |
JP3930446B2 (en) * | 2003-03-13 | 2007-06-13 | 株式会社東芝 | Semiconductor device |
US7187602B2 (en) | 2003-06-13 | 2007-03-06 | Infineon Technologies Aktiengesellschaft | Reducing memory failures in integrated circuits |
DE102004027423A1 (en) * | 2004-06-04 | 2006-07-20 | Infineon Technologies Ag | Memory circuit with redundant memory areas |
KR20130048999A (en) * | 2011-11-03 | 2013-05-13 | 삼성전자주식회사 | Semiconductor test device and address scramble generating method thereof |
KR101862379B1 (en) | 2013-04-19 | 2018-07-05 | 삼성전자주식회사 | Memory device with error correction code and redundancy repair operations |
US20150255176A1 (en) * | 2014-03-10 | 2015-09-10 | Advantest Corporation | Memory test ecc auto-correction of failing data |
KR102189780B1 (en) * | 2014-08-11 | 2020-12-11 | 삼성전자주식회사 | Semiconductor memory device and memory system including the same |
KR20160125745A (en) * | 2015-04-22 | 2016-11-01 | 에스케이하이닉스 주식회사 | Semiconductor device |
US10204700B1 (en) * | 2016-09-21 | 2019-02-12 | Samsung Electronics Co., Ltd. | Memory systems and methods of operating semiconductor memory devices |
US10389379B2 (en) * | 2017-05-12 | 2019-08-20 | Qualcomm Incorporated | Error correcting code testing |
-
2017
- 2017-06-08 KR KR1020170071601A patent/KR20180134120A/en unknown
- 2017-11-21 US US15/819,411 patent/US10290361B2/en active Active
-
2019
- 2019-03-29 US US16/370,327 patent/US10811116B2/en active Active
- 2019-03-29 US US16/370,439 patent/US20190228834A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US10290361B2 (en) | 2019-05-14 |
US10811116B2 (en) | 2020-10-20 |
US20190228833A1 (en) | 2019-07-25 |
US20180358108A1 (en) | 2018-12-13 |
KR20180134120A (en) | 2018-12-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10847243B2 (en) | Methods of testing cell arrays and semiconductor devices executing the same | |
US10572341B2 (en) | Semiconductor devices | |
KR20180019791A (en) | Semiconductor device and semiconductor system | |
US10162703B2 (en) | Methods of correcting data errors and semiconductor devices used therein | |
US10579472B2 (en) | Semiconductor devices | |
US10811116B2 (en) | Semiconductor systems | |
US11456021B2 (en) | Methods, semiconductor devices, and semiconductor systems | |
US10013305B2 (en) | Semiconductor devices and methods relating to the repairing of the same | |
US10153028B2 (en) | Semiconductor devices | |
US20180018219A1 (en) | Semiconductor devices and semiconductor systems | |
US10261860B2 (en) | Semiconductor systems | |
US20170344422A1 (en) | Semiconductor devices and semiconductor systems | |
US10460826B2 (en) | Test methods of semiconductor devices and semiconductor systems used therein | |
US10552277B2 (en) | Electronic devices | |
US10635517B2 (en) | Semiconductor devices comparing error codes and semiconductor systems including the same | |
US10379786B2 (en) | Semiconductor devices | |
US11429477B2 (en) | Semiconductor devices | |
US10360105B2 (en) | Semiconductor devices and semiconductor systems including the same | |
US20210263815A1 (en) | Semiconductor devices and semiconductor systems | |
US10621039B2 (en) | Electronic devices | |
US10014073B2 (en) | Semiconductor devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SK HYNIX INC., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, WOONGRAE;LEE, SANGKWON;REEL/FRAME:048745/0331 Effective date: 20190318 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |