US20190221571A1 - Semiconductor memory device and manufacturing method thereof - Google Patents

Semiconductor memory device and manufacturing method thereof Download PDF

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US20190221571A1
US20190221571A1 US15/885,729 US201815885729A US2019221571A1 US 20190221571 A1 US20190221571 A1 US 20190221571A1 US 201815885729 A US201815885729 A US 201815885729A US 2019221571 A1 US2019221571 A1 US 2019221571A1
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conductive layer
layer
silicon
memory device
disposed
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US10340278B1 (en
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Wei-Hsin Liu
Cheng-Hsu Huang
Jui-Min Lee
Yi-Wei Chen
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
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    • H10B12/50—Peripheral circuit region structures
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Definitions

  • the present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a semiconductor memory device including a patterned conductive structure and a manufacturing method thereof.
  • DRAM Dynamic random access memory
  • MOS metal oxide semiconductor
  • the MOS transistors in the memory cells may have different structural design because of the product specification and/or the memory cell density requirements. Therefore, the structure of the MOS transistor in the memory cell may be different from that of transistors on other regions within the same chip, and the manufacturing process will become more complicated. Accordingly, it is very important for the related field to effectively integrate the manufacturing process of the memory cell and the manufacturing process of the devices in other regions.
  • a semiconductor memory device and a manufacturing method thereof are provided in the present invention.
  • An interface layer is inserted into a silicon conductive layer in a patterned conductive structure, and the interface layer may be used to block boron penetration effects and prevent the silicon conductive layer from reacting with other material layers too seriously and forming defects.
  • the manufacturing yield may be enhanced accordingly.
  • a semiconductor memory device includes a semiconductor substrate and a patterned conductive structure.
  • the patterned conductive structure is disposed on the semiconductor substrate.
  • the patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer.
  • the second silicon conductive layer is disposed on the first silicon conductive layer.
  • the interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen.
  • the barrier layer is disposed on the second silicon conductive layer.
  • the metal conductive layer is disposed on the barrier layer.
  • a manufacturing method of a semiconductor memory device includes the following steps.
  • a semiconductor substrate is provided, and a patterned conductive structure is formed on the semiconductor substrate.
  • the patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer.
  • the second silicon conductive layer is disposed on the first silicon conductive layer.
  • the interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen.
  • the barrier layer is disposed on the second silicon conductive layer.
  • the metal conductive layer is disposed on the barrier layer.
  • FIG. 1 is a schematic drawing illustrating a semiconductor memory device according to a first embodiment of the present invention.
  • FIG. 2 is a top view schematic drawing illustrating the semiconductor memory device according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional diagram taken along a line B-B′ in FIG. 2 .
  • FIGS. 4-8 are schematic drawings illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present invention, wherein
  • FIG. 5 is a schematic drawing in a step subsequent to FIG. 4 .
  • FIG. 6 is a schematic drawing in a step subsequent to FIG. 5 .
  • FIG. 7 is a schematic drawing in a step subsequent to FIG. 6 .
  • FIG. 8 is a schematic drawing in a step subsequent to FIG. 7 .
  • FIG. 9 is a schematic drawing illustrating a manufacturing method of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 1 is a schematic drawing illustrating a semiconductor memory device according to a first embodiment of the present invention.
  • FIG. 2 is a top view schematic drawing illustrating the semiconductor memory device according to the first embodiment of the present invention.
  • the left part of FIG. 1 may be regarded as a cross-sectional diagram taken along a line A-A′ in FIG. 2
  • FIG. 3 is a cross-sectional diagram taken along a line B-B′ in FIG. 2 .
  • a semiconductor memory device 100 is provided in this embodiment.
  • the semiconductor memory device 100 includes a semiconductor substrate 10 and a patterned conductive structure 40 .
  • the patterned conductive structure 40 is disposed on the semiconductor substrate 10 .
  • the patterned conductive structure 40 includes a first silicon conductive layer 41 A, a second silicon conductive layer 41 B, an interface layer 42 , a barrier layer 45 , and a metal conductive layer 47 .
  • the second silicon conductive layer 41 B is disposed on the first silicon conductive layer 41 A.
  • the interface layer 42 is disposed between the first silicon conductive layer 41 A and the second silicon conductive layer 41 B, and the interface layer 42 includes oxygen.
  • the barrier layer 45 is disposed on the second silicon conductive layer 41 B.
  • the metal conductive layer 47 is disposed on the barrier layer 45 .
  • the semiconductor substrate 10 may include a silicon substrate, an epitaxial substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto.
  • a memory cell region R 1 and a peripheral region R 2 may be defined on the semiconductor substrate 10 , and the patterned conductive structure 40 may be disposed on the memory cell region R 1 and the peripheral region R 2 , but not limited thereto.
  • the patterned conductive structure 40 may be disposed on the memory cell region R 1 only, disposed on the peripheral region R 2 only, or be disposed on other regions of the semiconductor substrate 10 only.
  • the patterned conductive structure 40 disposed on the memory cell region R 1 may include a bit line structure BL
  • the patterned conductive structure 40 disposed on the peripheral region R 2 may include a gate structure 40 G.
  • at least a part of the patterned conductive structure 40 disposed on the memory cell region R 1 may be used as a bit line structure BL of a memory cell
  • at least a part of the patterned conductive structure 40 disposed on the peripheral region R 2 may be used as a gate structure 40 G of a transistor on the peripheral region R 2
  • the structure of the bit line structure BL may be similar to the structure of the gate structure 40 G because the bit line structure BL and the gate structure 40 G are formed by the patterned conductive structure 40 .
  • the semiconductor memory device 100 may include a plurality of the bit line structures BL.
  • Each of the bit line structures BL may be elongated in a first direction D 1
  • the bit line structures BL may be disposed repeatedly in a second direction D 2
  • the second direction D 2 may be substantially orthogonal to the first direction D 1 , but not limited thereto.
  • the material of the first silicon conductive layer 41 A and the second silicon conductive layer 41 B may include polysilicon, amorphous silicon, or other non-metal conductive materials containing silicon
  • the interface layer 42 may include silicon oxide, silicon oxynitride, or other interface materials containing oxygen and silicon.
  • the material of the first silicon conductive layer 41 A may be identical to or different from the material of the second silicon conductive layer 41 B.
  • the barrier layer 45 may include titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), or other appropriate barrier materials.
  • the metal conductive layer 47 may include aluminum, tungsten, copper, titanium aluminide, or other suitable metal conductive materials with low electrical resistivity.
  • a first silicide layer 44 may be formed between the second silicon conductive layer 41 B and the barrier layer 45
  • a second silicide layer 46 may be formed between the barrier layer 45 and the metal conductive layer 47 , but not limited thereto.
  • the first silicide layer 44 may include silicide of the material in the barrier layer 46 , such as titanium silicide (TiSi), and the second silicide layer 46 may include silicide of the material in the metal conductive layer 47 , such as tungsten silicide (WSi), but not limited thereto.
  • TiSi titanium silicide
  • WSi tungsten silicide
  • the interface layer 42 located between the first silicon conductive layer 41 A and the second silicon conductive layer 41 B in a thickness direction of the semiconductor substrate 10 may be used to block the dopants in the second silicon conductive layer 41 B from penetrating downwards (such as the boron penetration effect), and the electrical performance of the semiconductor memory device 100 may be enhanced accordingly. Additionally, the interface layer 42 may also be used to block the material in the barrier layer 45 (such as titanium) from diffusing downwards and reacting with silicon for forming silicide or generating defects, and the manufacturing yield may be improved accordingly. Therefore, the interface layer 42 may be remarkably thinner than the first silicon conductive layer 41 A and the second silicon conductive layer 41 B.
  • the thickness of the interface layer 42 may be less than or equal to 50 angstroms ( ⁇ ), and the total thickness of the first silicon conductive layer 41 A and the second silicon conductive layer 41 B may be about 300 angstroms, but not limited thereto.
  • the location of the interface layer 42 may be modified to be relatively lower, and the thickness of the first silicon conductive layer 41 A may be smaller than the thickness of the second silicon conductive layer 41 B.
  • the location of the interface layer 42 may be modified to be relatively higher, and the thickness of the first silicon conductive layer 41 A may be greater than the thickness of the second silicon conductive layer 41 B.
  • the ratio of the thickness of the first silicon conductive layer 41 A to the thickness of the second silicon conductive layer 41 B may be modified for forming the interface layer 42 at the required position according to different requirements.
  • a first trench isolation 11 may be formed in the semiconductor substrate 10 for defining a plurality of first active regions 12 .
  • a second trench isolation 13 may be formed in the semiconductor substrate 10 for defining a second active region 14 .
  • the first trench isolation 11 and the second trench isolation 13 may respectively include a single layer or multiple layers of insulation material, such as silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), or other suitable insulation materials.
  • word line structures WL may be formed in the semiconductor substrate 10 , and the word line structures WL may be buried word lines, but not limited thereto.
  • Each of the word line structures WL may be elongated in the second direction D 2 , and each of the word line structures WL may include a word line dielectric layer 21 , a word line 22 , and a word line cap layer 23 , but not limited thereto.
  • Trenches may be formed in the semiconductor substrate 10 , and the word line dielectric layer 21 , the word line 22 , and the word line cap layer 23 mentioned above may be sequentially formed in the trench, but not limited thereto.
  • the other types of word line structures may also be applied according to other considerations.
  • the word line dielectric layer 21 may include silicon oxide or other suitable dielectric materials
  • the word line 22 may include aluminum, tungsten, copper, titanium aluminide (TiAl), or other suitable conductive materials
  • the word line cap layer 23 may include silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulation materials.
  • Mask layers such as a first mask layer 31 , a second mask layer 32 , and a third mask layer 33 may be disposed on the word line structures WL.
  • the first mask layer 31 , the second mask layer 32 , and the third mask layer 33 may be an interface layer composed of an oxide-nitride-oxide (ONO) structure, but not limited thereto.
  • the first mask layer 31 may be a silicon oxide layer
  • the second mask layer 32 may be a silicon nitride layer
  • the third mask layer 33 may be a silicon oxide layer, but not limited thereto.
  • the semiconductor memory device 100 may further include a bit line contact structure 43 disposed on the memory cell region R 1 , and the bit line contact structure 43 may be disposed between the barrier layer 45 and the semiconductor substrate 10 in the third direction D 3 .
  • the bit line structure BL may be electrically connected with the corresponding first active region 12 via the bit line contact structure 43
  • the bit line contact structure 43 may include a metal conductive material or a non-metal conductive material, such as polysilicon, amorphous silicon, or other non-metal conductive material containing silicon, but not limited thereto. As shown in FIG.
  • the bit line contact structure 43 may penetrate the first silicon conductive layer 41 A, the interface layer 42 , and the second silicon conductive layer 41 B, and the bit line contact structure 43 may directly contact the first silicon conductive layer 41 A, the interface layer 42 , and the second silicon conductive layer 41 B, but not limited thereto. Additionally, at least a part of the bit line contact structure 43 may be disposed in a contact hole CH penetrating the first silicon conductive layer 41 A, the interface layer 42 , and the second silicon conductive layer 41 B.
  • Spacers such as a first spacer 51 and a second spacer 52 may be formed on sidewalls of the bit line structure BL, and at least a part of the spacer, such as the first spacer 51 , may be partially disposed in the contact hole CH.
  • the semiconductor memory device 100 may further include an isolation structure 70 disposed on the semiconductor substrate 10 , and storage node contacts 80 may be formed in openings of the isolation structure 70 and electrically connected with the corresponding first active regions 12 .
  • the isolation structure 70 may include silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulation materials
  • the storage node contacts 80 may include amorphous silicon, polysilicon, or other conductive materials including silicon or not.
  • a gate dielectric layer 34 may be disposed between the gate structure 40 G and the second active region 14 , a third spacer 53 may be formed on the sidewalls of the gate structure 40 G, and doped regions 60 may be formed in the second active region 14 at two sides of the gate structure 40 G for being used as source/drain regions of a transistor, but not limited thereto.
  • the patterned conductive structure 40 may further include a first cap layer 48 disposed on the metal conductive layer 47 , and the first cap layer 48 may include silicon nitride, silicon oxide, or other suitable insulation materials.
  • FIGS. 4-8 are schematic drawings illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present invention, and FIGS. 1-3 may be regarded as schematic drawings in a step subsequent to FIG. 8 .
  • the manufacturing method of the semiconductor memory device in this embodiment may include the following steps. Firstly, the semiconductor substrate 10 is provided, and the patterned conductive structure 40 is formed on the semiconductor substrate 10 .
  • the patterned conductive structure 40 includes the first silicon conductive layer 41 A, the second silicon conductive layer 41 B, the interface layer 42 , the barrier layer 45 , and the metal conductive layer 47 .
  • the second silicon conductive layer 41 B is disposed on the first silicon conductive layer 41 A.
  • the interface layer 42 is disposed between the first silicon conductive layer 41 A and the second silicon conductive layer 41 B, and the interface layer 42 includes oxygen.
  • the barrier layer 45 is disposed on the second silicon conductive layer 41 B.
  • the metal conductive layer 47 is disposed on the barrier layer 45 .
  • the manufacturing method of the semiconductor memory device 100 in this embodiment may include but is not limited to the following steps.
  • a first deposition process 91 is performed to form the first silicon conductive layer 41 A on the memory cell region R 1 and the peripheral region R 2 of the semiconductor substrate 10 .
  • a first treatment 92 is performed to a top surface of the first silicon conductive layer 41 A for forming the interface layer 42 .
  • the first treatment 92 may include a nitrous oxide (N 2 O) treatment or other suitable oxidation treatments.
  • N 2 O nitrous oxide
  • a second deposition process 93 is performed to form the second silicon conductive layer 41 B on the interface layer 42 .
  • the first deposition process 91 , the first treatment 92 , and the second deposition process 93 may be performed in the same chemical vapor deposition apparatus and/or in the same process chamber.
  • the first treatment 92 may be regarded as an in-situ treatment, but not limited thereto.
  • the barrier layer 45 and the metal conductive layer 47 are then formed on the second silicon conductive layer 41 B, and a thermal anneal process 94 is performed after the step of forming the metal conductive layer 47 .
  • the thermal anneal process 94 may include a rapid thermal processing (RTP), but not limited thereto.
  • RTP rapid thermal processing
  • the bit line contact structure 43 may be formed on the memory cell region R 1 before the step of forming the barrier layer 45 and the metal conductive layer 47 .
  • the bit line contact structure 43 may be formed in the contact hole CH penetrating the second silicon conductive layer 41 B, the interface layer 42 , the first silicon conductive layer 41 A, the third mask layer 33 , the second mask layer 32 , and the first mask layer 31 , and the bit line contact structure 43 may directly contact the first silicon conductive layer 41 A, the interface layer 42 , and the second silicon conductive layer 41 B, but not limited thereto.
  • the first cap layer 48 and a second cap layer 49 are formed on the metal conductive layer 47 , and the second cap layer 49 may include silicon nitride, silicon oxide, or other suitable insulation materials. Subsequently, as shown in FIG. 7 and FIG. 8 , after the thermal anneal process 94 , the first cap layer 48 and a second cap layer 49 are formed on the metal conductive layer 47 , and the second cap layer 49 may include silicon nitride, silicon oxide, or other suitable insulation materials. Subsequently, as shown in FIG.
  • a patterning process is performed to the first silicon conductive layer 41 A, the interface layer 42 , the second silicon conductive layer 41 B, the first silicide layer 44 , the barrier layer 45 , the second silicide layer 46 , and the metal conductive layer 47 for forming the patterned conductive structure 40 , and the above mentioned parts, such as the first spacer 51 , the second spacer 52 , the third spacer 53 , the doped regions 60 , the isolation structure 70 , and the storage node contacts 80 , may be formed after the step of forming the patterned conductive structure 40 .
  • the barrier layer 45 and the metal conductive layer 47 may be patterned by the process patterning the first silicon conductive layer 41 A, the interface layer 42 , and the second silicon conductive layer 41 B, and the barrier layer 45 and the metal conductive layer 47 may be formed after the second deposition process mentioned above and before the patterning process mentioned above, but not limited thereto.
  • FIG. 9 is a schematic drawing illustrating a manufacturing method of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 9 may be regarded as a schematic drawing in a step subsequent to FIG. 6
  • FIG. 7 may be regarded as a schematic drawing in a step subsequent to FIG. 9 .
  • the difference between the manufacturing method in this embodiment and the manufacturing method in the first embodiment described above is that the manufacturing method in this embodiment may further include performing a second treatment 95 to a top surface of the second silicon conductive layer 41 B before the step of forming the barrier layer 45 .
  • the second treatment 95 may include a nitridation treatment, such as a decoupled plasma nitridation (DPN) treatment.
  • the second treatment 95 may be used to form a silicon nitride barrier layer on the top surface of the second silicon conductive layer 41 B for preventing the second silicon conductive layer 41 B from reacting with the barrier layer 45 too severely in the high temperature environment of the thermal anneal process 94 performed subsequently and generating defects.
  • the nitridation depth in the second silicon conductive layer 41 B may range from 10 angstroms to 30 angstroms, but not limited thereto.
  • the interface layer may be formed on the first silicon conductive layer by a surface treatment, and the second silicon conductive layer is then formed on the interface layer.
  • the interface layer may be used to block the boron penetration effect and prevent the silicon conductive layer from reacting with other material layers too seriously and forming defects in the subsequent processes.
  • the electrical performance of the semiconductor memory device may be improved and the manufacturing yield may be enhanced accordingly.

Abstract

A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.

Description

    BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a semiconductor memory device including a patterned conductive structure and a manufacturing method thereof.
    • 2. Description of the Prior Art
  • Dynamic random access memory (DRAM) is a kind of volatile storage device which is an indispensable key part of many electronic products. DRAM includes a great number of memory cells arranged for forming an array configured to store data. Each of the memory cells may be composed of a metal oxide semiconductor (MOS) transistor and a capacitor connected in series.
  • The MOS transistors in the memory cells may have different structural design because of the product specification and/or the memory cell density requirements. Therefore, the structure of the MOS transistor in the memory cell may be different from that of transistors on other regions within the same chip, and the manufacturing process will become more complicated. Accordingly, it is very important for the related field to effectively integrate the manufacturing process of the memory cell and the manufacturing process of the devices in other regions.
    • SUMMARY OF THE INVENTION
  • A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An interface layer is inserted into a silicon conductive layer in a patterned conductive structure, and the interface layer may be used to block boron penetration effects and prevent the silicon conductive layer from reacting with other material layers too seriously and forming defects. The manufacturing yield may be enhanced accordingly.
  • According to an embodiment of the present invention, a semiconductor memory device is provided. The semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.
  • According to an embodiment of the present invention, a manufacturing method of a semiconductor memory device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided, and a patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic drawing illustrating a semiconductor memory device according to a first embodiment of the present invention.
  • FIG. 2 is a top view schematic drawing illustrating the semiconductor memory device according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional diagram taken along a line B-B′ in FIG. 2.
  • FIGS. 4-8 are schematic drawings illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present invention, wherein
  • FIG. 5 is a schematic drawing in a step subsequent to FIG. 4,
  • FIG. 6 is a schematic drawing in a step subsequent to FIG. 5,
  • FIG. 7 is a schematic drawing in a step subsequent to FIG. 6, and
  • FIG. 8 is a schematic drawing in a step subsequent to FIG. 7.
  • FIG. 9 is a schematic drawing illustrating a manufacturing method of a semiconductor device according to a second embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • Please refer to FIGS. 1-3. FIG. 1 is a schematic drawing illustrating a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a top view schematic drawing illustrating the semiconductor memory device according to the first embodiment of the present invention. The left part of FIG. 1 may be regarded as a cross-sectional diagram taken along a line A-A′ in FIG. 2, and FIG. 3 is a cross-sectional diagram taken along a line B-B′ in FIG. 2. As shown in FIGS. 1-3, a semiconductor memory device 100 is provided in this embodiment. The semiconductor memory device 100 includes a semiconductor substrate 10 and a patterned conductive structure 40. The patterned conductive structure 40 is disposed on the semiconductor substrate 10. The patterned conductive structure 40 includes a first silicon conductive layer 41A, a second silicon conductive layer 41B, an interface layer 42, a barrier layer 45, and a metal conductive layer 47. The second silicon conductive layer 41B is disposed on the first silicon conductive layer 41A. The interface layer 42 is disposed between the first silicon conductive layer 41A and the second silicon conductive layer 41B, and the interface layer 42 includes oxygen. The barrier layer 45 is disposed on the second silicon conductive layer 41B. The metal conductive layer 47 is disposed on the barrier layer 45. In some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. A memory cell region R1 and a peripheral region R2 may be defined on the semiconductor substrate 10, and the patterned conductive structure 40 may be disposed on the memory cell region R1 and the peripheral region R2, but not limited thereto. In some embodiments, the patterned conductive structure 40 may be disposed on the memory cell region R1 only, disposed on the peripheral region R2 only, or be disposed on other regions of the semiconductor substrate 10 only.
  • In some embodiments, the patterned conductive structure 40 disposed on the memory cell region R1 may include a bit line structure BL, and the patterned conductive structure 40 disposed on the peripheral region R2 may include a gate structure 40G. In other words, at least a part of the patterned conductive structure 40 disposed on the memory cell region R1 may be used as a bit line structure BL of a memory cell, and at least a part of the patterned conductive structure 40 disposed on the peripheral region R2 may be used as a gate structure 40G of a transistor on the peripheral region R2. The structure of the bit line structure BL may be similar to the structure of the gate structure 40G because the bit line structure BL and the gate structure 40G are formed by the patterned conductive structure 40. The semiconductor memory device 100 may include a plurality of the bit line structures BL. Each of the bit line structures BL may be elongated in a first direction D1, the bit line structures BL may be disposed repeatedly in a second direction D2, and the second direction D2 may be substantially orthogonal to the first direction D1, but not limited thereto. In other patterned conductive structure 40, the material of the first silicon conductive layer 41A and the second silicon conductive layer 41B may include polysilicon, amorphous silicon, or other non-metal conductive materials containing silicon, and the interface layer 42 may include silicon oxide, silicon oxynitride, or other interface materials containing oxygen and silicon. In some embodiments, the material of the first silicon conductive layer 41A may be identical to or different from the material of the second silicon conductive layer 41B. Additionally, the barrier layer 45 may include titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), or other appropriate barrier materials. The metal conductive layer 47 may include aluminum, tungsten, copper, titanium aluminide, or other suitable metal conductive materials with low electrical resistivity. In some embodiments, a first silicide layer 44 may be formed between the second silicon conductive layer 41B and the barrier layer 45, and a second silicide layer 46 may be formed between the barrier layer 45 and the metal conductive layer 47, but not limited thereto. The first silicide layer 44 may include silicide of the material in the barrier layer 46, such as titanium silicide (TiSi), and the second silicide layer 46 may include silicide of the material in the metal conductive layer 47, such as tungsten silicide (WSi), but not limited thereto.
  • The interface layer 42 located between the first silicon conductive layer 41A and the second silicon conductive layer 41B in a thickness direction of the semiconductor substrate 10 (such as a third direction D3 shown in FIGS. 1-3) may be used to block the dopants in the second silicon conductive layer 41B from penetrating downwards (such as the boron penetration effect), and the electrical performance of the semiconductor memory device 100 may be enhanced accordingly. Additionally, the interface layer 42 may also be used to block the material in the barrier layer 45 (such as titanium) from diffusing downwards and reacting with silicon for forming silicide or generating defects, and the manufacturing yield may be improved accordingly. Therefore, the interface layer 42 may be remarkably thinner than the first silicon conductive layer 41A and the second silicon conductive layer 41B. For example, the thickness of the interface layer 42 may be less than or equal to 50 angstroms (Å), and the total thickness of the first silicon conductive layer 41A and the second silicon conductive layer 41B may be about 300 angstroms, but not limited thereto. In some embodiments, for enhancing the performance of blocking the boron penetration effect described above, the location of the interface layer 42 may be modified to be relatively lower, and the thickness of the first silicon conductive layer 41A may be smaller than the thickness of the second silicon conductive layer 41B. In some embodiments, for enhancing the above mentioned performance of blocking the material in the barrier layer 45 from diffusing downwards, the location of the interface layer 42 may be modified to be relatively higher, and the thickness of the first silicon conductive layer 41A may be greater than the thickness of the second silicon conductive layer 41B. In other words, the ratio of the thickness of the first silicon conductive layer 41A to the thickness of the second silicon conductive layer 41B may be modified for forming the interface layer 42 at the required position according to different requirements.
  • Specifically, in the memory cell region R1, a first trench isolation 11 may be formed in the semiconductor substrate 10 for defining a plurality of first active regions 12. Comparatively, in the peripheral region R2, a second trench isolation 13 may be formed in the semiconductor substrate 10 for defining a second active region 14. The first trench isolation 11 and the second trench isolation 13 may respectively include a single layer or multiple layers of insulation material, such as silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), or other suitable insulation materials. Additionally, word line structures WL may be formed in the semiconductor substrate 10, and the word line structures WL may be buried word lines, but not limited thereto. Each of the word line structures WL may be elongated in the second direction D2, and each of the word line structures WL may include a word line dielectric layer 21, a word line 22, and a word line cap layer 23, but not limited thereto. Trenches may be formed in the semiconductor substrate 10, and the word line dielectric layer 21, the word line 22, and the word line cap layer 23 mentioned above may be sequentially formed in the trench, but not limited thereto. In some embodiments, the other types of word line structures may also be applied according to other considerations. Additionally, the word line dielectric layer 21 may include silicon oxide or other suitable dielectric materials, the word line 22 may include aluminum, tungsten, copper, titanium aluminide (TiAl), or other suitable conductive materials, and the word line cap layer 23 may include silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulation materials. Mask layers such as a first mask layer 31, a second mask layer 32, and a third mask layer 33 may be disposed on the word line structures WL. In some embodiments, the first mask layer 31, the second mask layer 32, and the third mask layer 33 may be an interface layer composed of an oxide-nitride-oxide (ONO) structure, but not limited thereto. For example, the first mask layer 31 may be a silicon oxide layer, the second mask layer 32 may be a silicon nitride layer, and the third mask layer 33 may be a silicon oxide layer, but not limited thereto.
  • In some embodiments, the semiconductor memory device 100 may further include a bit line contact structure 43 disposed on the memory cell region R1, and the bit line contact structure 43 may be disposed between the barrier layer 45 and the semiconductor substrate 10 in the third direction D3. The bit line structure BL may be electrically connected with the corresponding first active region 12 via the bit line contact structure 43, and the bit line contact structure 43 may include a metal conductive material or a non-metal conductive material, such as polysilicon, amorphous silicon, or other non-metal conductive material containing silicon, but not limited thereto. As shown in FIG. 3, in some embodiments, the bit line contact structure 43 may penetrate the first silicon conductive layer 41A, the interface layer 42, and the second silicon conductive layer 41B, and the bit line contact structure 43 may directly contact the first silicon conductive layer 41A, the interface layer 42, and the second silicon conductive layer 41B, but not limited thereto. Additionally, at least a part of the bit line contact structure 43 may be disposed in a contact hole CH penetrating the first silicon conductive layer 41A, the interface layer 42, and the second silicon conductive layer 41B. Spacers such as a first spacer 51 and a second spacer 52 may be formed on sidewalls of the bit line structure BL, and at least a part of the spacer, such as the first spacer 51, may be partially disposed in the contact hole CH. In addition, the semiconductor memory device 100 may further include an isolation structure 70 disposed on the semiconductor substrate 10, and storage node contacts 80 may be formed in openings of the isolation structure 70 and electrically connected with the corresponding first active regions 12. The isolation structure 70 may include silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulation materials, and the storage node contacts 80 may include amorphous silicon, polysilicon, or other conductive materials including silicon or not.
  • In the peripheral region R2, a gate dielectric layer 34 may be disposed between the gate structure 40G and the second active region 14, a third spacer 53 may be formed on the sidewalls of the gate structure 40G, and doped regions 60 may be formed in the second active region 14 at two sides of the gate structure 40G for being used as source/drain regions of a transistor, but not limited thereto. In some embodiments, the patterned conductive structure 40 may further include a first cap layer 48 disposed on the metal conductive layer 47, and the first cap layer 48 may include silicon nitride, silicon oxide, or other suitable insulation materials.
  • Please refer to FIGS. 1-8. FIGS. 4-8 are schematic drawings illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present invention, and FIGS. 1-3 may be regarded as schematic drawings in a step subsequent to FIG. 8. As shown in FIGS. 1-3, the manufacturing method of the semiconductor memory device in this embodiment may include the following steps. Firstly, the semiconductor substrate 10 is provided, and the patterned conductive structure 40 is formed on the semiconductor substrate 10. The patterned conductive structure 40 includes the first silicon conductive layer 41A, the second silicon conductive layer 41B, the interface layer 42, the barrier layer 45, and the metal conductive layer 47. The second silicon conductive layer 41B is disposed on the first silicon conductive layer 41A. The interface layer 42 is disposed between the first silicon conductive layer 41A and the second silicon conductive layer 41B, and the interface layer 42 includes oxygen. The barrier layer 45 is disposed on the second silicon conductive layer 41B. The metal conductive layer 47 is disposed on the barrier layer 45.
  • Specifically, the manufacturing method of the semiconductor memory device 100 in this embodiment may include but is not limited to the following steps. As shown in FIG. 4, after the step of forming the third mask layer 33, a first deposition process 91 is performed to form the first silicon conductive layer 41A on the memory cell region R1 and the peripheral region R2 of the semiconductor substrate 10. Subsequently, as shown in FIG. 5, a first treatment 92 is performed to a top surface of the first silicon conductive layer 41A for forming the interface layer 42. In some embodiments, the first treatment 92 may include a nitrous oxide (N2O) treatment or other suitable oxidation treatments. Subsequently, as shown in FIG. 6, a second deposition process 93 is performed to form the second silicon conductive layer 41B on the interface layer 42. As shown in FIGS. 4-6, in some embodiments, the first deposition process 91, the first treatment 92, and the second deposition process 93 may be performed in the same chemical vapor deposition apparatus and/or in the same process chamber. In other words, the first treatment 92 may be regarded as an in-situ treatment, but not limited thereto. As shown in FIG. 7, the barrier layer 45 and the metal conductive layer 47 are then formed on the second silicon conductive layer 41B, and a thermal anneal process 94 is performed after the step of forming the metal conductive layer 47. In some embodiments, the thermal anneal process 94 may include a rapid thermal processing (RTP), but not limited thereto. It is worth noting that, in some embodiments, the bit line contact structure 43 may be formed on the memory cell region R1 before the step of forming the barrier layer 45 and the metal conductive layer 47. The bit line contact structure 43 may be formed in the contact hole CH penetrating the second silicon conductive layer 41B, the interface layer 42, the first silicon conductive layer 41A, the third mask layer 33, the second mask layer 32, and the first mask layer 31, and the bit line contact structure 43 may directly contact the first silicon conductive layer 41A, the interface layer 42, and the second silicon conductive layer 41B, but not limited thereto.
  • As shown in FIG. 7 and FIG. 8, after the thermal anneal process 94, the first cap layer 48 and a second cap layer 49 are formed on the metal conductive layer 47, and the second cap layer 49 may include silicon nitride, silicon oxide, or other suitable insulation materials. Subsequently, as shown in FIG. 1, a patterning process is performed to the first silicon conductive layer 41A, the interface layer 42, the second silicon conductive layer 41B, the first silicide layer 44, the barrier layer 45, the second silicide layer 46, and the metal conductive layer 47 for forming the patterned conductive structure 40, and the above mentioned parts, such as the first spacer 51, the second spacer 52, the third spacer 53, the doped regions 60, the isolation structure 70, and the storage node contacts 80, may be formed after the step of forming the patterned conductive structure 40. In other words, the barrier layer 45 and the metal conductive layer 47 may be patterned by the process patterning the first silicon conductive layer 41A, the interface layer 42, and the second silicon conductive layer 41B, and the barrier layer 45 and the metal conductive layer 47 may be formed after the second deposition process mentioned above and before the patterning process mentioned above, but not limited thereto.
  • The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.
  • Please refer to FIG. 6, FIG. 7, and FIG. 9. FIG. 9 is a schematic drawing illustrating a manufacturing method of a semiconductor device according to a second embodiment of the present invention. FIG. 9 may be regarded as a schematic drawing in a step subsequent to FIG. 6, and FIG. 7 may be regarded as a schematic drawing in a step subsequent to FIG. 9. As shown in FIG. 6, FIG. 7, and FIG. 9, the difference between the manufacturing method in this embodiment and the manufacturing method in the first embodiment described above is that the manufacturing method in this embodiment may further include performing a second treatment 95 to a top surface of the second silicon conductive layer 41B before the step of forming the barrier layer 45. In some embodiments, the second treatment 95 may include a nitridation treatment, such as a decoupled plasma nitridation (DPN) treatment. The second treatment 95 may be used to form a silicon nitride barrier layer on the top surface of the second silicon conductive layer 41B for preventing the second silicon conductive layer 41B from reacting with the barrier layer 45 too severely in the high temperature environment of the thermal anneal process 94 performed subsequently and generating defects. In some embodiments, the nitridation depth in the second silicon conductive layer 41B may range from 10 angstroms to 30 angstroms, but not limited thereto.
  • To summarize the above descriptions, according to the semiconductor memory device and the manufacturing method thereof in the present invention, the interface layer may be formed on the first silicon conductive layer by a surface treatment, and the second silicon conductive layer is then formed on the interface layer. The interface layer may be used to block the boron penetration effect and prevent the silicon conductive layer from reacting with other material layers too seriously and forming defects in the subsequent processes. The electrical performance of the semiconductor memory device may be improved and the manufacturing yield may be enhanced accordingly.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (20)

1: A semiconductor memory device, comprising:
a semiconductor substrate, wherein a memory cell region and a peripheral region are defined on the semiconductor substrate;
a patterned conductive structure disposed on the semiconductor substrate, wherein the patterned conductive structure is disposed on the memory cell region and the peripheral region, and the patterned conductive structure comprises:
a first silicon conductive layer;
a second silicon conductive layer disposed on the first silicon conductive layer;
an interface layer disposed between the first silicon conductive layer and the second silicon conductive layer, wherein the interface layer comprises oxygen;
a barrier layer disposed on the second silicon conductive layer; and
a metal conductive layer disposed on the barrier layer, wherein the patterned conductive structure disposed on the memory cell region comprises a bit line structure; and
a bit line contact structure disposed on the memory cell region, wherein the bit line contact structure is disposed between the barrier layer and the semiconductor substrate.
2. (canceled)
3. (canceled)
4. (canceled)
5: The semiconductor memory device according to claim 1, wherein the bit line contact structure directly contacts the first silicon conductive layer, the interface layer, and the second silicon conductive layer.
6: The semiconductor memory device according to claim 1, wherein the patterned conductive structure disposed on the peripheral region comprises a gate structure.
7: The semiconductor memory device according to claim 1, wherein a material of the second silicon conductive layer is identical to a material of the first silicon conductive layer.
8: The semiconductor memory device according to claim 1, wherein the interface layer is thinner than the first silicon conductive layer and the second silicon conductive layer.
9: The semiconductor memory device according to claim 1, wherein the thickness of the interface layer is less than or equal to 50 angstroms (Å).
10: The semiconductor memory device according to claim 1, wherein the interface layer comprises silicon oxide or silicon oxynitride.
11: A manufacturing method of a semiconductor memory device, comprising:
providing a semiconductor substrate, wherein a memory cell region and a peripheral region are defined on the semiconductor substrate;
forming a patterned conductive structure on the semiconductor substrate, wherein the patterned conductive structure is formed on the memory cell region and the peripheral region, and the patterned conductive structure comprises:
a first silicon conductive layer;
a second silicon conductive layer disposed on the first silicon conductive layer;
an interface layer disposed between the first silicon conductive layer and the second silicon conductive layer, wherein the interface layer comprises oxygen;
a barrier layer disposed on the second silicon conductive layer; and
a metal conductive layer disposed on the barrier layer, wherein the patterned conductive structure formed on the memory cell region comprises a bit line structure; and
forming a bit line contact structure on the memory cell region, wherein the bit line contact structure is disposed between the barrier layer and the semiconductor substrate.
12: The manufacturing method of the semiconductor memory device according to claim 11, wherein the step of forming the patterned conductive structure comprises:
performing a first deposition process to form the first silicon conductive layer on the semiconductor substrate;
performing a first treatment to a top surface of the first silicon conductive layer for forming the interface layer;
performing a second deposition process to form the second silicon conductive layer on the interface layer; and
performing a patterning process to the first silicon conductive layer, the interface layer, and the second silicon conductive layer.
13: The manufacturing method of the semiconductor memory device according to claim 12, wherein the first treatment comprises a nitrous oxide (N2O) treatment.
14: The manufacturing method of the semiconductor memory device according to claim 12, wherein the first deposition process, the first treatment, and the second deposition process are performed in the same chemical vapor deposition apparatus.
15: The manufacturing method of the semiconductor memory device according to claim 12, further comprising:
performing a thermal anneal process after the step of forming the metal conductive layer, wherein the barrier layer and the metal conductive layer are formed after the second deposition process and before the patterning process.
16: The manufacturing method of the semiconductor memory device according to claim 15, further comprising:
performing a second treatment to a top surface of the second silicon conductive layer before the step of forming the barrier layer, wherein the second treatment comprises a nitridation treatment.
17: The manufacturing method of the semiconductor memory device according to claim 11, wherein the patterned conductive structure formed on the peripheral region comprises a gate structure.
18: The manufacturing method of the semiconductor memory device according to claim 11,
wherein the bit line contact structure directly contacts the first silicon conductive layer, the interface layer, and the second silicon conductive layer.
19: The manufacturing method of the semiconductor memory device according to claim 11, wherein the interface layer is thinner than the first silicon conductive layer and the second silicon conductive layer.
20: The manufacturing method of the semiconductor memory device according to claim 11, wherein the interface layer comprises silicon oxide or silicon oxynitride.
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