US20190221562A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
US20190221562A1
US20190221562A1 US15/880,492 US201815880492A US2019221562A1 US 20190221562 A1 US20190221562 A1 US 20190221562A1 US 201815880492 A US201815880492 A US 201815880492A US 2019221562 A1 US2019221562 A1 US 2019221562A1
Authority
US
United States
Prior art keywords
shaped structures
fin shaped
semiconductor device
cladding layer
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US15/880,492
Other versions
US10366991B1 (en
Inventor
Hsu Ting
Yu-Ying Lin
Yen-Hsing Chen
Chun-Jen Chen
Chun-Wei Yu
Keng-Jen Lin
Yu-Ren Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, CHUN-JEN, CHEN, YEN-HSING, LIN, KENG-JEN, LIN, YU-YING, TING, HSU, WANG, YU-REN, YU, CHUN-WEI
Publication of US20190221562A1 publication Critical patent/US20190221562A1/en
Application granted granted Critical
Publication of US10366991B1 publication Critical patent/US10366991B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including fin shaped structures and a manufacturing method thereof.
  • a semiconductor device and a manufacturing method thereof are provided in the present invention.
  • a fin shaped structure having a first portion disposed above a top surface of an isolation structure and a second portion disposed on the first portion is formed.
  • a width of the second portion is smaller than a width of the first portion.
  • a cladding layer having a curved surface is formed on the first portion and the second portion of the fin shaped structure for enhancing the electrical performance of the semiconductor device.
  • a semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure.
  • the semiconductor substrate includes fin shaped structures.
  • the isolation structure is disposed between the fin shaped structures.
  • Each of the fin shaped structures includes a first portion and a second portion. The first portion is disposed above a top surface of the isolation structure. The second portion is disposed on the first portion. A width of the second portion is smaller than a width of the first portion.
  • the cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures, and the cladding layer includes a curved surface.
  • the gate structure is disposed straddling the fin shaped structures.
  • a manufacturing method of a semiconductor device includes the following steps.
  • a semiconductor substrate is provided, and the semiconductor substrate includes fin shaped structures.
  • An isolation structure is formed between the fin shaped structures.
  • Each of the fin shaped structures includes a first portion and a second portion. The first portion is disposed above a top surface of the isolation structure. The second portion is disposed on the first portion. A width of the second portion is smaller than a width of the first portion.
  • a cladding layer is formed on the first portion and the second portion of each of the fin shaped structures, and the cladding layer includes a curved surface.
  • a gate structure is formed straddling the fin shaped structures.
  • FIG. 1 is a schematic drawing illustrating a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a stereoscopic schematic drawing illustrating the semiconductor device according to the first embodiment of the present invention.
  • FIGS. 3-5 are schematic drawings illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present invention, wherein
  • FIG. 4 is a schematic drawing in a step subsequent to FIG. 3 .
  • FIG. 5 is a schematic drawing in a step subsequent to FIG. 4 .
  • FIG. 6 is a schematic drawing illustrating a semiconductor device according to a second embodiment of the present invention.
  • FIGS. 7-11 are schematic drawings illustrating a manufacturing method of a semiconductor device according to a third embodiment of the present invention, wherein
  • FIG. 8 is a schematic drawing in a step subsequent to FIG. 7 .
  • FIG. 9 is a schematic drawing in a step subsequent to FIG. 8 .
  • FIG. 10 is a schematic drawing in a step subsequent to FIG. 9 .
  • FIG. 11 is a schematic drawing in a step subsequent to FIG. 10 .
  • FIG. 1 is a schematic drawing illustrating a semiconductor device according to a first embodiment of the present invention
  • FIG. 2 is a stereoscopic schematic drawing illustrating the semiconductor device in this embodiment.
  • a semiconductor device 101 is provided in this embodiment.
  • the semiconductor device 101 includes a semiconductor substrate 10 , an isolation structure 20 , a cladding layer 30 , and a gate structure 40 G.
  • the semiconductor substrate 10 may include a silicon substrate, an epitaxial substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto.
  • SOI silicon-on-insulator
  • the semiconductor substrate 10 includes at least one fin shaped structure 10 F, and the fin shaped structure 10 F includes a fin shaped structure of a semiconductor material, such as a silicon semiconductor fin shaped structure.
  • the semiconductor substrate 10 may include a plurality of the fin shaped structures 10 F.
  • Each of the fin shaped structures 10 F may be elongated in a first direction D 1
  • the fin shaped structures 10 F may be arranged repeatedly in a second direction D 2
  • the first direction D 1 may be substantially perpendicular to the second direction D 2 , but not limited thereto.
  • the fin shaped structures 10 F may be formed by performing a patterning process (such as a multiple exposure process and an etching process) to the semiconductor substrate 10 .
  • the isolation structure 20 is disposed between the fin shaped structures 10 F.
  • the isolation structure 20 may be regarded as a shallow trench isolation, and the isolation structure 20 may include a single layer or multiple layers of insulation materials, such as an oxide insulation material, but not limited thereto.
  • Each of the fin shaped structures 10 F may be partly covered by the isolation structure 20 and partly not covered by the isolation structure 20 .
  • the portion of each of the fin shaped structures 10 F which is not covered by the isolation structure 20 may be located above a top surface of the isolation structure 20 (such as a first top surface S 1 shown in FIG. 1 ) in a thickness direction of the semiconductor substrate 10 (such as a third direction D 3 shown in FIG. 1 and FIG. 2 ), and the first top surface S 1 may be the topmost surface of the isolation structure 20 in the third direction D 3 , but not limited thereto.
  • each of the fin shaped structures 10 F may include a third portion P 3 , a first portion P 1 , and a second portion P 2 sequentially arranged and disposed in the third direction D 3 .
  • the third portion P 3 of each of the fin shaped structures 10 F may be covered by the isolation structure 20 , and the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F are not covered by the isolation structure 20 .
  • the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F may be disposed above the first top surface S 1 of the isolation structure 20 in the third direction D 3 , and the second portion P 2 is disposed on the first portion P 1 in the third direction D 3 .
  • the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F may protrude from the first top surface S 1 of the isolation structure 20 .
  • a width of the second portion P 2 (such as a second width W 2 shown in FIG. 1 ) is smaller than a width of the first portion P 1 (such as a first width W 1 shown in FIG. 1 ).
  • the first width W 1 of the first portion P 1 and the second width W 2 of the second portion P 2 may also be regarded as lengths in the second direction D 2 , but not limited thereto.
  • the cladding layer 30 is disposed on the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F, and the cladding layer 30 includes a curved surface CS.
  • the curved surface CS of the cladding layer 30 may be a surface which does not contact the fin shaped structure 10 F, but not limited thereto.
  • a width of the cladding layer 30 disposed on one of the fin shaped structures 10 F (such as a third width W 3 shown in FIG.
  • the cladding layer 30 covering the first portion P 1 and the second portion P 2 of the fin shaped structure 10 F has the curved surface CS protruding outwards and the cladding layer 30 may be disposed on two opposite sides of the first portion P 1 of each fin shaped structure 10 F in the second direction D 2 and on two opposite sides of the second portion P 2 of each fin shaped structure 10 F in the second direction D 2 .
  • the first width W 1 , the second width W 2 , and the third width W 3 may be the maximum widths of the first portion P 1 , the second portion P 2 , and the cladding layer 30 on one of the fin shaped structures 10 F respectively, but not limited thereto.
  • a lattice constant of the cladding layer 30 may be different from a lattice constant of the fin shaped structures 10 F.
  • the material of the cladding layer 30 may include germanium (Ge), silicon germanium (SiGe), silicon phosphide (SiP), or other suitable semiconductor materials.
  • the first portion P 1 and the second portion P 2 of the fin shaped structure 10 F and the cladding layer 30 may be regarded as the channel region in the semiconductor device 101 .
  • the cladding layer 30 disposed on two adjacent fin shaped structures 10 F may be separated from each other, but not limited thereto.
  • the cladding layer 30 disposed on the two opposite sides of the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F may provide a compressive stress to the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F for enhancing the carrier mobility of the channel region, but not limited thereto.
  • the cladding layer 30 may be disposed on a sidewall of the first portion P 1 (such as a first sidewall SW 1 shown in FIG. 1 ) of each of the fin shaped structures 10 F and a sidewall of the second portion P 2 (such as a second sidewall SW 2 shown in FIG. 1 ) of each of the fin shaped structures 10 F.
  • a slope of the first sidewall SW 1 of the first portion P 1 of each of the fin shaped structures 10 F may be smaller than a slope of the second sidewall SW 2 of the second portion P 2 of each of the fin shaped structures 10 F.
  • a horizontal plane (such as a plane formed by the first direction D 1 and the second direction D 2 ) may be used to calculate the slope of the first sidewall SW 1 and the slope of the second sidewall SW 2 mentioned above, but not limited thereto.
  • the second sidewall SW 2 of the second portion P 2 of each fin shaped structure 10 F may be steeper than the first sidewall SW 1 of the first portion P 1 , and the distribution of the first sidewall SW 1 and the second sidewall SW 2 may be formed by an etching process, but not limited thereto.
  • the gate structure 40 G is disposed straddling the fin shaped structures 10 F.
  • the gate structure 40 G may be elongated in the second direction D 2 , but not limited thereto.
  • the gate structure 40 G may include a dummy gate structure, a metal gate structure, or other suitable types of gate structures.
  • the dummy gate structure mentioned above may be a dummy gate structure used in a replacement metal gate (RMG) process, and the material of the dummy gate structure may include a semiconductor material such as polysilicon and amorphous silicon, but not limited thereto.
  • RMG replacement metal gate
  • the gate structure 40 G may also include conductive materials and insulation materials according to other considerations, such as a low resistivity metal conductive material, a work function metal layer, and a high dielectric constant (high-k) dielectric layer in a metal gate structure, but not limited thereto.
  • a spacer 50 may be disposed on sidewalls of the gate structure 40 G.
  • the material of the spacer 50 may include oxide, nitride, oxynitride, or other suitable insulation materials, and the spacer 50 may be formed by a single layer or multiple layers of the materials mentioned above.
  • the spacer 50 may partly disposed on the cladding layer 30 , but not limited thereto.
  • the gate structure 40 G may be partially disposed on the cladding layer 30 .
  • the contact area between the gate structure 40 G and the cladding layer 30 may be increased because the cladding layer 30 has the curved surface CS protruding outwards, and the electrical performance of the semiconductor device 101 may be enhanced accordingly.
  • a top surface of the second portion P 2 (such as a second top surface S 2 shown in FIG. 1 ) of each of the fin shaped structures 10 F may not be covered by the cladding layer 30 , but not limited thereto.
  • FIGS. 3-5 and FIG. 1 are schematic drawings illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present invention, and FIG. 1 may be regarded as a schematic drawing in a step subsequent to FIG. 5 .
  • the manufacturing method of the semiconductor device 101 may include the following steps. Firstly, the semiconductor substrate 10 is provided, and the semiconductor substrate 10 includes the fin shaped structures 10 F. The isolation structure 20 is formed between the fin shaped structures 10 F. Each of the fin shaped structures 10 F includes the first portion P 1 and the second portion P 2 .
  • the first portion P 1 is disposed above the first top surface S 1 of the isolation structure 20 in the third direction D 3 , and the second portion P 2 is disposed on the first portion P 1 .
  • the second width W 2 of the second portion P 2 is smaller than the first width W 1 of the first portion P 1 .
  • the cladding layer 30 is formed on the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F, and the cladding layer 30 includes the curved surface CS.
  • the gate structure 40 G is formed straddling the fin shaped structures 10 F.
  • the manufacturing method of the semiconductor device 101 in this embodiment may include but is not limited to the following steps.
  • an isolation material is formed on the semiconductor substrate 10 and the fin shaped structures 10 F, and an etching back process is performed to the isolation material for exposing the top portion of each of the fin shaped structures 10 F and forming the isolation structure 20 .
  • the first top surface S 1 of the isolation structure 20 is lower than the topmost surface of each of the fin shaped structures 10 F in the third direction D 3 .
  • an etching process 91 is performed to the part of each of the fin shaped structures 10 F which is not covered by the isolation structure 20 for forming the first portion P 1 and the second portion P 2 mentioned above.
  • the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F is formed by performing the etching process 91 to the fin shaped structures after the step of forming the isolation structure 20 , but not limited thereto.
  • the etching process 91 may include an isotropic etching process, such as a wet etching process using tetramethylammonium hydroxide (TMAH) or wet etching processes using other suitable etchants.
  • TMAH tetramethylammonium hydroxide
  • the differences in width and sidewall conditions between the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F may be obtained by the difference in etching rate between different lattice directions of the fin shaped structure 10 F in the etchant of the wet etching process.
  • the etching rate of the ⁇ 111> surface of silicon in TMAH is lower than the etching rate of the ⁇ 100> surface of silicon in TMAH
  • the first portion P 1 may be formed with larger width, and the slope of the first sidewall SW 1 of the first portion P 1 may be smaller than the slope of the second sidewall SW 2 of the second portion P 2 accordingly.
  • the cladding layer 30 is subsequently formed on the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F.
  • the step of forming the cladding layer 30 may include a selective epitaxial growth (SEG) process 92 , but the present invention is not limited to this.
  • SEG selective epitaxial growth
  • other processes such as a deposition process and a patterning process may also be used to form the cladding layer 30 according to other considerations.
  • the third width W 3 of the cladding layer 30 formed on one of the fin shaped structures 10 F may be larger than the first width W 1 of the first portion P 1 of the fin shaped structure 10 F because the cladding layer 30 covering the first portion P 1 and the second portion P 2 of the fin shaped structure 10 F has the curved surface CS protruding outwards and the cladding layer 30 may be formed on two opposite sides of the first portion P 1 of each fin shaped structure 10 F in the second direction D 2 and on two opposite sides of the second portion P 2 of each fin shaped structure 10 F in the second direction D 2 .
  • the cladding layer 30 may be formed on the first sidewall SW 1 of the first portion P 1 of each fin shaped structure 10 F and on the second sidewall SW 2 of the second portion P 2 of each fin shaped structure 10 F, and the slope of the first sidewall SW 1 may be smaller than the slope of the second sidewall SW 2 .
  • the gate structure 40 G and the spacer 50 are formed subsequently.
  • the gate structure 40 G may be formed after the step of forming the cladding layer 30 , and the gate structure 40 G may include a dummy gate structure, a metal gate structure, or other suitable types of gate structures.
  • the gate structure 40 G may be partially formed on the cladding layer 30 , and the gate structure 40 G may be formed between the cladding layers 30 on two of the fin shaped structures 10 F adjacent to each other in the second direction D 2 .
  • source/drain regions may be formed in portions of the fin shaped structures 10 F and the cladding layer 30 which are not covered by the gate structure 40 G.
  • the source/drain regions may be formed by performing one or more doping processes to the portions of the fin shaped structures 10 F and the cladding layer 30 which are not covered by the gate structure 40 G, or the portions of the fin shaped structures 10 F and the cladding layer 30 which are not covered by the gate structure 40 G may be partially removed for forming epitaxial layers of source/drain regions.
  • the epitaxial layers of the source/drain regions and the cladding layer 30 of the channel region may be formed together for process simplification, but not limited thereto.
  • FIG. 6 is a schematic drawing illustrating a semiconductor device 102 according to a second embodiment of the present invention.
  • the difference between the semiconductor device 102 and the semiconductor device of the first embodiment mentioned above is that, in the semiconductor device 102 , the cladding layer 30 may be further disposed on the second top surface S 2 of the second portion P 2 of each of the fin shaped structures 10 F.
  • the cladding layer 30 may be further formed on the second top surface S 2 of the second portion P 2 of each of the fin shaped structures 10 F by modifying the process conditions for forming the cladding layer 30 (such as the process conditions of the selective epitaxial growth process).
  • FIGS. 7-11 are schematic drawings illustrating a manufacturing method of a semiconductor device according to a third embodiment of the present invention.
  • a dummy gate structure 40 D may be formed straddling the fin shaped structures 10 F.
  • the material of the dummy gate structure 40 D may include a semiconductor material such as polysilicon and amorphous silicon, but not limited thereto.
  • the spacer 50 may be formed on the sidewall of the dummy gate structure 40 D, and an interlayer dielectric layer 60 may be formed covering the dummy gate structure 40 D and the spacer 50 .
  • a planarization process such as a chemical mechanical polishing process may be performed to remove the interlayer dielectric layer 60 above the dummy gate structure 40 D and expose the dummy gate structure 40 D.
  • the dummy gate structure 40 D is removed for forming a gate trench TR surrounded by the spacer 50 and exposing apart of each of the fin shaped structures 10 F.
  • the gate trench TR may expose the top portion of each of the fin shaped structures 10 F which is not covered by the isolation structure 20 .
  • the etching process 91 is performed subsequently for forming the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F. In other words, as shown in FIGS.
  • the dummy gate structure 40 D may be formed before the etching process 91 , and the dummy gate structure 40 D may be removed before the etching process 91 , but not limited thereto.
  • a process such as a selective epitaxial growth process, may be performed to form the cladding layer 30 on the first portion P 1 and the second portion P 2 of each of the fin shaped structures 10 F exposed by the gate trench TR.
  • the gate structure 40 G may then be formed in the gate trench TR, and the gate structure 40 G may include a metal gate structure 40 M.
  • the metal gate structure 40 M may be composed of a high-k dielectric layer, a work function metal layer, a barrier layer, and a low resistivity metal conductive material, but not limited thereto.
  • the semiconductor device 103 in this embodiment may include the metal gate structure 40 M straddling the fin shaped structures 10 F and the cladding layer 30 .
  • the first portion and the second portion of the fin shaped structure above the top surface of the isolation structure may be formed by the etching process, and the width of the second portion is smaller than the width of the first portion.
  • the cladding layer having the curved surface is formed on the first portion and the second portion of the fin shaped structure.
  • the first portion and the second portion of the fin shaped structure and the cladding layer may form the channel region of the semiconductor device.
  • the cladding layer disposed on the two opposite sides of the first portion and the second portion of the fin shaped structure may provide a compressive stress to the fin shaped structure for enhancing the carrier mobility of the channel region.
  • the contact area between the gate structure and the cladding layer may be increased because the cladding layer has the curved surface protruding outwards, and the electrical performance of the semiconductor device may be further enhanced accordingly.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

Description

    BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including fin shaped structures and a manufacturing method thereof.
    • 2. Description of the Prior Art
  • The development of semiconductor integrated circuit technology progresses continuously and circuit designs in products of the new generation become smaller and more complicated than those of the former generation. The amount and the density of the functional devices in each chip region are increased constantly according to the requirements of innovated products, and the size of each device has to become smaller accordingly. Transistors are important semiconductor devices in the integrated circuits. In recent years, there is a development for three-dimensional or non-planar field effect transistors (FETs) such as fin field effect transistors (Fin-FETs) for replacing the planar FETs. However, with the increasing miniaturization of electronic products, it is still important to modify the structural and/or the material design of the Fin-FETs for improving the manufacturing yield and enhancing the device performance.
    • SUMMARY OF THE INVENTION
  • A semiconductor device and a manufacturing method thereof are provided in the present invention. A fin shaped structure having a first portion disposed above a top surface of an isolation structure and a second portion disposed on the first portion is formed. A width of the second portion is smaller than a width of the first portion. A cladding layer having a curved surface is formed on the first portion and the second portion of the fin shaped structure for enhancing the electrical performance of the semiconductor device.
  • According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion and a second portion. The first portion is disposed above a top surface of the isolation structure. The second portion is disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures, and the cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.
  • According to an embodiment of the present invention, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided, and the semiconductor substrate includes fin shaped structures. An isolation structure is formed between the fin shaped structures. Each of the fin shaped structures includes a first portion and a second portion. The first portion is disposed above a top surface of the isolation structure. The second portion is disposed on the first portion. A width of the second portion is smaller than a width of the first portion. A cladding layer is formed on the first portion and the second portion of each of the fin shaped structures, and the cladding layer includes a curved surface. A gate structure is formed straddling the fin shaped structures.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic drawing illustrating a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a stereoscopic schematic drawing illustrating the semiconductor device according to the first embodiment of the present invention.
  • FIGS. 3-5 are schematic drawings illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present invention, wherein
  • FIG. 4 is a schematic drawing in a step subsequent to FIG. 3, and
  • FIG. 5 is a schematic drawing in a step subsequent to FIG. 4.
  • FIG. 6 is a schematic drawing illustrating a semiconductor device according to a second embodiment of the present invention.
  • FIGS. 7-11 are schematic drawings illustrating a manufacturing method of a semiconductor device according to a third embodiment of the present invention, wherein
  • FIG. 8 is a schematic drawing in a step subsequent to FIG. 7,
  • FIG. 9 is a schematic drawing in a step subsequent to FIG. 8,
  • FIG. 10 is a schematic drawing in a step subsequent to FIG. 9, and
  • FIG. 11 is a schematic drawing in a step subsequent to FIG. 10.
    •  DETAILED DESCRIPTION
  • Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic drawing illustrating a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a stereoscopic schematic drawing illustrating the semiconductor device in this embodiment. As shown in FIG. 1 and FIG. 2, a semiconductor device 101 is provided in this embodiment. The semiconductor device 101 includes a semiconductor substrate 10, an isolation structure 20, a cladding layer 30, and a gate structure 40G. In some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. The semiconductor substrate 10 includes at least one fin shaped structure 10F, and the fin shaped structure 10F includes a fin shaped structure of a semiconductor material, such as a silicon semiconductor fin shaped structure. In this embodiment, the semiconductor substrate 10 may include a plurality of the fin shaped structures 10F. Each of the fin shaped structures 10F may be elongated in a first direction D1, the fin shaped structures 10F may be arranged repeatedly in a second direction D2, and the first direction D1 may be substantially perpendicular to the second direction D2, but not limited thereto. The fin shaped structures 10F may be formed by performing a patterning process (such as a multiple exposure process and an etching process) to the semiconductor substrate 10. The isolation structure 20 is disposed between the fin shaped structures 10F.
  • The isolation structure 20 may be regarded as a shallow trench isolation, and the isolation structure 20 may include a single layer or multiple layers of insulation materials, such as an oxide insulation material, but not limited thereto. Each of the fin shaped structures 10F may be partly covered by the isolation structure 20 and partly not covered by the isolation structure 20. The portion of each of the fin shaped structures 10F which is not covered by the isolation structure 20 may be located above a top surface of the isolation structure 20 (such as a first top surface S1 shown in FIG. 1) in a thickness direction of the semiconductor substrate 10 (such as a third direction D3 shown in FIG. 1 and FIG. 2), and the first top surface S1 may be the topmost surface of the isolation structure 20 in the third direction D3, but not limited thereto. Specifically, each of the fin shaped structures 10F may include a third portion P3, a first portion P1, and a second portion P2 sequentially arranged and disposed in the third direction D3. The third portion P3 of each of the fin shaped structures 10F may be covered by the isolation structure 20, and the first portion P1 and the second portion P2 of each of the fin shaped structures 10F are not covered by the isolation structure 20. In other words, the first portion P1 and the second portion P2 of each of the fin shaped structures 10F may be disposed above the first top surface S1 of the isolation structure 20 in the third direction D3, and the second portion P2 is disposed on the first portion P1 in the third direction D3. The first portion P1 and the second portion P2 of each of the fin shaped structures 10F may protrude from the first top surface S1 of the isolation structure 20. A width of the second portion P2 (such as a second width W2 shown in FIG. 1) is smaller than a width of the first portion P1 (such as a first width W1 shown in FIG. 1). Additionally, the first width W1 of the first portion P1 and the second width W2 of the second portion P2 may also be regarded as lengths in the second direction D2, but not limited thereto.
  • The cladding layer 30 is disposed on the first portion P1 and the second portion P2 of each of the fin shaped structures 10F, and the cladding layer 30 includes a curved surface CS. Specifically, the curved surface CS of the cladding layer 30 may be a surface which does not contact the fin shaped structure 10F, but not limited thereto. A width of the cladding layer 30 disposed on one of the fin shaped structures 10F (such as a third width W3 shown in FIG. 1) may be larger than the first width W1 of the first portion P1 of the fin shaped structure 10F because the cladding layer 30 covering the first portion P1 and the second portion P2 of the fin shaped structure 10F has the curved surface CS protruding outwards and the cladding layer 30 may be disposed on two opposite sides of the first portion P1 of each fin shaped structure 10F in the second direction D2 and on two opposite sides of the second portion P2 of each fin shaped structure 10F in the second direction D2. The first width W1, the second width W2, and the third width W3 may be the maximum widths of the first portion P1, the second portion P2, and the cladding layer 30 on one of the fin shaped structures 10F respectively, but not limited thereto. In some embodiments, a lattice constant of the cladding layer 30 may be different from a lattice constant of the fin shaped structures 10F. For example, the material of the cladding layer 30 may include germanium (Ge), silicon germanium (SiGe), silicon phosphide (SiP), or other suitable semiconductor materials. The first portion P1 and the second portion P2 of the fin shaped structure 10F and the cladding layer 30 may be regarded as the channel region in the semiconductor device 101. Additionally, the cladding layer 30 disposed on two adjacent fin shaped structures 10F may be separated from each other, but not limited thereto. In some embodiments, the cladding layer 30 disposed on the two opposite sides of the first portion P1 and the second portion P2 of each of the fin shaped structures 10F may provide a compressive stress to the first portion P1 and the second portion P2 of each of the fin shaped structures 10F for enhancing the carrier mobility of the channel region, but not limited thereto.
  • In some embodiments, the cladding layer 30 may be disposed on a sidewall of the first portion P1 (such as a first sidewall SW1 shown in FIG. 1) of each of the fin shaped structures 10F and a sidewall of the second portion P2 (such as a second sidewall SW2 shown in FIG. 1) of each of the fin shaped structures 10F. A slope of the first sidewall SW1 of the first portion P1 of each of the fin shaped structures 10F may be smaller than a slope of the second sidewall SW2 of the second portion P2 of each of the fin shaped structures 10F. A horizontal plane (such as a plane formed by the first direction D1 and the second direction D2) may be used to calculate the slope of the first sidewall SW1 and the slope of the second sidewall SW2 mentioned above, but not limited thereto. In other words, the second sidewall SW2 of the second portion P2 of each fin shaped structure 10F may be steeper than the first sidewall SW1 of the first portion P1, and the distribution of the first sidewall SW1 and the second sidewall SW2 may be formed by an etching process, but not limited thereto.
  • As shown in FIG. 1 and FIG. 2, the gate structure 40G is disposed straddling the fin shaped structures 10F. In some embodiments, the gate structure 40G may be elongated in the second direction D2, but not limited thereto. Additionally, the gate structure 40G may include a dummy gate structure, a metal gate structure, or other suitable types of gate structures. The dummy gate structure mentioned above may be a dummy gate structure used in a replacement metal gate (RMG) process, and the material of the dummy gate structure may include a semiconductor material such as polysilicon and amorphous silicon, but not limited thereto. In some embodiments, the gate structure 40G may also include conductive materials and insulation materials according to other considerations, such as a low resistivity metal conductive material, a work function metal layer, and a high dielectric constant (high-k) dielectric layer in a metal gate structure, but not limited thereto. Additionally, a spacer 50 may be disposed on sidewalls of the gate structure 40G. The material of the spacer 50 may include oxide, nitride, oxynitride, or other suitable insulation materials, and the spacer 50 may be formed by a single layer or multiple layers of the materials mentioned above. In some embodiments, the spacer 50 may partly disposed on the cladding layer 30, but not limited thereto. Additionally, the gate structure 40G may be partially disposed on the cladding layer 30. The contact area between the gate structure 40G and the cladding layer 30 may be increased because the cladding layer 30 has the curved surface CS protruding outwards, and the electrical performance of the semiconductor device 101 may be enhanced accordingly. Additionally, in some embodiments, a top surface of the second portion P2 (such as a second top surface S2 shown in FIG. 1) of each of the fin shaped structures 10F may not be covered by the cladding layer 30, but not limited thereto.
  • Please refer to FIGS. 3-5 and FIG. 1. FIGS. 3-5 are schematic drawings illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present invention, and FIG. 1 may be regarded as a schematic drawing in a step subsequent to FIG. 5. As shown in FIG. 1, the manufacturing method of the semiconductor device 101 may include the following steps. Firstly, the semiconductor substrate 10 is provided, and the semiconductor substrate 10 includes the fin shaped structures 10F. The isolation structure 20 is formed between the fin shaped structures 10F. Each of the fin shaped structures 10F includes the first portion P1 and the second portion P2. The first portion P1 is disposed above the first top surface S1 of the isolation structure 20 in the third direction D3, and the second portion P2 is disposed on the first portion P1. The second width W2 of the second portion P2 is smaller than the first width W1 of the first portion P1. Subsequently, the cladding layer 30 is formed on the first portion P1 and the second portion P2 of each of the fin shaped structures 10F, and the cladding layer 30 includes the curved surface CS. The gate structure 40G is formed straddling the fin shaped structures 10F.
  • Specifically, the manufacturing method of the semiconductor device 101 in this embodiment may include but is not limited to the following steps. As shown in FIG. 3, after performing the patterning process to the semiconductor substrate 10 for forming the fin shaped structures 10F, an isolation material is formed on the semiconductor substrate 10 and the fin shaped structures 10F, and an etching back process is performed to the isolation material for exposing the top portion of each of the fin shaped structures 10F and forming the isolation structure 20. In other words, the first top surface S1 of the isolation structure 20 is lower than the topmost surface of each of the fin shaped structures 10F in the third direction D3. Subsequently, as shown in FIG. 4, an etching process 91 is performed to the part of each of the fin shaped structures 10F which is not covered by the isolation structure 20 for forming the first portion P1 and the second portion P2 mentioned above. In other words, in some embodiments, the first portion P1 and the second portion P2 of each of the fin shaped structures 10F is formed by performing the etching process 91 to the fin shaped structures after the step of forming the isolation structure 20, but not limited thereto. It is worth noting that the etching process 91 may include an isotropic etching process, such as a wet etching process using tetramethylammonium hydroxide (TMAH) or wet etching processes using other suitable etchants. The differences in width and sidewall conditions between the first portion P1 and the second portion P2 of each of the fin shaped structures 10F may be obtained by the difference in etching rate between different lattice directions of the fin shaped structure 10F in the etchant of the wet etching process. For example, when the fin shaped structures 10F are silicon fin shaped structures, the etching rate of the <111> surface of silicon in TMAH is lower than the etching rate of the <100> surface of silicon in TMAH, the first portion P1 may be formed with larger width, and the slope of the first sidewall SW1 of the first portion P1 may be smaller than the slope of the second sidewall SW2 of the second portion P2 accordingly.
  • As shown in FIG. 5, the cladding layer 30 is subsequently formed on the first portion P1 and the second portion P2 of each of the fin shaped structures 10F. In some embodiments, the step of forming the cladding layer 30 may include a selective epitaxial growth (SEG) process 92, but the present invention is not limited to this. In some embodiments, other processes such as a deposition process and a patterning process may also be used to form the cladding layer 30 according to other considerations. The third width W3 of the cladding layer 30 formed on one of the fin shaped structures 10F may be larger than the first width W1 of the first portion P1 of the fin shaped structure 10F because the cladding layer 30 covering the first portion P1 and the second portion P2 of the fin shaped structure 10F has the curved surface CS protruding outwards and the cladding layer 30 may be formed on two opposite sides of the first portion P1 of each fin shaped structure 10F in the second direction D2 and on two opposite sides of the second portion P2 of each fin shaped structure 10F in the second direction D2. Additionally, the cladding layer 30 may be formed on the first sidewall SW1 of the first portion P1 of each fin shaped structure 10F and on the second sidewall SW2 of the second portion P2 of each fin shaped structure 10F, and the slope of the first sidewall SW1 may be smaller than the slope of the second sidewall SW2. As shown in FIG. 1, the gate structure 40G and the spacer 50 are formed subsequently. In other words, in some embodiments, the gate structure 40G may be formed after the step of forming the cladding layer 30, and the gate structure 40G may include a dummy gate structure, a metal gate structure, or other suitable types of gate structures. In addition, the gate structure 40G may be partially formed on the cladding layer 30, and the gate structure 40G may be formed between the cladding layers 30 on two of the fin shaped structures 10F adjacent to each other in the second direction D2.
  • As shown in FIG. 1 and FIG. 2, in some embodiments, source/drain regions may be formed in portions of the fin shaped structures 10F and the cladding layer 30 which are not covered by the gate structure 40G. The source/drain regions may be formed by performing one or more doping processes to the portions of the fin shaped structures 10F and the cladding layer 30 which are not covered by the gate structure 40G, or the portions of the fin shaped structures 10F and the cladding layer 30 which are not covered by the gate structure 40G may be partially removed for forming epitaxial layers of source/drain regions. In other words, in some embodiments, the epitaxial layers of the source/drain regions and the cladding layer 30 of the channel region may be formed together for process simplification, but not limited thereto.
  • The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.
  • Please refer to FIG. 6. FIG. 6 is a schematic drawing illustrating a semiconductor device 102 according to a second embodiment of the present invention. As shown in FIG. 6, the difference between the semiconductor device 102 and the semiconductor device of the first embodiment mentioned above is that, in the semiconductor device 102, the cladding layer 30 may be further disposed on the second top surface S2 of the second portion P2 of each of the fin shaped structures 10F. In other words, in the manufacturing method of the semiconductor device 102, the cladding layer 30 may be further formed on the second top surface S2 of the second portion P2 of each of the fin shaped structures 10F by modifying the process conditions for forming the cladding layer 30 (such as the process conditions of the selective epitaxial growth process).
  • Please refer to FIGS. 7-11. FIGS. 7-11 are schematic drawings illustrating a manufacturing method of a semiconductor device according to a third embodiment of the present invention. As shown in FIG. 7, the difference between the manufacturing method in this embodiment and the manufacturing method in the first embodiment mentioned above is that a dummy gate structure 40D may be formed straddling the fin shaped structures 10F. In some embodiments, the material of the dummy gate structure 40D may include a semiconductor material such as polysilicon and amorphous silicon, but not limited thereto. In addition, the spacer 50 may be formed on the sidewall of the dummy gate structure 40D, and an interlayer dielectric layer 60 may be formed covering the dummy gate structure 40D and the spacer 50. Subsequently, a planarization process such as a chemical mechanical polishing process may be performed to remove the interlayer dielectric layer 60 above the dummy gate structure 40D and expose the dummy gate structure 40D. As shown in FIG. 8, the dummy gate structure 40D is removed for forming a gate trench TR surrounded by the spacer 50 and exposing apart of each of the fin shaped structures 10F. In other words, the gate trench TR may expose the top portion of each of the fin shaped structures 10F which is not covered by the isolation structure 20. As shown in FIG. 9, the etching process 91 is performed subsequently for forming the first portion P1 and the second portion P2 of each of the fin shaped structures 10F. In other words, as shown in FIGS. 7-9, in some embodiments, the dummy gate structure 40D may be formed before the etching process 91, and the dummy gate structure 40D may be removed before the etching process 91, but not limited thereto. Subsequently, as shown in FIG. 10, a process, such as a selective epitaxial growth process, may be performed to form the cladding layer 30 on the first portion P1 and the second portion P2 of each of the fin shaped structures 10F exposed by the gate trench TR. As shown in FIG. 9 and FIG. 10, the gate structure 40G may then be formed in the gate trench TR, and the gate structure 40G may include a metal gate structure 40M. In some embodiments, the metal gate structure 40M may be composed of a high-k dielectric layer, a work function metal layer, a barrier layer, and a low resistivity metal conductive material, but not limited thereto. In other words, the semiconductor device 103 in this embodiment may include the metal gate structure 40M straddling the fin shaped structures 10F and the cladding layer 30.
  • To summarize the above descriptions, in the semiconductor device and the manufacturing method according to the present invention, the first portion and the second portion of the fin shaped structure above the top surface of the isolation structure may be formed by the etching process, and the width of the second portion is smaller than the width of the first portion. The cladding layer having the curved surface is formed on the first portion and the second portion of the fin shaped structure. The first portion and the second portion of the fin shaped structure and the cladding layer may form the channel region of the semiconductor device. The cladding layer disposed on the two opposite sides of the first portion and the second portion of the fin shaped structure may provide a compressive stress to the fin shaped structure for enhancing the carrier mobility of the channel region. Additionally, the contact area between the gate structure and the cladding layer may be increased because the cladding layer has the curved surface protruding outwards, and the electrical performance of the semiconductor device may be further enhanced accordingly.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (23)

1: A semiconductor device, comprising:
a semiconductor substrate comprising fin shaped structures;
an isolation structure disposed between the fin shaped structures, wherein each of the fin shaped structures comprises:
a first portion disposed above a top surface of the isolation structure; and
a second portion disposed on the first portion, wherein a width of the second portion is smaller than a width of the first portion;
a cladding layer disposed on the first portion and the second portion of each of the fin shaped structures, wherein the cladding layer comprises a curved surface;
a gate structure disposed straddling the fin shaped structures and the cladding layer disposed on each of the fin structures and
a spacer disposed directly on the cladding layer, wherein a material composition of the spacer comprises oxide or oxynitride.
2: The semiconductor device according to claim 1, wherein the gate structure is partially disposed on the cladding layer.
3: The semiconductor device according to claim 1, wherein the first portion and the second portion of each of the fin shaped structures protrude from the top surface of the isolation structure.
4: The semiconductor device according to claim 1, wherein a maximum width of the cladding layer disposed on one of the fin shaped structures is larger than the width of the first portion of the fin shaped structure.
5: The semiconductor device according to claim 1, wherein the cladding layer is disposed on a sidewall of the first portion of each of the fin shaped structures and a sidewall of the second portion of each of the fin shaped structures.
6: The semiconductor device according to claim 5, wherein the cladding layer is further disposed on a top surface of the second portion of each of the fin shaped structures.
7: The semiconductor device according to claim 5, wherein a slope of the first sidewall of the first portion of each of the fin shaped structures is smaller than a slope of the second sidewall of the second portion of each of the fin shaped structures.
8: The semiconductor device according to claim 1, wherein a lattice constant of the cladding layer is different from a lattice constant of each of the fin shaped structures.
9: A manufacturing method of a semiconductor device, comprising:
providing a semiconductor substrate, the semiconductor substrate comprising fin shaped structures;
forming an isolation structure between the fin shaped structures, wherein each of the fin shaped structures comprises:
a first portion disposed above a top surface of the isolation structure; and
a second portion disposed on the first portion, wherein a width of the second portion is smaller than a width of the first portion;
forming a cladding layer on the first portion and the second portion of each of the fin shaped structures, wherein the cladding layer comprises a curved surface; and
forming a gate structure straddling the fin shaped structures.
10: The manufacturing method of the semiconductor device according to claim 9, wherein the gate structure is partially formed on the cladding layer.
11: The manufacturing method of the semiconductor device according to claim 9, wherein the first portion and the second portion of each of the fin shaped structures is formed by performing an etching process to the fin shaped structures after the step of forming the isolation structure.
12: The manufacturing method of the semiconductor device according to claim 11, wherein the etching process comprises a wet etching process using tetramethylammonium hydroxide (TMAH).
13: The manufacturing method of the semiconductor device according to claim 11, further comprising:
forming a dummy gate structure straddling the fin shaped structures before the etching process; and
removing the dummy gate structure for exposing a part of each of the fin shaped structures before the etching process.
14: The manufacturing method of the semiconductor device according to claim 9, wherein the gate structure is formed after the step of forming the cladding layer, and the gate structure comprises a dummy gate structure or a metal gate structure.
15: The manufacturing method of the semiconductor device according to claim 9, wherein a width of the cladding layer formed on one of the fin shaped structures is larger than the width of the first portion of the fin shaped structure.
16: The manufacturing method of the semiconductor device according to claim 9, wherein the cladding layer is formed on a sidewall of the first portion of each of the fin shaped structures and a sidewall of the second portion of each of the fin shaped structures.
17: The manufacturing method of the semiconductor device according to claim 16, wherein the cladding layer is further formed on a top surface of the second portion of each of the fin shaped structures.
18: The manufacturing method of the semiconductor device according to claim 16, wherein a slope of the first sidewall of the first portion of each of the fin shaped structures is smaller than a slope of the second sidewall of the second portion of each of the fin shaped structures.
19: The manufacturing method of the semiconductor device according to claim 9, wherein the step of forming the cladding layer comprises a selective epitaxial growth (SEG) process.
20: The manufacturing method of the semiconductor device according to claim 9, wherein a lattice constant of the cladding layer is different from a lattice constant of each of the fin shaped structures.
21: The semiconductor device according to claim 1, wherein a part of the gate structure is disposed between two of the fin structures adjacent to each other and disposed between the cladding layers disposed on the two fin structures adjacent to each other.
22: The semiconductor device according to claim 1, wherein a top surface of the second portion of each of the fin shaped structures is not covered by the cladding layer.
23: The semiconductor device according to claim 1, wherein a topmost surface of the cladding is not higher than a top surface of the second portion of each of the fin shaped structures.
US15/880,492 2018-01-15 2018-01-25 Semiconductor device and manufacturing method thereof Active US10366991B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201810035934.7 2018-01-15
CN201810035934.7A CN110047926B (en) 2018-01-15 2018-01-15 Semiconductor device and method for manufacturing the same
CN201810035934 2018-01-15

Publications (2)

Publication Number Publication Date
US20190221562A1 true US20190221562A1 (en) 2019-07-18
US10366991B1 US10366991B1 (en) 2019-07-30

Family

ID=67214261

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/880,492 Active US10366991B1 (en) 2018-01-15 2018-01-25 Semiconductor device and manufacturing method thereof

Country Status (2)

Country Link
US (1) US10366991B1 (en)
CN (1) CN110047926B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220147616A1 (en) * 2020-11-11 2022-05-12 Red Hat, Inc. Implementing trusted clients using secure execution environments

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7705345B2 (en) * 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US7615806B2 (en) * 2005-10-31 2009-11-10 Freescale Semiconductor, Inc. Method for forming a semiconductor structure and structure thereof
US9455348B2 (en) * 2007-02-01 2016-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET for device characterization
US8174073B2 (en) * 2007-05-30 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structures with multiple FinFETs
US9312179B2 (en) * 2010-03-17 2016-04-12 Taiwan-Semiconductor Manufacturing Co., Ltd. Method of making a finFET, and finFET formed by the method
US9076817B2 (en) * 2011-08-04 2015-07-07 International Business Machines Corporation Epitaxial extension CMOS transistor
US8659032B2 (en) * 2012-01-31 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US20130200483A1 (en) * 2012-02-08 2013-08-08 United Microelectronics Corp. Fin structure and method of forming the same
CN103367253B (en) * 2012-03-29 2015-03-11 中芯国际集成电路制造(上海)有限公司 Fin type field effect transistor forming method
US8785909B2 (en) * 2012-09-27 2014-07-22 Intel Corporation Non-planar semiconductor device having channel region with low band-gap cladding layer
JP6309299B2 (en) * 2013-02-27 2018-04-11 ルネサスエレクトロニクス株式会社 Semiconductor device having compressive strain channel region and manufacturing method thereof
US9472652B2 (en) * 2013-12-20 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of semiconductor device
WO2015099680A1 (en) * 2013-12-23 2015-07-02 Intel Corporation Pre-sculpting of si fin elements prior to cladding for transistor channel applications
US9853154B2 (en) * 2014-01-24 2017-12-26 Taiwan Semiconductor Manufacturing Company Ltd. Embedded source or drain region of transistor with downward tapered region under facet region
US9136356B2 (en) * 2014-02-10 2015-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Non-planar field effect transistor having a semiconductor fin and method for manufacturing
US10403626B2 (en) 2014-03-24 2019-09-03 Intel Corporation Fin sculpting and cladding during replacement gate process for transistor channel applications
US10153372B2 (en) 2014-03-27 2018-12-11 Intel Corporation High mobility strained channels for fin-based NMOS transistors
US9985030B2 (en) * 2014-04-07 2018-05-29 International Business Machines Corporation FinFET semiconductor device having integrated SiGe fin
US9263555B2 (en) * 2014-07-03 2016-02-16 Globalfoundries Inc. Methods of forming a channel region for a semiconductor device by performing a triple cladding process
CN106328702B (en) * 2015-06-15 2020-03-06 联华电子股份有限公司 Method for filling gaps of semiconductor element and semiconductor element formed by method
CN107026084B (en) * 2016-02-02 2020-03-31 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method for manufacturing the same
US9847392B1 (en) * 2016-10-11 2017-12-19 United Microelectronics Corp. Semiconductor device and method for fabricating the same

Also Published As

Publication number Publication date
US10366991B1 (en) 2019-07-30
CN110047926B (en) 2023-08-29
CN110047926A (en) 2019-07-23

Similar Documents

Publication Publication Date Title
US10580864B2 (en) Method of forming semiconductor device
US10170623B2 (en) Method of fabricating semiconductor device
TWI682467B (en) Fabricating method of fin field effect transistor, semiconductor device and fabricating method thereof
TWI542007B (en) Device and method for manufacturing the same
US9530777B2 (en) FinFETs of different compositions formed on a same substrate
US8975129B1 (en) Method of making a FinFET device
US10263095B2 (en) Method of forming semiconductor fin structure
US10818660B2 (en) Semiconductor device
CN112530943A (en) Semiconductor device and method for manufacturing the same
JPWO2006006438A1 (en) Semiconductor device and manufacturing method thereof
US10490627B2 (en) Semiconductor structure and manufacturing method thereof
US20170170300A1 (en) Fin field effect transistor, semiconductor device and fabricating method thereof
US9076870B2 (en) Method for forming fin-shaped structure
CN106158748B (en) Semiconductor element and manufacturing method thereof
US10043675B2 (en) Semiconductor device and method for fabricating the same
US9929153B2 (en) Method of making a FinFET device
US10366991B1 (en) Semiconductor device and manufacturing method thereof
US10460997B2 (en) Manufacturing method of semiconductor device
US10431497B1 (en) Manufacturing method of epitaxial fin-shaped structure

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNITED MICROELECTRONICS CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TING, HSU;LIN, YU-YING;CHEN, YEN-HSING;AND OTHERS;REEL/FRAME:044734/0054

Effective date: 20180124

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4