US20190214253A1 - SiGe FINS FORMED ON A SUBSTRATE - Google Patents
SiGe FINS FORMED ON A SUBSTRATE Download PDFInfo
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- US20190214253A1 US20190214253A1 US16/358,227 US201916358227A US2019214253A1 US 20190214253 A1 US20190214253 A1 US 20190214253A1 US 201916358227 A US201916358227 A US 201916358227A US 2019214253 A1 US2019214253 A1 US 2019214253A1
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 124
- 239000000758 substrate Substances 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 230000001590 oxidative effect Effects 0.000 claims description 9
- 230000000873 masking effect Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 description 14
- 230000003647 oxidation Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
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- 238000004519 manufacturing process Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
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- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02634—Homoepitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
Description
- SiGe Fin field-effect transistor (FinFET) semiconductor structures are a viable option for continued scaling of FinFET to 10 nm and beyond, however, there are two major issues with SiGe fin fabrication. SiGe fins formed by growing a SiGe layer on a bulk Si substrate is limited by the so-called critical thickness. When SiGe is grown on Si, beyond the critical thickness, dislocations start to generate in SiGe films, resulting in defective SiGe fins. Isolation of SiGe fin from the bulk Si is not trivial. N-type dopants (e.g., phosphorus or arsenic) are used for a punchthrough stopping region under SiGe fins to suppress source/drain punchthrough. Unfortunately, N-type dopants have a greater diffusion rate in SiGe than in Si, resulting in undesired encroachment of punchthrough Si (PTS) dopants into SiGe channel, resulting in degradation of device performance and increase of device variability.
- Embodiments relate to semiconductor structures, in particular, for defect-free silicon-germanium (SiGe)-on-insulator fins formed on a bulk silicon (Si) substrate and a method of manufacturing the same. In one embodiment, a semiconductor structure includes at least one SiGe fin with a first width. The semiconductor structure includes at least one Si fin with a second width. An oxide layer isolates the at least one SiGe fin with the first width from a substrate. The at least one SiGe fin with the first width, the at least one Si fin with the second width and a surface of the substrate below the at least one Si fin are each oxidized.
- In one embodiment, a method includes selectively forming a SiGe layer on a substrate by epitaxially growing the SiGe layer on a top surface of the substrate. At least one fin with a first width is formed from the SiGe layer by forming a masking layer on the top surface of the SiGe layer, etching the at least one fin with the first width, and forming a spacer layer on the at least one fin with the first width. At least one other fin with a second width is formed from the substrate by etching the substrate to form the at least one other fin with the second width. The second width is less than the first width. The spacer layer is selectively removed from the at least one fin with the first width. The at least one fin with the first width, the at least one other fin with the second width and a surface of the substrate below the at least one other fin with the second width are oxidized. The first width is condensed in width to a target width. The at least one other fin is completely oxidized forming an oxide layer between the at least one fin with the first width and the substrate.
- These and other features, aspects and advantages of the embodiments will become understood with reference to the following description, appended claims and accompanying figures.
-
FIG. 1 is a cross-sectional view of an exemplary semiconductor structure with a silicon-germanium (SiGe) layer formed on a substrate, according to one embodiment; -
FIG. 2 is a cross-sectional view of a result of the exemplary structure ofFIG. 1 after selective formation of at least one SiGe fin with a first width from the SiGe layer, according to an embodiment; -
FIG. 3 is a cross-sectional view of a result of the exemplary structure ofFIG. 2 after forming a spacer layer, according to an embodiment; -
FIG. 4 is a cross-sectional view of the result of the exemplary structure ofFIG. 3 after formation of at least one silicon (Si) fin with a second width from the substrate, according to an embodiment; -
FIG. 5 is a cross-sectional view of the result of the exemplary structure ofFIG. 4 after selectively removing the spacer layer from the SiGe fins, according to an embodiment; -
FIG. 6 is a cross-sectional view of the result of the exemplary structure ofFIG. 5 after condensing the at least one SiGe fin with the first width and the at least one Si fin with the second width, according to an embodiment; -
FIG. 7 is a cross-sectional view of the result of the exemplary structure ofFIG. 6 after selectively removing an oxide layer from the at least one SiGe fin with a first width, according to an embodiment; and -
FIG. 8 illustrates a block diagram for a process for forming defect-free silicon-germanium (SiGe)-on-insulator fins on a bulk Si substrate, according to one embodiment. - The descriptions of the various embodiments have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
- As used herein, a “lengthwise” element is an element that extends along a corresponding lengthwise direction, and a “widthwise” element is an element that extends along a corresponding widthwise direction.
-
FIG. 1 is a cross-sectional view of anexemplary semiconductor structure 100 with a silicon-germanium (SiGe)layer 102 formed on asubstrate 100, according to one embodiment. In one embodiment, thesubstrate 100 is a commercial silicon (Si) substrate atop which theSiGe layer 102 is formed. In one embodiment, theSiGe layer 102 is epitaxially grown atop thesubstrate 100. In one embodiment, the SiGelayer 102 has a relatively low Ge percentage (e.g., 5-15 percent) as compared to the overall makeup of theSiGe layer 102. The low Ge percentage in the SiGelayer 102 allows for the manufacture of taller SiGe fins without defects. Further, theSiGe layer 102 is taller than the desired SiGe fins (112,FIG. 6 ), taking into account the height and width reduction in the condensing step (208,FIG. 8 ). In one embodiment, the SiGe layer may be gown to a height of at least 50 nm. It is appreciated that the taller the SiGe layer, the taller the resultant SiGe fins can be manufactured. -
FIG. 2 is a cross-sectional view of a result of theexemplary structure 100 ofFIG. 1 after selective formation of at least oneSiGe fin 104 with a first width from the SiGe layer 102 (FIG. 1 ), according to an embodiment. In this embodiment, prior to formation of the SiGe fins 104 ahardmask layer 106 is applied and/or formed on a top surface of the SiGe layer 102 (FIG. 1 ). In one embodiment, the hardmask layer is silicon nitride and applied in the conventional spacer image and transfer (STI) process. The SiGefins 104 are formed in a conventional process (e.g., dry etching, wet etching, etc.). At this point in the process, theSiGe fins 104 have a first width which is greater than the width of the SiGe fins after the condensing/oxidation step (208,FIG. 8 ). In one embodiment, the first width of theSiGe fins 104 is 20 nm, where the target/final width may be 8 nm. -
FIG. 3 is a cross-sectional view of a result of theexemplary structure 100 ofFIG. 2 after forming aspacer layer 108, according to an embodiment. In this embodiment, thespacer layer 108 is applied only to the sidewalls of the SiGefins 104. Thespacer layer 108 may be made up of the same material as the hardmask 106 (e.g., silicon-nitride) or distinct from the hardmask 106 (e.g., oxide). In one embodiment, the thickness of thespacer layer 108 is less than the thickness of thehardmask layer 106 to allow for subsequent removal (e.g., etching) of thespacer layer 106 from theSiGe fins 104 while maintaining thehardmask layer 106. -
FIG. 4 is a cross-sectional view of the result of theexemplary structure 100 ofFIG. 3 after formation of at least oneSi fin 110 with a second width from thesubstrate 100, according to an embodiment. In this embodiment, only portions of thesubstrate 100 is selective removed (e.g., dry etching, wet etching, etc.) to form Si fins 110. It is appreciated that for eachSiGe fin 104, there is acorresponding Si fin 110. Further, theSi fins 110 have a width which is less than the width of theSiGe fins 104. This allows for complete oxidation of theSi fins 110 without complete oxidation of theSiGe fins 104 at the condensing/oxidation step (208,FIG. 8 ). In one embodiment theSi fins 104 have a width of 10 nm. -
FIG. 5 is a cross-sectional view of the result of theexemplary structure 100 ofFIG. 4 after selectively removing thespacer layer 108 from theSiGe fins 104, according to an embodiment. In one embodiment, the spacer layer 108 (FIG. 4 ) is selectively removed from thestructure 100 by etching (e.g., wet etching, dry etching, time etching, etc.). -
FIG. 6 is a cross-sectional view of the result of theexemplary structure 100 ofFIG. 5 after condensing the at least oneSiGe fin 104 with the first width and the at least oneSi fin 110 with the second width, according to one embodiment. In this embodiment, condensing thestructure 100 includes performing an oxidation to each of theSiGe fins 104, the Si fins 110 (FIG. 5 ) and the top surface of thesubstrate 100. In one embodiment, theSi fins 110 are completely oxidized by the condensing/oxidization process, forming an oxide layer (e.g. barrier) between theSiGe fins 104 and thesubstrate 100. Oxidization of theSiGe fins 104 to remove a portion of the Si from the SiGe fins results inSiGe fins 112 with a higher Ge percentage as compared to the percentage of Ge in the SiGe layer 102 (FIG. 1 ). Oxidization also has the effect of condensing the width of the SiGe fins. In this embodiment, the oxide layer (e.g., barrier) 114 isolates theSiGe fins 112 from thesubstrate 100. The result is that in this configuration, there is no need to employ a punchthrough, thus reducing the risk of leakage into the substrate. - For example, with
SiGe fins 104 having a 20 nm width and theSi fins 110 having a 10 nm width, a 20 nm oxidization of theSiGe fins 104 andSi fins 110 will result in fully oxidized Si fins oxidize 12 nm oxidization of theSiGe fin 112. As a result, the percentage of Ge in theoxidized SiGe fins 112 is higher than the percentage of Ge to Si in the SiGe layer 102 (e.g., 25 percent compared to 10 percent). Moreover, the higherGe SiGe fins 112 have been condensed in width to their target width (8 nm in this example). -
FIG. 7 is a cross-sectional view of the result of theexemplary structure 100 ofFIG. 6 after selectively removing an oxide layer 114 (FIG. 6 ) from the at least one SiGe fin with a first width (112), according to one embodiment. In this embodiment, the oxide layer 114 (FIG. 6 ) is selectively removed from the side surfaces of theSiGe fins 102 having a higher concentration ofGe 112. Here, theoxide layer 114 may be thermal oxide. Further, anitride liner 116 may be deposited on the surface of theoxide layer 114 and then aflowable oxide layer 118 may be deposited on thenitride liner 116. It will be appreciated that complete Fin field-effect transistor (FinFET) fabrication is not detailed inFIG. 7 . -
FIG. 8 illustrates a block diagram for aprocess 200 for forming defect-free silicon-germanium (SiGe)-on-insulator fins 112 (FIG. 7 ) on a bulk silicon (Si) substrate 100 (FIG. 7 ), according to one embodiment. In one embodiment, in block 202 a SiGe layer is formed on a top surface of a substrate. The SiGe layer may be formed by epitaxially growing the SiGe on a Si substrate. In one embodiment, the SiGe layer will have a percentage of Ge of between 5-15% compared to the percentage of Si. Moreover, the SiGe layer will have an optimal height greater than a height of formed SiGe fins to account for condensing of the fin inblock 208. - In one embodiment, in
block 204 formation of SiGe fins may comprise forming a hardmask layer (106,FIG. 2 ) on a top surface of the SiGe layer (102,FIG. 2 ), then etching the SiGe fins from the SiGe layer. In one embodiment, the hardmask layer is silicon nitride and applied in the conventional spacer image and transfer (STI) process. The resultant SiGe fins have a first width which is greater than the width of the SiGe fins after the condensingstep 208. For example, with a target width of 8 nm, the SiGe fins formed inblock 204 may have a thickness of 20 nm. - In one embodiment, block 206 comprises applying a spacer layer 108 (
FIG. 4 ) to the side surfaces of the SiGe fins 104 (FIG. 4 ). Thereafter, the Si fins 110 (FIG. 4 ) are formed (e.g., etched) from the substrate 100 (FIG. 4 ). In one embodiment, after forming theSi fins 110, thespacer layer 108 is removed from the SiGe fins 104 (FIG. 5 ). In one embodiment, the spacer layer 108 (FIG. 4 ) is selectively removed from thestructure 100 by etching (e.g., wet etching, dry etching, time etching, etc.). - In one embodiment,
step 208 involves condensing the SiGe fins 104 (FIG. 6 ) by means of oxidizing theSiGe fins 104,Si fins 110 and the top surface of the substrate 100 (FIG. 5 ). By oxidizing Si from the SiGe fins, the resultant fin has a higher percentage of Ge as compared to the percentage of Ge in the SiGe layer. Further, the resultant fin has a width more narrow than the fabricated (pre-oxidized) SiGe fins inblock 204. - Moreover, in one embodiment, as a result of condensing the SiGe fins and Si fins in
block 208, the Si is fully oxidized from the Si fins, resulting in the formation of an oxide layer 114 (FIG. 6 ) isolating the SiGe fins from the substrate. - In one embodiment, by forming the
Si fins 204, the Si fins have a width which is less than the width of the SiGe fins 104 (FIG. 5 ) to allow for complete oxidation of theSi fins 110 without complete oxidation of theSiGe fins 104 during condensing 208. - The exemplary methods and techniques described herein may be used in the fabrication of IC chips. In one embodiment, the IC chips may be distributed by a fabricator in raw wafer form (i.e., as a single wafer that has multiple unpackaged IC chips), as a bare die, or in a packaged form. In the latter case, the IC chip is mounted in a single IC chip package (e.g., a plastic carrier with leads that are affixed to a motherboard or other higher level carrier) or in a multiIC chip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). The IC chip is then integrated with other IC chips, discrete circuit elements and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product, such as microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, toys and digital cameras, as non-limiting examples. One or more embodiments may be applied in any of various highly integrated semiconductor devices.
- Unless described otherwise or in addition to that described herein, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited, including, but not limited to: CVD, LPCVD, PECVD, semi-atmosphere CVD (SACVD), high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, PVD, ALD, chemical oxidation, MBE, plating or evaporation. Any references to “poly” or “poly silicon” should be understood to refer to polycrystalline silicon.
- References herein to terms such as “vertical”, “horizontal,” etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to the conventional plane or surface of the substrate, regardless of the actual spatial orientation of the semiconductor substrate. The term “vertical” refers to a direction perpendicular to the horizontal, as just defined. Terms, such as “on,” “above,” “below,” “side” (as in “sidewall”), “higher,” “lower,” “over,” “beneath” and “under,” are defined with respect to the horizontal plane. It is understood that various other frames of reference may be employed for describing one or more embodiments without departing from the spirit and scope of the one or more embodiments.
- References in the claims to an element in the singular is not intended to mean “one and only” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described exemplary embodiment that are currently known or later come to be known to those of ordinary skill in the art are intended to be encompassed by the present claims. No claim element herein is to be construed under the provisions of 35 U.S.C.
section 112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or “step for.” - The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, materials, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, materials, components, and/or groups thereof.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the embodiments. The embodiment was chosen and described in order to best explain the principles of the embodiments and the practical application, and to enable others of ordinary skill in the art to understand the embodiments with various modifications as are suited to the particular use contemplated.
Claims (11)
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US16/358,227 US20190214253A1 (en) | 2015-11-30 | 2019-03-19 | SiGe FINS FORMED ON A SUBSTRATE |
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US14/954,581 US10297448B2 (en) | 2015-11-30 | 2015-11-30 | SiGe fins formed on a substrate |
US16/358,227 US20190214253A1 (en) | 2015-11-30 | 2019-03-19 | SiGe FINS FORMED ON A SUBSTRATE |
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US16/358,227 Abandoned US20190214253A1 (en) | 2015-11-30 | 2019-03-19 | SiGe FINS FORMED ON A SUBSTRATE |
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US10297448B2 (en) * | 2015-11-30 | 2019-05-21 | International Business Machines Corporation | SiGe fins formed on a substrate |
US20190157160A1 (en) * | 2017-11-20 | 2019-05-23 | Qualcomm Incorporated | Bulk finfet with self-aligned bottom isolation |
KR102620595B1 (en) | 2018-01-22 | 2024-01-03 | 삼성전자주식회사 | Semiconductor device including insulating layers and method of manufacturing the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8048723B2 (en) * | 2008-12-05 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs having dielectric punch-through stoppers |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7705345B2 (en) | 2004-01-07 | 2010-04-27 | International Business Machines Corporation | High performance strained silicon FinFETs device and method for forming same |
KR20050108916A (en) * | 2004-05-14 | 2005-11-17 | 삼성전자주식회사 | Methods of forming a fin field effect transistor using damascene process |
EP2009679A1 (en) * | 2007-06-25 | 2008-12-31 | Interuniversitair Microelektronica Centrum (IMEC) | Semiconductor device |
US8106459B2 (en) * | 2008-05-06 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs having dielectric punch-through stoppers |
US7871873B2 (en) * | 2009-03-27 | 2011-01-18 | Global Foundries Inc. | Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material |
EP2284870B1 (en) * | 2009-08-12 | 2012-02-22 | Imec | Method for forming a floating gate non-volatile memory cell |
US8211772B2 (en) * | 2009-12-23 | 2012-07-03 | Intel Corporation | Two-dimensional condensation for uniaxially strained semiconductor fins |
US8395195B2 (en) * | 2010-02-09 | 2013-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bottom-notched SiGe FinFET formation using condensation |
US8735869B2 (en) * | 2012-09-27 | 2014-05-27 | Intel Corporation | Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates |
US20140120678A1 (en) | 2012-10-29 | 2014-05-01 | Matheson Tri-Gas | Methods for Selective and Conformal Epitaxy of Highly Doped Si-containing Materials for Three Dimensional Structures |
US9082853B2 (en) * | 2012-10-31 | 2015-07-14 | International Business Machines Corporation | Bulk finFET with punchthrough stopper region and method of fabrication |
US8987823B2 (en) * | 2012-11-07 | 2015-03-24 | International Business Machines Corporation | Method and structure for forming a localized SOI finFET |
US9299809B2 (en) * | 2012-12-17 | 2016-03-29 | Globalfoundries Inc. | Methods of forming fins for a FinFET device wherein the fins have a high germanium content |
US9202917B2 (en) * | 2013-07-29 | 2015-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Buried SiGe oxide FinFET scheme for device enhancement |
US8951870B2 (en) | 2013-03-14 | 2015-02-10 | International Business Machines Corporation | Forming strained and relaxed silicon and silicon germanium fins on the same wafer |
US8975125B2 (en) * | 2013-03-14 | 2015-03-10 | International Business Machines Corporation | Formation of bulk SiGe fin with dielectric isolation by anodization |
US8895395B1 (en) | 2013-06-06 | 2014-11-25 | International Business Machines Corporation | Reduced resistance SiGe FinFET devices and method of forming same |
US9093534B2 (en) * | 2013-07-29 | 2015-07-28 | International Business Machines Corporation | Dielectric filler fins for planar topography in gate level |
US9093326B2 (en) | 2013-10-21 | 2015-07-28 | International Business Machines Corporation | Electrically isolated SiGe fin formation by local oxidation |
US9209202B2 (en) * | 2014-02-11 | 2015-12-08 | Broadcom Corporation | Enabling bulk FINFET-based devices for FINFET technology with dielectric isolation |
US9147616B1 (en) * | 2014-08-28 | 2015-09-29 | Globalfoundries Inc. | Methods of forming isolated fins for a FinFET semiconductor device with alternative channel materials |
US20160268378A1 (en) * | 2015-03-12 | 2016-09-15 | Globalfoundries Inc. | Integrated strained fin and relaxed fin |
US9711535B2 (en) * | 2015-03-13 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming FinFET channel |
US9773705B2 (en) * | 2015-06-30 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET channel on oxide structures and related methods |
CN107851664A (en) * | 2015-09-25 | 2018-03-27 | 英特尔公司 | Technology for the sub- fin electric leakage of controlling transistor |
US10297448B2 (en) * | 2015-11-30 | 2019-05-21 | International Business Machines Corporation | SiGe fins formed on a substrate |
US9484347B1 (en) * | 2015-12-15 | 2016-11-01 | International Business Machines Corporation | FinFET CMOS with Si NFET and SiGe PFET |
US11018254B2 (en) * | 2016-03-31 | 2021-05-25 | International Business Machines Corporation | Fabrication of vertical fin transistor with multiple threshold voltages |
US10256328B2 (en) * | 2016-05-18 | 2019-04-09 | International Business Machines Corporation | Dummy dielectric fins for finFETs with silicon and silicon germanium channels |
US10446669B2 (en) * | 2017-11-30 | 2019-10-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain surface treatment for multi-gate field effect transistors |
US10396151B1 (en) * | 2018-06-14 | 2019-08-27 | International Business Machines Corporation | Vertical field effect transistor with reduced gate to source/drain capacitance |
-
2015
- 2015-11-30 US US14/954,581 patent/US10297448B2/en not_active Expired - Fee Related
-
2019
- 2019-03-19 US US16/358,240 patent/US20190214254A1/en not_active Abandoned
- 2019-03-19 US US16/358,227 patent/US20190214253A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8048723B2 (en) * | 2008-12-05 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs having dielectric punch-through stoppers |
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US20190214254A1 (en) | 2019-07-11 |
US20170154788A1 (en) | 2017-06-01 |
US10297448B2 (en) | 2019-05-21 |
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