US20190165144A1 - Smoothing surface roughness of iii-v semiconductor fins formed from silicon mandrels by regrowth - Google Patents
Smoothing surface roughness of iii-v semiconductor fins formed from silicon mandrels by regrowth Download PDFInfo
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- US20190165144A1 US20190165144A1 US15/827,607 US201715827607A US2019165144A1 US 20190165144 A1 US20190165144 A1 US 20190165144A1 US 201715827607 A US201715827607 A US 201715827607A US 2019165144 A1 US2019165144 A1 US 2019165144A1
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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Definitions
- the present invention generally relates to alleviating surface roughness on grown III-V semiconductor fins, and more particularly to epitaxially growing III-V semiconductor on the rough mandrel growth face of III-V semiconductor fins.
- a Field Effect Transistor typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the channel.
- Field Effect Transistors can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and FinFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain.
- the channel for the FinFET can be an upright slab of thin rectangular silicon (Si), commonly referred to as the fin with a gate on the fin, as compared to a MOSFET with a single gate parallel with the plane of the substrate.
- Si thin rectangular silicon
- MOSFET MOSFET with a single gate parallel with the plane of the substrate.
- an n-FET or a p-FET can be formed.
- FETs can include a metal-oxide-semiconductor field effect transistor (MOSFET) and an insulated-gate field-effect transistor (IGFET). Two FETs also can be coupled to form a complementary metal oxide semiconductor (CMOS) device, where a p-channel MOSFET and n-channel MOSFET are coupled together.
- MOSFET metal-oxide-semiconductor field effect transistor
- IGFET insulated-gate field-effect transistor
- a method of forming a III-V semiconductor vertical fin includes forming a fin mandrel on a substrate. The method further includes forming a spacer layer on the substrate surrounding the fin mandrel. The method further includes forming a wetting layer on each of the sidewalls of the fin mandrel. The method further includes forming a fin layer on each of the wetting layers. The method further includes removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.
- a method of forming a III-V semiconductor vertical fin includes forming a fin mandrel on a substrate. The method further includes forming a spacer layer on the substrate surrounding the fin mandrel. The method further includes forming a wetting layer on each of the sidewalls of the fin mandrel. The method further includes forming a fin layer on each of the wetting layers, where the fin layer is a binary or ternary III-V semiconductor material. The method further includes removing the fin mandrel and removing the wetting layer on each of the fin layers.
- the method further includes forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers, and forming a dummy gate layer over a middle section of a vertical fin including the fin layer regrowth and the fin layer.
- a III-V semiconductor vertical fin device in accordance with yet another embodiment of the present invention, includes a spacer layer on a substrate, wherein the material of the spacer layer is a flowable oxide, a vertical fin on the spacer layer, where the vertical fin is a binary or ternary III-V semiconductor material, and a gate structure over a middle section of the vertical fin.
- FIG. 1 is a cross-sectional side view showing a plurality of fin mandrels formed on a substrate and a mandrel template on each fin mandrel, in accordance with an embodiment of the present invention
- FIG. 2 is a cross-sectional side view showing a spacer layer between each pair of the plurality of fin mandrels, in accordance with an embodiment of the present invention
- FIG. 3 is a cross-sectional side view showing a wetting layer on the sidewalls of each fin mandrel and mandrel template, in accordance with an embodiment of the present invention
- FIG. 4 is a cross-sectional side view showing a fin layer formed on the wetting layers on each of the fin mandrels and mandrel templates, in accordance with an embodiment of the present invention
- FIG. 5 is a cross-sectional side view showing a fill layer on the fin layers and mandrel templates, in accordance with an embodiment of the present invention
- FIG. 6 is a cross-sectional side view showing removal of extraneous fin layer islands from the top surface of the mandrel templates, in accordance with an embodiment of the present invention
- FIG. 7 is a cross-sectional side view showing the fin layers, wetting layers, fin templates, and spacer layer after removing the fill layer, in accordance with an embodiment of the present invention.
- FIG. 8 is a cross-sectional side view showing the fin layers and wetting layers on the spacer layer after removing the fin templates and reducing the height of the fin mandrels, in accordance with an embodiment of the present invention
- FIG. 9 is a cross-sectional side view showing the fin layers after removing the wetting layers, in accordance with an embodiment of the present invention.
- FIG. 10 is a top view showing the dummy gate layer formed on a middle section of the fin layers, and fin layer regrowth on the rough sidewalls of the fin layers, in accordance with an embodiment of the present invention
- FIG. 11 is a cross-sectional side view showing the dummy gate layer formed on a portion of the fin layers along the A-A cutting plane of FIG. 10 , in accordance with an embodiment of the present invention
- FIG. 12 is a top view showing source/drains formed on the fin layers and fin layer regrowth on opposite sides of the dummy gate layer, in accordance with an embodiment of the present invention.
- FIG. 13 is a cross-sectional side view showing source/drains on the fin layers and fin layer regrowths along the B-B cutting plane of FIG. 12 , in accordance with an embodiment of the present invention
- FIG. 14 is a top view showing cover layers formed on the source/drains on opposite sides of the dummy gate layer, in accordance with an embodiment of the present invention.
- FIG. 15 is a cross-sectional side view showing the cover layer on the source/drains along the B-B cutting plane of FIG. 14 , in accordance with an embodiment of the present invention.
- FIG. 16 is a top view showing the fin layers and an oxide layer exposed after removing the dummy gate layer from between the cover layers, in accordance with an embodiment of the present invention
- FIG. 17 is a top view showing the fin layer regrowth on the middle section of the fin layers to form a plurality of vertical fins on the spacer layer, in accordance with an embodiment of the present invention
- FIG. 18 is a cross-sectional side view showing the fin layer regrowth on the middle section of the fin layers along the A-A cutting plane of FIG. 17 , in accordance with an embodiment of the present invention.
- FIG. 19 is a top view showing a gate structure formed on the middle section of the vertical fins, in accordance with an embodiment of the present invention.
- Embodiments of the present invention relate generally to growing III-V semiconductor fins on a wetting layer, removing the wetting layer, and growing additional III-V semiconductor material to smooth the rough surface exposed by removing the wetting layer.
- Embodiments of the present invention also relate generally to smoothing the rough face of a III-V semiconductor fin by additional epitaxial growth of the III-V semiconductor fin.
- III-V semiconductor fins grown on (111) silicon mandrel sidewalls can have excessively rough surfaces at the Si/III-V semiconductor interface that can reduce and/or limit electron transport properties of subsequently fabricated devices.
- the Si/III-V interface can be significantly rougher than the exposed growth front of the fin.
- Embodiments of the present invention also relate generally to smoothing the rough face of a III-V semiconductor fin by growing the additional III-V material before replacement of a dummy gate structure. Thick III-V semiconductor fins can be thinned to a final width by using a digital etch (e.g., a plasma oxidation and acid rinse).
- a digital etch e.g., a plasma oxidation and acid rinse
- Exemplary applications/uses to which the present invention can be applied include, but are not limited to: Complementary metal-oxide-semiconductor devices and static random access memory devices, where the present invention can be applied to transistors having high speed or lower power usage in the logic and memory devices.
- FIG. 1 a cross-sectional side view of a plurality of fin mandrels formed on a substrate and a mandrel template on each fin mandrel is shown, in accordance with an embodiment of the present invention.
- a substrate 110 can be, for example, a single crystal semiconductor material wafer or a semiconductor-on-insulator stacked wafer.
- the substrate can include a support layer that provides structural support, and an active semiconductor layer that can form devices.
- An insulating layer may be between the active semiconductor layer and the support layer to form a semiconductor-on-insulator substrate (SeOI) (e.g., a silicon-on-insulator substrate (SOI)).
- the substrate can be a single crystal silicon wafer.
- the active semiconductor layer can be a crystalline semiconductor, for example, a IV or IV-IV semiconductor (e.g., silicon (Si), silicon carbide (SiC), silicon-germanium (SiGe), germanium (Ge)), or a III-V semiconductor (e.g., gallium-arsenide (GaAs), indium-phosphide (InP), indium-antimonide (InSb)).
- a IV or IV-IV semiconductor e.g., silicon (Si), silicon carbide (SiC), silicon-germanium (SiGe), germanium (Ge)
- a III-V semiconductor e.g., gallium-arsenide (GaAs), indium-phosphide (InP), indium-antimonide (InSb)
- substrates with crystal structures similar to silicon single crystal that can form (111) crystal planes can be used.
- one or more fin mandrels 120 can be formed on the substrate 110 .
- the fin mandrels 120 can be formed from the substrate by masking portions of the substrate with mandrel templates 130 having the predetermined dimensions of the fin mandrel, and etching the substrate using a crystallographic wet etch, such as tetramethyl ammonium hydroxide (TMAH)), that can etch essentially straight sidewalls 122 for the fin mandrels 120 , or a combination of a directional etch (e.g., Reactive Ion Etch (RIE)) and crystallographic wet etch.
- TMAH tetramethyl ammonium hydroxide
- RIE Reactive Ion Etch
- the crystallographic wet etch can be used to obtain a smooth face for epitaxial growth, where the (111) crystal face can be atomically smooth.
- the mandrel templates 130 can be a hardmask, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon boronitride (SiBN), silicon carbonitride (SiCN), silicon borocarbonitride (SiBCN), or a combination thereof.
- silicon oxide SiO
- silicon nitride SiN
- silicon oxynitride SiON
- silicon boronitride SiBN
- SiCN silicon carbonitride
- SiBCN silicon borocarbonitride
- the fin mandrels 120 can be single crystal silicon, where the fin mandrels 120 are formed from a single crystal silicon substrate 110 .
- the mandrel templates 130 and fin mandrels 120 can be aligned with the crystal planes of the single crystal substrate, such that the exposed faces of the sidewalls 122 of the fin mandrels 120 are ⁇ 111 ⁇ silicon crystal faces.
- FIG. 2 is a cross-sectional side view showing a spacer layer between each pair of the plurality of fin mandrels, in accordance with an embodiment of the present invention.
- a spacer layer 140 can be formed on the exposed surface of the substrate 110 , where the spacer layer 140 can be between adjacent pairs of the fin mandrels 120 .
- the spacer layer can surround each of the fin mandrels on the substrate 110 .
- the spacer layer 140 can be made of a dielectric material, including, but not limited to a flowable oxide (e.g., hydrogen silsesquioxane (HSQ)) or a silicon oxide (SiO).
- a flowable oxide e.g., hydrogen silsesquioxane (HSQ)
- SiO silicon oxide
- the flowable oxide can be blanket deposited on the substrate 110 , mandrel templates 130 , and fin mandrels 120 , and flowable oxide extending above the mandrel templates 130 removed using a chemical-mechanical polishing (CMP).
- CMP chemical-mechanical polishing
- the silicon oxide can be formed using a high density plasma (HDP) and excess silicon oxide removed using CMP.
- the spacer layer 140 can be recessed to a predetermined height by a controlled, selective etch to expose a predetermined height of the fin mandrel sidewalls 122 .
- the fin mandrels 120 can have exposed sidewalls 122 with a height in the range of about 30 nm to about 70 nm, or in the range of about 30 nm to about 50 nm, or in the range of about 50 nm to about 70 nm, after recessing the spacer layer 140 .
- the exposed fin mandrel sidewalls can have a (111) crystal face.
- FIG. 3 is a cross-sectional side view showing a wetting layer on the sidewalls of each fin mandrel and mandrel template, in accordance with an embodiment of the present invention.
- a wetting layer 150 can be formed on the exposed sidewalls 122 of the one or more fin mandrels 120 , where the exposed sidewalls 122 can be ⁇ 111 ⁇ crystal faces.
- the wetting layer 150 can be formed by a metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition/atomic layer epitaxy (ALD/ALE).
- MOCVD metal-organic chemical vapor deposition
- ALD/ALE atomic layer deposition/atomic layer epitaxy
- the wetting layer 150 forms on the exposed sidewalls 122 of the one or more fin mandrels 120 without forming on the exposed top surface of the spacer layer 140 .
- the wetting layer 150 may form on the top surfaces of the mandrel templates 130 , but not on the surface of the spacer layer 140 .
- the wetting layer 150 can be made of III-V semiconductor materials, for example, aluminum arsenide (AlAs) or indium phosphide (InP).
- AlAs aluminum arsenide
- InP indium phosphide
- the wetting material can be selected based on the ability to deposit on ⁇ 111 ⁇ crystal faces of the exposed sidewalls 122 of the fin mandrels.
- the crystal lattice of the wetting material may not be matched to the ⁇ 111 ⁇ crystal faces of the sidewalls 122 .
- the wetting layer 150 can have a thickness on the sidewalls of the fin mandrels 120 in the range of about 1 nm to about 10 nm, or in the range of about 1 nm to about 2 nm, or in the range of about 5 nm to about 7 nm, where the wetting layer is sufficiently thick to completely cover each the sidewalls 122 of the fin mandrels 120 .
- FIG. 4 is a cross-sectional side view showing a fin layer formed on the wetting layers on each of the fin mandrels and mandrel templates, in accordance with an embodiment of the present invention.
- a fin layer 160 can be formed on each of the wetting layers 150 , where the fin layer 160 can be a binary or ternary III-V semiconductor material.
- the fin layer can be formed by a heteroepitaxial growth process, where the fin layer 160 can grow laterally on the wetting layer 150 from the sidewalls of the fin mandrel 120 .
- the fin layer 160 can be formed by a metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition/atomic layer epitaxy (ALD/ALE).
- MOCVD metal-organic chemical vapor deposition
- ALD/ALE atomic layer deposition/atomic layer epitaxy
- the fin layer 160 forms on the wetting layers 150 without forming on the exposed top surface of the spacer layer 140 .
- Fin layer islands 165 can form on the tops surfaces of the mandrel templates 130 , for example, when the mandrel templates 130 are silicon nitride (SiN), from extraneous material forming the fin layer 160 .
- the fin layer islands 165 can be randomly oriented single crystals or polycrystalline deposits of the III-V fin layer material.
- the fin layer 160 can be made of a binary or tertiary III-V semiconductor material, including, but not limited to, indium phosphide (InP), indium arsenide (InAs), indium-gallium-arsenide (InGaAs), and combinations thereof (e.g., multilayers, heterostructures).
- indium phosphide InP
- InAs indium arsenide
- InGaAs indium-gallium-arsenide
- combinations thereof e.g., multilayers, heterostructures.
- the fin layer 160 can be grown to a thickness in the range of about 10 nm to about 35 nm, or in the range of about 10 nm to about 30 nm, or in the range of about 15 nm to about 25 nm, where the smoothness of the exposed surface of the fin layer can improve with increasing thickness.
- FIG. 5 is a cross-sectional side view showing a fill layer on the fin layers and mandrel templates, in accordance with an embodiment of the present invention.
- a fill layer 170 can be formed on the fin layers 160 , wetting layers 150 , fin layer islands 165 , exposed portions of the mandrel templates 130 , and exposed portions of the spacer layer 140 .
- the fill layer 170 can be made of amorphous silicon (a-Si), amorphous carbon (a-C), a flowable oxide (e.g. polymeric silicon oxides (SiO), for example, HSQ), a spin-on-glass, or an organic resist material/organic planarization material.
- a fill layer 170 made of a flowable oxide may be densified.
- the fill layer 170 can be formed to a height that covers the tops of the extraneous fin layer islands 165 .
- the top surface of the fill layer 170 can be chemically-mechanically polished to provide a smooth, flat surface.
- FIG. 6 is a cross-sectional side view showing removal of extraneous fin layer islands from the top surface of the mandrel templates, in accordance with an embodiment of the present invention.
- an upper portion of the fill layer 170 and the fin layer islands 165 can be removed, where the upper portion of the fill layer 170 and the fin layer islands 165 can be removed by a chemical-mechanical polishing (CMP).
- CMP chemical-mechanical polishing
- FIG. 7 is a cross-sectional side view showing the fin layers, wetting layers, fin templates, and spacer layer after removing the fill layer, in accordance with an embodiment of the present invention.
- the fill layer 170 can be removed after the CMP to re-expose portions of the fin layers 160 , wetting layers 150 , fin templates 130 , and spacer layer 140 , where the fill layer 170 can be removed using a selective etch.
- FIG. 8 is a cross-sectional side view showing the fin layers and wetting layers on the spacer layer after removing the fin templates and reducing the height of the fin mandrels, in accordance with an embodiment of the present invention.
- the fin templates 130 can be removed from the top surfaces of the fin mandrels 120 , where the fin templates 130 can be removed using a selective wet or dry etch, for example, RIE, dry plasma etch, basic oxide etch (BOE), phosphoric acid, etc.
- RIE reactive ion etch
- BOE basic oxide etch
- the height of the fin mandrels 120 can be reduced to form fin mandrel slabs 125 , where the height of the fin mandrels can be reduced to expose the sidewalls of the wetting layers 150 .
- the height of the fin mandrels 120 can be reduced below the top surfaces of the spacer layer 140 , such that the entire sidewall of the wetting layers 150 are exposed.
- the top surfaces of the fin mandrel slabs can be less than the height of the spacer layer 140 .
- the height of the fin mandrels 120 can be reduced using a selective wet or dry etch.
- the spacer layer 140 can support the fin layers 160 and wetting layers 150 after removal of the fin mandrels from the wetting layers.
- FIG. 9 is a cross-sectional side view showing the fin layers after removing the wetting layers, in accordance with an embodiment of the present invention.
- the wetting layers 150 can be removed to expose the rough sidewalls 167 of the fin layers 160 .
- the wetting layers 150 can be removed using a wet chemical etch, for example, hydrochloric acid (HCl) etch or ammonium hydroxide (NH 4 OH) etch.
- HCl hydrochloric acid
- NH 4 OH ammonium hydroxide
- the wetting layers 150 and fin mandrels 120 can be etched at the same time.
- a dry plasma etch or hydrogen fluoride (HF) etch may not be used.
- FIG. 10 is a top view showing the dummy gate layer formed on a middle section of the fin layers, and fin layer regrowth on the rough sidewalls of the fin layers, in accordance with an embodiment of the present invention.
- a dummy gate layer 180 can be formed across a central portion of one or more of the fin layers 160 .
- the fin layers 160 can be masked, and a trench formed in the mask over a predetermined portion of the fin layers, where the dummy gate layer 180 can be formed across a central portion of one or more of the fin layers 160 .
- the dummy gate layer 180 can define a gate length of a subsequently formed gate structure on the vertical fins.
- the dummy gate layer 180 can have a width in the range of about 10 nm to about 1 ⁇ m, or in the range of about 20 nm to about 100 nm, or in the range of about 10 nm to about 70 nm, or in the range of about 10 nm to about 30 nm.
- the dummy gate layer 180 can be made of a material, including, but not limited to, amorphous silicon (a-Si), amorphous carbon (a-C), silicon-germanium (SiGe), flowable oxide, or silicon nitride (SiN).
- a-Si amorphous silicon
- a-C amorphous carbon
- SiGe silicon-germanium
- SiN silicon nitride
- the material of the dummy gate 180 can selectively etchable relative to the spacer layer 140 and subsequently formed cover layers, or the material of the dummy gate and spacer layer can be the same.
- fin layer regrowth 220 can be formed on the exposed rough sidewalls 167 of the fin layers 160 , where the fin layer regrowth 220 can be formed by epitaxial growth.
- the fin layer 160 and fin layer regrowth 220 can form the two components of a vertical fin 190 .
- the fin layer regrowth 220 can be formed on the exposed rough sidewalls 167 of the fin layers 160 before or after the dummy gate layer is formed.
- the fin layer regrowth 220 can be the same III-V semiconductor material as the fin layer 160 III-V semiconductor material.
- FIG. 11 is a cross-sectional side view showing the dummy gate layer formed on a portion of the fin layers along the A-A cutting plane of FIG. 10 , in accordance with an embodiment of the present invention.
- the dummy gate layer 180 can extend above the top surfaces of the fin layers 160 , and fill in the shallow area over the fin mandrel slabs 125 .
- the mask material can be removed after formation of the dummy gate layer 180 .
- FIG. 12 is a top view showing source/drains formed on the fin layers and fin layer regrowth on opposite sides of the dummy gate layer, in accordance with an embodiment of the present invention.
- source/drains 200 can be formed on opposite sides of the dummy gate layer 180 on the exposed portions of the fin layers 160 and fin layer regrowth 220 forming the vertical fins 190 .
- the source/drains 200 can be formed by epitaxial growth on the exposed surfaces of the vertical fins 190 adjacent to the dummy gate layer 180 .
- the epitaxial growth can be terminated before the source/drains 200 merge across all the fin layers 160 , or the source/drains 200 can grow laterally until source/drains 200 on adjacent fin layers merge.
- Sections of the fin mandrel slabs 125 can be exposed between adjacent, unmerged, source/drains 200 . Merged source/drains can cover the fin mandrel slabs 125 and prevent shorting and substrate leakage from metal contacts.
- the source/drains 200 can be made of the same material as the fin layers 160 and fin layer regrowths 220 , where the source/drains are formed by epitaxial growth on single crystal fin layers 160 and fin layer regrowths 220 .
- a layer of InAs can be formed on the source/drains 200 to improve electrical contact.
- the source/drains can be doped with an n-type dopant to form an N-type fin field effect transistor (FinFET).
- FinFET N-type fin field effect transistor
- FIG. 13 is a cross-sectional side view showing source/drains on the fin layers and fin layer regrowths along the B-B cutting plane of FIG. 12 , in accordance with an embodiment of the present invention.
- a source/drain 200 can be formed on three sides of one or more adjacent fin layers 160 and fin layer regrowths 220 , where the source/drain 200 can grow from the exposed surfaces of the fin layer 160 .
- the source/drain 200 can overhang an edge of the spacer layer, where a portion of the bottom surface of the source/drain can be exposed.
- Adjacent source/drains 200 can grow to a size at which they merge into a single source/drain 200 spanning two or more adjacent fin layers 160 and fin layer regrowths 220 forming the vertical fins. There can be a gap between the merged source/drain 200 and top surface of the fin mandrel slab 125 .
- an oxide layer 129 can form on the fin mandrel slabs 125 , where the oxide layer 129 can be a native oxide layer (e.g., silicon oxide (SiO)) formed from the fin mandrel slab material.
- the oxide layer 129 can be thinner than the depth of the gap between the bottom surface of the source/drains 200 or merged source/drain 200 and the top surface of the fin mandrel slab 125 , so there can still be a gap between the merged source/drain 200 and surface of the oxide layer 129 , or the oxide layer can be sufficiently thick to fill the gap.
- a native oxide layer can remain, since a hydrogen fluoride (HF) etch may not be used.
- the oxide layer 129 can prevent formation of the III-V fin layer regrowth 220 on the fin mandrel slabs 125 .
- FIG. 14 is a top view showing cover layers formed on the source/drains on opposite sides of the dummy gate layer, in accordance with an embodiment of the present invention.
- a cover layer 210 can be formed over the source/drains 200 and the fin mandrel slabs 125 , where the cover layer can fill in the gaps between the source/drains 200 .
- the cover layer can be a dielectric material that physically and electrically isolates adjacent source/drains 200 .
- the cover layer can be formed by CVD, a spin-on process, or HDP.
- the dummy gate material can be selectively etchable relative to the cover layer 210 .
- the cover layer 210 can be flowable oxide, silicon oxide (SiO), silicon nitride (SiN), or a combination thereof.
- a CMP can be used to remove excess cover layer 210 and planarize the cover layer 210 at the level of the top of the dummy gate layer 180 .
- FIG. 15 is a cross-sectional side view showing the cover layer on the source/drains along the B-B cutting plane of FIG. 14 , in accordance with an embodiment of the present invention.
- the cover layer 210 can extend above the top surfaces of the source/drains 200 and fill in the gaps between the source/drains.
- FIG. 16 is a top view showing the fin layers and an oxide layer exposed after removing the dummy gate layer from between the cover layers, in accordance with an embodiment of the present invention.
- the dummy gate layer 180 can be removed, where the dummy gate layer can be removed using a selective isotropic etch (e.g., a wet chemical etch). Removal of the dummy gate layer can expose the central portion of the fin layers 160 , spacer layer 140 , and oxide layer 129 on fin mandrel slabs 125 , between the source/drains 200 and the cover layers 210 .
- a selective isotropic etch e.g., a wet chemical etch
- FIG. 17 is a top view showing the fin layer regrowth on the middle section of the fin layers to form a plurality of vertical fins on the spacer layer, in accordance with an embodiment of the present invention.
- fin layer regrowth 220 can be formed on the exposed rough surfaces of the fin layers 160 , where the fin layer regrowth 220 can be formed by epitaxial growth.
- the fin layer regrowth 220 can be the same III-V semiconductor material as the fin layer 160 III-V semiconductor material.
- the fin layer 160 and fin layer regrowth 220 can form the two components of a vertical fin 190 , where the fin layer regrowth 220 formed on the fin layer 160 exposed by removing the dummy gate layer 180 can be in physical and electrical contact with the fin layer regrowth 220 under the source/drains 200 .
- FIG. 18 is a cross-sectional side view showing the fin layer regrowth on the fin layers along the A-A cutting plane of FIG. 17 , in accordance with an embodiment of the present invention.
- the fin regrowth layer 220 can have a thickness in the range of about 6 nm to about 25 nm, or in the range of about 10 nm to about 20 nm, where the thickness of the fin regrowth layer 220 is sufficient to cover the rough surface 167 and reduce the roughness of the exposed surfaces of the vertical fins 190 .
- the oxide layer 129 can be formed on the fin mandrel slabs 125 , where the oxide layer 129 can be a native oxide that formed on the fin mandrel slabs 125 during processing.
- the oxide layer 129 can be thinner than the depth of the gap between the bottom surface of the source/drains 200 or merged source/drain 200 and the top surface of the fin mandrel slab 125 , so there can still be a gap between the fin regrowth layer 220 and surface of the oxide layer 129 , or the oxide layer can be sufficiently thick to fill the gap.
- the oxide layer 129 can prevent formation of the III-V fin layer regrowth 220 on the fin mandrel slabs 125 .
- the width of the vertical fin 190 can be reduced using a digital etch, where the III-V semiconductor structure can be thinned using a two-step plasma oxidation and acid etch.
- FIG. 19 is a top view showing a gate structure formed on the middle section of the vertical fins, in accordance with an embodiment of the present invention.
- a gate structure can be formed on the vertical fins formed by the fin layer 160 and fin regrowth layer 220 forming the vertical fins 190 .
- the gate structure can be formed by depositing a gate dielectric layer on the exposed portions of the vertical fins 190 , depositing a work metal layer on the gate dielectric layer, and depositing a conductive gate fill on the work function layer.
- a CMP can be used to remove excess conductive gate fill and planarize the conductive gate fill at the level of the top of the cover layers 210 .
- electrical contacts can be formed to the source/drains 200 and the gate structure.
- the present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly.
- the stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer.
- the photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes Si x Ge 1-x where x is less than or equal to 1, etc.
- SiGe includes Si x Ge 1-x where x is less than or equal to 1, etc.
- other elements can be included in the compound and still function in accordance with the present principles.
- the compounds with additional elements will be referred to herein as alloys.
- any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B).
- such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C).
- This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below.
- the device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.
- a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.
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Abstract
Description
- The present invention generally relates to alleviating surface roughness on grown III-V semiconductor fins, and more particularly to epitaxially growing III-V semiconductor on the rough mandrel growth face of III-V semiconductor fins.
- A Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the channel. Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and FinFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain. The channel for the FinFET can be an upright slab of thin rectangular silicon (Si), commonly referred to as the fin with a gate on the fin, as compared to a MOSFET with a single gate parallel with the plane of the substrate. Depending on the doping of the source and drain, an n-FET or a p-FET can be formed.
- Examples of FETs can include a metal-oxide-semiconductor field effect transistor (MOSFET) and an insulated-gate field-effect transistor (IGFET). Two FETs also can be coupled to form a complementary metal oxide semiconductor (CMOS) device, where a p-channel MOSFET and n-channel MOSFET are coupled together.
- With ever decreasing device dimensions, forming the individual components and electrical contacts becomes more difficult. An approach is therefore needed that retains the positive aspects of traditional FET structures, while overcoming the scaling issues created by forming smaller device components.
- In accordance with an embodiment of the present invention, a method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate. The method further includes forming a spacer layer on the substrate surrounding the fin mandrel. The method further includes forming a wetting layer on each of the sidewalls of the fin mandrel. The method further includes forming a fin layer on each of the wetting layers. The method further includes removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.
- In accordance with another embodiment of the present invention, a method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate. The method further includes forming a spacer layer on the substrate surrounding the fin mandrel. The method further includes forming a wetting layer on each of the sidewalls of the fin mandrel. The method further includes forming a fin layer on each of the wetting layers, where the fin layer is a binary or ternary III-V semiconductor material. The method further includes removing the fin mandrel and removing the wetting layer on each of the fin layers. The method further includes forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers, and forming a dummy gate layer over a middle section of a vertical fin including the fin layer regrowth and the fin layer.
- In accordance with yet another embodiment of the present invention, a III-V semiconductor vertical fin device is provided. The III-V semiconductor vertical fin device includes a spacer layer on a substrate, wherein the material of the spacer layer is a flowable oxide, a vertical fin on the spacer layer, where the vertical fin is a binary or ternary III-V semiconductor material, and a gate structure over a middle section of the vertical fin.
- These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
- The following description will provide details of preferred embodiments with reference to the following figures wherein:
-
FIG. 1 is a cross-sectional side view showing a plurality of fin mandrels formed on a substrate and a mandrel template on each fin mandrel, in accordance with an embodiment of the present invention; -
FIG. 2 is a cross-sectional side view showing a spacer layer between each pair of the plurality of fin mandrels, in accordance with an embodiment of the present invention; -
FIG. 3 is a cross-sectional side view showing a wetting layer on the sidewalls of each fin mandrel and mandrel template, in accordance with an embodiment of the present invention; -
FIG. 4 is a cross-sectional side view showing a fin layer formed on the wetting layers on each of the fin mandrels and mandrel templates, in accordance with an embodiment of the present invention; -
FIG. 5 is a cross-sectional side view showing a fill layer on the fin layers and mandrel templates, in accordance with an embodiment of the present invention; -
FIG. 6 is a cross-sectional side view showing removal of extraneous fin layer islands from the top surface of the mandrel templates, in accordance with an embodiment of the present invention; -
FIG. 7 is a cross-sectional side view showing the fin layers, wetting layers, fin templates, and spacer layer after removing the fill layer, in accordance with an embodiment of the present invention; -
FIG. 8 is a cross-sectional side view showing the fin layers and wetting layers on the spacer layer after removing the fin templates and reducing the height of the fin mandrels, in accordance with an embodiment of the present invention; -
FIG. 9 is a cross-sectional side view showing the fin layers after removing the wetting layers, in accordance with an embodiment of the present invention; -
FIG. 10 is a top view showing the dummy gate layer formed on a middle section of the fin layers, and fin layer regrowth on the rough sidewalls of the fin layers, in accordance with an embodiment of the present invention; -
FIG. 11 is a cross-sectional side view showing the dummy gate layer formed on a portion of the fin layers along the A-A cutting plane ofFIG. 10 , in accordance with an embodiment of the present invention; -
FIG. 12 is a top view showing source/drains formed on the fin layers and fin layer regrowth on opposite sides of the dummy gate layer, in accordance with an embodiment of the present invention; -
FIG. 13 is a cross-sectional side view showing source/drains on the fin layers and fin layer regrowths along the B-B cutting plane ofFIG. 12 , in accordance with an embodiment of the present invention; -
FIG. 14 is a top view showing cover layers formed on the source/drains on opposite sides of the dummy gate layer, in accordance with an embodiment of the present invention; -
FIG. 15 is a cross-sectional side view showing the cover layer on the source/drains along the B-B cutting plane ofFIG. 14 , in accordance with an embodiment of the present invention; -
FIG. 16 is a top view showing the fin layers and an oxide layer exposed after removing the dummy gate layer from between the cover layers, in accordance with an embodiment of the present invention; -
FIG. 17 is a top view showing the fin layer regrowth on the middle section of the fin layers to form a plurality of vertical fins on the spacer layer, in accordance with an embodiment of the present invention; -
FIG. 18 is a cross-sectional side view showing the fin layer regrowth on the middle section of the fin layers along the A-A cutting plane ofFIG. 17 , in accordance with an embodiment of the present invention; and -
FIG. 19 is a top view showing a gate structure formed on the middle section of the vertical fins, in accordance with an embodiment of the present invention. - Embodiments of the present invention relate generally to growing III-V semiconductor fins on a wetting layer, removing the wetting layer, and growing additional III-V semiconductor material to smooth the rough surface exposed by removing the wetting layer.
- Embodiments of the present invention also relate generally to smoothing the rough face of a III-V semiconductor fin by additional epitaxial growth of the III-V semiconductor fin. III-V semiconductor fins grown on (111) silicon mandrel sidewalls can have excessively rough surfaces at the Si/III-V semiconductor interface that can reduce and/or limit electron transport properties of subsequently fabricated devices. The Si/III-V interface can be significantly rougher than the exposed growth front of the fin.
- Embodiments of the present invention also relate generally to smoothing the rough face of a III-V semiconductor fin by growing the additional III-V material before replacement of a dummy gate structure. Thick III-V semiconductor fins can be thinned to a final width by using a digital etch (e.g., a plasma oxidation and acid rinse).
- Exemplary applications/uses to which the present invention can be applied include, but are not limited to: Complementary metal-oxide-semiconductor devices and static random access memory devices, where the present invention can be applied to transistors having high speed or lower power usage in the logic and memory devices.
- It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.
- Referring now to the drawings in which like numerals represent the same or similar elements and initially to
FIG. 1 , a cross-sectional side view of a plurality of fin mandrels formed on a substrate and a mandrel template on each fin mandrel is shown, in accordance with an embodiment of the present invention. - In one or more embodiments, a
substrate 110 can be, for example, a single crystal semiconductor material wafer or a semiconductor-on-insulator stacked wafer. The substrate can include a support layer that provides structural support, and an active semiconductor layer that can form devices. An insulating layer may be between the active semiconductor layer and the support layer to form a semiconductor-on-insulator substrate (SeOI) (e.g., a silicon-on-insulator substrate (SOI)). In one or more embodiments, the substrate can be a single crystal silicon wafer. - The active semiconductor layer can be a crystalline semiconductor, for example, a IV or IV-IV semiconductor (e.g., silicon (Si), silicon carbide (SiC), silicon-germanium (SiGe), germanium (Ge)), or a III-V semiconductor (e.g., gallium-arsenide (GaAs), indium-phosphide (InP), indium-antimonide (InSb)). In various embodiments, substrates with crystal structures similar to silicon single crystal that can form (111) crystal planes can be used.
- In one or more embodiments, one or
more fin mandrels 120 can be formed on thesubstrate 110. The fin mandrels 120 can be formed from the substrate by masking portions of the substrate withmandrel templates 130 having the predetermined dimensions of the fin mandrel, and etching the substrate using a crystallographic wet etch, such as tetramethyl ammonium hydroxide (TMAH)), that can etch essentiallystraight sidewalls 122 for thefin mandrels 120, or a combination of a directional etch (e.g., Reactive Ion Etch (RIE)) and crystallographic wet etch. The crystallographic wet etch can be used to obtain a smooth face for epitaxial growth, where the (111) crystal face can be atomically smooth. - In various embodiments, the
mandrel templates 130 can be a hardmask, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon boronitride (SiBN), silicon carbonitride (SiCN), silicon borocarbonitride (SiBCN), or a combination thereof. - In various embodiments, the
fin mandrels 120 can be single crystal silicon, where thefin mandrels 120 are formed from a singlecrystal silicon substrate 110. Themandrel templates 130 andfin mandrels 120 can be aligned with the crystal planes of the single crystal substrate, such that the exposed faces of thesidewalls 122 of thefin mandrels 120 are {111} silicon crystal faces. -
FIG. 2 is a cross-sectional side view showing a spacer layer between each pair of the plurality of fin mandrels, in accordance with an embodiment of the present invention. - In one or more embodiments, a
spacer layer 140 can be formed on the exposed surface of thesubstrate 110, where thespacer layer 140 can be between adjacent pairs of thefin mandrels 120. The spacer layer can surround each of the fin mandrels on thesubstrate 110. - In various embodiments, the
spacer layer 140 can be made of a dielectric material, including, but not limited to a flowable oxide (e.g., hydrogen silsesquioxane (HSQ)) or a silicon oxide (SiO). The flowable oxide can be blanket deposited on thesubstrate 110,mandrel templates 130, andfin mandrels 120, and flowable oxide extending above themandrel templates 130 removed using a chemical-mechanical polishing (CMP). The silicon oxide can be formed using a high density plasma (HDP) and excess silicon oxide removed using CMP. Thespacer layer 140 can be recessed to a predetermined height by a controlled, selective etch to expose a predetermined height of thefin mandrel sidewalls 122. - In various embodiments, the
fin mandrels 120 can have exposedsidewalls 122 with a height in the range of about 30 nm to about 70 nm, or in the range of about 30 nm to about 50 nm, or in the range of about 50 nm to about 70 nm, after recessing thespacer layer 140. The exposed fin mandrel sidewalls can have a (111) crystal face. -
FIG. 3 is a cross-sectional side view showing a wetting layer on the sidewalls of each fin mandrel and mandrel template, in accordance with an embodiment of the present invention. - In one or more embodiments, a
wetting layer 150 can be formed on the exposed sidewalls 122 of the one ormore fin mandrels 120, where the exposed sidewalls 122 can be {111} crystal faces. Thewetting layer 150 can be formed by a metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition/atomic layer epitaxy (ALD/ALE). In various embodiments, thewetting layer 150 forms on the exposed sidewalls 122 of the one ormore fin mandrels 120 without forming on the exposed top surface of thespacer layer 140. Thewetting layer 150 may form on the top surfaces of themandrel templates 130, but not on the surface of thespacer layer 140. - In various embodiments, the
wetting layer 150 can be made of III-V semiconductor materials, for example, aluminum arsenide (AlAs) or indium phosphide (InP). The wetting material can be selected based on the ability to deposit on {111} crystal faces of the exposed sidewalls 122 of the fin mandrels. The crystal lattice of the wetting material may not be matched to the {111} crystal faces of thesidewalls 122. - In various embodiments, the
wetting layer 150 can have a thickness on the sidewalls of thefin mandrels 120 in the range of about 1 nm to about 10 nm, or in the range of about 1 nm to about 2 nm, or in the range of about 5 nm to about 7 nm, where the wetting layer is sufficiently thick to completely cover each thesidewalls 122 of thefin mandrels 120. -
FIG. 4 is a cross-sectional side view showing a fin layer formed on the wetting layers on each of the fin mandrels and mandrel templates, in accordance with an embodiment of the present invention. - In one or more embodiments, a
fin layer 160 can be formed on each of the wetting layers 150, where thefin layer 160 can be a binary or ternary III-V semiconductor material. The fin layer can be formed by a heteroepitaxial growth process, where thefin layer 160 can grow laterally on thewetting layer 150 from the sidewalls of thefin mandrel 120. Thefin layer 160 can be formed by a metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition/atomic layer epitaxy (ALD/ALE). In various embodiments, thefin layer 160 forms on the wettinglayers 150 without forming on the exposed top surface of thespacer layer 140.Fin layer islands 165 can form on the tops surfaces of themandrel templates 130, for example, when themandrel templates 130 are silicon nitride (SiN), from extraneous material forming thefin layer 160. Thefin layer islands 165 can be randomly oriented single crystals or polycrystalline deposits of the III-V fin layer material. - In various embodiments, the
fin layer 160 can be made of a binary or tertiary III-V semiconductor material, including, but not limited to, indium phosphide (InP), indium arsenide (InAs), indium-gallium-arsenide (InGaAs), and combinations thereof (e.g., multilayers, heterostructures). - In various embodiments, the
fin layer 160 can be grown to a thickness in the range of about 10 nm to about 35 nm, or in the range of about 10 nm to about 30 nm, or in the range of about 15 nm to about 25 nm, where the smoothness of the exposed surface of the fin layer can improve with increasing thickness. -
FIG. 5 is a cross-sectional side view showing a fill layer on the fin layers and mandrel templates, in accordance with an embodiment of the present invention. - In one or more embodiments, a
fill layer 170 can be formed on the fin layers 160, wettinglayers 150,fin layer islands 165, exposed portions of themandrel templates 130, and exposed portions of thespacer layer 140. - In various embodiments, the
fill layer 170 can be made of amorphous silicon (a-Si), amorphous carbon (a-C), a flowable oxide (e.g. polymeric silicon oxides (SiO), for example, HSQ), a spin-on-glass, or an organic resist material/organic planarization material. In various embodiments, afill layer 170 made of a flowable oxide may be densified. Thefill layer 170 can be formed to a height that covers the tops of the extraneousfin layer islands 165. The top surface of thefill layer 170 can be chemically-mechanically polished to provide a smooth, flat surface. -
FIG. 6 is a cross-sectional side view showing removal of extraneous fin layer islands from the top surface of the mandrel templates, in accordance with an embodiment of the present invention. - In one or more embodiments, an upper portion of the
fill layer 170 and thefin layer islands 165 can be removed, where the upper portion of thefill layer 170 and thefin layer islands 165 can be removed by a chemical-mechanical polishing (CMP). The top surface of themandrel templates 130 can be exposed after the CMP. -
FIG. 7 is a cross-sectional side view showing the fin layers, wetting layers, fin templates, and spacer layer after removing the fill layer, in accordance with an embodiment of the present invention. - In one or more embodiments, the
fill layer 170 can be removed after the CMP to re-expose portions of the fin layers 160, wettinglayers 150,fin templates 130, andspacer layer 140, where thefill layer 170 can be removed using a selective etch. -
FIG. 8 is a cross-sectional side view showing the fin layers and wetting layers on the spacer layer after removing the fin templates and reducing the height of the fin mandrels, in accordance with an embodiment of the present invention. - In one or more embodiments, the
fin templates 130 can be removed from the top surfaces of thefin mandrels 120, where thefin templates 130 can be removed using a selective wet or dry etch, for example, RIE, dry plasma etch, basic oxide etch (BOE), phosphoric acid, etc. - In one or more embodiments, the height of the
fin mandrels 120 can be reduced to formfin mandrel slabs 125, where the height of the fin mandrels can be reduced to expose the sidewalls of the wetting layers 150. The height of thefin mandrels 120 can be reduced below the top surfaces of thespacer layer 140, such that the entire sidewall of the wettinglayers 150 are exposed. The top surfaces of the fin mandrel slabs can be less than the height of thespacer layer 140. The height of thefin mandrels 120 can be reduced using a selective wet or dry etch. Thespacer layer 140 can support the fin layers 160 and wettinglayers 150 after removal of the fin mandrels from the wetting layers. -
FIG. 9 is a cross-sectional side view showing the fin layers after removing the wetting layers, in accordance with an embodiment of the present invention. - In one or more embodiments, the wetting
layers 150 can be removed to expose therough sidewalls 167 of the fin layers 160. The wetting layers 150 can be removed using a wet chemical etch, for example, hydrochloric acid (HCl) etch or ammonium hydroxide (NH4OH) etch. In various embodiments, the wettinglayers 150 andfin mandrels 120 can be etched at the same time. A dry plasma etch or hydrogen fluoride (HF) etch may not be used. -
FIG. 10 is a top view showing the dummy gate layer formed on a middle section of the fin layers, and fin layer regrowth on the rough sidewalls of the fin layers, in accordance with an embodiment of the present invention. - In one or more embodiments, a
dummy gate layer 180 can be formed across a central portion of one or more of the fin layers 160. The fin layers 160 can be masked, and a trench formed in the mask over a predetermined portion of the fin layers, where thedummy gate layer 180 can be formed across a central portion of one or more of the fin layers 160. - In various embodiments, the
dummy gate layer 180 can define a gate length of a subsequently formed gate structure on the vertical fins. Thedummy gate layer 180 can have a width in the range of about 10 nm to about 1 μm, or in the range of about 20 nm to about 100 nm, or in the range of about 10 nm to about 70 nm, or in the range of about 10 nm to about 30 nm. - In various embodiments, the
dummy gate layer 180 can be made of a material, including, but not limited to, amorphous silicon (a-Si), amorphous carbon (a-C), silicon-germanium (SiGe), flowable oxide, or silicon nitride (SiN). The material of thedummy gate 180 can selectively etchable relative to thespacer layer 140 and subsequently formed cover layers, or the material of the dummy gate and spacer layer can be the same. - In one or more embodiments,
fin layer regrowth 220 can be formed on the exposedrough sidewalls 167 of the fin layers 160, where thefin layer regrowth 220 can be formed by epitaxial growth. Thefin layer 160 andfin layer regrowth 220 can form the two components of avertical fin 190. Thefin layer regrowth 220 can be formed on the exposedrough sidewalls 167 of the fin layers 160 before or after the dummy gate layer is formed. Thefin layer regrowth 220 can be the same III-V semiconductor material as thefin layer 160 III-V semiconductor material. -
FIG. 11 is a cross-sectional side view showing the dummy gate layer formed on a portion of the fin layers along the A-A cutting plane ofFIG. 10 , in accordance with an embodiment of the present invention. - In one or more embodiments, the
dummy gate layer 180 can extend above the top surfaces of the fin layers 160, and fill in the shallow area over thefin mandrel slabs 125. The mask material can be removed after formation of thedummy gate layer 180. -
FIG. 12 is a top view showing source/drains formed on the fin layers and fin layer regrowth on opposite sides of the dummy gate layer, in accordance with an embodiment of the present invention. - In one or more embodiments, source/drains 200 can be formed on opposite sides of the
dummy gate layer 180 on the exposed portions of the fin layers 160 andfin layer regrowth 220 forming thevertical fins 190. The source/drains 200 can be formed by epitaxial growth on the exposed surfaces of thevertical fins 190 adjacent to thedummy gate layer 180. The epitaxial growth can be terminated before the source/drains 200 merge across all the fin layers 160, or the source/drains 200 can grow laterally until source/drains 200 on adjacent fin layers merge. Sections of thefin mandrel slabs 125 can be exposed between adjacent, unmerged, source/drains 200. Merged source/drains can cover thefin mandrel slabs 125 and prevent shorting and substrate leakage from metal contacts. - In various embodiments, the source/drains 200 can be made of the same material as the fin layers 160 and
fin layer regrowths 220, where the source/drains are formed by epitaxial growth on single crystal fin layers 160 andfin layer regrowths 220. In various embodiments, a layer of InAs can be formed on the source/drains 200 to improve electrical contact. - In various embodiments, the source/drains can be doped with an n-type dopant to form an N-type fin field effect transistor (FinFET).
-
FIG. 13 is a cross-sectional side view showing source/drains on the fin layers and fin layer regrowths along the B-B cutting plane ofFIG. 12 , in accordance with an embodiment of the present invention. - In one or more embodiments, a source/
drain 200 can be formed on three sides of one or more adjacent fin layers 160 andfin layer regrowths 220, where the source/drain 200 can grow from the exposed surfaces of thefin layer 160. The source/drain 200 can overhang an edge of the spacer layer, where a portion of the bottom surface of the source/drain can be exposed. Adjacent source/drains 200 can grow to a size at which they merge into a single source/drain 200 spanning two or more adjacent fin layers 160 andfin layer regrowths 220 forming the vertical fins. There can be a gap between the merged source/drain 200 and top surface of thefin mandrel slab 125. - In various embodiments, an
oxide layer 129 can form on thefin mandrel slabs 125, where theoxide layer 129 can be a native oxide layer (e.g., silicon oxide (SiO)) formed from the fin mandrel slab material. Theoxide layer 129 can be thinner than the depth of the gap between the bottom surface of the source/drains 200 or merged source/drain 200 and the top surface of thefin mandrel slab 125, so there can still be a gap between the merged source/drain 200 and surface of theoxide layer 129, or the oxide layer can be sufficiently thick to fill the gap. A native oxide layer can remain, since a hydrogen fluoride (HF) etch may not be used. Theoxide layer 129 can prevent formation of the III-Vfin layer regrowth 220 on thefin mandrel slabs 125. -
FIG. 14 is a top view showing cover layers formed on the source/drains on opposite sides of the dummy gate layer, in accordance with an embodiment of the present invention. - In one or more embodiments, a
cover layer 210 can be formed over the source/drains 200 and thefin mandrel slabs 125, where the cover layer can fill in the gaps between the source/drains 200. The cover layer can be a dielectric material that physically and electrically isolates adjacent source/drains 200. The cover layer can be formed by CVD, a spin-on process, or HDP. The dummy gate material can be selectively etchable relative to thecover layer 210. - In various embodiments, the
cover layer 210 can be flowable oxide, silicon oxide (SiO), silicon nitride (SiN), or a combination thereof. A CMP can be used to removeexcess cover layer 210 and planarize thecover layer 210 at the level of the top of thedummy gate layer 180. -
FIG. 15 is a cross-sectional side view showing the cover layer on the source/drains along the B-B cutting plane ofFIG. 14 , in accordance with an embodiment of the present invention. - In various embodiments, the
cover layer 210 can extend above the top surfaces of the source/drains 200 and fill in the gaps between the source/drains. -
FIG. 16 is a top view showing the fin layers and an oxide layer exposed after removing the dummy gate layer from between the cover layers, in accordance with an embodiment of the present invention. - In one or more embodiments, the
dummy gate layer 180 can be removed, where the dummy gate layer can be removed using a selective isotropic etch (e.g., a wet chemical etch). Removal of the dummy gate layer can expose the central portion of the fin layers 160,spacer layer 140, andoxide layer 129 onfin mandrel slabs 125, between the source/drains 200 and the cover layers 210. -
FIG. 17 is a top view showing the fin layer regrowth on the middle section of the fin layers to form a plurality of vertical fins on the spacer layer, in accordance with an embodiment of the present invention. - In one or more embodiments,
fin layer regrowth 220 can be formed on the exposed rough surfaces of the fin layers 160, where thefin layer regrowth 220 can be formed by epitaxial growth. Thefin layer regrowth 220 can be the same III-V semiconductor material as thefin layer 160 III-V semiconductor material. - The
fin layer 160 andfin layer regrowth 220 can form the two components of avertical fin 190, where thefin layer regrowth 220 formed on thefin layer 160 exposed by removing thedummy gate layer 180 can be in physical and electrical contact with thefin layer regrowth 220 under the source/drains 200. -
FIG. 18 is a cross-sectional side view showing the fin layer regrowth on the fin layers along the A-A cutting plane ofFIG. 17 , in accordance with an embodiment of the present invention. - In one or more embodiments, the
fin regrowth layer 220 can have a thickness in the range of about 6 nm to about 25 nm, or in the range of about 10 nm to about 20 nm, where the thickness of thefin regrowth layer 220 is sufficient to cover therough surface 167 and reduce the roughness of the exposed surfaces of thevertical fins 190. - In various embodiments, the
oxide layer 129 can be formed on thefin mandrel slabs 125, where theoxide layer 129 can be a native oxide that formed on thefin mandrel slabs 125 during processing. Theoxide layer 129 can be thinner than the depth of the gap between the bottom surface of the source/drains 200 or merged source/drain 200 and the top surface of thefin mandrel slab 125, so there can still be a gap between thefin regrowth layer 220 and surface of theoxide layer 129, or the oxide layer can be sufficiently thick to fill the gap. Theoxide layer 129 can prevent formation of the III-Vfin layer regrowth 220 on thefin mandrel slabs 125. - In one or more embodiments, the width of the
vertical fin 190 can be reduced using a digital etch, where the III-V semiconductor structure can be thinned using a two-step plasma oxidation and acid etch. -
FIG. 19 is a top view showing a gate structure formed on the middle section of the vertical fins, in accordance with an embodiment of the present invention. - In one or more embodiments, a gate structure can be formed on the vertical fins formed by the
fin layer 160 andfin regrowth layer 220 forming thevertical fins 190. The gate structure can be formed by depositing a gate dielectric layer on the exposed portions of thevertical fins 190, depositing a work metal layer on the gate dielectric layer, and depositing a conductive gate fill on the work function layer. A CMP can be used to remove excess conductive gate fill and planarize the conductive gate fill at the level of the top of the cover layers 210. - In various embodiments, electrical contacts can be formed to the source/drains 200 and the gate structure.
- The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
- Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe1-x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.
- Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
- It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.
- It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
- It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
- Having described preferred embodiments of a device and method of fabricating a device (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
Claims (16)
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US11205709B2 (en) * | 2018-06-25 | 2021-12-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect filling in patterned layer |
CN112242357A (en) * | 2019-07-18 | 2021-01-19 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
KR20210010799A (en) * | 2019-07-18 | 2021-01-28 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Hybrid source drain regions formed based on same fin and methods forming same |
KR102269458B1 (en) * | 2019-07-18 | 2021-06-29 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Hybrid source drain regions formed based on same fin and methods forming same |
US11049774B2 (en) | 2019-07-18 | 2021-06-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid source drain regions formed based on same Fin and methods forming same |
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US20190237565A1 (en) | 2019-08-01 |
US10304947B1 (en) | 2019-05-28 |
US10600891B2 (en) | 2020-03-24 |
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