US20190115394A1 - Semiconductor structure and the method of making the same - Google Patents

Semiconductor structure and the method of making the same Download PDF

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US20190115394A1
US20190115394A1 US15/807,528 US201715807528A US2019115394A1 US 20190115394 A1 US20190115394 A1 US 20190115394A1 US 201715807528 A US201715807528 A US 201715807528A US 2019115394 A1 US2019115394 A1 US 2019115394A1
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layer
substrate
lower electrode
metal silicide
semiconductor structure
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US10283564B1 (en
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Chih-Chien Liu
Chao-Ching Hsieh
Yu-Ru Yang
Hsiao-Pang Chou
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United Microelectronics Corp
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    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H01L27/2436—
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
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    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
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    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
    • H01L45/1608—

Definitions

  • Embodiments of the invention generally relate to a semiconductor structure, and more particularly, to a transistor and a resistive random access memory (hereinafter abbreviated as RRAM) structure and the manufacturing method thereof.
  • RRAM resistive random access memory
  • Resistive random access memory has a simple structure, low operating voltage, high-speed, good endurance, and CMOS process compatibility. RRAM is the most promising alternative to provide a downsized replacement for traditional flash memory. RRAM is finding wide application in devices such as optical disks and non-volatile memory arrays.
  • An RRAM cell stores data within a layer of material that can be induced to undergo a phase change.
  • the phase change can be induced within all or part of the layer to switch between a high resistance state and a low resistance state.
  • the resistance state can be queried and interpreted as representing either a “0” or a “1”.
  • the data storage layer includes an amorphous metal oxide.
  • a metallic bridge is induced to form across the data storage layer, which results in the low resistance state.
  • the metallic bridge can be disrupted and the high resistance state restored by applying a short high current density pulse that melts or otherwise breaks down all or part of the metallic structure.
  • the data storage layer quickly cools and remains in the high resistance state until the low resistance state is induced again.
  • the present invention provides a semiconductor structure, the semiconductor structure includes a substrate having a diffusion region therein, a transistor structure located on the substrate, and a resistive random access memory (RRAM) located on the substrate, wherein the resistive random access memory comprises at least one metal silicide layer, the metal silicide layer contacts the diffusion region directly, and a lower electrode, a resistive switching layer and a top electrode sequentially located on the metal silicide layer.
  • RRAM resistive random access memory
  • the present invention further provides a method for fabricating a semiconductor structure, the method includes: a substrate is provided, having a diffusion region disposed therein, a transistor structure is formed on the substrate, and a resistive random access memory (RRAM) is formed on the substrate, wherein the resistive random access memory comprises at least one metal silicide layer, the metal silicide layer contacts the diffusion region directly, and a lower electrode, a resistive conversion layer and a top electrode sequentially formed on the metal silicide layer.
  • RRAM resistive random access memory
  • One of the features of the present invention is that the high-k dielectric layer of the transistor and the resistive switching layer in the RRAM are formed by the same material layer in the same step during the manufacturing process. So the completed transistor's high-k dielectric layer and RRAM's resistance switching layer have the same material.
  • the present invention saves process steps and integrates the RRAM process with the transistor process.
  • FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4 and FIG. 5 illustrate the schematic diagrams of the process for forming a semiconductor structure according to a first embodiment of the present invention.
  • FIG. 2A illustrates the schematic diagram of a semiconductor structure according to another embodiment of the present invention.
  • FIG. 6 , FIG. 7 and FIG. 8 illustrate the schematic diagrams of the process for forming a semiconductor structure according to a second embodiment of the present invention.
  • FIGS. 1, 2, 3, 4 and 5 show the schematic diagrams for fabricating a semiconductor structure according to a first preferred embodiment of the present invention.
  • a substrate 10 is provided, such as a silicon substrate.
  • a transistor region 12 and a memory region 14 that disposed adjacent to the transistor region 12 are defined on the substrate 10 .
  • a transistor structure is predicted to be formed in the transistor region 12
  • a resistive random access memory (RRAM) is formed in the memory region 14 .
  • a diffusion region 16 is formed in the substrate 10 , such as an N-type diffusion region or a P-type diffusion region. The diffusion region 16 is located in the substrate 10 within the memory region 14 and in the substrate 10 within the transistor region 12 simultaneously.
  • a metal layer 20 , a lower electrode material layer 22 and a patterned mask layer 24 are sequentially formed on the substrate 10 .
  • the metal layer 20 includes metal materials such as titanium or tantalum
  • the lower electrode material layer 22 includes such as a titanium nitride layer or tantalum nitride layer
  • the patterned mask layer 24 defines the position of the RRAM that formed within the memory region 14 in the following steps.
  • the patterned mask layer 24 is used as a protective layer, and an etching process is performed, to remove parts of the lower electrode material layer 22 and the metal layer 20 that not covered by the patterned mask layer 24 .
  • An annealing step P 1 is then carried out to convert the metal layer 20 that directly contacting the substrate 10 into a metal silicide layer 30 , so as to form the structure shown in FIG. 2 .
  • the metal silicide layer 30 contacts the diffusion region 16 directly.
  • the metal silicide layer 30 and the lower electrode material layer 22 are formed by an etching process, so that the sidewall of the metal silicide layer 30 and the sidewall of the lower electrode material layer 22 are aligned with each other.
  • the method and materials for forming each element described in FIG. 1 and FIG. 2 are well known to those skilled in the art, and thus are not described here.
  • the patterning process (such as the etching process) is performed through a self-aligned process. In other words, this process removes parts of the lower electrode material layer 22 and the metal layer 20 by a vertical etching process. Therefore, the patterned lower electrode material layer 22 may cover the sidewalls of the metal silicide layer 30 , it is also within the scope of the present invention. However, the subsequent steps are continued with the structure shown in FIG. 2 .
  • the high-k dielectric layer 42 comprises such a dielectric material layer having a dielectric constant (k value) larger than 4 such as metallic oxide, hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta2O 9
  • the high-k dielectric layer 42 is located not only on the substrate 10 within the transistor region 12 , but also on the lower electrode material layer 22 within the memory region 14 . Therefore, in the following steps, the high-k dielectric layer 42 can be used not only as a high-k dielectric layer in the transistor, but also used as a resistance switching layer in a RRAM structure (typically, a RRAM includes at least one lower electrode, a resistance switching layer and upper electrode). In other words, it is not necessary to form a resistive switching layer of RRAM by other processes, it can simplify overall process steps.
  • the material of the metal layer 44 mentioned above includes such as a titanium nitride layer, a tantalum nitride layer or other suitable materials, but the present invention is not limited thereto.
  • the metal layer 44 located within the transistor region 12 covers on the high-k dielectric layer 42 , the metal layer 44 can be used as a bottom barrier layer of the transistor, and a portion of the metal layer 44 that covers the high-k dielectric constant layer 42 (the high-k dielectric layer 42 is also the resistive switching layer of the RRAM) within the memory region 14 can be used as the upper electrode of the RRAM.
  • the patterned mask layer 46 defines the position of the following-formed transistor gate and the position of the RRAM.
  • an etching step is performed, to remove parts of the metal layer 44 and the high-k dielectric layer 42 , and to define the pattern of the RRAM 50 in the memory region 14 .
  • the remaining high-k dielectric layer is defined as the resistance switching layer 43 .
  • the resistance switching layer 43 may has a flat cross-section structure or a reverse U-shaped cross-section structure.
  • the remaining patterned mask layer 46 is subsequently removed and a gate material layer 48 is formed at the top portion of the metal layer 44 within the transistor region 12 .
  • the gate material layer 48 includes such as a polysilicon layer, but is not limited thereto.
  • the high-k dielectric layer 42 , the metal layer 44 and the gate material layer 48 constitute a gate structure 52 . It is noteworthy that in the conventional process, the RRAM is usually formed on a contact structure, but in the present invention, the RRAM 50 is formed on the surface of the substrate 10 , and directly contacts the diffusion region 16 .
  • an ion implantation process is performed in the substrate 10 around the gate structure 52 , to form source/drain regions 54 in the substrate 10 on both sides of the gate structure 52 .
  • one side of the source/drain regions 54 overlaps the diffusion region 16 directly. That is, as shown in FIG. 5 , one of the source/drain regions 54 contacts the diffusion region 16 directly, but the concentrations of the implanted ions of the source/drain region 54 and the diffusion region 16 may be different.
  • the source/drain regions 54 may also be directly formed in the substrate 10 after the diffusion region 16 is completed, it is also be within the scope of the present invention.
  • a dielectric layer 60 is formed on the substrate 10 , and a plurality of contact structures 62 are formed in the dielectric layer 60 , the contact structures 62 electrically connecting the RRAM 50 , the gate structure 52 and the source/drain region 54 .
  • the material of the dielectric layer 60 includes such as silicon oxide or silicon nitride, and the material of the contact structure 62 includes materials having good conductivity, such as tungsten, etc., but the present invention is not limited thereto.
  • the contact structure 62 may be used as a selection line of a semiconductor device (e.g., the contact structure 62 A in FIG.
  • a word line e.g., the contact structure 62 B in FIG. 5
  • a bit line e.g., the contact structure 62 C in FIG. 5
  • FIG. 6 , FIG. 7 and FIG. 8 show the schematic diagrams for fabricating a semiconductor structure according to a second preferred embodiment of the present invention.
  • the substrate 10 is first provided, a transistor region 12 and a memory region 14 are defined on the substrate 10 , and a diffusion region 16 is formed in the substrate 10 .
  • a patterned metal silicide layer 30 and a lower electrode material layer 22 are formed in the memory region 14 .
  • the process is same as that shown in FIG. 2 of the first preferred embodiment. Therefore, the manufacturing method and material properties of each element is not repeated.
  • a dummy gate (not shown) comprising a dielectric layer and a polysilicon material is then formed in the transistor region 12 and the memory region 14 , a contact etching stop layer (not shown) is formed to cover the dummy gate, and a dielectric layer 120 comprising tetraethyl orthosilicate (TEOS) is formed on the contact etching stop layer. Thereafter, a replacement process can be performed.
  • a dummy gate comprising a dielectric layer and a polysilicon material is then formed in the transistor region 12 and the memory region 14
  • a contact etching stop layer (not shown) is formed to cover the dummy gate
  • a dielectric layer 120 comprising tetraethyl orthosilicate (TEOS) is formed on the contact etching stop layer.
  • TEOS tetraethyl orthosilicate
  • parts of the dielectric layer 120 and the contact etching stop layer are planarized, and a selective dry etching or wet etching process is performed, such as using the ammonia solution (NH 4 OH) or the tetramethylammonium hydroxide (TMAH) to remove the polysilicon material in each dummy gate, so that a first opening 121 and a second opening 122 are formed in the dielectric layer 120 .
  • the first opening 121 is located within the transistor region 12 , exposes a portion of the substrate 10
  • the second opening 122 is located within the memory region 14 , exposes the lower electrode material layer 22 .
  • the size of the second opening 122 is same as the size of the lower electrode material layer 22 .
  • the position of the first opening 121 defines the position of the following-formed transistor
  • the position of the second opening 122 defines the position of the RRAM.
  • other material layers formed in the following steps will be formed in the first opening 121 and the second opening 122 .
  • the dielectric layer 120 is firstly formed on the substrate 10 , it is preferable that the source/drain region 154 has been formed in the substrate before the dielectric layer 120 is formed, to prevent the source/drain region 154 cannot be formed in the substrate 10 easily after the dielectric layer 120 is formed.
  • a high-k dielectric layer 142 is formed, the high-k dielectric layer 142 is filled into the first opening 121 and the second opening 122 respectively.
  • the high-k dielectric layer 142 comprises the same material as that of the high-k dielectric layer 42 mentioned above, including a dielectric material layer having a dielectric constant (k value) larger than 4, such as metallic oxide, hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta2O 9 , SBT), lead zirconate titanate (PbZrxTi 1-x O 3 , PZT), bar
  • the present embodiment is characterized in that the high-k dielectric layer 142 is not only used as a high-k dielectric layer of the transistor, but also be used as a resistance switching layer of the RRAM. So the process steps can be simplified, the process for forming the RRAM can be integrated in the process for forming the transistor.
  • the flat metal silicide layer 30 and the lower electrode material layer 22 are formed firstly, and the dielectric layer 120 is then formed.
  • the metal silicide layer 30 and the lower electrode material layer 22 may be formed in the opening of the dielectric layer 120 after the dielectric layer 120 is formed.
  • the lower electrode material layer 22 may has an U-shaped cross section structure. This embodiment is also within the scope of the present invention.
  • a metal layer 144 and a conductive layer 146 are sequentially formed to fill the first opening 121 and the second opening 122 .
  • a planarization step P 2 is then performed to remove the extra conductive layer 146 , the metal layer 144 , and the high-k dielectric layer 142 on the surface of the dielectric layer 120 respectively, and form the RRAM 150 and the gate structure 152 respectively.
  • the high-k dielectric layer remaining in the memory region 14 is defined as the resistance switching layer 143 , and the resistance switching layer 143 has an U-shaped cross-sectional structure. It is to be noted that a top surface 150 a of the RRAM 150 and a top surface 152 a of the gate structure 152 are on a same level.
  • at least one contact structure 156 is formed in the dielectric layer 120 , and the contact structure 156 is electrically connected to the source/drain region 154 .
  • a dielectric layer 160 is formed on the dielectric layer 120 , and a plurality of contact structures 162 are formed in the dielectric layer 160 .
  • the contact structures 162 electrically connect the RRAM 150 , the gate structure 152 and the contact structures 156 described above.
  • the contact structure 162 may be used as a selection line (e.g., the contact structure 162 A in FIG. 8 ) of the semiconductor device, a word line (e.g., the contact structure 162 B in FIG. 8 ) of the semiconductor device, or a bit line (e.g., the contact structure 162 C in FIG. 8 .) of the semiconductor device.
  • the semiconductor structure in which the present invention integrates the transistor and the RRAM has been completed.
  • the semiconductor structure formed on the substrate 10 includes the diffusion region 16 located in the substrate 10 , the transistor 52 located on the substrate 10 , and the resistive random access memory (RRAM) 50 located on the substrate 10 .
  • the RRAM 50 comprises a metal silicide layer 30 contacting the diffusion region 16 directly.
  • a lower electrode 22 , a resistive switching layer 43 and an upper electrode 44 are sequentially located on the metal silicide layer 30 .
  • the resistance switching layer 143 has an U-shaped cross section structure.
  • One of the features of the present invention is that the high-k dielectric layer of the transistor and the resistive switching layer in the RRAM are formed by the same material layer in the same step during the manufacturing process. So the completed transistor's high-k dielectric layer and RRAM's resistance switching layer have the same material.
  • the present invention saves process steps and integrates the RRAM process with the transistor process.

Abstract

The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.

Description

    BACKGROUND OF THE INVENTION 1. Field of the Invention
  • Embodiments of the invention generally relate to a semiconductor structure, and more particularly, to a transistor and a resistive random access memory (hereinafter abbreviated as RRAM) structure and the manufacturing method thereof.
    • 2. Description of the Prior Art
  • Resistive random access memory (RRAM) has a simple structure, low operating voltage, high-speed, good endurance, and CMOS process compatibility. RRAM is the most promising alternative to provide a downsized replacement for traditional flash memory. RRAM is finding wide application in devices such as optical disks and non-volatile memory arrays.
  • An RRAM cell stores data within a layer of material that can be induced to undergo a phase change. The phase change can be induced within all or part of the layer to switch between a high resistance state and a low resistance state. The resistance state can be queried and interpreted as representing either a “0” or a “1”. In a typical RRAM cell, the data storage layer includes an amorphous metal oxide. Upon application of a sufficient voltage, a metallic bridge is induced to form across the data storage layer, which results in the low resistance state. The metallic bridge can be disrupted and the high resistance state restored by applying a short high current density pulse that melts or otherwise breaks down all or part of the metallic structure. The data storage layer quickly cools and remains in the high resistance state until the low resistance state is induced again.
    • SUMMARY OF THE INVENTION
  • The present invention provides a semiconductor structure, the semiconductor structure includes a substrate having a diffusion region therein, a transistor structure located on the substrate, and a resistive random access memory (RRAM) located on the substrate, wherein the resistive random access memory comprises at least one metal silicide layer, the metal silicide layer contacts the diffusion region directly, and a lower electrode, a resistive switching layer and a top electrode sequentially located on the metal silicide layer.
  • The present invention further provides a method for fabricating a semiconductor structure, the method includes: a substrate is provided, having a diffusion region disposed therein, a transistor structure is formed on the substrate, and a resistive random access memory (RRAM) is formed on the substrate, wherein the resistive random access memory comprises at least one metal silicide layer, the metal silicide layer contacts the diffusion region directly, and a lower electrode, a resistive conversion layer and a top electrode sequentially formed on the metal silicide layer.
  • One of the features of the present invention is that the high-k dielectric layer of the transistor and the resistive switching layer in the RRAM are formed by the same material layer in the same step during the manufacturing process. So the completed transistor's high-k dielectric layer and RRAM's resistance switching layer have the same material. The present invention saves process steps and integrates the RRAM process with the transistor process.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1, FIG. 2, FIG. 3, FIG. 4 and FIG. 5 illustrate the schematic diagrams of the process for forming a semiconductor structure according to a first embodiment of the present invention.
  • FIG. 2A illustrates the schematic diagram of a semiconductor structure according to another embodiment of the present invention.
  • FIG. 6, FIG. 7 and FIG. 8 illustrate the schematic diagrams of the process for forming a semiconductor structure according to a second embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • To provide a better understanding of the present invention to users skilled in the technology of the present invention, preferred embodiments are detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the contents and the effects to be achieved.
  • Please note that the figures are only for illustration and the figures may not be to scale. The scale may be further modified according to different design considerations. When referring to the words “up” or “down” that describe the relationship between components in the text, it is well known in the art and should be clearly understood that these words refer to relative positions that can be inverted to obtain a similar structure, and these structures should therefore not be precluded from the scope of the claims in the present invention.
  • Please refer to FIGS. 1, 2, 3, 4 and 5, these figures show the schematic diagrams for fabricating a semiconductor structure according to a first preferred embodiment of the present invention. Firstly, as shown in FIG. 1, a substrate 10 is provided, such as a silicon substrate. A transistor region 12 and a memory region 14 that disposed adjacent to the transistor region 12 are defined on the substrate 10. In the following steps, a transistor structure is predicted to be formed in the transistor region 12, and a resistive random access memory (RRAM) is formed in the memory region 14. A diffusion region 16 is formed in the substrate 10, such as an N-type diffusion region or a P-type diffusion region. The diffusion region 16 is located in the substrate 10 within the memory region 14 and in the substrate 10 within the transistor region 12 simultaneously. Next, a metal layer 20, a lower electrode material layer 22 and a patterned mask layer 24 are sequentially formed on the substrate 10. The metal layer 20 includes metal materials such as titanium or tantalum, the lower electrode material layer 22 includes such as a titanium nitride layer or tantalum nitride layer, and the patterned mask layer 24 defines the position of the RRAM that formed within the memory region 14 in the following steps.
  • Next, please refer to FIG. 2, the patterned mask layer 24 is used as a protective layer, and an etching process is performed, to remove parts of the lower electrode material layer 22 and the metal layer 20 that not covered by the patterned mask layer 24. An annealing step P1 is then carried out to convert the metal layer 20 that directly contacting the substrate 10 into a metal silicide layer 30, so as to form the structure shown in FIG. 2. In addition, the metal silicide layer 30 contacts the diffusion region 16 directly. In the present embodiment, the metal silicide layer 30 and the lower electrode material layer 22 are formed by an etching process, so that the sidewall of the metal silicide layer 30 and the sidewall of the lower electrode material layer 22 are aligned with each other. The method and materials for forming each element described in FIG. 1 and FIG. 2 are well known to those skilled in the art, and thus are not described here.
  • In another embodiment of the present invention, please refer to FIG. 2A, before the metal silicide layer 30 is formed, the patterning process (such as the etching process) is performed through a self-aligned process. In other words, this process removes parts of the lower electrode material layer 22 and the metal layer 20 by a vertical etching process. Therefore, the patterned lower electrode material layer 22 may cover the sidewalls of the metal silicide layer 30, it is also within the scope of the present invention. However, the subsequent steps are continued with the structure shown in FIG. 2.
  • Next, as shown in FIG. 3, a high-k dielectric layer 42, a metal layer 44 and a patterned mask layer 46 are sequentially formed in the transistor region 12 and the memory region 14. The high-k dielectric layer 42 comprises such a dielectric material layer having a dielectric constant (k value) larger than 4 such as metallic oxide, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST) or a combination thereof. One feature of the present invention is that the high-k dielectric layer 42 is located not only on the substrate 10 within the transistor region 12, but also on the lower electrode material layer 22 within the memory region 14. Therefore, in the following steps, the high-k dielectric layer 42 can be used not only as a high-k dielectric layer in the transistor, but also used as a resistance switching layer in a RRAM structure (typically, a RRAM includes at least one lower electrode, a resistance switching layer and upper electrode). In other words, it is not necessary to form a resistive switching layer of RRAM by other processes, it can simplify overall process steps.
  • The material of the metal layer 44 mentioned above includes such as a titanium nitride layer, a tantalum nitride layer or other suitable materials, but the present invention is not limited thereto. The metal layer 44 located within the transistor region 12 covers on the high-k dielectric layer 42, the metal layer 44 can be used as a bottom barrier layer of the transistor, and a portion of the metal layer 44 that covers the high-k dielectric constant layer 42 (the high-k dielectric layer 42 is also the resistive switching layer of the RRAM) within the memory region 14 can be used as the upper electrode of the RRAM. The patterned mask layer 46 defines the position of the following-formed transistor gate and the position of the RRAM.
  • Next, as shown in FIG. 4, an etching step is performed, to remove parts of the metal layer 44 and the high-k dielectric layer 42, and to define the pattern of the RRAM 50 in the memory region 14. At this step, the remaining high-k dielectric layer is defined as the resistance switching layer 43. According to different embodiments, the resistance switching layer 43 may has a flat cross-section structure or a reverse U-shaped cross-section structure. In addition, the remaining patterned mask layer 46 is subsequently removed and a gate material layer 48 is formed at the top portion of the metal layer 44 within the transistor region 12. The gate material layer 48 includes such as a polysilicon layer, but is not limited thereto. The high-k dielectric layer 42, the metal layer 44 and the gate material layer 48 constitute a gate structure 52. It is noteworthy that in the conventional process, the RRAM is usually formed on a contact structure, but in the present invention, the RRAM 50 is formed on the surface of the substrate 10, and directly contacts the diffusion region 16.
  • As shown in FIG. 5, after the gate structure 52 and the RRAM 50 are completed, an ion implantation process is performed in the substrate 10 around the gate structure 52, to form source/drain regions 54 in the substrate 10 on both sides of the gate structure 52. It is noteworthy that one side of the source/drain regions 54 overlaps the diffusion region 16 directly. That is, as shown in FIG. 5, one of the source/drain regions 54 contacts the diffusion region 16 directly, but the concentrations of the implanted ions of the source/drain region 54 and the diffusion region 16 may be different. It is to be noted that in other embodiments of the present invention, the source/drain regions 54 may also be directly formed in the substrate 10 after the diffusion region 16 is completed, it is also be within the scope of the present invention.
  • In the following steps, please still refer to FIG. 5, a dielectric layer 60 is formed on the substrate 10, and a plurality of contact structures 62 are formed in the dielectric layer 60, the contact structures 62 electrically connecting the RRAM 50, the gate structure 52 and the source/drain region 54. The material of the dielectric layer 60 includes such as silicon oxide or silicon nitride, and the material of the contact structure 62 includes materials having good conductivity, such as tungsten, etc., but the present invention is not limited thereto. Depending on the position of the contact structure 62, the contact structure 62 may be used as a selection line of a semiconductor device (e.g., the contact structure 62A in FIG. 5), a word line (e.g., the contact structure 62B in FIG. 5) of a semiconductor device, or a bit line (e.g., the contact structure 62C in FIG. 5) of a semiconductor device. At this step, the semiconductor structure that integrating the transistor and the RRAM has been completed.
  • The following description will detail the different embodiments of the semiconductor structure and the manufacturing method of the present invention. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.
  • Please refer to FIG. 6, FIG. 7 and FIG. 8, these figures show the schematic diagrams for fabricating a semiconductor structure according to a second preferred embodiment of the present invention. In the second embodiment of the present invention, as shown in FIG. 6, the substrate 10 is first provided, a transistor region 12 and a memory region 14 are defined on the substrate 10, and a diffusion region 16 is formed in the substrate 10. Next, a patterned metal silicide layer 30 and a lower electrode material layer 22 are formed in the memory region 14. Until this step, the process is same as that shown in FIG. 2 of the first preferred embodiment. Therefore, the manufacturing method and material properties of each element is not repeated. The difference between this embodiment and the first preferred embodiment is that after the metal silicide layer 30 and the lower electrode material layer 22 are formed, in the embodiment, a dummy gate (not shown) comprising a dielectric layer and a polysilicon material is then formed in the transistor region 12 and the memory region 14, a contact etching stop layer (not shown) is formed to cover the dummy gate, and a dielectric layer 120 comprising tetraethyl orthosilicate (TEOS) is formed on the contact etching stop layer. Thereafter, a replacement process can be performed. More precisely, parts of the dielectric layer 120 and the contact etching stop layer are planarized, and a selective dry etching or wet etching process is performed, such as using the ammonia solution (NH4OH) or the tetramethylammonium hydroxide (TMAH) to remove the polysilicon material in each dummy gate, so that a first opening 121 and a second opening 122 are formed in the dielectric layer 120. The first opening 121 is located within the transistor region 12, exposes a portion of the substrate 10, the second opening 122 is located within the memory region 14, exposes the lower electrode material layer 22. Preferably, the size of the second opening 122 is same as the size of the lower electrode material layer 22. More specifically, the position of the first opening 121 defines the position of the following-formed transistor, and the position of the second opening 122 defines the position of the RRAM. In other words, other material layers formed in the following steps will be formed in the first opening 121 and the second opening 122.
  • In addition, in the present embodiment, since the dielectric layer 120 is firstly formed on the substrate 10, it is preferable that the source/drain region 154 has been formed in the substrate before the dielectric layer 120 is formed, to prevent the source/drain region 154 cannot be formed in the substrate 10 easily after the dielectric layer 120 is formed. Next, a high-k dielectric layer 142 is formed, the high-k dielectric layer 142 is filled into the first opening 121 and the second opening 122 respectively. The high-k dielectric layer 142 comprises the same material as that of the high-k dielectric layer 42 mentioned above, including a dielectric material layer having a dielectric constant (k value) larger than 4, such as metallic oxide, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST) or a combination thereof. The present embodiment is characterized in that the high-k dielectric layer 142 is not only used as a high-k dielectric layer of the transistor, but also be used as a resistance switching layer of the RRAM. So the process steps can be simplified, the process for forming the RRAM can be integrated in the process for forming the transistor.
  • In addition, in the above embodiment, the flat metal silicide layer 30 and the lower electrode material layer 22 are formed firstly, and the dielectric layer 120 is then formed. However, in other embodiments of the present invention, the metal silicide layer 30 and the lower electrode material layer 22 may be formed in the opening of the dielectric layer 120 after the dielectric layer 120 is formed. In this case, the lower electrode material layer 22 may has an U-shaped cross section structure. This embodiment is also within the scope of the present invention.
  • As shown in FIG. 7, a metal layer 144 and a conductive layer 146 are sequentially formed to fill the first opening 121 and the second opening 122. A planarization step P2 is then performed to remove the extra conductive layer 146, the metal layer 144, and the high-k dielectric layer 142 on the surface of the dielectric layer 120 respectively, and form the RRAM 150 and the gate structure 152 respectively. The high-k dielectric layer remaining in the memory region 14 is defined as the resistance switching layer 143, and the resistance switching layer 143 has an U-shaped cross-sectional structure. It is to be noted that a top surface 150a of the RRAM 150 and a top surface 152a of the gate structure 152 are on a same level. In addition, at least one contact structure 156 is formed in the dielectric layer 120, and the contact structure 156 is electrically connected to the source/drain region 154.
  • Finally, as shown in FIG. 8, a dielectric layer 160 is formed on the dielectric layer 120, and a plurality of contact structures 162 are formed in the dielectric layer 160. The contact structures 162 electrically connect the RRAM 150, the gate structure 152 and the contact structures 156 described above. Depending on the position of the contact structure 162, the contact structure 162 may be used as a selection line (e.g., the contact structure 162A in FIG. 8) of the semiconductor device, a word line (e.g., the contact structure 162B in FIG. 8) of the semiconductor device, or a bit line (e.g., the contact structure 162C in FIG. 8.) of the semiconductor device. At this step, the semiconductor structure in which the present invention integrates the transistor and the RRAM has been completed.
  • In the semiconductor structure of the present invention, please refer to FIG. 5, the semiconductor structure formed on the substrate 10, the semiconductor structure includes the diffusion region 16 located in the substrate 10, the transistor 52 located on the substrate 10, and the resistive random access memory (RRAM) 50 located on the substrate 10. The RRAM 50 comprises a metal silicide layer 30 contacting the diffusion region 16 directly. And a lower electrode 22, a resistive switching layer 43 and an upper electrode 44 are sequentially located on the metal silicide layer 30. In other embodiments, please refer to FIG. 8, since partial material layers are formed in the opening, the resistance switching layer 143 has an U-shaped cross section structure. One of the features of the present invention is that the high-k dielectric layer of the transistor and the resistive switching layer in the RRAM are formed by the same material layer in the same step during the manufacturing process. So the completed transistor's high-k dielectric layer and RRAM's resistance switching layer have the same material. The present invention saves process steps and integrates the RRAM process with the transistor process.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (20)

1. A semiconductor structure, comprising:
a substrate having a diffusion region therein;
a transistor structure located on the substrate; and
a resistive random access memory (RRAM) located on the substrate, wherein the resistive random access memory comprises at least one metal silicide layer contacting the diffusion region directly, and a lower electrode, a resistive switching layer and a top electrode sequentially located on the metal silicide layer, wherein a sidewall of the lower electrode layer is aligned with a sidewall of the metal silicide layer.
2. The semiconductor structure of claim 1, wherein the transistor structure comprises a gate structure, the gate structure comprises a high-k dielectric layer, wherein a material of the high-k dielectric layer is same as the material of the resistive switching layer.
3. The semiconductor structure of claim 2, wherein a top surface of the gate structure and a top surface of the resistive random access memory are on a same level.
4. The semiconductor structure of claim 1, wherein the resistance switching layer has an U-shaped cross section profile.
5. The semiconductor structure of claim 1, wherein the resistance switching layer has a reverse U-shaped cross section profile.
6. The semiconductor structure of claim 1, wherein the transistor structure comprises a source/drain (S/D) region located in the substrate, wherein the source /drain region contacts the diffusion region directly.
7. (canceled)
8. The semiconductor structure of claim 1, wherein the lower electrode layer covers one sidewall of the metal silicide layer.
9. The semiconductor structure of claim 1, wherein a material of the lower electrode comprises titanium nitride.
10. The semiconductor structure of claim 1, further comprises a plurality of contact structures, electrically connected to the resistive random access memory and the transistor structure respectively.
11. A method for fabricating a semiconductor structure, comprising:
providing a substrate having a diffusion region disposed therein;
forming a transistor structure on the substrate; and
forming a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory comprises at least one metal silicide layer contacting the diffusion region directly, and a lower electrode, a resistive conversion layer and a top electrode sequentially formed on the metal silicide layer, a sidewall of the lower electrode layer is aligned with a sidewall of the metal silicide layer.
12. The method of claim 11, wherein the transistor structure comprises a gate structure, the gate structure comprises a high-k dielectric layer, wherein a material of the high-k dielectric layer is same as the material of the resistive switching layer.
13. The method of claim 12, wherein the step of forming the high-k dielectric layer and the resistance switching layer comprises:
forming the metal silicide layer and the lower electrode on the substrate;
forming a dielectric material layer on the substrate, wherein parts of the dielectric material layer is disposed on the lower electrode; and
performing an etching step to remove a portion of the dielectric material layer, and to form the high-k dielectric layer on the substrate and to form the resistance switching layer on the lower electrode simultaneously.
14. The method of claim 12, wherein a top surface of the gate structure and a top surface of the resistive random access memory are on a same level.
15. The method of claim 11, wherein the resistance switching layer has an U-shaped cross section profile.
16. The method of claim 11, wherein the resistance switching layer has a reverse U-shaped cross section profile.
17. The method of claim 11, wherein the transistor structure comprises a source/drain (S/D) region located in the substrate, wherein the source/drain region contacts the diffusion region directly.
18. (canceled)
19. The method of claim 11, wherein the lower electrode layer covers one sidewall of the metal silicide layer.
20. The method of claim 11, further comprises forming a plurality of contact structures, electrically connected to the resistive random access memory and the transistor structure respectively.
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