US20190089262A1 - Isolated dc-dc converter - Google Patents
Isolated dc-dc converter Download PDFInfo
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- US20190089262A1 US20190089262A1 US15/859,135 US201715859135A US2019089262A1 US 20190089262 A1 US20190089262 A1 US 20190089262A1 US 201715859135 A US201715859135 A US 201715859135A US 2019089262 A1 US2019089262 A1 US 2019089262A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
- H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33573—Full-bridge at primary side of an isolation transformer
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
- H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
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- H02M2001/0054—
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/01—Resonant DC/DC converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- This relates generally to isolated DC-DC converters, and more particularly to efficient, high input and/or output voltage isolated DC-DC converters.
- Isolated DC-DC converters typically include a transformer, with: (a) a power generating input side, typically called the primary side; and (b) a power output side, typically called the secondary side.
- the differences between an isolated converter and a non-isolated converter are that: (a) in an isolated converter, the primary side and the secondary side have different grounds; and (b) in a non-isolated converter, the primary side and the secondary side share a same ground (such as using an inductor, instead of a transformer, to convert voltage).
- Isolated DC-DC converters can be small enough to fit within an integrated circuit (“IC”) package, but may require significant current on the primary side to drive the secondary side across the isolation barrier, i.e., the gap between the transformer coils.
- Such converters can be used for transferring power from a high voltage domain to a low voltage domain, such as from a power line to a set of consumer electronics, or from a battery on an electric vehicle to electronics on that vehicle.
- Grounds in high voltage regimes e.g., the power line or battery
- Grounds in the low voltage regimes may have much smaller swings (such as much less than 1V), and devices connected to those low voltage grounds could be rendered inoperative if subjected to the voltage swings tolerated in a high voltage regime. Isolation barriers separate high voltage regimes from low voltage regimes, so that power transfer can be performed without damaging low voltage components.
- an isolated DC-DC converter includes: an output node for delivering an output voltage; a transformer comprising a secondary side having first and second terminals and a secondary side ground; and a plurality of modules.
- Ones of the modules include respective: first and second low-side switches, and first and second high-side switches.
- the first low-side switch is coupled between the first terminal and a low-voltage node
- the second low-side switch is coupled between the second terminal and the low-voltage node.
- a first voltage is across the first low-side switch
- a second voltage is across the second low-side switch.
- the first high-side switch is coupled between the first terminal and a high-voltage node, and is configured to be activated by a voltage at the second terminal.
- the second high-side switch is coupled between the second terminal and the high-voltage node, and is configured to be activated by a voltage at the first terminal.
- the isolated DC-DC converter also includes a switch controller configured to open and close the first and second low-side switches at times corresponding to a frequency of the converter, as follows.
- the first low-side switch is closed when the first voltage is zero.
- the first low-side switch is opened when the first voltage is zero and a current through the secondary side is zero.
- the second low-side switch is closed when the second voltage is zero.
- the second low-side switch is opened when the second voltage is zero and the current through the secondary side is zero.
- a first one of the modules is an output module whose high-voltage node includes the output node.
- a second one of the modules is a ground module whose low-voltage node includes the secondary side ground. The high-voltage node of the ground module is coupled to the low-voltage node of the output module.
- FIG. 1 shows an example of a transistor-level diagram of a circuit portion used to construct an isolated DC-DC converter.
- FIG. 2 shows a transistor-level diagram of an isolated DC-DC converter.
- FIG. 3 shows a timing diagram for an isolated DC-DC converter as shown in and described with respect to FIG. 2 .
- FIG. 4 shows a transistor-level diagram of a high output voltage isolated DC-DC converter.
- FIG. 5 shows a transistor-level diagram of a high output voltage isolated DC-DC converter.
- FIG. 6A shows an example of a process for controlling an isolated DC-DC converter.
- FIG. 6B shows an example of a process for controlling an isolated DC-DC converter.
- FIG. 7 shows an example of a transistor-level diagram of a circuit portion used to construct an isolated DC-DC converter.
- FIG. 8 shows a transistor-level diagram of an isolated DC-DC converter.
- FIG. 9 shows an example of a timing diagram for an isolated DC-DC converter as shown in FIG. 8 .
- FIG. 10 shows an example of a transistor-level diagram of a high voltage isolated DC-DC converter.
- Example embodiments include methods, devices and systems for efficient (and in some embodiments, high input-output voltage), isolated DC-DC converters, particularly using circuits and components that can be incorporated into an integrated circuit (IC) package.
- the converters are capable of operating at large minimum voltage differentials between Vin (input voltage) and primary ground, and/or between Vout (output voltage) and secondary ground (e.g., 10V or 15V), as further described hereinbelow.
- FIG. 1 shows an example of a transistor-level diagram of a circuit portion 100 used to construct an isolated DC-DC converter.
- an input voltage Vin 102 is connected to the sources of two PMOS transistors, P 1 104 and P 2 106 (PMOS conduction type).
- PMOS conduction type PMOS conduction type
- Nodes V 1 108 and V 2 110 are cross-coupled between the drains and gates of P 1 104 and P 2 106 (high side switches). Accordingly, node V 1 108 is connected to the drain of P 1 104 and is connected to the gate of P 2 106 ; and node V 2 110 is connected to the drain of P 2 106 and is connected to the gate of P 1 104 .
- An inductor 112 can also be considered a primary side or a secondary side of a transformer—accordingly, the primary side or secondary side of a transformer is an inductor, and circuit portion 100 can be used to construct an isolated DC-DC converter such that the primary side or secondary side of a transformer in the converter stands in place of the inductor 112 (see, e.g., FIGS. 2, 4, 5, 8 and 10 ).
- the inductor 112 is connected between nodes V 1 108 and V 2 110 .
- Parasitic capacitor C 1 114 and the source/drain path of NMOS transistor N 1 116 are connected in parallel between node V 1 108 and GND 118 (the source of N 1 116 is connected to GND 118 ).
- C 1 114 corresponds to (represents) parasitic capacitances of N 1 116 , P 1 104 and P 2 106 .
- C 1 114 includes drain-source capacitance of N 1 116 , drain-source capacitance of P 1 104 , and gate-source capacitance of P 2 106 .
- the gate of N 1 116 is connected to a (buffered) control signal G 1 120 .
- C 2 122 and the source/drain path of NMOS transistor N 2 124 are connected in parallel between node V 2 110 and GND 118 (the source of N 2 124 is connected to GND 118 ).
- C 2 122 corresponds to (represents) parasitic capacitances of N 2 124 , P 1 104 and P 2 106 .
- C 2 122 includes drain-source capacitance of N 2 124 , drain-source capacitance of P 2 106 , and gate-source capacitance of P 1 104 .
- the gate of N 2 124 is connected to a (buffered) control signal G 2 126 .
- N 1 116 and N 2 124 comprise low side switches.
- Inputs G 1 120 and G 2 126 are preferably generated by a control signal generator 128 .
- An isolated DC-DC converter e.g., as in FIGS. 2, 4, 5, 8 and 10 ) preferably comprises a primary control signal generator and a secondary control signal generator, with the generators respectively and separately connected to generate and deliver control signals to drive controlled switches (e.g., N 1 116 and N 2 124 ).
- Converters can lose power, such as through switching losses, conduction losses, and other dissipative losses.
- Switching losses in MOSFET devices come from the dynamic voltages and currents a MOSFET handles during the finite, nonzero time it takes to turn on or off.
- Conduction losses are power dissipation losses resulting from current moving through a component; for example, MOSFET devices have nonzero resistance.
- Other dissipative losses occur, such as when power is discharged to ground, e.g., when a charged gate or capacitor is connected to ground, resulting in the gate or capacitor discharging.
- the NMOS transistors N 1 116 and N 2 124 are preferably zero voltage switched (ZVS) and zero current switched (ZCS). Accordingly, G 1 120 and G 2 126 are respectively controlled to turn N 1 116 and N 2 124 on OR off (generally one or the other and not both; the other of turn-on or turn-off timing is determined using other criteria, such as further described with respect to FIG. 3 ), when corresponding adjacent nodes V 1 108 and V 2 110 are fully discharged (at zero voltage with respect to GND 118 ), and zero current flows across the inductor 112 (from node V 1 108 to node V 2 110 or vice versa).
- ZVS zero voltage switched
- ZCS zero current switched
- power cost for MOSFET control is reduced by making P 1 104 and P 2 106 self-driving. Accordingly, rather than requiring control signals to bias P 1 104 and P 2 106 , P 1 104 and P 2 106 are biased by charge driven to P 1 104 and P 2 106 via nodes V 2 110 and V 1 108 (respectively) by the current through the resonance (inductor 112 ). Self-driving P 1 104 and P 2 106 reduces the complexity and power cost of controlling the MOSFETS.
- those gate charges charges of gate-source parasitic capacitances
- charges of respective drain-source and other parasitic capacitances are driven out of C 1 114 or C 2 122 by the resonance current, turned into current across the inductor 112 , and (in part) are used to charge C 2 122 or C 1 114 (respectively).
- gate charge of P 1 104 and P 2 106 are reused, the tradeoff between QG (gate charge) and RDS (drain-source on resistance) can be largely avoided for P 1 104 and P 2 106 .
- a lower RDS can generally be used, thereby enabling faster switching and lower heat output, without resulting in excessive power costs due to a higher QG, because the gate charge power cost is largely avoided (energy used to bias P 1 104 and P 2 106 is repeatedly recovered) after initial charging.
- P 1 104 and P 2 106 to be self-driven is relatively non-dissipative compared to gate driving using control signals because energy is taken back from parasitic capacitances C 1 114 and C 2 122 .
- Energy “recycling” is performed by discharging capacitances and turning voltage into current through the inductor 112 . Switching losses are thereby minimized. (See also similar cross-coupled switches in FIG. 7 .)
- N 1 116 and N 2 124 are preferably connected directly to GND 118 , reducing the power required to bias N 1 116 and N 2 124 .
- N 1 116 and N 2 124 can be driven using fixed frequency, fixed or adaptive duty cycle signals. Driving N 1 116 and N 2 124 at a fixed frequency, with a fixed or adaptive duty cycle, reduces the complexity and power cost of controlling the MOSFETS. (Duty cycle can be adaptive to maintain zero voltage switching and zero current switching conditions despite variations of circuit parameters or switching frequency, as further described with respect to FIG. 2 .)
- RMS currents are minimized to thereby lower conduction losses.
- FIG. 2 shows a transistor-level diagram of an isolated DC-DC converter 200 .
- the converter 200 can be broadly described as two instances of the circuit portion 100 , one on the input side 202 and one on the output side 204 , except that the input side 202 also comprises a capacitor connected between Vin 206 and input ground GND_P 208 acting as an input filter 210 , and the output side 204 also comprises a capacitor connected between Vout 212 and output ground GND_S 214 acting as an output filter 216 (input and output filters 210 , 216 are further described hereinbelow).
- a transformer 218 comprises a primary side 220 and a secondary side 222 .
- the primary side 220 and secondary side 222 of the transformer 218 each preferably function similarly, with respect to their respective side of the converter 200 (i.e., the input side 202 and the output side 204 ), to the inductor 112 of the circuit portion 100 described with respect to FIG. 1 .
- input voltage Vin 206 is connected to the sources of two PMOS transistors, P 1 P 224 and P 2 P 226 .
- Nodes V 1 P 228 and V 2 P 230 are cross-coupled between the drains and gates of P 1 P 224 and P 2 P 226 . Accordingly, node V 1 P 228 is connected to the drain of P 1 P 224 and the gate of P 2 P 226 ; and node V 2 P 230 is connected to the drain of P 2 P 226 and the gate of P 1 P 224 .
- the primary side 220 of the transformer 218 is connected between V 1 P 228 and V 2 P 230 .
- V 1 P 228 is also connected to the drain of NMOS transistor N 1 P 232
- V 2 P 228 is also connected to the drain of NMOS transistor N 2 P 234 .
- Control signal G 1 P 236 (switch control voltage) is connected (through a buffer) to the gate of N 1 P 232
- control signal G 2 P 238 is connected (through a buffer) to the gate of N 2 P 234 .
- the sources of both N 1 P 232 and N 2 P 234 are connected to primary side ground GND_P 208 . (Parasitic capacitances corresponding to C 1 114 and C 2 122 exist, but are not shown.)
- Vout 212 is connected to the sources of two PMOS transistors, P 1 S 240 and P 2 S 242 .
- Nodes V 1 S 244 and V 2 S 246 are cross-coupled between the drains and gates of P 1 S 240 and P 2 S 242 . Accordingly, node V 1 S 244 is connected to the drain of P 1 S 240 and is connected to the gate of P 2 S 242 ; and node V 2 S 246 is connected to the drain of P 2 S 242 and is connected to the gate of P 1 S 240 .
- the secondary side 204 of the transformer 218 is connected between V 1 S 244 and V 2 S 246 .
- V 1 S 244 is also connected to the drain of NMOS transistor N 1 S 248
- V 2 S 246 is also connected to the drain of NMOS transistor N 2 S 250 .
- Control signal G 1 S 252 is connected (through a buffer) to the gate of N 1 S 248
- control signal G 2 S 254 is connected (through a buffer) to the gate of N 2 S 250
- the sources of both N 1 S 248 and N 2 S 250 are connected to secondary side ground GND_S 214 . (Parasitic capacitances corresponding to C 1 114 and C 2 122 exist, but are not shown.)
- Vin 206 is preferably connected to GND_P 208 through a capacitor acting as an input filter 210 (a decoupling capacitor), which reduces the “ripple”—the noise—in the power signal transmitted from the primary side 220 to the secondary side 222 of the transformer 218 .
- the input filter 210 also acts as a local bypass element to keep on-chip supply voltage stable regardless of voltage noise generated by the input current, rapid parametric variations in the package, and bond-wires series resistance and inductance.
- Vout 212 is preferably connected to GND_S 214 through a decoupling capacitor acting as an output filter 216 , which reduces the ripple in the output of the converter 200 , and acts as a local bypass element to keep on-chip supply voltage stable, similarly to the input filter 210 .
- the voltage difference between Vin 206 and GND_P 208 , and the voltage difference between Vout 212 and GND_S 214 are both about 5 volts or less.
- This enables use of smaller (smaller device area) input and output filters 210 , 216 that can be fabricated using relatively inexpensive and/or straightforward processing techniques (preferably the same class of techniques as used for the majority of other converter components), e.g., CMOS processing.
- capacitors rated for approximately 5 volts or less are generally higher density (take up less device area), cheaper to fabricate and can be fabricated with fewer additional process steps than capacitors rated for significantly more than 5 volts (e.g., 10 or 15 volts).
- Switching on the input side 202 and on the output side 204 is preferably adaptive. Accordingly, current through the primary and secondary sides 220 , 222 of the transformer 218 is (respectively) tracked at NMOS transistor turn-on on the primary side 220 , and at NMOS transistor turn-off on the secondary side 222 , to check whether current is positive or negative. Switch timing—signal timing for G 1 P 236 , G 2 P 238 , G 1 S 252 and G 2 S 254 —is then adjusted to enable zero current switching and zero voltage switching of respective NMOS transistors.
- G 1 P 236 and G 2 P 238 are preferably controlled to switch on N 1 P 232 and N 2 P 234 , respectively, when zero voltage is across switch N 1 P 232 or N 2 P 234 , respectively.
- turn-off of primary side switches N 1 P 232 and N 2 P 234 is controlled by a fixed timing (fixed frequency and adaptive duty cycle) selected to obtain zero voltage turn-on of N 2 P 234 and N 1 P 232 (respectively) in the subsequent phase of the cycle.
- the transition time between switching off N 1 P 232 and N 2 P 234 is selected to enable the transformer current to charge V 1 P 228 and V 2 P 230 to Vin (in respective cycle phases) and subsequently discharge V 2 P 230 and V 1 P 228 (respectively) to GND_P 208 , in order to turn on N 2 P 234 and N 1 P 232 (respectively) at zero voltage across the switches N 2 P 234 and N 1 P 232 .
- G 1 S 252 and G 2 S 254 are preferably controlled to switch off N 1 S 248 and N 2 S 250 , respectively, when zero current flows through the secondary side 222 of the transformer 218 , and zero voltage is across switches N 1 S 248 and N 2 S 250 .
- turn-on of secondary side switches N 1 S 248 and N 2 S 250 is controlled by a fixed timing (fixed frequency and adaptive duty cycle) according to a selected switching frequency of the converter 200 .
- Input side 202 and output side 204 switch timings are also preferably independent of each other.
- output side timings are similar to (or the same as) input side timings in having the same switching frequency and duty cycle, but with a phase delay with respect to input side timings—accordingly, output side timings are phase shifted later than corresponding input side timings.
- G 1 S 252 and G 2 S 254 can be tied to GND_S 214 or otherwise connected such that N S 248 and N 2 S 250 remain always off (providing a diode-like effect) and perform passive rectification (as described further with respect to FIGS. 3 and 5 ). This can generally be done without compromising function of the output side 204 , except that conduction losses from N 1 S 248 and N 2 S 250 will be higher than when they are switched (switching of N 1 S 248 and N 2 S 250 is further described with respect to FIG. 3 ).
- the increase in conduction losses from not switching N 1 S 248 and N 2 S 250 can be less relevant in high voltage applications, and may come with efficiency gains from avoiding use of control circuits to generate G 1 S 252 and G 2 S 254 signals. Whether switching N 1 S 248 and N 2 S 250 results in improved overall performance for the converter 200 —as determined with respect to efficiency and/or other metric(s)—may be application-dependent.
- FIG. 3 shows a timing diagram 300 for an isolated DC-DC converter 200 as shown in and described with respect to FIG. 2 .
- VLP 302 is the voltage across the primary side 220 of the transformer 218 and equals the voltage at V 1 P 228 minus the voltage at V 2 P 230 . Voltage across the primary side 220 is therefore positive when V 1 P 228 is higher voltage than V 2 P 230 and negative when V 2 P 230 is higher voltage than V 1 P 228 .
- ILP 304 is the current across the primary side 220 from node V 1 P 228 to node V 2 P 230 , and is positive flowing from V 1 P 228 to V 2 P 230 and negative flowing from V 2 P 230 to V 1 P 228 .
- VLS 306 is the voltage across the secondary side 222 of the transformer 218 and equals the voltage at V 1 S 244 minus the voltage at V 2 S 246 . Voltage across the secondary side 222 is therefore positive when V 1 S 244 is higher voltage than V 2 S 246 and negative when V 2 S 246 is higher voltage than V 1 S 244 .
- ILS 308 is the current across the secondary side 222 from node V 1 S 244 to node V 2 S 246 , and is positive flowing from V 1 S 244 to V 2 S 246 and negative flowing from V 2 S 246 to V 1 S 244 .
- G 1 P 236 is low, meaning N 1 P 232 is off, and G 2 P 238 is high, meaning N 2 P 234 is on. Because N 2 P 234 is on, V 2 P 230 and the gate of P 1 P 224 are connected to GND_P 208 and are therefore pulled low. As a result, P 1 P 224 is on, connecting V 1 P 228 and the gate of P 2 P 226 to Vin 206 and thereby pulling V 1 P 228 high, which causes P 2 P 226 to be off. This means that VLP 302 is high (V 1 P 228 is high and V 2 P 230 is low).
- ILP 304 (current across the primary side 220 ) has a slope determined by the interaction of Vin 206 , Vout 212 , and transformer parameters (e.g., the transformer turns ratio and the leakage inductance of the transformer 218 on the primary side 220 ).
- VLP 302 being high will contribute to increasing the slope of ILP 304 (in a positive direction).
- N 2 P 234 is turned off at a time selected to enable V 2 P 230 to be fully charged and V 1 P 228 to be fully discharged by the current through the inductor, ILP 304 , before G 1 P 236 going high to switch on N 1 P 232 (i.e., to enable zero voltage turn-on of N 1 P 232 ).
- the current across the primary side 220 , ILP 304 subsequently drives charge into the parasitic capacitances connected to V 2 P 230 (corresponding to C 2 122 , see FIG. 1 )—which includes the gate-source capacitance of P 1 P 224 , as described hereinabove with respect to FIG. 1 —causing V 2 P 230 to increase and causing VLP 302 to fall to zero.
- V 2 P 230 is high (fully charged by the current across the inductor 218 , as described with respect to FIG. 2 ) and VLP 302 reaches zero voltage—i.e., zero voltage difference exists between V 1 P 228 , which is high, and V 2 P 230 , which is also high.
- V 2 P 230 being high causes P 1 P 224 to turn off, so that V 1 P 228 is no longer pulled up by Vin 206 .
- VLP 302 below zero contributes to decreasing the slope of ILP 304 (increasing the slope of ILP 304 in a negative direction).
- V 1 P 228 reaches its low state, so G 1 P 236 is controlled to go high to turn on N 1 P 232 (zero voltage switch on, i.e., ZVS). This connects V 1 P 228 to GND_P 208 , pulling V 1 P 228 low. V 1 P 228 is already low when connected to GND_P 208 , so no (or minimal) losses occur from discharge of parasitic capacitances connected to V 1 P 228 (corresponding to C 1 114 ). V 1 P 228 being low turns on P 2 P 226 , which connects V 2 P 230 to Vin 206 , pulling V 2 P 230 high.
- signal behaviors of the converter 200 at times T 4 , T 5 and T 6 echo the signal behaviors described with respect to FIG. 3 at times T 1 , T 2 and T 3 , respectively, except: voltages and currents across the primary side 220 have the opposite sign; and P 2 P 226 , V 2 P 230 , N 2 P 234 and G 2 P 238 have the behaviors described hereinabove with respect to P 1 P 224 , V 1 P 228 , N 1 P 232 and G 1 P 236 , and vice versa. Accordingly, T 1 , T 2 , T 3 cover a half cycle of operation of the converter 200 , and T 4 , T 5 and T 6 cover another half cycle of operation of the converter 200 (in the same cycle).
- Operation of the converter 200 (switch behaviors) during the half cycle covered by T 4 , T 5 and T 6 is the same as operation of the converter 200 during the half cycle covered by T 1 , T 2 , T 3 , except that the roles of switches (on both the input side 202 and the output side 204 ) on different sides of respective inductors (the primary side 220 and the secondary side 222 ) are exchanged to enable current to flow in the reverse direction.
- This can also be thought of as repeating switch and signal behaviors of times T 1 , T 2 and T 3 at times T 4 , T 5 and T 6 as if the terminals of the primary side 220 are reversed, and the terminals of the secondary side 222 are reversed.
- Example timings for output side 204 switching and signals can be determined from FIG. 3 .
- the output side 204 timings shown in FIG. 3 are examples, as described hereinabove, and output side 204 timings are generally independent from input side 202 timings.
- output side 204 switch control signals G 1 S 252 and G 2 S 254 will preferably turn on NMOS transistors N 1 S 248 and N 2 S 250 when voltage across the respective transistor is zero (at a time corresponding to a specified switching frequency; preferably, as soon as the voltage across the transistor reaches zero to maximize power transmitted to Vout 212 ).
- This also corresponds to voltage across the secondary side 222 , VLS 306 , being at a maximum positive or negative value, meaning that one of V 1 S 244 or V 2 S 246 is low, and the other is high.
- G 1 S 252 switches on N 1 S 248
- V 2 S 246 is low (voltage across N 2 S 250 is zero)
- G 2 S 254 switches on N 2 S 250 (zero voltage turn-on).
- G 1 S 252 or G 2 S 254 will switch off NMOS transistor N 1 S 248 or N 2 S 250 (respectively) when current through the secondary side 222 , ILS 308 , is zero (zero current turn-off) and voltage across the respective NMOS transistor being turned off is zero (zero voltage turn-off).
- gates of low-side NMOS transistors N 1 S 248 and N 2 S 250 can be connected to ground so that they perform passive rectification on currents through the secondary side (ILS 308 ). This prevents negative output current (from Vout 212 to GND_S 214 ) and can reduce the need for complex rectification circuitry, at the cost of the voltage drop across N 1 S 248 and N 2 S 250 diodes.
- Active (or synchronous) rectification is performed by low-side NMOS transistors N 1 P 232 , N 2 P 234 , N 1 S 248 and N 2 S 250 switching on to conduct current when the current is or is about to flow in the correct (positive) direction (from Vin 206 to GND_P 208 , or from GND_S 214 to Vout 212 ), thereby preventing (negative) current in the opposite direction.
- V 1 P 228 , V 2 P 230 , V 1 S 244 or V 2 S 246 might otherwise be too high, potentially causing power losses by resulting in negative current or (on the output side 104 ) reduced output voltage (at Vout 212 )
- the problematic node will be grounded by N 1 P 232 , N 2 P 234 , N 1 S 248 or N 2 S 250 , respectively.
- Switch and signal timings described with respect to, e.g., FIGS. 2 and 3 are used to achieve these results.
- Secondary side diodes (of N 1 S 248 and N 2 S 250 ) also help to prevent negative output current; accordingly, in the converter 200 as shown in FIG. 2 , passive rectification is performed alongside active rectification.
- FIG. 4 shows a transistor-level diagram of a high output voltage isolated DC-DC converter 400 .
- the input side 402 of the converter 400 is arranged the same as the input side 202 of the converter 200 (see FIG. 2 ).
- the output side 404 of FIG. 4 comprises two instances of the output side 204 of the converter 200 , an output instance 406 and a ground instance 408 .
- the output instance 406 and the ground instance 408 are “stacked”.
- Vout 212 of the output instance 406 comprises Vout 410 of the converter 400 ;
- GND_S 214 of the ground instance 408 comprises GND_S 412 of the converter 400 ;
- GND_S 214 of the output instance 406 is connected to Vout 212 of the ground instance 408 at Vout/2 414 .
- V 1 S 244 and V 2 S 246 are connected to the terminals of the secondary side 222 of the transformer 218 through isolation capacitors 416 C1 and 416 C2 which isolate the respective V 1 S 244 and V 2 S 246 nodes of the output instance 406 and the ground instance 408 from each other.
- an output capacitor 418 O is connected between Vout 410 and Vout/2 414
- another output capacitor 418 G is connected between Vout/2 414 and GND_S 412 .
- the stacked output instance 406 and ground instance 408 act as a voltage doubler, with the input voltage of Vin 206 as the base (doubled) voltage.
- Vout/2 414 acts as the voltage output for the ground instance 408 and as the ground for the output instance 406 (the ground instance and output instance are otherwise isolated from each other by the isolation capacitors 416 C1 and 416 C2 ). Consequently, the voltage at Vout/2 414 is one half of the voltage at Vout 410 (and this voltage is also available as an output).
- the ground instance 408 and the output instance 406 each function similarly to the output side 204 of converter 200 of FIG. 2 .
- the converter 400 of FIG. 4 retains the efficiency advantages of the converter 200 of FIG. 2 , while being able to output twice as high a voltage—e.g., 10 volts output given a 5 volt input—without requiring components rated for a correspondingly higher voltage.
- a voltage e.g. 10 volts output given a 5 volt input
- isolation capacitors 416 and output capacitors 418 O , 418 G are 5 volt capacitors
- the various NMOS and PMOS transistors on the output side 204 of the converter 400 can be 5 volt transistors; with capacitors and transistors preferably fabricated using relatively inexpensive and/or straightforward processing techniques, preferably the same class of techniques, e.g., CMOS processing.
- Enabling high voltage output without requiring high voltage components lowers process complexity (e.g., component complexity, number of process steps and number of masks required) and therefore process cost and required device area, and preserves applicability of CMOS fabrication (which is relatively simple and low cost and avoids fabrication process limitations).
- This approach also enables use of a relatively low transformer turns ratio, e.g., 1:1, maintaining transformer symmetry.
- FIG. 5 shows a transistor-level diagram of a high output voltage isolated DC-DC converter 500 in which the bias of the NMOS transistors in the ground instance 408 of the output side 404 , N 1 S 248 and N 2 S 250 , are respectively connected to their own source, so that transistors N 1 S 248 and N 2 S 250 (of the ground instance 408 ) act as diodes.
- the resonance (the secondary side 214 ) is sufficient to drive charge into and out of the respective nodes V 1 S 242 and V 2 S 244 of the output instance 406 and the ground instance 408 to implement self-switching of respective PMOS transistors P 1 S 240 and P 2 S 242 and thereby drive the secondary side 222 . This avoids switching losses from N 1 S 248 and N 2 S 250 without using control signals and without paying the power (and device area) cost of corresponding control circuitry.
- the voltage drop across the NMOS transistors N 1 S 248 and N 2 S 250 in the ground instance 408 of the converter 500 shown in and described with respect to FIG. 5 is slightly higher than the voltage drop across the NMOS transistors N 1 S 248 and N 2 S 250 (switched using control signals G 1 S 252 and G 2 S 254 ) in the converter 400 shown in and described with respect to FIG. 4 .
- N 1 S 248 and N 2 S 250 in the ground instance 408 of the converter 500 in FIG. 5 are configured to act as diodes, rather than as switched transistors.
- slightly higher conduction losses occur in a converter 500 of FIG. 5 than in a converter 400 of FIG. 4 .
- N 1 S 248 and N 2 S 250 prevent negative output current due to their function as diodes.
- FIG. 6A shows an example of a process 600 for controlling an isolated DC-DC converter.
- an input side 202 low side switch e.g., NMOS
- NMOS primary side ground 208
- Zero voltage at the first primary side 220 terminal causes a high side switch (e.g., a PMOS that has its gate coupled to the first terminal, its drain coupled to a second primary side 220 transformer terminal and its source coupled to Vin 206 ) to turn on, connecting the second terminal to Vin 206 in step 604 .
- a high side switch e.g., a PMOS that has its gate coupled to the first terminal, its drain coupled to a second primary side 220 transformer terminal and its source coupled to Vin 206
- the low side switch After a period selected to enable a current through the primary side 220 to (after the low side switch is turned off) charge the first terminal to an input voltage 206 and discharge the second terminal to a primary side ground 208 voltage, the low side switch is turned off, disconnecting the first terminal from ground 208 in step 606 .
- the gate of the self-driven high side switch is released (from ground 208 ), which allows the high side switch gate to be driven by current through the primary side 220 to input voltage Vin 206 ; this causes the high side switch to open, disconnecting the second terminal from Vin 206 in step 608 .
- the current through the primary side 220 then drives the voltage at the second terminal to ground (GND_P 208 ) in step 610 .
- the process is then repeated in the opposite direction (as if the terminals were reversed, i.e., the first terminal substituted for the second and vice versa, using different corresponding high side and low side switches) in step 612 .
- the disoverlap time between the turn off of the first low side switch and the turn on time of the second low side switch is selected to allow the full voltage swing of the switching nodes, enabling zero voltage switching of the second low side switch.
- FIG. 6B shows an example of a process 614 for controlling an isolated DC-DC converter.
- an output side 204 low side (e.g., NMOS) switch is turned on at a specified time (corresponding to a specified switching frequency) when zero voltage is across the low side switch; turning on the low side switch connects a corresponding first secondary side 222 transformer terminal to the secondary side ground 214 (GND_S 214 ).
- the resulting zero voltage at the first secondary side 222 terminal causes a high side switch (e.g., PMOS) which is coupled to (when activated) connect a second secondary side 222 transformer terminal to Vout 212 to turn on, connecting the second terminal to Vout 212 in step 618 .
- PMOS secondary side switch
- the low side switch is turned off, disconnecting the first secondary side 222 terminal from the secondary side ground 214 in step 620 .
- the gate of the high side switch opens, disconnecting the second secondary side 222 terminal from Vout 212 in step 622 .
- the current through the secondary side 222 then drives the voltage at the second secondary side 222 terminal to the secondary side ground voltage in step 624 .
- the process is then repeated in the opposite direction (with different corresponding high side and low side switches) in step 626 .
- FIG. 7 shows an example of a transistor-level diagram of a circuit portion 700 used to construct an isolated DC-DC converter.
- the drains of two NMOS transistors HS 1 702 (high side 1 ) and HS 2 704 (high side 2 ) are connected to a voltage input Vin 706 .
- the gate of HS 1 702 is connected (via a buffer) to a control voltage G 1 708
- the gate of HS 2 704 is connected (via a buffer) to a control voltage G 2 710 .
- the source of HS 1 702 is connected to node V 1 712
- the source of HS 2 704 is connected to node V 2 714 .
- V 1 712 is connected to a first terminal of an inductor 716
- V 2 714 is connected to a second terminal of the inductor 716
- An NMOS transistor LS 1 718 (low side 1 ) is connected between V 1 712 and a ground GND 720
- An NMOS transistor LS 2 722 (low side 2 ) is connected between V 2 714 and GND 720 .
- the sources of LS 1 718 and LS 2 722 are connected to GND 720 .
- the gates and drains of LS 1 718 and LS 2 722 are cross-coupled between V 1 712 and V 2 714 .
- the drain of LS 1 718 is connected to V 1 712 , and the gate of LS 1 718 is connected to V 2 714 through a voltage limiter VL 1 724 ; and the drain of LS 2 722 is connected to V 2 714 , and the gate of LS 2 722 is connected to V 1 712 through a voltage limiter VL 2 726 .
- the bias voltage of LS 1 718 is V 2 714 , limited by voltage limiter VL 1 724
- the bias voltage of LS 2 722 is V 1 712 , limited by voltage limiter VL 2 726 .
- Voltage limiters VL 1 724 and VL 2 726 are further described with respect to FIG. 10 .
- the inductor 716 can also be considered a primary side or a secondary side of a transformer—accordingly, as described with respect to FIG. 1 , the primary side or secondary side of a transformer is an inductor.
- Circuit portion 700 can be used to construct an isolated DC-DC converter such that the primary side or secondary side of a transformer in the converter stands in place of the inductor 716 , as shown with respect to FIGS. 8 and 10 .
- the NMOS transistors HS 1 702 and HS 2 704 are preferably zero voltage switched and zero current switched. Accordingly, G 1 708 and G 2 710 are controlled to turn on OR off (generally one or the other and not both; the other of turn-on or turn-off timing is determined using other criteria, such as further described with respect to FIG. 9 ) HS 1 702 and HS 2 704 when corresponding adjacent source nodes V 1 712 and V 2 714 are fully charged to Vin 706 , and zero current flows across the inductor 716 (from node V 1 712 to node V 2 714 or vice versa). (Zero voltage switching and zero current switching are further described with respect to FIGS. 3 and 9 .) This results in minimal switching losses, because little or no voltage is across (or little or no current is conducted by) HS 1 702 or HS 2 704 (for either the turn-on or turn-off transition), while they are switched.
- power cost for MOSFET control is reduced by making LS 1 718 and LS 2 720 self-driving. Accordingly, rather than requiring control signals to bias LS 1 718 and LS 2 720 , LS 1 718 and LS 2 720 are biased by charge driven to LS 1 718 and LS 2 720 via nodes V 2 714 and V 1 712 (respectively; and through voltage limiters VL 1 724 and VL 2 726 , respectively) by the current through the resonance (inductor 716 ). Self-driving LS 1 718 and LS 2 720 reduces the complexity and power cost of controlling the MOSFETS.
- those gate charges charges of gate-source parasitic capacitances
- charges of respective drain-source parasitic capacitances are driven out of parasitic capacitances adjacent to V 1 712 or V 2 714 by the resonance current, turned into current across the inductor 716 , and (in part) are used to charge parasitic capacitances adjacent to V 2 714 or V 1 712 (respectively).
- gate charge of LS 1 718 and LS 2 720 are reused, the tradeoff between QG (gate charge) and RDS (drain-source on resistance) can be largely avoided for LS 1 718 and LS 2 720 .
- a lower RDS can generally be used, thereby enabling faster switching and lower heat output, without resulting in excessive power costs due to a higher QG, because the gate charge power cost is largely avoided (energy used to bias LS 1 718 and LS 2 720 is repeatedly recovered) after initial charging.
- the sources of LS 1 718 and LS 2 720 are preferably connected directly to GND 720 , reducing the power required to bias LS 1 718 and LS 2 720 .
- LS 1 718 and LS 2 720 can be driven using fixed frequency, fixed or adaptive duty cycle signals. Driving LS 1 718 and LS 2 720 at a fixed frequency, with a fixed or adaptive duty cycle, reduces the complexity and power cost of controlling the MOSFETS. (Duty cycle can be adaptive to maintain zero voltage switching and zero current switching conditions despite variations of circuit parameters or switching frequency.)
- RMS currents are minimized to thereby lower conduction losses.
- FIG. 8 shows a transistor-level diagram of an isolated DC-DC converter 800 .
- the converter 800 can be broadly described as two instances of the circuit portion 700 , one on the input side 802 and one on the output side 804 .
- a transformer 806 comprises a primary side 808 and a secondary side 810 .
- the primary side 808 and secondary side 810 of the transformer 806 each preferably function similarly, with respect to their respective side of the converter 800 (i.e., the input side 802 and the output side 804 ), to the inductor 716 of the circuit portion 700 described with respect to FIG. 7 .
- input voltage Vin 812 is connected to the drains of two high side NMOS transistors, HS 1 P 814 and HS 2 P 816 .
- HS 1 P 814 and HS 2 P 816 are switched by control signals G 1 P 818 and G 2 P 820 connected (through buffers) to the gates of HS 1 P 814 and HS 2 P 816 , respectively.
- Node V 1 P 822 is connected to the source of HS 1 P 814
- node V 2 P 824 is connected to the source of HS 2 P 816 .
- the drains and gates of low side NMOS transistors LS 1 P 826 and LS 2 P 828 are cross-coupled between V 1 P 822 and V 2 P 824 , the connections between nodes (V 2 P 824 and V 1 P 822 ) and gates (of LS 1 P 826 and LS 1 P 828 ) being made through voltage limiters VL 1 P 830 and VL 2 P 832 , respectively.
- the drain of LS 1 P 826 is connected to V 1 P 822 , and the gate of LS 1 P 826 is connected to VL 1 P 830 which is connected to V 2 P 824 ; and the drain of LS 2 P 828 is connected to V 2 P 824 , and the gate of LS 2 P 828 is connected to VL 2 P 832 which is connected to V 1 P 822 .
- Voltage limiters VL 1 P 830 and VL 2 P 832 limit the voltage that reaches the gates of LS 1 P 826 and LS 1 P 828 , respectively.
- VL 1 P 830 and VL 2 P 832 limit the voltages that reach the gates of LS 1 P 826 and LS 1 P 828 , respectively, to 5 volts.
- the sources of LS 1 P 826 and LS 2 P 828 are connected to primary side ground GND_P 834 .
- the primary side 808 of the transformer 806 is connected between V 1 P 822 and V 2 P 824 .
- output voltage Vout 834 is connected to the drains of two high side NMOS transistors, HS 1 S 836 and HS 2 S 838 .
- HS 1 S 836 and HS 2 S 838 are switched by control signals G 1 S 840 and G 2 S 842 connected (through buffers) to HS 1 S 836 and HS 2 S 838 , respectively.
- Node V 1 S 844 is connected to the source of HS 1 S 836
- node V 2 S 846 is connected to the source of HS 2 S 838 .
- NMOS transistors LS 1 S 848 and LS 2 S 850 are cross-coupled between V 1 S 844 and V 2 S 846 , the connections between nodes (V 2 S 846 and V 1 S 844 ) and gates (of LSS 848 and LSS 850 ) being made through voltage limiters VLS 852 and VL 2 S 854 , respectively.
- the drain of LS 1 S 848 is connected to V 1 S 844 , and the gate of LSS 848 is connected to VL 1 S 852 which is connected to V 2 S 846 ; and the drain of LS 2 S 850 is connected to V 2 S 846 , and the gate of LS 2 S 850 is connected to VL 2 S 854 which is connected to V 1 S 844 .
- the sources of LSS 848 and LS 2 S 850 are connected to secondary side ground GND_S 856 .
- the secondary side 810 of the transformer 806 is connected between V 1 S 844 and V 2 S 846 .
- Switching on the input side 802 and on the output side 804 is preferably adaptive. Accordingly, current through the primary and secondary sides 808 , 810 of the transformer 806 is (respectively) tracked at high side transistor turn-on on the primary side 808 , and at high side transistor turn-off on the secondary side 810 , to check whether current is positive or negative. Switch timing—signal timing for G 1 P 818 , G 2 P 820 , G 1 S 840 and G 2 S 842 —is then adjusted to enable zero current switching of respective high side transistors.
- G 1 P 818 and G 2 P 820 are preferably controlled to switch on HS 1 P 814 and HS 2 P 816 , respectively, when zero current flows through the primary side 808 of the transformer 806 and zero voltage is across the transistor being switched on.
- G 1 P 818 and G 2 P 820 are preferably controlled to switch off HS 1 P 814 and HS 2 P 816 , respectively, at a time selected to enable the current across the primary side to (after the high side transistor is switched off) fully discharge V 1 P 822 or V 2 P 824 (respectively) to the primary side ground voltage and fully charge V 2 P 824 or V 1 P 822 (respectively) to the input voltage.
- G 1 S 840 and G 2 S 842 are preferably controlled to switch on HS 1 S 836 and HS 2 S 838 , respectively, when zero voltage is across the transistor being switched on, at a time selected to correspond to a switching frequency dependent on the switching frequency of the primary side, and dependent on capacitor and inductor parameters.
- G 1 S 840 and G 2 S 842 are preferably controlled to switch off HS 1 S 836 and HS 2 S 838 , respectively, when zero current flows through the secondary side 810 of the transformer 806 and zero voltage is across the transistor being switched off.
- Input side 802 and output side 804 switch timings are also preferably independent of each other.
- the converter 800 also preferably comprises an input decoupling capacitor 858 connected between Vin 812 and GND_P 832 , and an output decoupling capacitor 860 connected between Vout 834 and GND_S 856 (as described hereinabove for decoupling capacitors, also called ripple capacitors, of FIG. 2 ).
- FIG. 9 shows an example of a timing diagram 900 for an isolated DC-DC converter 800 as shown in FIG. 8 .
- VLP 902 is the voltage across the primary side 808 of the transformer 806 and equals the voltage at V 1 P 822 minus the voltage at V 2 P 824 . Voltage across the primary side 808 is therefore positive when V 1 P 822 is higher voltage than V 2 P 824 and negative when V 2 P 824 is higher voltage than V 1 P 822 .
- ILP 904 is the current across the primary side 808 from node V 1 P 822 to node V 2 P 824 , and is positive flowing from V 1 P 822 to V 2 P 824 and negative flowing from V 2 P 824 to V 1 P 822 .
- VLS 906 is the voltage across the secondary side 810 of the transformer 806 and equals the voltage at V 1 S 844 minus the voltage at V 2 S 846 . Voltage across the secondary side 810 is therefore positive when V 1 S 844 is higher voltage than V 2 S 846 and negative when V 2 S 846 is higher voltage than V 1 S 844 .
- ILS 908 is the current across the secondary side 810 from node V 1 S 844 to node V 2 S 846 , and is positive flowing from V 1 S 844 to V 2 S 846 and negative flowing from V 2 S 846 to V 1 S 844 .
- V 1 P 822 is low, V 2 P 824 is high, G 1 P 818 is low, and G 2 P 820 is high. Because G 1 P 818 is low, HS 1 P 814 is off. Because G 2 P 820 is high, HS 2 P 816 is on, connecting V 2 P 824 to Vin 812 , pulling V 2 P 824 high. Because V 1 P 822 is low, LS 2 P 828 is off. Because V 2 P 824 is high, LS 1 P 826 is on, connecting V 1 P 822 to GND 834 , pulling V 1 P 822 low.
- VLP 902 is negative, and ILP 904 has a slope determined by Vin 812 , Vout 834 and parameters of the transformer 806 (as described hereinabove for current with respect to FIG. 3 ).
- Vin 812 Vin 812
- Vout 834 parameters of the transformer 806
- V 2 P 824 is zero, turning off LS 1 P 826 .
- VLP 902 is also zero (V 1 P 822 and V 2 P 824 are both zero).
- current across the primary side 808 ILP 904 ) charges the parasitic capacitances connected to V 1 P 822 , causing V 1 P 822 to rise and VLP 902 to increase above zero.
- V 1 P 822 is high, turning on LS 2 P 828 , and G 1 P 818 goes high, turning on HS 1 P 814 , which pulls up V 1 P 822 .
- the voltage across HS 1 P 814 is zero, because the source-drain path of HS 1 P 816 is connected to Vin 812 and V 1 P 822 , and V 2 P 822 is high.
- VLP 902 is positive.
- signal behaviors of the converter 800 at times T 4 , T 5 and T 6 echo the signal behaviors described with respect to FIG. 9 at times T 1 , T 2 and T 3 , respectively, except: voltages and currents across the primary side 808 have the opposite sign; and HS 1 P 814 , V 1 P 822 , LS 1 P 826 and G 1 P 818 have the behaviors described hereinabove with respect to HS 2 P 816 , V 2 P 824 , LS 2 P 828 and G 2 P 820 , and vice versa.
- the switch and signal behaviors of times times T 1 , T 2 and T 3 are preferably repeated at times T 4 , T 5 and T 6 as if the terminals of the primary side 808 and secondary side 810 had been reversed.
- Example timings for output side 804 switching and signals can be determined from FIG. 9 .
- the output side 804 timings shown in FIG. 9 are examples, as described hereinabove, and output side 804 timings are generally independent from input side 802 timings.
- output side 804 switch control signals G 1 S 840 and G 2 S 842 will preferably turn on HS 1 S 836 and HS 2 S 838 when VLS 906 is at a maximum positive or negative value, meaning that one of V 1 S 844 or V 2 S 846 is low, and the other is high. Accordingly, if V 1 S 844 is high, then G 1 S 840 switches on HS 1 S 836 , and if V 2 S 846 is high, then G 2 S 842 switches on HS 2 S 838 . Also, G 1 S 840 or G 2 S 842 will switch off NMOS transistor HS 1 S 836 or HS 2 S 838 (respectively) when current through the secondary side, ILS 810 , is zero (zero current turn-off).
- NMOS transistors HS 1 P 814 , HS 2 P 816 perform active rectification on currents across the primary side 808 (ILP 904 ), and NMOS transistors HS 1 S 836 and HS 2 S 838 perform passive and active rectification on currents across the secondary side 810 (ILS 908 ), as described hereinabove regarding active and passive rectification with respect to FIG. 3 .
- Switching of these NMOS transistors prevents both negative input currents and negative output currents. This can reduce the need for complex rectification circuitry.
- FIG. 10 shows an example of a transistor-level diagram of a high voltage isolated DC-DC converter 1000 .
- the converter 1000 of FIG. 10 is based on the converter 800 of FIG. 8 , with voltage limiters comprising clamping NMOS transistors and bootstrap circuits used to drive the high side transistors.
- Vin 812 and Vout 834 can be significantly higher than 5 volts, e.g., Vin 812 of 12 volts and Vout 834 of 12 volts.
- HS 1 P 814 , HS 2 P 816 , HS 1 S 836 and HS 2 S 838 are LDMOS transistors, enabling them to function effectively when biased by high voltages (e.g., 17 volts).
- voltage limiter VL 1 P 830 comprises an NMOS transistor VL 1 P 1002 and voltage limiter VL 2 P 832 comprises an NMOS transistor VL 2 P 1004 .
- Both VL 1 P 1002 and VL 2 P 1004 preferably have their gates connected to an input voltage V clamp P 1006 , which acts as a clamping voltage.
- V clamp P 1006 is preferably set to 5 volts so that the low side transistors LS 1 P 826 and LS 2 P 828 will not be biased by more than 5 volts. This enables LS 1 P 826 and LS 2 P 828 to be fabricated as CMOS devices (usually rated for 5 volts or less).
- the source of VL 1 P 1002 is preferably connected to the gate of LS 1 P 826 , a capacitor C 1 P 1008 which is also connected to primary ground GND_P 834 , and the source of a bootstrap circuit-controlling NMOS transistor BS 1 P 1010 .
- the drain of VL 1 P 1002 is preferably connected to V 2 P 824 and to the gate of BS 1 P 1010 .
- the drain of BS 1 P 1010 is preferably connected to a node V BS 1 P 1012 , which is also connected to bootstrap capacitor C BS 1 P 1014 and to supply a level shifting buffer B BS 1 P 1016 (bootstrap capacitor C BS 1 P 1014 acts as the supply for the buffer B BS 1 P 1016 ).
- C BS 1 P 1014 is also connected to V 1 P 822 .
- Buffer B BS 1 P 1016 is also connected to connect G 1 P 818 to the gate of HS 1 P 814 . Because the voltage at V BS 1 P 1012 preferably rises several volts above the maximum voltage reached by V 1 P 822 (as further described hereinbelow), which itself is preferably significantly above 5 volts (e.g., 12 volts), B BS 1 P 1016 is used to protect control circuits producing G 1 P 818 (usually operating at 5 volts or less) from that elevated voltage, and to enable G 1 P 818 to effectively control HS 1 P 814 .
- An example level shifting buffer can include multiple inverters, with successive inverters (in the direction of travel from the lower voltage regime to the higher voltage regime) having larger area transistors than preceding inverters.
- the source of VL 2 P 1004 is preferably connected to the gate of LS 2 P 828 , a capacitor C 2 P 1018 which is also connected to primary ground GND_P 834 , and the source of a bootstrap circuit-controlling NMOS transistor BS 2 P 1020 .
- the drain of VL 2 P 1004 is preferably connected to V 1 P 822 and to the gate of BS 2 P 1020 .
- the drain of BS 2 P 1020 is preferably connected to a node V BS 2 P 1022 , which is also connected to bootstrap capacitor C BS 2 P 1024 and to supply a level shifting buffer B BS 2 P 1026 (bootstrap capacitor C BS 2 P 1024 acts as the supply for the buffer B BS 2 P 1026 ).
- C BS 2 P 1024 is also connected to V 2 P 824 .
- Buffer B BS 2 P 1026 is also connected to connect G 2 P 820 to the gate of HS 2 P 816 . Because the voltage at V BS 2 P 1022 preferably rises several volts above the maximum voltage reached by V 2 P 824 (as further described hereinbelow), which itself is preferably significantly above 5 volts (e.g., 12 volts), B BS 2 P 1026 is used to protect control circuits producing G 2 P 820 (usually operating at 5 volts or less) from that elevated voltage, and to enable G 2 P 820 to effectively control HS 2 P 816 .
- voltage limiter VL 1 S 852 comprises an NMOS transistor VL 1 S 1028 and voltage limiter VL 2 S 854 comprises an NMOS transistor VL 2 S 1030 .
- Both VL 1 S 1028 and VL 2 S 1030 preferably have their gates connected to an input voltage V clamp S 1032 , which acts as a clamping voltage.
- V clamp S 1032 is preferably set to 5 volts so that the low side transistors LS 1 S 848 and LS 2 S 850 will not be biased by more than 5 volts. This enables LS 1 S 848 and LS 2 S 850 to be fabricated as CMOS devices (usually rated for 5 volts or less).
- the source of VL 1 S 1028 is preferably connected to the gate of LS 1 S 848 , a capacitor C 1 S 1034 which is also connected to secondary ground GND_S 856 , and the source of a bootstrap circuit-controlling NMOS transistor BS 1 S 1036 .
- the drain of VL 1 S 1028 is preferably connected to V 2 S 846 and to the gate of BS 1 S 1036 .
- the drain of BS 1 S 1036 is preferably connected to a node V BS 1 S 1038 , which is also connected to bootstrap capacitor C BS 1 S 1040 and to supply a level shifting buffer B BS 1 S 1042 (bootstrap capacitor C BS 1 S 1040 acts as the supply for the buffer B BS 1 S 1042 ).
- C BS 1 S 1040 is also connected to V 1 S 844 .
- B BS 1 S 1042 is also connected to connect G 1 S 840 to the gate of HS 1 S 836 . Because the voltage at V BS 1 S 1038 preferably rises several volts above the maximum voltage reached by V 1 S 844 (as further described hereinbelow), which itself is preferably significantly above 5 volts (e.g., 12 volts), B BS 1 S 1042 is used to protect control circuits producing G 1 S 840 (usually operating at 5 volts or less) from that elevated voltage, and to enable G 1 S 840 to effectively control HS 1 S 836 .
- the source of VL 2 S 1030 is preferably connected to the gate of LS 2 S 850 , a capacitor C 2 S 1044 which is also connected to secondary ground GND_S 856 , and the source of a bootstrap circuit-controlling NMOS transistor BS 2 S 1046 .
- the drain of VL 2 S 1030 is preferably connected to V 2 S 846 and to the gate of BS 2 S 1046 .
- the drain of BS 2 S 1046 is preferably connected to a node V BS 2 S 1048 , which is also connected to bootstrap capacitor C BS 2 S 1050 and to supply a level shifting buffer B BS 2 S 1052 (bootstrap capacitor C BS 2 S 1050 acts as the supply for the buffer B BS 2 S 1052 ).
- C BS 2 S 1050 is also connected to V 2 S 846 .
- B BS 2 S 1052 is also connected to connect G 2 S 842 to the gate of HS 2 S 838 . Because the voltage at V BS 2 S 1048 preferably rises several volts above the maximum voltage reached by V 2 S 846 (as further described hereinbelow), which itself is preferably significantly above 5 volts (e.g., 12 volts), B BS 2 S 1052 is used to protect control circuits producing G 2 S 842 (usually operating at 5 volts or less) from that elevated voltage, and to enable G 2 S 842 to effectively control HS 2 S 838 .
- Low side capacitors C 1 P 1008 , C 2 P 1018 , C 1 S 1034 and C 2 S 1044 help reduce the resonance frequency of the converter 1000 .
- Maximum output power of the converter 1000 is a function of the resonance frequency and transformer 806 self inductance.
- Capacitors C 1 P 1008 , C 2 P 1018 , C 1 S 1034 can be physical capacitors, or can correspond to parasitic capacitance, depending on the maximum output power and the design of the transformer 806 .
- An NMOS transistor is turned on when its gate voltage is sufficiently higher than its source voltage.
- the bootstrap capacitors 1016 , 1026 , 1042 , 1052 are used to elevate the gate voltage provided by respective control signals 818 , 820 , 840 , 842 to enable their respective high side PMOS transistors 814 , 816 , 836 , 838 to turn on.
- source voltages (V 1 P 822 , V 2 P 824 ) of input side 802 high side PMOS transistors 814 , 816 can reach approximately Vin 812 ; and source voltages (V 1 S 844 and V 2 S 846 ) of output side 804 high side PMOS transistors 836 , 838 can reach approximately Vout 822 .
- bootstrap capacitors enables high side PMOS transistor gate control voltages (outputs of level shifting buffers 1016 , 1026 , 1042 , 1052 , which are dependent on control voltages 818 , 820 , 840 , 842 ) to reach higher than the input voltage Vin 812 or output voltage Vout 834 (as appropriate).
- the charging path for bootstrap capacitor C BS 1 P 1014 (path of current that charges the capacitor) runs from Vin 812 , through HS 2 P 816 , to V 2 P 824 , through VL 1 P 1002 and BS 1 P 1010 , to V BS 1 P 1012 , to C BS 1 P 1014 .
- the charging path for bootstrap capacitor C BS 2 P 1024 runs from Vin 812 , through HS 1 P 814 , to V 1 P 822 , through VL 2 P 1004 and BS 2 P 1020 , to V BS 2 P 1022 , to C BS 2 P 1024 .
- the charging path for bootstrap capacitor C BS 1 S 1040 runs from GND_S 856 , through LS 2 S 850 to V 2 S 846 , through VL 1 S 1028 and BS 1 S 1036 , to V BS 1 S 1038 , to C BS 1 S 1040 .
- the charging path for bootstrap capacitor C BS 2 S 1050 runs from GND_S 856 , through LS 1 S 848 to V 2 S 844 , through VL 2 S 1030 and BS 2 S 1046 , to V BS 1 S 1048 , to C BS 1 S 1050 .
- the bootstrap capacitors 1014 , 1024 , 1040 , 1050 charge when their respective adjacent node 822 , 824 , 844 , 846 is low. Accordingly, C BS 1 P 1014 charges when V 1 P 822 is low; C BS 2 P 1024 charges when V 2 P 824 is low; C BS 1 S 1040 charges when V 1 S 844 is low; and C BS 2 S 1050 charges when V 2 S 846 is low.
- the converter 1000 also preferably comprises an input decoupling capacitor 858 connected between Vin 812 and GND_P 832 , and an output decoupling capacitor 860 connected between Vout 834 and GND_S 856 (as described hereinabove for decoupling capacitors, also called ripple capacitors, of FIG. 2 ). Input and output decoupling capacitors 858 , 860 are not shown for simplicity.
- the described embodiments provide one or more of at least the following advantages. However, not all of these advantages result from every one of the described embodiments, and this list of advantages is not necessarily exhaustive.
- PMOS transistors cross-coupled between different terminals of a primary or secondary side of a transformer connect that side to a voltage input (on the primary side) or a voltage output (on the secondary side).
- NMOS transistors couple different terminals of that side of the transformer to the respective (primary or secondary side) ground. This enables the voltage input-connected transistors to be self-driven such that gate charge is reused, turned into current across the respective side of the transformer when the gate discharges.
- NMOS transistors are preferably zero current switched (ZCS) and zero voltage switched (ZVS), avoiding significant switching losses. Also, transistor configuration and switch timing avoids negative input and output current. As a result, embodiments using high side cross-coupled switches are highly efficient.
- high side NMOS transistors couple different terminals of a primary or secondary side of a transformer to a voltage input (on the primary side) or a voltage output (on the secondary side).
- Low side NMOS transistors, cross-coupled (through voltage limiters coupled to the low side NMOS transistors' gates) to different terminals of the primary or secondary side of the transformer connect that side to the respective (primary or secondary side) ground. This enables the ground-connected transistors to be self-driven such that gate charge is reused, turned into current through the respective side of the transformer when the gate discharges.
- high side transistors are preferably zero current switched (ZCS) and zero voltage switched (ZVS), avoiding significant switching losses.
- transistor configuration and switch timing avoids negative input and output current. As a result, embodiments using high side cross-coupled switches are useful with high input and/or output voltages and are highly efficient.
- the converter's efficiency specification is stated as a minimum threshold efficiency (such as 50%, which is a ratio of 1 ⁇ 2) for the converter to sustain during its usual operation.
- the converter's efficiency specification is one criteria to help determine whether the converter is suitable for use within a particular operating environment.
- the transformer includes a magnetic coil, and the converter's efficiency specification is 80% or higher.
- biases and sources of respective NMOS transistors are connected to each other, such that NMOS transistors act as diodes, as shown in FIG. 5 .
- an isolated DC-DC converter as shown in FIG. 2, 4 or 5 can comprise NMOS instead of PMOS, and/or PMOS instead of NMOS. In some embodiments, an isolated DC-DC converter as shown in FIG. 2, 4 or 5 can comprise switches made using technologies other than (or supplementary to) CMOS, e.g., LDMOS.
- a high input voltage and high output voltage isolated DC-DC converter comprises an input side and an output side, each side comprising a “stacked” configuration as described with respect to the output side of FIG. 4 .
- the output side comprises a “stacked” output side as described with respect to FIG. 4 ;
- the input side comprises an input instance and a ground instance of the input side of FIG. 2 , the Vin (input voltage) of the input instance comprising the Vin of the input side (i.e., the voltage input for the converter), the ground of the ground instance comprising the ground of the input side, and the ground of the input instance connected to the Vin of the ground instance.
- the input side can comprise stacked instances of the input side of, e.g., FIG. 2 .
- isolation capacitors isolate the ground instance from the transformer. In some embodiments as shown in FIGS. 4 and 5 , isolation capacitors isolate both the ground instance and the output instance from the transformer.
- the output instance and ground instance are also called an output module and ground module herein.
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Abstract
Description
- This application is a non-provisional of and claims priority to U.S. Provisional Pat. App. No. 62/560,647, filed on Sep. 19, 2017, which is hereby incorporated by reference.
- This application is related to co-pending and co-assigned U.S. patent application Ser. No. ______ (docket TI-77168), filed on even date, and entitled, “ISOLATED DC-DC CONVERTER;” and to co-pending and co-assigned U.S. patent application Ser. No. ______ (docket TI-78124), filed on even date, and entitled, “ISOLATED DC-DC CONVERTER.”
- This relates generally to isolated DC-DC converters, and more particularly to efficient, high input and/or output voltage isolated DC-DC converters.
- Isolated DC-DC converters typically include a transformer, with: (a) a power generating input side, typically called the primary side; and (b) a power output side, typically called the secondary side. The differences between an isolated converter and a non-isolated converter are that: (a) in an isolated converter, the primary side and the secondary side have different grounds; and (b) in a non-isolated converter, the primary side and the secondary side share a same ground (such as using an inductor, instead of a transformer, to convert voltage).
- Isolated DC-DC converters can be small enough to fit within an integrated circuit (“IC”) package, but may require significant current on the primary side to drive the secondary side across the isolation barrier, i.e., the gap between the transformer coils. Such converters can be used for transferring power from a high voltage domain to a low voltage domain, such as from a power line to a set of consumer electronics, or from a battery on an electric vehicle to electronics on that vehicle. Grounds in high voltage regimes (e.g., the power line or battery) may have voltage swings (such as 1000V or 1500V swings), which the devices connecting to those grounds are designed to tolerate. Grounds in the low voltage regimes may have much smaller swings (such as much less than 1V), and devices connected to those low voltage grounds could be rendered inoperative if subjected to the voltage swings tolerated in a high voltage regime. Isolation barriers separate high voltage regimes from low voltage regimes, so that power transfer can be performed without damaging low voltage components.
- In described examples, an isolated DC-DC converter includes: an output node for delivering an output voltage; a transformer comprising a secondary side having first and second terminals and a secondary side ground; and a plurality of modules. Ones of the modules include respective: first and second low-side switches, and first and second high-side switches. The first low-side switch is coupled between the first terminal and a low-voltage node, and the second low-side switch is coupled between the second terminal and the low-voltage node. A first voltage is across the first low-side switch, and a second voltage is across the second low-side switch. The first high-side switch is coupled between the first terminal and a high-voltage node, and is configured to be activated by a voltage at the second terminal. The second high-side switch is coupled between the second terminal and the high-voltage node, and is configured to be activated by a voltage at the first terminal. The isolated DC-DC converter also includes a switch controller configured to open and close the first and second low-side switches at times corresponding to a frequency of the converter, as follows. The first low-side switch is closed when the first voltage is zero. During a first phase, the first low-side switch is opened when the first voltage is zero and a current through the secondary side is zero. The second low-side switch is closed when the second voltage is zero. During a second phase, the second low-side switch is opened when the second voltage is zero and the current through the secondary side is zero. A first one of the modules is an output module whose high-voltage node includes the output node. A second one of the modules is a ground module whose low-voltage node includes the secondary side ground. The high-voltage node of the ground module is coupled to the low-voltage node of the output module.
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FIG. 1 shows an example of a transistor-level diagram of a circuit portion used to construct an isolated DC-DC converter. -
FIG. 2 shows a transistor-level diagram of an isolated DC-DC converter. -
FIG. 3 shows a timing diagram for an isolated DC-DC converter as shown in and described with respect toFIG. 2 . -
FIG. 4 shows a transistor-level diagram of a high output voltage isolated DC-DC converter. -
FIG. 5 shows a transistor-level diagram of a high output voltage isolated DC-DC converter. -
FIG. 6A shows an example of a process for controlling an isolated DC-DC converter. -
FIG. 6B shows an example of a process for controlling an isolated DC-DC converter. -
FIG. 7 shows an example of a transistor-level diagram of a circuit portion used to construct an isolated DC-DC converter. -
FIG. 8 shows a transistor-level diagram of an isolated DC-DC converter. -
FIG. 9 shows an example of a timing diagram for an isolated DC-DC converter as shown inFIG. 8 . -
FIG. 10 shows an example of a transistor-level diagram of a high voltage isolated DC-DC converter. - Example embodiments include methods, devices and systems for efficient (and in some embodiments, high input-output voltage), isolated DC-DC converters, particularly using circuits and components that can be incorporated into an integrated circuit (IC) package. In some embodiments, the converters are capable of operating at large minimum voltage differentials between Vin (input voltage) and primary ground, and/or between Vout (output voltage) and secondary ground (e.g., 10V or 15V), as further described hereinbelow.
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FIG. 1 shows an example of a transistor-level diagram of acircuit portion 100 used to construct an isolated DC-DC converter. As shown inFIG. 1 , aninput voltage Vin 102 is connected to the sources of two PMOS transistors,P1 104 and P2 106 (PMOS conduction type). (Diodes shown are intrinsic diodes of respective PMOS and NMOS transistors.) NodesV1 108 andV2 110 are cross-coupled between the drains and gates ofP1 104 and P2 106 (high side switches). Accordingly,node V1 108 is connected to the drain ofP1 104 and is connected to the gate ofP2 106; andnode V2 110 is connected to the drain ofP2 106 and is connected to the gate ofP1 104. - An
inductor 112 can also be considered a primary side or a secondary side of a transformer—accordingly, the primary side or secondary side of a transformer is an inductor, andcircuit portion 100 can be used to construct an isolated DC-DC converter such that the primary side or secondary side of a transformer in the converter stands in place of the inductor 112 (see, e.g.,FIGS. 2, 4, 5, 8 and 10 ). Theinductor 112 is connected betweennodes V1 108 andV2 110. -
Parasitic capacitor C1 114 and the source/drain path of NMOS transistor N1 116 (NMOS conduction type) are connected in parallel betweennode V1 108 and GND 118 (the source ofN1 116 is connected to GND 118).C1 114 corresponds to (represents) parasitic capacitances ofN1 116, P1 104 and P2 106. For example, C1 114 includes drain-source capacitance ofN1 116, drain-source capacitance ofP1 104, and gate-source capacitance ofP2 106. The gate ofN1 116 is connected to a (buffered)control signal G1 120. -
Parasitic capacitor C2 122 and the source/drain path ofNMOS transistor N2 124 are connected in parallel betweennode V2 110 and GND 118 (the source ofN2 124 is connected to GND 118).C2 122 corresponds to (represents) parasitic capacitances ofN2 124, P1 104 andP2 106. For example,C2 122 includes drain-source capacitance ofN2 124, drain-source capacitance ofP2 106, and gate-source capacitance ofP1 104. The gate ofN2 124 is connected to a (buffered)control signal G2 126. (N1 116 andN2 124 comprise low side switches.) -
Inputs G1 120 and G2 126 are preferably generated by acontrol signal generator 128. An isolated DC-DC converter (e.g., as inFIGS. 2, 4, 5, 8 and 10 ) preferably comprises a primary control signal generator and a secondary control signal generator, with the generators respectively and separately connected to generate and deliver control signals to drive controlled switches (e.g.,N1 116 and N2 124). - Preferably, power losses are minimized. Converters can lose power, such as through switching losses, conduction losses, and other dissipative losses. Switching losses in MOSFET devices come from the dynamic voltages and currents a MOSFET handles during the finite, nonzero time it takes to turn on or off. Conduction losses are power dissipation losses resulting from current moving through a component; for example, MOSFET devices have nonzero resistance. Other dissipative losses occur, such as when power is discharged to ground, e.g., when a charged gate or capacitor is connected to ground, resulting in the gate or capacitor discharging.
- In operation, the
NMOS transistors N1 116 andN2 124 are preferably zero voltage switched (ZVS) and zero current switched (ZCS). Accordingly,G1 120 andG2 126 are respectively controlled to turnN1 116 andN2 124 on OR off (generally one or the other and not both; the other of turn-on or turn-off timing is determined using other criteria, such as further described with respect toFIG. 3 ), when correspondingadjacent nodes V1 108 andV2 110 are fully discharged (at zero voltage with respect to GND 118), and zero current flows across the inductor 112 (fromnode V1 108 tonode V2 110 or vice versa). This results in minimal switching losses for either the turn-on or turn-off transition, because little or no voltage is across (and little or no current is conducted by)N1 116 andN2 124 while they are switched. Zero voltage switching and zero current switching are further described hereinbelow with respect toFIG. 3 . (Where this description refers to zero voltage at a node, rather than across a component, it means that the node is at a voltage of a corresponding ground of a primary side or secondary side of a transformer.) - In embodiments as shown in
FIG. 1 , power cost for MOSFET control is reduced by makingP1 104 andP2 106 self-driving. Accordingly, rather than requiring control signals to biasP1 104 andP2 106,P1 104 andP2 106 are biased by charge driven toP1 104 andP2 106 vianodes V2 110 and V1 108 (respectively) by the current through the resonance (inductor 112). Self-drivingP1 104 andP2 106 reduces the complexity and power cost of controlling the MOSFETS. - Further power savings are achieved by using the current across the inductor 112 (the resonance current) to drive charge out of the gates of
MOSFETS P1 104 andP2 106 and turn that charge into current across theinductor 112. Some of that currentcharges capacitances C2 122 andC1 114. (Capacitances C1 114 andC2 122 include gate-source parasitic capacitances ofP1 106 andP2 104, respectively.) This recycling avoids dissipation of gate charges (Cgs charges) whenP1 104 andP2 106 are switched, because those gate charges are reused. Accordingly, those gate charges (charges of gate-source parasitic capacitances), along with charges of respective drain-source and other parasitic capacitances, are driven out ofC1 114 orC2 122 by the resonance current, turned into current across theinductor 112, and (in part) are used to chargeC2 122 or C1 114 (respectively). - Because gate charge of
P1 104 andP2 106 are reused, the tradeoff between QG (gate charge) and RDS (drain-source on resistance) can be largely avoided forP1 104 andP2 106. For example, a lower RDS can generally be used, thereby enabling faster switching and lower heat output, without resulting in excessive power costs due to a higher QG, because the gate charge power cost is largely avoided (energy used to biasP1 104 andP2 106 is repeatedly recovered) after initial charging. (The figure of merit FOM=QG*RDS will generally be approximately constant for a given process technology). Accordingly, the configuration shown inFIG. 1 enablingP1 104 andP2 106 to be self-driven is relatively non-dissipative compared to gate driving using control signals because energy is taken back fromparasitic capacitances C1 114 andC2 122. Energy “recycling” is performed by discharging capacitances and turning voltage into current through theinductor 112. Switching losses are thereby minimized. (See also similar cross-coupled switches inFIG. 7 .) - The sources of
N1 116 andN2 124 are preferably connected directly toGND 118, reducing the power required to biasN1 116 andN2 124. Also,N1 116 andN2 124 can be driven using fixed frequency, fixed or adaptive duty cycle signals. DrivingN1 116 andN2 124 at a fixed frequency, with a fixed or adaptive duty cycle, reduces the complexity and power cost of controlling the MOSFETS. (Duty cycle can be adaptive to maintain zero voltage switching and zero current switching conditions despite variations of circuit parameters or switching frequency, as further described with respect toFIG. 2 .) - Preferably, RMS currents are minimized to thereby lower conduction losses.
-
FIG. 2 shows a transistor-level diagram of an isolated DC-DC converter 200. Theconverter 200 can be broadly described as two instances of thecircuit portion 100, one on theinput side 202 and one on theoutput side 204, except that theinput side 202 also comprises a capacitor connected betweenVin 206 andinput ground GND_P 208 acting as aninput filter 210, and theoutput side 204 also comprises a capacitor connected betweenVout 212 andoutput ground GND_S 214 acting as an output filter 216 (input andoutput filters transformer 218 comprises aprimary side 220 and asecondary side 222. Theprimary side 220 andsecondary side 222 of thetransformer 218 each preferably function similarly, with respect to their respective side of the converter 200 (i.e., theinput side 202 and the output side 204), to theinductor 112 of thecircuit portion 100 described with respect toFIG. 1 . - As shown in
FIG. 2 , on theinput side 202,input voltage Vin 206 is connected to the sources of two PMOS transistors,P1P 224 andP2P 226. Nodes V1P 228 andV2P 230 are cross-coupled between the drains and gates ofP1P 224 andP2P 226. Accordingly,node V1P 228 is connected to the drain ofP1P 224 and the gate ofP2P 226; andnode V2P 230 is connected to the drain ofP2P 226 and the gate ofP1P 224. Theprimary side 220 of thetransformer 218 is connected betweenV1P 228 andV2P 230.V1P 228 is also connected to the drain ofNMOS transistor N1P 232, andV2P 228 is also connected to the drain ofNMOS transistor N2P 234. - Control signal G1P 236 (switch control voltage) is connected (through a buffer) to the gate of
N1P 232, andcontrol signal G2P 238 is connected (through a buffer) to the gate ofN2P 234. The sources of bothN1P 232 andN2P 234 are connected to primaryside ground GND_P 208. (Parasitic capacitances corresponding toC1 114 andC2 122 exist, but are not shown.) - On the
output side 204,Vout 212 is connected to the sources of two PMOS transistors,P1S 240 andP2S 242. Nodes V1S 244 andV2S 246 are cross-coupled between the drains and gates ofP1S 240 andP2S 242. Accordingly,node V1S 244 is connected to the drain ofP1S 240 and is connected to the gate ofP2S 242; andnode V2S 246 is connected to the drain ofP2S 242 and is connected to the gate ofP1S 240. Thesecondary side 204 of thetransformer 218 is connected betweenV1S 244 andV2S 246.V1S 244 is also connected to the drain ofNMOS transistor N1S 248, andV2S 246 is also connected to the drain ofNMOS transistor N2S 250. -
Control signal G1S 252 is connected (through a buffer) to the gate ofN1S 248, andcontrol signal G2S 254 is connected (through a buffer) to the gate ofN2S 250. The sources of bothN1S 248 andN2S 250 are connected to secondaryside ground GND_S 214. (Parasitic capacitances corresponding toC1 114 andC2 122 exist, but are not shown.) -
Vin 206 is preferably connected to GND_P 208 through a capacitor acting as an input filter 210 (a decoupling capacitor), which reduces the “ripple”—the noise—in the power signal transmitted from theprimary side 220 to thesecondary side 222 of thetransformer 218. Theinput filter 210 also acts as a local bypass element to keep on-chip supply voltage stable regardless of voltage noise generated by the input current, rapid parametric variations in the package, and bond-wires series resistance and inductance. Similarly,Vout 212 is preferably connected to GND_S 214 through a decoupling capacitor acting as anoutput filter 216, which reduces the ripple in the output of theconverter 200, and acts as a local bypass element to keep on-chip supply voltage stable, similarly to theinput filter 210. - Preferably, in embodiments as shown in
FIG. 2 , the voltage difference betweenVin 206 andGND_P 208, and the voltage difference betweenVout 212 andGND_S 214, are both about 5 volts or less. This enables use of smaller (smaller device area) input andoutput filters - Switching on the
input side 202 and on theoutput side 204 is preferably adaptive. Accordingly, current through the primary andsecondary sides transformer 218 is (respectively) tracked at NMOS transistor turn-on on theprimary side 220, and at NMOS transistor turn-off on thesecondary side 222, to check whether current is positive or negative. Switch timing—signal timing forG1P 236,G2P 238,G1S 252 andG2S 254—is then adjusted to enable zero current switching and zero voltage switching of respective NMOS transistors. -
G1P 236 andG2P 238 are preferably controlled to switch onN1P 232 andN2P 234, respectively, when zero voltage is acrossswitch N1P 232 orN2P 234, respectively. Preferably, turn-off of primary side switchesN1P 232 andN2P 234 is controlled by a fixed timing (fixed frequency and adaptive duty cycle) selected to obtain zero voltage turn-on ofN2P 234 and N1P 232 (respectively) in the subsequent phase of the cycle. Accordingly, the transition time between switching offN1P 232 andN2P 234 is selected to enable the transformer current to chargeV1P 228 andV2P 230 to Vin (in respective cycle phases) and subsequently dischargeV2P 230 and V1P 228 (respectively) to GND_P 208, in order to turn onN2P 234 and N1P 232 (respectively) at zero voltage across the switches N2P 234 andN1P 232. -
G1S 252 andG2S 254 are preferably controlled to switch offN1S 248 andN2S 250, respectively, when zero current flows through thesecondary side 222 of thetransformer 218, and zero voltage is acrossswitches N1S 248 andN2S 250. Preferably, turn-on of secondary side switchesN1S 248 andN2S 250 is controlled by a fixed timing (fixed frequency and adaptive duty cycle) according to a selected switching frequency of theconverter 200. -
Input side 202 andoutput side 204 switch timings are also preferably independent of each other. Preferably, output side timings are similar to (or the same as) input side timings in having the same switching frequency and duty cycle, but with a phase delay with respect to input side timings—accordingly, output side timings are phase shifted later than corresponding input side timings. - In some embodiments,
G1S 252 andG2S 254 can be tied to GND_S 214 or otherwise connected such thatN S 248 andN2S 250 remain always off (providing a diode-like effect) and perform passive rectification (as described further with respect toFIGS. 3 and 5 ). This can generally be done without compromising function of theoutput side 204, except that conduction losses fromN1S 248 andN2S 250 will be higher than when they are switched (switching ofN1S 248 andN2S 250 is further described with respect toFIG. 3 ). The increase in conduction losses from not switchingN1S 248 andN2S 250 can be less relevant in high voltage applications, and may come with efficiency gains from avoiding use of control circuits to generateG1S 252 andG2S 254 signals. Whether switchingN1S 248 andN2S 250 results in improved overall performance for theconverter 200—as determined with respect to efficiency and/or other metric(s)—may be application-dependent. -
FIG. 3 shows a timing diagram 300 for an isolated DC-DC converter 200 as shown in and described with respect toFIG. 2 . - In
FIG. 3 ,VLP 302 is the voltage across theprimary side 220 of thetransformer 218 and equals the voltage atV1P 228 minus the voltage atV2P 230. Voltage across theprimary side 220 is therefore positive whenV1P 228 is higher voltage thanV2P 230 and negative whenV2P 230 is higher voltage thanV1P 228. ILP 304 is the current across theprimary side 220 fromnode V1P 228 tonode V2P 230, and is positive flowing fromV1P 228 toV2P 230 and negative flowing fromV2P 230 toV1P 228. -
VLS 306 is the voltage across thesecondary side 222 of thetransformer 218 and equals the voltage atV1S 244 minus the voltage atV2S 246. Voltage across thesecondary side 222 is therefore positive whenV1S 244 is higher voltage thanV2S 246 and negative whenV2S 246 is higher voltage thanV1S 244. ILS 308 is the current across thesecondary side 222 fromnode V1S 244 tonode V2S 246, and is positive flowing fromV1S 244 toV2S 246 and negative flowing fromV2S 246 toV1S 244. - As shown in the timing diagram 300 of
FIG. 3 , at time T0 G1P 236 is low, meaningN1P 232 is off, andG2P 238 is high, meaningN2P 234 is on. BecauseN2P 234 is on,V2P 230 and the gate ofP1P 224 are connected to GND_P 208 and are therefore pulled low. As a result,P1P 224 is on, connectingV1P 228 and the gate ofP2P 226 toVin 206 and thereby pullingV1P 228 high, which causesP2P 226 to be off. This means thatVLP 302 is high (V1P 228 is high andV2P 230 is low). ILP 304 (current across the primary side 220) has a slope determined by the interaction ofVin 206,Vout 212, and transformer parameters (e.g., the transformer turns ratio and the leakage inductance of thetransformer 218 on the primary side 220).VLP 302 being high will contribute to increasing the slope of ILP 304 (in a positive direction). - At time T1,
G2P 238 goes low, switching offN2P 234 so thatGND_P 208 is no longer pulling downV2P 230.N2P 234 is turned off at a time selected to enableV2P 230 to be fully charged andV1P 228 to be fully discharged by the current through the inductor, ILP 304, beforeG1P 236 going high to switch on N1P 232 (i.e., to enable zero voltage turn-on of N1P 232). The current across theprimary side 220, ILP 304, subsequently drives charge into the parasitic capacitances connected to V2P 230 (corresponding toC2 122, seeFIG. 1 )—which includes the gate-source capacitance ofP1P 224, as described hereinabove with respect toFIG. 1 —causingV2P 230 to increase and causingVLP 302 to fall to zero. - At time T2,
V2P 230 is high (fully charged by the current across theinductor 218, as described with respect toFIG. 2 ) andVLP 302 reaches zero voltage—i.e., zero voltage difference exists betweenV1P 228, which is high, andV2P 230, which is also high.V2P 230 beinghigh causes P1P 224 to turn off, so thatV1P 228 is no longer pulled up byVin 206. This allows ILP 304 to drive charge out of P2P's 226 gate capacitance and other parasitic capacitances at node V1P 228 (corresponding toC1 114, seeFIG. 1 ) and recycle that charge as current across theprimary side 220, resulting inV1P 228 going low, which causesVLP 302 to continue to fall.VLP 302 below zero contributes to decreasing the slope of ILP 304 (increasing the slope of ILP 304 in a negative direction). - At time T3 316,
V1P 228 reaches its low state, soG1P 236 is controlled to go high to turn on N1P 232 (zero voltage switch on, i.e., ZVS). This connectsV1P 228 toGND_P 208, pullingV1P 228 low.V1P 228 is already low when connected toGND_P 208, so no (or minimal) losses occur from discharge of parasitic capacitances connected to V1P 228 (corresponding to C1 114).V1P 228 being low turns onP2P 226, which connectsV2P 230 toVin 206, pullingV2P 230 high. - As shown in the timing diagram 300, signal behaviors of the
converter 200 at times T4, T5 and T6 echo the signal behaviors described with respect toFIG. 3 at times T1, T2 and T3, respectively, except: voltages and currents across theprimary side 220 have the opposite sign; andP2P 226,V2P 230,N2P 234 andG2P 238 have the behaviors described hereinabove with respect toP1P 224,V1P 228,N1P 232 andG1P 236, and vice versa. Accordingly, T1, T2, T3 cover a half cycle of operation of theconverter 200, and T4, T5 and T6 cover another half cycle of operation of the converter 200 (in the same cycle). Operation of the converter 200 (switch behaviors) during the half cycle covered by T4, T5 and T6 is the same as operation of theconverter 200 during the half cycle covered by T1, T2, T3, except that the roles of switches (on both theinput side 202 and the output side 204) on different sides of respective inductors (theprimary side 220 and the secondary side 222) are exchanged to enable current to flow in the reverse direction. (This can also be thought of as repeating switch and signal behaviors of times T1, T2 and T3 at times T4, T5 and T6 as if the terminals of theprimary side 220 are reversed, and the terminals of thesecondary side 222 are reversed.) - Example timings for
output side 204 switching and signals can be determined fromFIG. 3 . Theoutput side 204 timings shown inFIG. 3 are examples, as described hereinabove, andoutput side 204 timings are generally independent frominput side 202 timings. - For example,
output side 204 switch control signals G1S 252 andG2S 254 will preferably turn onNMOS transistors N1S 248 andN2S 250 when voltage across the respective transistor is zero (at a time corresponding to a specified switching frequency; preferably, as soon as the voltage across the transistor reaches zero to maximize power transmitted to Vout 212). This also corresponds to voltage across thesecondary side 222,VLS 306, being at a maximum positive or negative value, meaning that one ofV1S 244 orV2S 246 is low, and the other is high. Accordingly, ifV1S 244 is low (voltage acrossN1S 248 is zero), thenG1S 252 switches onN1S 248, and ifV2S 246 is low (voltage acrossN2S 250 is zero), thenG2S 254 switches on N2S 250 (zero voltage turn-on). Also,G1S 252 orG2S 254 will switch offNMOS transistor N1S 248 or N2S 250 (respectively) when current through thesecondary side 222, ILS 308, is zero (zero current turn-off) and voltage across the respective NMOS transistor being turned off is zero (zero voltage turn-off). - As shown in
FIG. 5 , in some embodiments, gates of low-sideNMOS transistors N1S 248 andN2S 250 can be connected to ground so that they perform passive rectification on currents through the secondary side (ILS 308). This prevents negative output current (fromVout 212 to GND_S 214) and can reduce the need for complex rectification circuitry, at the cost of the voltage drop acrossN1S 248 andN2S 250 diodes. - Active (or synchronous) rectification is performed by low-side NMOS transistors N1P 232,
N2P 234,N1S 248 andN2S 250 switching on to conduct current when the current is or is about to flow in the correct (positive) direction (fromVin 206 toGND_P 208, or fromGND_S 214 to Vout 212), thereby preventing (negative) current in the opposite direction. Thus, whenV1P 228,V2P 230,V1S 244 orV2S 246 might otherwise be too high, potentially causing power losses by resulting in negative current or (on the output side 104) reduced output voltage (at Vout 212), the problematic node will be grounded byN1P 232,N2P 234,N1S 248 orN2S 250, respectively. Switch and signal timings described with respect to, e.g.,FIGS. 2 and 3 are used to achieve these results. Secondary side diodes (ofN1S 248 and N2S 250) also help to prevent negative output current; accordingly, in theconverter 200 as shown inFIG. 2 , passive rectification is performed alongside active rectification. -
FIG. 4 shows a transistor-level diagram of a high output voltage isolated DC-DC converter 400. In embodiments as shown inFIG. 4 , theinput side 402 of theconverter 400 is arranged the same as theinput side 202 of the converter 200 (seeFIG. 2 ). Theoutput side 404 ofFIG. 4 comprises two instances of theoutput side 204 of theconverter 200, an output instance 406 and a ground instance 408. The output instance 406 and the ground instance 408 are “stacked”. Accordingly,Vout 212 of the output instance 406 comprisesVout 410 of theconverter 400;GND_S 214 of the ground instance 408 comprisesGND_S 412 of theconverter 400; andGND_S 214 of the output instance 406 is connected toVout 212 of the ground instance 408 at Vout/2 414. - Also,
V1S 244 andV2S 246 are connected to the terminals of thesecondary side 222 of thetransformer 218 through isolation capacitors 416 C1 and 416 C2 which isolate therespective V1S 244 andV2S 246 nodes of the output instance 406 and the ground instance 408 from each other. Preferably, an output capacitor 418 O is connected betweenVout 410 and Vout/2 414, and another output capacitor 418 G is connected between Vout/2 414 andGND_S 412. - The stacked output instance 406 and ground instance 408 act as a voltage doubler, with the input voltage of
Vin 206 as the base (doubled) voltage. Vout/2 414 acts as the voltage output for the ground instance 408 and as the ground for the output instance 406 (the ground instance and output instance are otherwise isolated from each other by the isolation capacitors 416 C1 and 416 C2). Consequently, the voltage at Vout/2 414 is one half of the voltage at Vout 410 (and this voltage is also available as an output). The ground instance 408 and the output instance 406 each function similarly to theoutput side 204 ofconverter 200 ofFIG. 2 . - This means that the
converter 400 ofFIG. 4 retains the efficiency advantages of theconverter 200 ofFIG. 2 , while being able to output twice as high a voltage—e.g., 10 volts output given a 5 volt input—without requiring components rated for a correspondingly higher voltage. For example, for a 5 volt input and 10 volt output, preferably, isolation capacitors 416 and output capacitors 418 O, 418 G are 5 volt capacitors; and the various NMOS and PMOS transistors on theoutput side 204 of theconverter 400 can be 5 volt transistors; with capacitors and transistors preferably fabricated using relatively inexpensive and/or straightforward processing techniques, preferably the same class of techniques, e.g., CMOS processing. Enabling high voltage output without requiring high voltage components lowers process complexity (e.g., component complexity, number of process steps and number of masks required) and therefore process cost and required device area, and preserves applicability of CMOS fabrication (which is relatively simple and low cost and avoids fabrication process limitations). This approach also enables use of a relatively low transformer turns ratio, e.g., 1:1, maintaining transformer symmetry. -
FIG. 5 shows a transistor-level diagram of a high output voltage isolated DC-DC converter 500 in which the bias of the NMOS transistors in the ground instance 408 of theoutput side 404,N1S 248 andN2S 250, are respectively connected to their own source, so thattransistors N1S 248 and N2S 250 (of the ground instance 408) act as diodes. In embodiments as shown inFIG. 5 , the resonance (the secondary side 214) is sufficient to drive charge into and out of the respective nodes V1S 242 andV2S 244 of the output instance 406 and the ground instance 408 to implement self-switching of respectivePMOS transistors P1S 240 andP2S 242 and thereby drive thesecondary side 222. This avoids switching losses fromN1S 248 andN2S 250 without using control signals and without paying the power (and device area) cost of corresponding control circuitry. - However, the voltage drop across the
NMOS transistors N1S 248 andN2S 250 in the ground instance 408 of theconverter 500 shown in and described with respect toFIG. 5 is slightly higher than the voltage drop across theNMOS transistors N1S 248 and N2S 250 (switched using control signals G1S 252 and G2S 254) in theconverter 400 shown in and described with respect toFIG. 4 . This is becauseN1S 248 andN2S 250 in the ground instance 408 of theconverter 500 inFIG. 5 are configured to act as diodes, rather than as switched transistors. As a result, slightly higher conduction losses occur in aconverter 500 ofFIG. 5 than in aconverter 400 ofFIG. 4 . (In the ground instance 408 of theconverter 500 ofFIG. 5 ,N1S 248 andN2S 250 prevent negative output current due to their function as diodes.) - It may therefore be application-dependent as to whether a converter 400 (as in
FIG. 4 ) or a converter 500 (as inFIG. 5 ) is more suited to a particular purpose or otherwise performs better with respect to application-related performance metrics. -
FIG. 6A shows an example of aprocess 600 for controlling an isolated DC-DC converter. As shown inFIG. 6A , aninput side 202 low side switch (e.g., NMOS) is turned on when zero voltage is across the low side switch, connecting a corresponding firstprimary side 220 transformer terminal to the primary side ground 208 (GND_P 208) instep 602. Zero voltage at the firstprimary side 220 terminal causes a high side switch (e.g., a PMOS that has its gate coupled to the first terminal, its drain coupled to a secondprimary side 220 transformer terminal and its source coupled to Vin 206) to turn on, connecting the second terminal toVin 206 instep 604. After a period selected to enable a current through theprimary side 220 to (after the low side switch is turned off) charge the first terminal to aninput voltage 206 and discharge the second terminal to a primary side ground 208 voltage, the low side switch is turned off, disconnecting the first terminal fromground 208 instep 606. As a result, the gate of the self-driven high side switch is released (from ground 208), which allows the high side switch gate to be driven by current through theprimary side 220 to inputvoltage Vin 206; this causes the high side switch to open, disconnecting the second terminal fromVin 206 instep 608. The current through theprimary side 220 then drives the voltage at the second terminal to ground (GND_P 208) instep 610. The process is then repeated in the opposite direction (as if the terminals were reversed, i.e., the first terminal substituted for the second and vice versa, using different corresponding high side and low side switches) instep 612. - The disoverlap time between the turn off of the first low side switch and the turn on time of the second low side switch is selected to allow the full voltage swing of the switching nodes, enabling zero voltage switching of the second low side switch.
-
FIG. 6B shows an example of aprocess 614 for controlling an isolated DC-DC converter. As shown inFIG. 6B , instep 616, anoutput side 204 low side (e.g., NMOS) switch is turned on at a specified time (corresponding to a specified switching frequency) when zero voltage is across the low side switch; turning on the low side switch connects a corresponding firstsecondary side 222 transformer terminal to the secondary side ground 214 (GND_S 214). The resulting zero voltage at the firstsecondary side 222 terminal causes a high side switch (e.g., PMOS) which is coupled to (when activated) connect a secondsecondary side 222 transformer terminal toVout 212 to turn on, connecting the second terminal toVout 212 instep 618. If zero current flows through thesecondary side 222, and zero voltage is across the low side switch, then the low side switch is turned off, disconnecting the firstsecondary side 222 terminal from thesecondary side ground 214 instep 620. This allows the firstsecondary side 222 terminal, and thus the high side switch gate, to be driven tooutput voltage Vout 212 by current through thesecondary side 222. As a result, the gate of the high side switch opens, disconnecting the secondsecondary side 222 terminal fromVout 212 instep 622. The current through thesecondary side 222 then drives the voltage at the secondsecondary side 222 terminal to the secondary side ground voltage instep 624. The process is then repeated in the opposite direction (with different corresponding high side and low side switches) instep 626. -
FIG. 7 shows an example of a transistor-level diagram of acircuit portion 700 used to construct an isolated DC-DC converter. As shown inFIG. 7 , the drains of two NMOS transistors HS1 702 (high side 1) and HS2 704 (high side 2) are connected to avoltage input Vin 706. The gate ofHS1 702 is connected (via a buffer) to acontrol voltage G1 708, and the gate ofHS2 704 is connected (via a buffer) to acontrol voltage G2 710. The source ofHS1 702 is connected tonode V1 712, and the source ofHS2 704 is connected tonode V2 714. -
V1 712 is connected to a first terminal of aninductor 716, andV2 714 is connected to a second terminal of theinductor 716. An NMOS transistor LS1 718 (low side 1) is connected betweenV1 712 and aground GND 720. An NMOS transistor LS2 722 (low side 2) is connected betweenV2 714 andGND 720. The sources ofLS1 718 andLS2 722 are connected toGND 720. The gates and drains ofLS1 718 andLS2 722 are cross-coupled betweenV1 712 andV2 714. Accordingly, the drain ofLS1 718 is connected toV1 712, and the gate ofLS1 718 is connected toV2 714 through avoltage limiter VL1 724; and the drain ofLS2 722 is connected toV2 714, and the gate ofLS2 722 is connected toV1 712 through avoltage limiter VL2 726. The bias voltage ofLS1 718 isV2 714, limited byvoltage limiter VL1 724, and the bias voltage ofLS2 722 isV1 712, limited byvoltage limiter VL2 726.Voltage limiters VL1 724 andVL2 726 are further described with respect toFIG. 10 . - The
inductor 716 can also be considered a primary side or a secondary side of a transformer—accordingly, as described with respect toFIG. 1 , the primary side or secondary side of a transformer is an inductor.Circuit portion 700 can be used to construct an isolated DC-DC converter such that the primary side or secondary side of a transformer in the converter stands in place of theinductor 716, as shown with respect toFIGS. 8 and 10 . - In operation, the
NMOS transistors HS1 702 andHS2 704 are preferably zero voltage switched and zero current switched. Accordingly,G1 708 andG2 710 are controlled to turn on OR off (generally one or the other and not both; the other of turn-on or turn-off timing is determined using other criteria, such as further described with respect toFIG. 9 )HS1 702 andHS2 704 when corresponding adjacentsource nodes V1 712 andV2 714 are fully charged toVin 706, and zero current flows across the inductor 716 (fromnode V1 712 tonode V2 714 or vice versa). (Zero voltage switching and zero current switching are further described with respect toFIGS. 3 and 9 .) This results in minimal switching losses, because little or no voltage is across (or little or no current is conducted by)HS1 702 or HS2 704 (for either the turn-on or turn-off transition), while they are switched. - In embodiments as shown in
FIG. 7 , power cost for MOSFET control is reduced by makingLS1 718 andLS2 720 self-driving. Accordingly, rather than requiring control signals to biasLS1 718 andLS2 720,LS1 718 andLS2 720 are biased by charge driven toLS1 718 andLS2 720 vianodes V2 714 and V1 712 (respectively; and throughvoltage limiters VL1 724 andVL2 726, respectively) by the current through the resonance (inductor 716). Self-drivingLS1 718 andLS2 720 reduces the complexity and power cost of controlling the MOSFETS. - Further power savings are achieved by using the current across the inductor 716 (the resonance current) to drive charge out of the gates of
LS1 718 andLS2 720 and turn that charge into current across theinductor 716. Some of that current charges respective drain-source parasitic capacitances of adjacent high side and low side transistors, and gate-source parasitic capacitances of low side transistors. This recycling avoids dissipation of gate charges (Cgs charges) whenLS1 718 andLS2 720 are switched, because those gate charges are reused. Accordingly, those gate charges (charges of gate-source parasitic capacitances), along with charges of respective drain-source parasitic capacitances, are driven out of parasitic capacitances adjacent toV1 712 orV2 714 by the resonance current, turned into current across theinductor 716, and (in part) are used to charge parasitic capacitances adjacent toV2 714 or V1 712 (respectively). - Because gate charge of
LS1 718 andLS2 720 are reused, the tradeoff between QG (gate charge) and RDS (drain-source on resistance) can be largely avoided forLS1 718 andLS2 720. For example, a lower RDS can generally be used, thereby enabling faster switching and lower heat output, without resulting in excessive power costs due to a higher QG, because the gate charge power cost is largely avoided (energy used to biasLS1 718 andLS2 720 is repeatedly recovered) after initial charging. (The figure of merit FOM=QG*RDS will generally be approximately constant for a given process technology). Accordingly, the configuration shown inFIG. 7 enablingLS1 718 andLS2 720 to be self-driven is relatively non-dissipative compared to gate driving using control signals because energy is taken back from parasitic capacitances. Energy “recycling” is performed by discharging capacitances and turning voltage into current through theinductor 716. Switching losses are thereby minimized. - The sources of
LS1 718 andLS2 720 are preferably connected directly toGND 720, reducing the power required to biasLS1 718 andLS2 720. Also,LS1 718 andLS2 720 can be driven using fixed frequency, fixed or adaptive duty cycle signals. DrivingLS1 718 andLS2 720 at a fixed frequency, with a fixed or adaptive duty cycle, reduces the complexity and power cost of controlling the MOSFETS. (Duty cycle can be adaptive to maintain zero voltage switching and zero current switching conditions despite variations of circuit parameters or switching frequency.) - Preferably, RMS currents are minimized to thereby lower conduction losses.
-
FIG. 8 shows a transistor-level diagram of an isolated DC-DC converter 800. Theconverter 800 can be broadly described as two instances of thecircuit portion 700, one on theinput side 802 and one on theoutput side 804. Atransformer 806 comprises aprimary side 808 and asecondary side 810. Theprimary side 808 andsecondary side 810 of thetransformer 806 each preferably function similarly, with respect to their respective side of the converter 800 (i.e., theinput side 802 and the output side 804), to theinductor 716 of thecircuit portion 700 described with respect toFIG. 7 . - As shown in
FIG. 8 , on the input (i.e., primary)side 802,input voltage Vin 812 is connected to the drains of two high side NMOS transistors,HS1P 814 andHS2P 816.HS1P 814 andHS2P 816 are switched bycontrol signals G1P 818 andG2P 820 connected (through buffers) to the gates ofHS1P 814 andHS2P 816, respectively.Node V1P 822 is connected to the source ofHS1P 814, andnode V2P 824 is connected to the source ofHS2P 816. - The drains and gates of low side NMOS transistors LS1P 826 and
LS2P 828 are cross-coupled betweenV1P 822 andV2P 824, the connections between nodes (V2P 824 and V1P 822) and gates (ofLS1P 826 and LS1P 828) being made through voltage limiters VL1P 830 andVL2P 832, respectively. Accordingly, the drain ofLS1P 826 is connected toV1P 822, and the gate ofLS1P 826 is connected toVL1P 830 which is connected toV2P 824; and the drain ofLS2P 828 is connected toV2P 824, and the gate ofLS2P 828 is connected to VL2P 832 which is connected toV1P 822.Voltage limiters VL1P 830 andVL2P 832 limit the voltage that reaches the gates ofLS1P 826 andLS1P 828, respectively. For example, ifVin 812 is 12 volts, andLS1P 826 andLS1P 828 are fabricated to be biased by 5 volts, then VL1P 830 andVL2P 832 limit the voltages that reach the gates ofLS1P 826 andLS1P 828, respectively, to 5 volts. - The sources of
LS1P 826 andLS2P 828 are connected to primaryside ground GND_P 834. Theprimary side 808 of thetransformer 806 is connected betweenV1P 822 andV2P 824. - On the
output side 804,output voltage Vout 834 is connected to the drains of two high side NMOS transistors,HS1S 836 andHS2S 838.HS1S 836 andHS2S 838 are switched by control signals G1S 840 andG2S 842 connected (through buffers) to HS1S 836 andHS2S 838, respectively.Node V1S 844 is connected to the source ofHS1S 836, andnode V2S 846 is connected to the source ofHS2S 838. - The drains and gates of NMOS transistors LS1S 848 and
LS2S 850 are cross-coupled betweenV1S 844 andV2S 846, the connections between nodes (V2S 846 and V1S 844) and gates (ofLSS 848 and LSS 850) being made through voltage limiters VLS 852 andVL2S 854, respectively. Accordingly, the drain ofLS1S 848 is connected toV1S 844, and the gate ofLSS 848 is connected toVL1S 852 which is connected toV2S 846; and the drain ofLS2S 850 is connected toV2S 846, and the gate ofLS2S 850 is connected toVL2S 854 which is connected toV1S 844. The sources ofLSS 848 andLS2S 850 are connected to secondaryside ground GND_S 856. - The
secondary side 810 of thetransformer 806 is connected betweenV1S 844 andV2S 846. - Switching on the
input side 802 and on theoutput side 804 is preferably adaptive. Accordingly, current through the primary andsecondary sides transformer 806 is (respectively) tracked at high side transistor turn-on on theprimary side 808, and at high side transistor turn-off on thesecondary side 810, to check whether current is positive or negative. Switch timing—signal timing forG1P 818,G2P 820,G1S 840 andG2S 842—is then adjusted to enable zero current switching of respective high side transistors.G1P 818 andG2P 820 are preferably controlled to switch onHS1P 814 andHS2P 816, respectively, when zero current flows through theprimary side 808 of thetransformer 806 and zero voltage is across the transistor being switched on.G1P 818 andG2P 820 are preferably controlled to switch off HS1P 814 andHS2P 816, respectively, at a time selected to enable the current across the primary side to (after the high side transistor is switched off) fully dischargeV1P 822 or V2P 824 (respectively) to the primary side ground voltage and fully chargeV2P 824 or V1P 822 (respectively) to the input voltage.G1S 840 andG2S 842 are preferably controlled to switch onHS1S 836 andHS2S 838, respectively, when zero voltage is across the transistor being switched on, at a time selected to correspond to a switching frequency dependent on the switching frequency of the primary side, and dependent on capacitor and inductor parameters.G1S 840 andG2S 842 are preferably controlled to switch off HS1S 836 andHS2S 838, respectively, when zero current flows through thesecondary side 810 of thetransformer 806 and zero voltage is across the transistor being switched off.Input side 802 andoutput side 804 switch timings are also preferably independent of each other. - The
converter 800 also preferably comprises aninput decoupling capacitor 858 connected betweenVin 812 andGND_P 832, and anoutput decoupling capacitor 860 connected betweenVout 834 and GND_S 856 (as described hereinabove for decoupling capacitors, also called ripple capacitors, ofFIG. 2 ). -
FIG. 9 shows an example of a timing diagram 900 for an isolated DC-DC converter 800 as shown inFIG. 8 . InFIG. 9 ,VLP 902 is the voltage across theprimary side 808 of thetransformer 806 and equals the voltage atV1P 822 minus the voltage atV2P 824. Voltage across theprimary side 808 is therefore positive whenV1P 822 is higher voltage thanV2P 824 and negative whenV2P 824 is higher voltage thanV1P 822.ILP 904 is the current across theprimary side 808 fromnode V1P 822 tonode V2P 824, and is positive flowing fromV1P 822 toV2P 824 and negative flowing fromV2P 824 toV1P 822. -
VLS 906 is the voltage across thesecondary side 810 of thetransformer 806 and equals the voltage atV1S 844 minus the voltage atV2S 846. Voltage across thesecondary side 810 is therefore positive whenV1S 844 is higher voltage thanV2S 846 and negative whenV2S 846 is higher voltage thanV1S 844.ILS 908 is the current across thesecondary side 810 fromnode V1S 844 tonode V2S 846, and is positive flowing fromV1S 844 toV2S 846 and negative flowing fromV2S 846 toV1S 844. - At time T0,
V1P 822 is low,V2P 824 is high,G1P 818 is low, andG2P 820 is high. BecauseG1P 818 is low,HS1P 814 is off. BecauseG2P 820 is high,HS2P 816 is on, connectingV2P 824 toVin 812, pullingV2P 824 high. BecauseV1P 822 is low,LS2P 828 is off. BecauseV2P 824 is high,LS1P 826 is on, connectingV1P 822 toGND 834, pullingV1P 822 low. Also,VLP 902 is negative, andILP 904 has a slope determined byVin 812,Vout 834 and parameters of the transformer 806 (as described hereinabove for current with respect toFIG. 3 ). At time T0, the voltage acrossHS2P 816 is zero, because the source-drain path ofHS2P 816 is connected toVin 812 andV2P 824, andV2P 824 is high. - At time T1, while the voltage across
HS2P 816 is zero and the current through theinductor ILP 904 is zero,G2P 820 is controlled to go low, turning off HS2P 816 and thereby achieving the desired zero voltage and zero current turn-off (ZVS and ZCS). As a result, charge in parasitic capacitances connected toV2P 824 is converted into current across the primary side 808 (ILP 904), causing V2P 824 (and therefore VLP 902) to fall. - At time T2,
V2P 824 is zero, turning offLS1P 826.VLP 902 is also zero (V1P 822 andV2P 824 are both zero). As a result, current across the primary side 808 (ILP 904) charges the parasitic capacitances connected toV1P 822, causingV1P 822 to rise andVLP 902 to increase above zero. - At time T3,
V1P 822 is high, turning onLS2P 828, andG1P 818 goes high, turning onHS1P 814, which pulls upV1P 822. At time T3, the voltage acrossHS1P 814 is zero, because the source-drain path ofHS1P 816 is connected toVin 812 andV1P 822, andV2P 822 is high. Also at time T3,VLP 902 is positive. - As shown in the timing diagram 900, signal behaviors of the
converter 800 at times T4, T5 and T6 echo the signal behaviors described with respect toFIG. 9 at times T1, T2 and T3, respectively, except: voltages and currents across theprimary side 808 have the opposite sign; andHS1P 814,V1P 822,LS1P 826 andG1P 818 have the behaviors described hereinabove with respect to HS2P 816,V2P 824,LS2P 828 andG2P 820, and vice versa. (Accordingly, the switch and signal behaviors of times times T1, T2 and T3 are preferably repeated at times T4, T5 and T6 as if the terminals of theprimary side 808 andsecondary side 810 had been reversed.) - Example timings for
output side 804 switching and signals can be determined fromFIG. 9 . Theoutput side 804 timings shown inFIG. 9 (voltage across thesecondary side 810,VLS 906, and current through thesecondary side 810, ILS 908) are examples, as described hereinabove, andoutput side 804 timings are generally independent frominput side 802 timings. - For example,
output side 804 switch control signals G1S 840 andG2S 842 will preferably turn onHS1S 836 andHS2S 838 whenVLS 906 is at a maximum positive or negative value, meaning that one ofV1S 844 orV2S 846 is low, and the other is high. Accordingly, ifV1S 844 is high, thenG1S 840 switches onHS1S 836, and ifV2S 846 is high, thenG2S 842 switches onHS2S 838. Also,G1S 840 orG2S 842 will switch offNMOS transistor HS1S 836 or HS2S 838 (respectively) when current through the secondary side,ILS 810, is zero (zero current turn-off). - As shown in
FIGS. 8 and 9 , NMOS transistors HS1P 814,HS2P 816 perform active rectification on currents across the primary side 808 (ILP 904), and NMOS transistors HS1S 836 andHS2S 838 perform passive and active rectification on currents across the secondary side 810 (ILS 908), as described hereinabove regarding active and passive rectification with respect toFIG. 3 . Switching of these NMOS transistors prevents both negative input currents and negative output currents. This can reduce the need for complex rectification circuitry. -
FIG. 10 shows an example of a transistor-level diagram of a high voltage isolated DC-DC converter 1000. Theconverter 1000 ofFIG. 10 is based on theconverter 800 ofFIG. 8 , with voltage limiters comprising clamping NMOS transistors and bootstrap circuits used to drive the high side transistors. Generally, the operation and signal timings of theconverter 1000 ofFIG. 10 should be similar to those ofFIG. 8 .Vin 812 andVout 834 can be significantly higher than 5 volts, e.g.,Vin 812 of 12 volts andVout 834 of 12 volts. Preferably,HS1P 814,HS2P 816,HS1S 836 andHS2S 838 are LDMOS transistors, enabling them to function effectively when biased by high voltages (e.g., 17 volts). - As shown in
FIG. 10 , starting from theconverter 800 ofFIG. 8 : on theinput side 802,voltage limiter VL1P 830 comprises anNMOS transistor VL1P 1002 andvoltage limiter VL2P 832 comprises anNMOS transistor VL2P 1004. BothVL1P 1002 andVL2P 1004 preferably have their gates connected to an input voltage VclampP 1006, which acts as a clamping voltage. VclampP 1006 is preferably set to 5 volts so that the low side transistors LS1P 826 andLS2P 828 will not be biased by more than 5 volts. This enablesLS1P 826 andLS2P 828 to be fabricated as CMOS devices (usually rated for 5 volts or less). - The source of
VL1P 1002 is preferably connected to the gate ofLS1P 826, acapacitor C1P 1008 which is also connected toprimary ground GND_P 834, and the source of a bootstrap circuit-controllingNMOS transistor BS1P 1010. The drain ofVL1P 1002 is preferably connected toV2P 824 and to the gate ofBS1P 1010. The drain ofBS1P 1010 is preferably connected to a node VBS 1P 1012, which is also connected to bootstrap capacitor CBS 1P 1014 and to supply a level shifting buffer BBS 1P 1016 (bootstrap capacitor CBS 1P 1014 acts as the supply for the buffer BBS 1P 1016). CBS 1P 1014 is also connected toV1P 822. Buffer BBS 1P 1016 is also connected to connectG1P 818 to the gate ofHS1P 814. Because the voltage at VBS 1P 1012 preferably rises several volts above the maximum voltage reached by V1P 822 (as further described hereinbelow), which itself is preferably significantly above 5 volts (e.g., 12 volts), BBS 1P 1016 is used to protect control circuits producing G1P 818 (usually operating at 5 volts or less) from that elevated voltage, and to enableG1P 818 to effectively controlHS1P 814. An example level shifting buffer can include multiple inverters, with successive inverters (in the direction of travel from the lower voltage regime to the higher voltage regime) having larger area transistors than preceding inverters. - The source of
VL2P 1004 is preferably connected to the gate ofLS2P 828, acapacitor C2P 1018 which is also connected toprimary ground GND_P 834, and the source of a bootstrap circuit-controllingNMOS transistor BS2P 1020. The drain ofVL2P 1004 is preferably connected toV1P 822 and to the gate ofBS2P 1020. The drain ofBS2P 1020 is preferably connected to a node VBS 2P 1022, which is also connected to bootstrap capacitor CBS 2P 1024 and to supply a level shifting buffer BBS 2P 1026 (bootstrap capacitor CBS 2P 1024 acts as the supply for the buffer BBS 2P 1026). CBS 2P 1024 is also connected toV2P 824. Buffer BBS 2P 1026 is also connected to connectG2P 820 to the gate ofHS2P 816. Because the voltage at VBS 2P 1022 preferably rises several volts above the maximum voltage reached by V2P 824 (as further described hereinbelow), which itself is preferably significantly above 5 volts (e.g., 12 volts), BBS 2P 1026 is used to protect control circuits producing G2P 820 (usually operating at 5 volts or less) from that elevated voltage, and to enableG2P 820 to effectively controlHS2P 816. - On the
output side 804,voltage limiter VL1S 852 comprises anNMOS transistor VL1S 1028 andvoltage limiter VL2S 854 comprises anNMOS transistor VL2S 1030. BothVL1S 1028 andVL2S 1030 preferably have their gates connected to an input voltage VclampS 1032, which acts as a clamping voltage. VclampS 1032 is preferably set to 5 volts so that the low side transistors LS1S 848 andLS2S 850 will not be biased by more than 5 volts. This enablesLS1S 848 andLS2S 850 to be fabricated as CMOS devices (usually rated for 5 volts or less). - The source of
VL1S 1028 is preferably connected to the gate ofLS1S 848, acapacitor C1S 1034 which is also connected tosecondary ground GND_S 856, and the source of a bootstrap circuit-controllingNMOS transistor BS1S 1036. The drain ofVL1S 1028 is preferably connected toV2S 846 and to the gate ofBS1S 1036. The drain ofBS1S 1036 is preferably connected to a node VBS 1S 1038, which is also connected to bootstrap capacitor CBS 1S 1040 and to supply a level shifting buffer BBS 1S 1042 (bootstrap capacitor CBS 1S 1040 acts as the supply for the buffer BBS 1S 1042). CBS 1S 1040 is also connected toV1S 844. BBS 1S 1042 is also connected to connectG1S 840 to the gate ofHS1S 836. Because the voltage at VBS 1S 1038 preferably rises several volts above the maximum voltage reached by V1S 844 (as further described hereinbelow), which itself is preferably significantly above 5 volts (e.g., 12 volts), BBS 1S 1042 is used to protect control circuits producing G1S 840 (usually operating at 5 volts or less) from that elevated voltage, and to enableG1S 840 to effectively controlHS1S 836. - The source of
VL2S 1030 is preferably connected to the gate ofLS2S 850, acapacitor C2S 1044 which is also connected tosecondary ground GND_S 856, and the source of a bootstrap circuit-controllingNMOS transistor BS2S 1046. The drain ofVL2S 1030 is preferably connected toV2S 846 and to the gate ofBS2S 1046. The drain ofBS2S 1046 is preferably connected to a node VBS 2S 1048, which is also connected to bootstrap capacitor CBS 2S 1050 and to supply a level shifting buffer BBS 2S 1052 (bootstrap capacitor CBS 2S 1050 acts as the supply for the buffer BBS 2S 1052). CBS 2S 1050 is also connected toV2S 846. BBS 2S 1052 is also connected to connectG2S 842 to the gate ofHS2S 838. Because the voltage at VBS 2S 1048 preferably rises several volts above the maximum voltage reached by V2S 846 (as further described hereinbelow), which itself is preferably significantly above 5 volts (e.g., 12 volts), BBS 2S 1052 is used to protect control circuits producing G2S 842 (usually operating at 5 volts or less) from that elevated voltage, and to enableG2S 842 to effectively controlHS2S 838. - Low
side capacitors C1P 1008,C2P 1018,C1S 1034 andC2S 1044 help reduce the resonance frequency of theconverter 1000. Maximum output power of theconverter 1000 is a function of the resonance frequency andtransformer 806 self inductance.Capacitors C1P 1008,C2P 1018,C1S 1034 can be physical capacitors, or can correspond to parasitic capacitance, depending on the maximum output power and the design of thetransformer 806. - An NMOS transistor is turned on when its gate voltage is sufficiently higher than its source voltage. The
bootstrap capacitors side PMOS transistors FIG. 10 , source voltages (V1P 822, V2P 824) ofinput side 802 highside PMOS transistors Vin 812; and source voltages (V1S 844 and V2S 846) ofoutput side 804 highside PMOS transistors Vout 822. Using bootstrap capacitors enables high side PMOS transistor gate control voltages (outputs oflevel shifting buffers control voltages input voltage Vin 812 or output voltage Vout 834 (as appropriate). - The charging path for bootstrap capacitor CBS 1P 1014 (path of current that charges the capacitor) runs from
Vin 812, throughHS2P 816, toV2P 824, throughVL1P 1002 andBS1P 1010, to VBS 1P 1012, to CBS 1P 1014. - The charging path for bootstrap capacitor CBS 2P 1024 runs from
Vin 812, throughHS1P 814, toV1P 822, throughVL2P 1004 andBS2P 1020, to VBS 2P 1022, to CBS 2P 1024. - The charging path for bootstrap capacitor CBS 1S 1040 runs from
GND_S 856, throughLS2S 850 toV2S 846, throughVL1S 1028 andBS1S 1036, to VBS 1S 1038, to CBS 1S 1040. - The charging path for bootstrap capacitor CBS 2S 1050 runs from
GND_S 856, throughLS1S 848 toV2S 844, throughVL2S 1030 andBS2S 1046, to VBS 1S 1048, to CBS 1S 1050. - The
bootstrap capacitors adjacent node V1P 822 is low; CBS 2P 1024 charges whenV2P 824 is low; CBS 1S 1040 charges whenV1S 844 is low; and CBS 2S 1050 charges whenV2S 846 is low. - The
converter 1000 also preferably comprises aninput decoupling capacitor 858 connected betweenVin 812 andGND_P 832, and anoutput decoupling capacitor 860 connected betweenVout 834 and GND_S 856 (as described hereinabove for decoupling capacitors, also called ripple capacitors, ofFIG. 2 ). Input andoutput decoupling capacitors - The described embodiments provide one or more of at least the following advantages. However, not all of these advantages result from every one of the described embodiments, and this list of advantages is not necessarily exhaustive.
-
- Enables higher efficiency and decreased power use;
- zero voltage and zero current switching;
- enables higher voltage input and output with high efficiency;
- enables higher voltage output and/or input without non-CMOS input and/or output capacitors;
- enables integrated capacitances;
- reduces device area requirements for input and/or output capacitors;
- enables use of a low transformer turns ratio
- enables use of higher switching frequencies;
- avoids driving losses and QG/RDS tradeoff in self-driven transistors;
- enables use of simplified rectification circuitry;
- enables use of simplified driving control on the secondary side; and
- reduces heat output.
- In some embodiments, PMOS transistors cross-coupled between different terminals of a primary or secondary side of a transformer connect that side to a voltage input (on the primary side) or a voltage output (on the secondary side). NMOS transistors couple different terminals of that side of the transformer to the respective (primary or secondary side) ground. This enables the voltage input-connected transistors to be self-driven such that gate charge is reused, turned into current across the respective side of the transformer when the gate discharges. Further, NMOS transistors are preferably zero current switched (ZCS) and zero voltage switched (ZVS), avoiding significant switching losses. Also, transistor configuration and switch timing avoids negative input and output current. As a result, embodiments using high side cross-coupled switches are highly efficient.
- In some embodiments, high side NMOS transistors couple different terminals of a primary or secondary side of a transformer to a voltage input (on the primary side) or a voltage output (on the secondary side). Low side NMOS transistors, cross-coupled (through voltage limiters coupled to the low side NMOS transistors' gates) to different terminals of the primary or secondary side of the transformer connect that side to the respective (primary or secondary side) ground. This enables the ground-connected transistors to be self-driven such that gate charge is reused, turned into current through the respective side of the transformer when the gate discharges. Further, high side transistors are preferably zero current switched (ZCS) and zero voltage switched (ZVS), avoiding significant switching losses. Also, transistor configuration and switch timing avoids negative input and output current. As a result, embodiments using high side cross-coupled switches are useful with high input and/or output voltages and are highly efficient.
- This description has various references to a “zero” current, a “zero” voltage, and a “zero” difference between voltages (e.g., “zero” voltage difference). As applied to example embodiments: (a) “zero” means equal to 0 or else approximately 0; and (b) “approximately 0” means near enough to 0 for the converter to satisfy its efficiency specification, notwithstanding any remaining losses (e.g., switching losses). In at least one example, efficiency is a ratio between: (a) power received from the converter; and (b) power applied to the converter. For an isolated DC-DC converter of example embodiments, the converter's efficiency specification is stated as a minimum threshold efficiency (such as 50%, which is a ratio of ½) for the converter to sustain during its usual operation. The converter's efficiency specification is one criteria to help determine whether the converter is suitable for use within a particular operating environment. In some examples, the transformer includes a magnetic coil, and the converter's efficiency specification is 80% or higher.
- In some embodiments as shown in
FIGS. 2 and 6 , biases and sources of respective NMOS transistors are connected to each other, such that NMOS transistors act as diodes, as shown inFIG. 5 . - In some embodiments, an isolated DC-DC converter as shown in
FIG. 2, 4 or 5 can comprise NMOS instead of PMOS, and/or PMOS instead of NMOS. In some embodiments, an isolated DC-DC converter as shown inFIG. 2, 4 or 5 can comprise switches made using technologies other than (or supplementary to) CMOS, e.g., LDMOS. - In some embodiments, a high input voltage and high output voltage isolated DC-DC converter comprises an input side and an output side, each side comprising a “stacked” configuration as described with respect to the output side of
FIG. 4 . Accordingly, the output side comprises a “stacked” output side as described with respect toFIG. 4 ; and the input side comprises an input instance and a ground instance of the input side ofFIG. 2 , the Vin (input voltage) of the input instance comprising the Vin of the input side (i.e., the voltage input for the converter), the ground of the ground instance comprising the ground of the input side, and the ground of the input instance connected to the Vin of the ground instance. (Accordingly, the input side can comprise stacked instances of the input side of, e.g.,FIG. 2 .) - In some embodiments as shown in
FIGS. 4 and 5 , isolation capacitors isolate the ground instance from the transformer. In some embodiments as shown inFIGS. 4 and 5 , isolation capacitors isolate both the ground instance and the output instance from the transformer. - The output instance and ground instance are also called an output module and ground module herein.
- Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
Claims (20)
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US15/859,135 Abandoned US20190089262A1 (en) | 2017-09-19 | 2017-12-29 | Isolated dc-dc converter |
US15/859,005 Active US10601332B2 (en) | 2017-09-19 | 2017-12-29 | Isolated DC-DC converter |
US15/859,145 Active US10622908B2 (en) | 2017-09-19 | 2017-12-29 | Isolated DC-DC converter |
US16/822,268 Active US11336193B2 (en) | 2017-09-19 | 2020-03-18 | Isolated DC-DC converter |
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US15/859,005 Active US10601332B2 (en) | 2017-09-19 | 2017-12-29 | Isolated DC-DC converter |
US15/859,145 Active US10622908B2 (en) | 2017-09-19 | 2017-12-29 | Isolated DC-DC converter |
US16/822,268 Active US11336193B2 (en) | 2017-09-19 | 2020-03-18 | Isolated DC-DC converter |
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US20230412083A1 (en) * | 2022-05-31 | 2023-12-21 | Texas Instruments Incorporated | Quasi-resonant isolated voltage converter |
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Also Published As
Publication number | Publication date |
---|---|
US20200287473A1 (en) | 2020-09-10 |
US11336193B2 (en) | 2022-05-17 |
US10601332B2 (en) | 2020-03-24 |
US20190089261A1 (en) | 2019-03-21 |
US10622908B2 (en) | 2020-04-14 |
US20190089263A1 (en) | 2019-03-21 |
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