US20190068521A1 - Technologies for automated network congestion management - Google Patents
Technologies for automated network congestion management Download PDFInfo
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- US20190068521A1 US20190068521A1 US15/858,288 US201715858288A US2019068521A1 US 20190068521 A1 US20190068521 A1 US 20190068521A1 US 201715858288 A US201715858288 A US 201715858288A US 2019068521 A1 US2019068521 A1 US 2019068521A1
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Definitions
- Datacenters and other large computer networks typically include multiple layers of switches.
- servers may be installed in racks, and each server in a rack may be connected to a top-of-rack switch.
- Multiple top-of-rack switches may be connected to an upstream switch, and so on. Therefore, communicating between servers or other nodes in different racks may require traversing multiple switch layers. Traversing each layer of switches may introduce queuing latency.
- FIG. 1 is a simplified diagram of at least one embodiment of a data center for executing workloads with disaggregated resources
- FIG. 2 is a simplified diagram of at least one embodiment of a pod of the data center of FIG. 1 ;
- FIG. 3 is a perspective view of at least one embodiment of a rack that may be included in the pod of FIG. 2 ;
- FIG. 4 is a side plan elevation view of the rack of FIG. 3 ;
- FIG. 5 is a perspective view of the rack of FIG. 3 having a sled mounted therein;
- FIG. 6 is a is a simplified block diagram of at least one embodiment of a top side of the sled of FIG. 5 ;
- FIG. 7 is a simplified block diagram of at least one embodiment of a bottom side of the sled of FIG. 6 ;
- FIG. 8 is a simplified block diagram of at least one embodiment of a compute sled usable in the data center of FIG. 1 ;
- FIG. 9 is a top perspective view of at least one embodiment of the compute sled of FIG. 8 ;
- FIG. 10 is a simplified block diagram of at least one embodiment of an accelerator sled usable in the data center of FIG. 1 ;
- FIG. 11 is a top perspective view of at least one embodiment of the accelerator sled of FIG. 10 ;
- FIG. 12 is a simplified block diagram of at least one embodiment of a storage sled usable in the data center of FIG. 1 ;
- FIG. 13 is a top perspective view of at least one embodiment of the storage sled of FIG. 12 ;
- FIG. 14 is a simplified block diagram of at least one embodiment of a memory sled usable in the data center of FIG. 1 ;
- FIG. 15 is a simplified block diagram of a system that may be established within the data center of FIG. 1 to execute workloads with managed nodes composed of disaggregated resources.
- FIG. 16 is a simplified block diagram of an at least one embodiment of a system for bandwidth allocation
- FIG. 17 is a simplified block diagram of at least one embodiment of a computing device of FIG. 16 ;
- FIG. 18 is a simplified block diagram of at least one embodiment of an environment of the resource manager of FIGS. 16 and 17 ;
- FIG. 19 is a simplified block diagram of at least one embodiment of an environment of a sled of FIGS. 16 and 17 ;
- FIG. 20 is a simplified flow diagram of at least one embodiment of a method for bandwidth allocation that may be executed by the resource manager server of FIGS. 16-18 ;
- FIG. 21 is a simplified flow diagram of at least one embodiment of a method for bandwidth allocation that may be executed by the sled of FIGS. 16-17 and 19 .
- references in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
- items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
- the disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof.
- the disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors.
- a machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
- a data center 100 in which disaggregated resources may cooperatively execute one or more workloads includes multiple pods 110 , 120 , 130 , 140 , each of which includes one or more rows of racks.
- each rack houses multiple sleds, which each may be embodied as a compute device, such as a server, that is primarily equipped with a particular type of resource (e.g., memory devices, data storage devices, accelerator devices, general purpose processors).
- the sleds in each pod 110 , 120 , 130 , 140 are connected to multiple pod switches (e.g., switches that route data communications to and from sleds within the pod).
- the pod switches connect with spine switches 150 that switch communications among pods (e.g., the pods 110 , 120 , 130 , 140 ) in the data center 100 .
- the sleds may be connected with a fabric using Intel Omni-Path technology.
- resources within sleds in the data center 100 may be allocated to a group (referred to herein as a “managed node”) containing resources from one or more other sleds to be collectively utilized in the execution of a workload.
- the workload can execute as if the resources belonging to the managed node were located on the same sled.
- the resources in a managed node may even belong to sleds belonging to different racks, and even to different pods 110 , 120 , 130 , 140 .
- Some resources of a single sled may be allocated to one managed node while other resources of the same sled are allocated to a different managed node (e.g., one processor assigned to one managed node and another processor of the same sled assigned to a different managed node).
- the data center 100 By disaggregating resources to sleds comprised predominantly of a single type of resource (e.g., compute sleds comprising primarily compute resources, memory sleds containing primarily memory resources), and selectively allocating and deallocating the disaggregated resources to form a managed node assigned to execute a workload, the data center 100 provides more efficient resource usage over typical data centers comprised of hyperconverged servers containing compute, memory, storage and perhaps additional resources). As such, the data center 100 may provide greater performance (e.g., throughput, operations per second, latency, etc.) than a typical data center that has the same number of resources.
- compute sleds comprising primarily compute resources
- the data center 100 may provide greater performance (e.g., throughput, operations per second, latency, etc.) than a typical data center that has the same number of resources.
- the pod 110 in the illustrative embodiment, includes a set of rows 200 , 210 , 220 , 230 of racks 240 .
- Each rack 240 may house multiple sleds (e.g., sixteen sleds) and provide power and data connections to the housed sleds, as described in more detail herein.
- the racks in each row 200 , 210 , 220 , 230 are connected to multiple pod switches 250 , 260 .
- the pod switch 250 includes a set of ports 252 to which the sleds of the racks of the pod 110 are connected and another set of ports 254 that connect the pod 110 to the spine switches 150 to provide connectivity to other pods in the data center 100 .
- the pod switch 260 includes a set of ports 262 to which the sleds of the racks of the pod 110 are connected and a set of ports 264 that connect the pod 110 to the spine switches 150 . As such, the use of the pair of switches 250 , 260 provides an amount of redundancy to the pod 110 .
- the switches 150 , 250 , 260 may be embodied as dual-mode optical switches, capable of routing both Ethernet protocol communications carrying Internet Protocol (IP) packets and communications according to a second, high-performance link-layer protocol (e.g., Intel's Omni-Path Architecture's, Infiniband) via optical signaling media of an optical fabric.
- IP Internet Protocol
- a second, high-performance link-layer protocol e.g., Intel's Omni-Path Architecture's, Infiniband
- each of the other pods 120 , 130 , 140 may be similarly structured as, and have components similar to, the pod 110 shown in and described in regard to FIG. 2 (e.g., each pod may have rows of racks housing multiple sleds as described above). Additionally, while two pod switches 250 , 260 are shown, it should be understood that in other embodiments, each pod 110 , 120 , 130 , 140 may be connected to different number of pod switches (e.g., providing even more failover capacity).
- each illustrative rack 240 of the data center 100 includes two elongated support posts 302 , 304 , which are arranged vertically.
- the elongated support posts 302 , 304 may extend upwardly from a floor of the data center 100 when deployed.
- the rack 240 also includes one or more horizontal pairs 310 of elongated support arms 312 (identified in FIG. 3 via a dashed ellipse) configured to support a sled of the data center 100 as discussed below.
- One elongated support arm 312 of the pair of elongated support arms 312 extends outwardly from the elongated support post 302 and the other elongated support arm 312 extends outwardly from the elongated support post 304 .
- each sled of the data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below.
- the rack 240 is configured to receive the chassis-less sleds.
- each pair 310 of elongated support arms 312 defines a sled slot 320 of the rack 240 , which is configured to receive a corresponding chassis-less sled.
- each illustrative elongated support arm 312 includes a circuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled.
- Each circuit board guide 330 is secured to, or otherwise mounted to, a top side 332 of the corresponding elongated support arm 312 .
- each circuit board guide 330 is mounted at a distal end of the corresponding elongated support arm 312 relative to the corresponding elongated support post 302 , 304 .
- not every circuit board guide 330 may be referenced in each Figure.
- Each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 configured to receive the chassis-less circuit board substrate of a sled 400 when the sled 400 is received in the corresponding sled slot 320 of the rack 240 .
- a user aligns the chassis-less circuit board substrate of an illustrative chassis-less sled 400 to a sled slot 320 .
- the user, or robot may then slide the chassis-less circuit board substrate forward into the sled slot 320 such that each side edge 414 of the chassis-less circuit board substrate is received in a corresponding circuit board slot 380 of the circuit board guides 330 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320 as shown in FIG. 4 .
- each type of resource can be upgraded independently of each other and at their own optimized refresh rate.
- the sleds are configured to blindly mate with power and data communication cables in each rack 240 , enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced.
- the data center 100 may operate (e.g., execute workloads, undergo maintenance and/or upgrades, etc.) without human involvement on the data center floor.
- a human may facilitate one or more maintenance or upgrade operations in the data center 100 .
- each circuit board guide 330 is dual sided. That is, each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 on each side of the circuit board guide 330 . In this way, each circuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack 240 to turn the rack 240 into a two-rack solution that can hold twice as many sled slots 320 as shown in FIG. 3 .
- the illustrative rack 240 includes seven pairs 310 of elongated support arms 312 that define a corresponding seven sled slots 320 , each configured to receive and support a corresponding sled 400 as discussed above.
- the rack 240 may include additional or fewer pairs 310 of elongated support arms 312 (i.e., additional or fewer sled slots 320 ). It should be appreciated that because the sled 400 is chassis-less, the sled 400 may have an overall height that is different than typical servers. As such, in some embodiments, the height of each sled slot 320 may be shorter than the height of a typical server (e.g., shorter than a single rank unit, “1U”).
- each of the elongated support posts 302 , 304 may have a length of six feet or less.
- the rack 240 may have different dimensions.
- the rack 240 does not include any walls, enclosures, or the like. Rather, the rack 240 is an enclosure-less rack that is opened to the local environment.
- an end plate may be attached to one of the elongated support posts 302 , 304 in those situations in which the rack 240 forms an end-of-row rack in the data center 100 .
- each elongated support post 302 , 304 includes an inner wall that defines an inner chamber in which the interconnect may be located.
- the interconnects routed through the elongated support posts 302 , 304 may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to each sled slot 320 , power interconnects to provide power to each sled slot 320 , and/or other types of interconnects.
- the rack 240 in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted.
- Each optical data connector is associated with a corresponding sled slot 320 and is configured to mate with an optical data connector of a corresponding sled 400 when the sled 400 is received in the corresponding sled slot 320 .
- optical connections between components (e.g., sleds, racks, and switches) in the data center 100 are made with a blind mate optical connection.
- a door on each cable may prevent dust from contaminating the fiber inside the cable.
- the door is pushed open when the end of the cable enters the connector mechanism. Subsequently, the optical fiber inside the cable enters a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.
- the illustrative rack 240 also includes a fan array 370 coupled to the cross-support arms of the rack 240 .
- the fan array 370 includes one or more rows of cooling fans 372 , which are aligned in a horizontal line between the elongated support posts 302 , 304 .
- the fan array 370 includes a row of cooling fans 372 for each sled slot 320 of the rack 240 .
- each sled 400 does not include any on-board cooling system in the illustrative embodiment and, as such, the fan array 370 provides cooling for each sled 400 received in the rack 240 .
- Each rack 240 also includes a power supply associated with each sled slot 320 .
- Each power supply is secured to one of the elongated support arms 312 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320 .
- the rack 240 may include a power supply coupled or secured to each elongated support arm 312 extending from the elongated support post 302 .
- Each power supply includes a power connector configured to mate with a power connector of the sled 400 when the sled 400 is received in the corresponding sled slot 320 .
- the sled 400 does not include any on-board power supply and, as such, the power supplies provided in the rack 240 supply power to corresponding sleds 400 when mounted to the rack 240 .
- each sled 400 in the illustrative embodiment, is configured to be mounted in a corresponding rack 240 of the data center 100 as discussed above.
- each sled 400 may be optimized or otherwise configured for performing particular tasks, such as compute tasks, acceleration tasks, data storage tasks, etc.
- the sled 400 may be embodied as a compute sled 800 as discussed below in regard to FIGS. 8-9 , an accelerator sled 1000 as discussed below in regard to FIGS. 10-11 , a storage sled 1200 as discussed below in regard to FIGS. 12-13 , or as a sled optimized or otherwise configured to perform other specialized tasks, such as a memory sled 1400 , discussed below in regard to FIG. 14 .
- the illustrative sled 400 includes a chassis-less circuit board substrate 602 , which supports various physical resources (e.g., electrical components) mounted thereon.
- the circuit board substrate 602 is “chassis-less” in that the sled 400 does not include a housing or enclosure. Rather, the chassis-less circuit board substrate 602 is open to the local environment.
- the chassis-less circuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon.
- the chassis-less circuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-less circuit board substrate 602 in other embodiments.
- the chassis-less circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602 .
- the chassis-less circuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled 400 by reducing those structures that may inhibit air flow.
- the chassis-less circuit board substrate 602 is not positioned in an individual housing or enclosure, there is no backplane (e.g., a backplate of the chassis) to the chassis-less circuit board substrate 602 , which could inhibit air flow across the electrical components.
- the chassis-less circuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate 602 .
- the illustrative chassis-less circuit board substrate 602 has a width 604 that is greater than a depth 606 of the chassis-less circuit board substrate 602 .
- the chassis-less circuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches.
- an airflow path 608 that extends from a front edge 610 of the chassis-less circuit board substrate 602 toward a rear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled 400 .
- the various physical resources mounted to the chassis-less circuit board substrate 602 are mounted in corresponding locations such that no two substantively heat-producing electrical components shadow each other as discussed in more detail below.
- no two electrical components which produce appreciable heat during operation (i.e., greater than a nominal heat sufficient enough to adversely impact the cooling of another electrical component), are mounted to the chassis-less circuit board substrate 602 linearly in-line with each other along the direction of the airflow path 608 (i.e., along a direction extending from the front edge 610 toward the rear edge 612 of the chassis-less circuit board substrate 602 ).
- the illustrative sled 400 includes one or more physical resources 620 mounted to a top side 650 of the chassis-less circuit board substrate 602 .
- the physical resources 620 may be embodied as any type of processor, controller, or other compute circuit capable of performing various tasks such as compute functions and/or controlling the functions of the sled 400 depending on, for example, the type or intended functionality of the sled 400 .
- the physical resources 620 may be embodied as high-performance processors in embodiments in which the sled 400 is embodied as a compute sled, as accelerator co-processors or circuits in embodiments in which the sled 400 is embodied as an accelerator sled, storage controllers in embodiments in which the sled 400 is embodied as a storage sled, or a set of memory devices in embodiments in which the sled 400 is embodied as a memory sled.
- the sled 400 also includes one or more additional physical resources 630 mounted to the top side 650 of the chassis-less circuit board substrate 602 .
- the additional physical resources include a network interface controller (NIC) as discussed in more detail below.
- NIC network interface controller
- the physical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments.
- the physical resources 620 are communicatively coupled to the physical resources 630 via an input/output (I/O) subsystem 622 .
- the I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with the physical resources 620 , the physical resources 630 , and/or other components of the sled 400 .
- the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations.
- the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDRS data bus.
- DDR4 double data rate 4
- the sled 400 may also include a resource-to-resource interconnect 624 .
- the resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications.
- the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622 ).
- the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.
- QPI QuickPath Interconnect
- UPI UltraPath Interconnect
- the sled 400 also includes a power connector 640 configured to mate with a corresponding power connector of the rack 240 when the sled 400 is mounted in the corresponding rack 240 .
- the sled 400 receives power from a power supply of the rack 240 via the power connector 640 to supply power to the various electrical components of the sled 400 . That is, the sled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of the sled 400 .
- the exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-less circuit board substrate 602 , which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602 as discussed above.
- power is provided to the processors 820 through vias directly under the processors 820 (e.g., through the bottom side 750 of the chassis-less circuit board substrate 602 ), providing an increased thermal budget, additional current and/or voltage, and better voltage control over typical boards.
- the sled 400 may also include mounting features 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in a rack 240 by the robot.
- the mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp the sled 400 without damaging the chassis-less circuit board substrate 602 or the electrical components mounted thereto.
- the mounting features 642 may be embodied as non-conductive pads attached to the chassis-less circuit board substrate 602 .
- the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate 602 .
- the particular number, shape, size, and/or make-up of the mounting feature 642 may depend on the design of the robot configured to manage the sled 400 .
- the sled 400 in addition to the physical resources 630 mounted on the top side 650 of the chassis-less circuit board substrate 602 , the sled 400 also includes one or more memory devices 720 mounted to a bottom side 750 of the chassis-less circuit board substrate 602 . That is, the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board.
- the physical resources 620 are communicatively coupled to the memory devices 720 via the I/O subsystem 622 .
- the physical resources 620 and the memory devices 720 may be communicatively coupled by one or more vias extending through the chassis-less circuit board substrate 602 .
- Each physical resource 620 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each physical resource 620 may be communicatively coupled to each memory devices 720 .
- the memory devices 720 may be embodied as any type of memory device capable of storing data for the physical resources 620 during operation of the sled 400 , such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory.
- Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium.
- Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM).
- RAM random access memory
- DRAM dynamic random access memory
- SRAM static random access memory
- SDRAM synchronous dynamic random access memory
- DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org).
- LPDDR Low Power DDR
- Such standards may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
- the memory device is a block addressable memory device, such as those based on NAND or NOR technologies.
- a memory device may also include next-generation nonvolatile devices, such as Intel 3D XPointTM memory or other byte addressable write-in-place nonvolatile memory devices.
- the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory.
- PCM Phase Change Memory
- MRAM magnetoresistive random access memory
- MRAM magnetoresistive random access memory
- STT spin transfer torque
- the memory device may refer to the die itself and/or to a packaged memory product.
- the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
- the sled 400 may be embodied as a compute sled 800 .
- the compute sled 800 is optimized, or otherwise configured, to perform compute tasks.
- the compute sled 800 may rely on other sleds, such as acceleration sleds and/or storage sleds, to perform such compute tasks.
- the compute sled 800 includes various physical resources (e.g., electrical components) similar to the physical resources of the sled 400 , which have been identified in FIG. 8 using the same reference numbers.
- the description of such components provided above in regard to FIGS. 6 and 7 applies to the corresponding components of the compute sled 800 and is not repeated herein for clarity of the description of the compute sled 800 .
- the physical resources 620 are embodied as processors 820 . Although only two processors 820 are shown in FIG. 8 , it should be appreciated that the compute sled 800 may include additional processors 820 in other embodiments.
- the processors 820 are embodied as high-performance processors 820 and may be configured to operate at a relatively high power rating. Although the processors 820 generate additional heat operating at power ratings greater than typical processors (which operate at around 155-230 W), the enhanced thermal cooling characteristics of the chassis-less circuit board substrate 602 discussed above facilitate the higher power operation.
- the processors 820 are configured to operate at a power rating of at least 250 W. In some embodiments, the processors 820 may be configured to operate at a power rating of at least 350 W.
- the compute sled 800 may also include a processor-to-processor interconnect 842 .
- the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications.
- the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622 ).
- processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
- QPI QuickPath Interconnect
- UPI UltraPath Interconnect
- point-to-point interconnect dedicated to processor-to-processor communications.
- the compute sled 800 also includes a communication circuit 830 .
- the illustrative communication circuit 830 includes a network interface controller (NIC) 832 , which may also be referred to as a host fabric interface (HFI).
- NIC network interface controller
- HFI host fabric interface
- the NIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, other devices that may be used by the compute sled 800 to connect with another compute device (e.g., with other sleds 400 ).
- the NIC 832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors.
- the NIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 832 .
- the local processor of the NIC 832 may be capable of performing one or more of the functions of the processors 820 .
- the local memory of the NIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.
- the communication circuit 830 is communicatively coupled to an optical data connector 834 .
- the optical data connector 834 is configured to mate with a corresponding optical data connector of the rack 240 when the compute sled 800 is mounted in the rack 240 .
- the optical data connector 834 includes a plurality of optical fibers which lead from a mating surface of the optical data connector 834 to an optical transceiver 836 .
- the optical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector.
- the optical transceiver 836 may form a portion of the communication circuit 830 in other embodiments.
- the compute sled 800 may also include an expansion connector 840 .
- the expansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled 800 .
- the additional physical resources may be used, for example, by the processors 820 during operation of the compute sled 800 .
- the expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate.
- the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources.
- the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
- processors memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
- FPGA field programmable gate arrays
- ASICs application-specific integrated circuits
- security co-processors graphics processing units (GPUs)
- GPUs graphics processing units
- machine learning circuits or other specialized processors, controllers, devices, and/or circuits.
- the processors 820 , communication circuit 830 , and optical data connector 834 are mounted to the top side 650 of the chassis-less circuit board substrate 602 .
- Any suitable attachment or mounting technology may be used to mount the physical resources of the compute sled 800 to the chassis-less circuit board substrate 602 .
- the various physical resources may be mounted in corresponding sockets (e.g., a processor socket), holders, or brackets.
- some of the electrical components may be directly mounted to the chassis-less circuit board substrate 602 via soldering or similar techniques.
- the individual processors 820 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other.
- the processors 820 and communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of the airflow path 608 .
- the optical data connector 834 is in-line with the communication circuit 830 , the optical data connector 834 produces no or nominal heat during operation.
- the memory devices 720 of the compute sled 800 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400 . Although mounted to the bottom side 750 , the memory devices 720 are communicatively coupled to the processors 820 located on the top side 650 via the I/O subsystem 622 . Because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the processors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602 . Of course, each processor 820 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments.
- each processor 820 may be communicatively coupled to each memory device 720 .
- the memory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate 602 and may interconnect with a corresponding processor 820 through a ball-grid array.
- Each of the processors 820 includes a heatsink 850 secured thereto. Due to the mounting of the memory devices 720 to the bottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of the sleds 400 in the corresponding rack 240 ), the top side 650 of the chassis-less circuit board substrate 602 includes additional “free” area or space that facilitates the use of heatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602 , none of the processor heatsinks 850 include cooling fans attached thereto. That is, each of the heatsinks 850 is embodied as a fan-less heatsinks.
- the sled 400 may be embodied as an accelerator sled 1000 .
- the accelerator sled 1000 is optimized, or otherwise configured, to perform specialized compute tasks, such as machine learning, encryption, hashing, or other computational-intensive task.
- a compute sled 800 may offload tasks to the accelerator sled 1000 during operation.
- the accelerator sled 1000 includes various components similar to components of the sled 400 and/or compute sled 800 , which have been identified in FIG. 10 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the accelerator sled 1000 and is not repeated herein for clarity of the description of the accelerator sled 1000 .
- the physical resources 620 are embodied as accelerator circuits 1020 .
- the accelerator sled 1000 may include additional accelerator circuits 1020 in other embodiments.
- the accelerator sled 1000 may include four accelerator circuits 1020 in some embodiments.
- the accelerator circuits 1020 may be embodied as any type of processor, co-processor, compute circuit, or other device capable of performing compute or processing operations.
- the accelerator circuits 1020 may be embodied as, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
- FPGA field programmable gate arrays
- ASICs application-specific integrated circuits
- GPUs graphics processing units
- machine learning circuits or other specialized processors, controllers, devices, and/or circuits.
- the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042 . Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622 ).
- the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
- the accelerator circuits 1020 may be daisy-chained with a primary accelerator circuit 1020 connected to the NIC 832 and memory 720 through the I/O subsystem 622 and a secondary accelerator circuit 1020 connected to the NIC 832 and memory 720 through a primary accelerator circuit 1020 .
- FIG. 11 an illustrative embodiment of the accelerator sled 1000 is shown.
- the accelerator circuits 1020 , communication circuit 830 , and optical data connector 834 are mounted to the top side 650 of the chassis-less circuit board substrate 602 .
- the individual accelerator circuits 1020 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other as discussed above.
- the memory devices 720 of the accelerator sled 1000 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 600 .
- each of the accelerator circuits 1020 may include a heatsink 1070 that is larger than a traditional heatsink used in a server. As discussed above with reference to the heatsinks 870 , the heatsinks 1070 may be larger than tradition heatsinks because of the “free” area provided by the memory devices 750 being located on the bottom side 750 of the chassis-less circuit board substrate 602 rather than on the top side 650 .
- the sled 400 may be embodied as a storage sled 1200 .
- the storage sled 1200 is optimized, or otherwise configured, to store data in a data storage 1250 local to the storage sled 1200 .
- a compute sled 800 or an accelerator sled 1000 may store and retrieve data from the data storage 1250 of the storage sled 1200 .
- the storage sled 1200 includes various components similar to components of the sled 400 and/or the compute sled 800 , which have been identified in FIG. 12 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7 , and 8 apply to the corresponding components of the storage sled 1200 and is not repeated herein for clarity of the description of the storage sled 1200 .
- the physical resources 620 are embodied as storage controllers 1220 . Although only two storage controllers 1220 are shown in FIG. 12 , it should be appreciated that the storage sled 1200 may include additional storage controllers 1220 in other embodiments.
- the storage controllers 1220 may be embodied as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into the data storage 1250 based on requests received via the communication circuit 830 .
- the storage controllers 1220 are embodied as relatively low-power processors or controllers.
- the storage controllers 1220 may be configured to operate at a power rating of about 75 watts.
- the storage sled 1200 may also include a controller-to-controller interconnect 1242 .
- the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications.
- the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622 ).
- controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
- QPI QuickPath Interconnect
- UPI UltraPath Interconnect
- point-to-point interconnect dedicated to processor-to-processor communications.
- the data storage 1250 is embodied as, or otherwise includes, a storage cage 1252 configured to house one or more solid state drives (SSDs) 1254 .
- the storage cage 1252 includes a number of mounting slots 1256 , each of which is configured to receive a corresponding solid state drive 1254 .
- Each of the mounting slots 1256 includes a number of drive guides 1258 that cooperate to define an access opening 1260 of the corresponding mounting slot 1256 .
- the storage cage 1252 is secured to the chassis-less circuit board substrate 602 such that the access openings face away from (i.e., toward the front of) the chassis-less circuit board substrate 602 .
- solid state drives 1254 are accessible while the storage sled 1200 is mounted in a corresponding rack 204 .
- a solid state drive 1254 may be swapped out of a rack 240 (e.g., via a robot) while the storage sled 1200 remains mounted in the corresponding rack 240 .
- the storage cage 1252 illustratively includes sixteen mounting slots 1256 and is capable of mounting and storing sixteen solid state drives 1254 .
- the storage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments.
- the solid state drivers are mounted vertically in the storage cage 1252 , but may be mounted in the storage cage 1252 in a different orientation in other embodiments.
- Each solid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above.
- the storage controllers 1220 , the communication circuit 830 , and the optical data connector 834 are illustratively mounted to the top side 650 of the chassis-less circuit board substrate 602 .
- any suitable attachment or mounting technology may be used to mount the electrical components of the storage sled 1200 to the chassis-less circuit board substrate 602 including, for example, sockets (e.g., a processor socket), holders, brackets, soldered connections, and/or other mounting or securing techniques.
- the individual storage controllers 1220 and the communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other.
- the storage controllers 1220 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those electrical components are linearly in-line with other along the direction of the airflow path 608 .
- the memory devices 720 of the storage sled 1200 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400 . Although mounted to the bottom side 750 , the memory devices 720 are communicatively coupled to the storage controllers 1220 located on the top side 650 via the I/O subsystem 622 . Again, because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the storage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602 . Each of the storage controllers 1220 includes a heatsink 1270 secured thereto.
- each of the heatsinks 1270 includes cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink.
- the sled 400 may be embodied as a memory sled 1400 .
- the storage sled 1400 is optimized, or otherwise configured, to provide other sleds 400 (e.g., compute sleds 800 , accelerator sleds 1000 , etc.) with access to a pool of memory (e.g., in two or more sets 1430 , 1432 of memory devices 720 ) local to the memory sled 1200 .
- a compute sled 800 or an accelerator sled 1000 may remotely write to and/or read from one or more of the memory sets 1430 , 1432 of the memory sled 1200 using a logical address space that maps to physical addresses in the memory sets 1430 , 1432 .
- the memory sled 1400 includes various components similar to components of the sled 400 and/or the compute sled 800 , which have been identified in FIG. 14 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the memory sled 1400 and is not repeated herein for clarity of the description of the memory sled 1400 .
- the physical resources 620 are embodied as memory controllers 1420 . Although only two memory controllers 1420 are shown in FIG. 14 , it should be appreciated that the memory sled 1400 may include additional memory controllers 1420 in other embodiments.
- the memory controllers 1420 may be embodied as any type of processor, controller, or control circuit capable of controlling the writing and reading of data into the memory sets 1430 , 1432 based on requests received via the communication circuit 830 .
- each storage controller 1220 is connected to a corresponding memory set 1430 , 1432 to write to and read from memory devices 720 within the corresponding memory set 1430 , 1432 and enforce any permissions (e.g., read, write, etc.) associated with sled 400 that has sent a request to the memory sled 1400 to perform a memory access operation (e.g., read or write).
- a memory access operation e.g., read or write
- the memory sled 1400 may also include a controller-to-controller interconnect 1442 .
- the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications.
- the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622 ).
- the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
- a memory controller 1420 may access, through the controller-to-controller interconnect 1442 , memory that is within the memory set 1432 associated with another memory controller 1420 .
- a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled 1400 ).
- the chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)).
- the combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels).
- the memory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to the memory set 1430 , the next memory address is mapped to the memory set 1432 , and the third address is mapped to the memory set 1430 , etc.).
- the interleaving may be managed within the memory controllers 1420 , or from CPU sockets (e.g., of the compute sled 800 ) across network links to the memory sets 1430 , 1432 , and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.
- the memory sled 1400 may be connected to one or more other sleds 400 (e.g., in the same rack 240 or an adjacent rack 240 ) through a waveguide, using the waveguide connector 1480 .
- the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit) lanes.
- Each lane in the illustrative embodiment, is either 16 Ghz or 32 Ghz. In other embodiments, the frequencies may be different.
- Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430 , 1432 ) to another sled (e.g., a sled 400 in the same rack 240 or an adjacent rack 240 as the memory sled 1400 ) without adding to the load on the optical data connector 834 .
- the memory pool e.g., the memory sets 1430 , 1432
- another sled e.g., a sled 400 in the same rack 240 or an adjacent rack 240 as the memory sled 1400
- the system 1510 includes an orchestrator server 1520 , which may be embodied as a managed node comprising a compute device (e.g., a compute sled 800 ) executing management software (e.g., a cloud operating environment, such as OpenStack) that is communicatively coupled to multiple sleds 400 including a large number of compute sleds 1530 (e.g., each similar to the compute sled 800 ), memory sleds 1540 (e.g., each similar to the memory sled 1400 ), accelerator sleds 1550 (e.g., each similar to the memory sled 1000 ), and storage sleds 1560 (e.g., each similar to the storage sled 1200 ).
- a compute device e.g., a compute sled 800
- management software e.g., a cloud operating environment, such as OpenStack
- multiple sleds 400 including a large number of compute sleds 1530 (e.g., each
- One or more of the sleds 1530 , 1540 , 1550 , 1560 may be grouped into a managed node 1570 , such as by the orchestrator server 1520 , to collectively perform a workload (e.g., an application 1532 executed in a virtual machine or in a container).
- the managed node 1570 may be embodied as an assembly of physical resources 620 , such as processors 820 , memory resources 720 , accelerator circuits 1020 , or data storage 1250 , from the same or different sleds 400 .
- the managed node may be established, defined, or “spun up” by the orchestrator server 1520 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node.
- the orchestrator server 1520 may selectively allocate and/or deallocate physical resources 620 from the sleds 400 and/or add or remove one or more sleds 400 from the managed node 1570 as a function of quality of service (QoS) targets (e.g., performance targets associated with a throughput, latency, instructions per second, etc.) associated with a service level agreement for the workload (e.g., the application 1532 ).
- QoS quality of service
- the orchestrator server 1520 may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in each sled 400 of the managed node 1570 and compare the telemetry data to the quality of service targets to determine whether the quality of service targets are being satisfied. If the so, the orchestrator server 1520 may additionally determine whether one or more physical resources may be deallocated from the managed node 1570 while still satisfying the QoS targets, thereby freeing up those physical resources for use in another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not presently satisfied, the orchestrator server 1520 may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application 1532 ) while the workload is executing
- performance conditions e.g., throughput, latency, instructions per second, etc.
- the orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532 ), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532 ) and pre-emptively identifying available resources in the data center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning).
- phases of execution e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed
- the orchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center 100 .
- the orchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA).
- the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled 400 on which the resource is located).
- the orchestrator server 1520 may generate a map of heat generation in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center 100 .
- telemetry data e.g., temperatures, fan speeds, etc.
- the orchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes.
- resource utilizations e.g., cause a different internal temperature, use a different percentage of processor or memory capacity
- the orchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center 100 .
- the orchestrator server 1520 may send self- test information to the sleds 400 to enable each sled 400 to locally (e.g., on the sled 400 ) determine whether telemetry data generated by the sled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each sled 400 may then report back a simplified result (e.g., yes or no) to the orchestrator server 1520 , which the orchestrator server 1520 may utilize in determining the allocation of resources to managed nodes.
- a simplified result e.g., yes or no
- a system 1600 for bandwidth allocation may be implemented in accordance with the data center 100 described above with reference to FIGS. 1-15 .
- the system 1600 includes a resource manager server 1602 and multiple sleds 1610 , 1612 , 1614 , 1616 , 1618 , 1620 in communication over a network using multiple switches 1604 , 1606 , 1608 .
- Each of the resource manager server 1602 and the sleds 1610 , 1612 , 1614 , 1616 , 1618 , 1620 may be embodied as server computer, a rack server, a blade server, a compute node, and/or a sled in a data center, such as a sled 400 as described above in connection with FIGS. 1-15 or another sled of the data center.
- the network elements of the system 1600 are organized into a network topology.
- the sleds 1610 , 1612 , 1614 may be organized into a rack and each connected to the switch 1606 , which may be embodied as a top-of-rack switch, middle-of-rack switch, end-of-row switch, or other switch device.
- the sleds 1616 , 1618 , 1620 are connected to the switch 1608 .
- the switches 1606 , 1608 are in turn connected to the switch 1604 , which may be embodied as a data center domain switch or other upstream switch.
- the resource manager server 1602 is illustrated as being connected to the upstream switch 1604 , however, in other embodiments it may be connected to any other location in the network topology.
- the switches 1604 , 1606 , 1608 are organized into multiple layers, and sending data across layers may add switching latency, queuing latency, or other latencies.
- the resource manager server 1602 is illustrated as a single server computing device, in some embodiments, the resource manager server 1602 may be embodied as a “virtual server” formed from multiple computing devices distributed across the system 1600 and/or operating in a public or private cloud. Accordingly, although the resource manager server 1602 is illustrated in FIG. 16 and described below as embodied as a single server computing device, it should be appreciated that the resource manager server 1602 may be embodied as multiple devices cooperating together to facilitate the functionality described below.
- the resource manager server 1602 may discover the network topology of the system 1600 and construct a model of resource oversubscription in the system 1600 .
- Resource oversubscription may include network uplink oversubscription, storage resource oversubscription, or any other circumstance in which the aggregate bandwidth or other demand generated by the sleds exceeds the available bandwidth or other capacity of the system 1600 .
- the resource manager server 1602 may determine bandwidth limits for each sled or other network element of the system 1600 and program those bandwidth limits to the network elements. Each network element enforces the programmed bandwidth limits, which may reduce network congestion. By reducing congestion, the system 1600 may eliminate or reduce queuing latency for each layer of switches.
- bandwidth limits for a storage sled 1610 may ensure that non-volatile memory express (NVMe) over Ethernet data traffic generated by the storage sled 1610 (and other storage sleds) does not exceed available upstream bandwidth. Accordingly, the system 1600 may improve network latency and reduce network congestion, without implementing expensive bandwidth reservation mechanisms at the switch level.
- NVMe non-volatile memory express
- the computing device 1700 may be the resource manager server 1602 , a sled 400 , a storage sled 1200 , 1610 , 1614 , 1616 , 1620 , an accelerator sled 1000 , a memory sled 1400 , a compute sled 800 , 1612 , 1618 , and/or a similar server computing device. As shown in FIG. 17 , an illustrative computing device 1700 is shown.
- the computing device 1700 may be the resource manager server 1602 , a sled 400 , a storage sled 1200 , 1610 , 1614 , 1616 , 1620 , an accelerator sled 1000 , a memory sled 1400 , a compute sled 800 , 1612 , 1618 , and/or a similar server computing device. As shown in FIG.
- the computing device 1700 illustratively includes a processor 1720 , an input/output subsystem 1722 , a memory 1724 , a data storage device 1726 , a communication subsystem 1728 , and/or other components and devices commonly found in a sled 400 , a storage sled 1200 , 1610 , 1614 , 1616 , 1620 , an accelerator sled 1000 , a memory sled 1400 , a compute sled 800 , 1612 , 1618 , and/or a similar server computing device.
- the computing device 1700 may include other or additional components, such as those commonly found in a server computer (e.g., various input/output devices), in other embodiments.
- one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component.
- the memory 1724 or portions thereof, may be incorporated in the processor 1720 in some embodiments.
- the processor 1720 may be embodied as any type of processor capable of performing the functions described herein.
- the processor 1720 may be embodied as a single or multi-core processor(s), digital signal processor, microcontroller, or other processor or processing/controlling circuit.
- the memory 1724 may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. In operation, the memory 1724 may store various data and software used during operation of the computing device 1700 such operating systems, applications, programs, libraries, and drivers.
- the memory 1724 is communicatively coupled to the processor 1720 via the I/O subsystem 1722 , which may be embodied as circuitry and/or components to facilitate input/output operations with the processor 1720 , the memory 1724 , and other components of the computing device 1700 .
- the I/O subsystem 1722 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, sensor hubs, firmware devices, communication links (i.e., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.) and/or other components and subsystems to facilitate the input/output operations.
- the I/O subsystem 1722 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor 1720 , the memory 1724 , and other components of the computing device 1700 , on a single integrated circuit chip.
- SoC system-on-a-chip
- the data storage device 1726 may be embodied as any type of device or devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, non-volatile flash memory, or other data storage devices.
- the computing device 1700 may also include a communications subsystem 1728 , which may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications between the computing device 1700 and other remote devices over a computer network (not shown).
- the communications subsystem 1728 may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, InfiniBand®, Bluetooth®, Wi-Fi®, WiMAX, 3G, 4G LTE, etc.) to effect such communication.
- the communication subsystem 1728 may include a network interface controller (NIC) 1330 .
- NIC network interface controller
- the illustrative communications subsystem 1728 includes a network interface controller (NIC) 1330 .
- the NIC 1730 may be embodied as one or more add-in-boards, daughtercards, controller chips, chipsets, circuits, or other devices that may be used by the computing device 1700 for network communications with remote devices.
- the NIC 1730 may be embodied as an expansion card coupled to the I/O subsystem 1722 over an expansion bus such as PCI Express.
- the NIC 1730 may be embodied as a network controller, host fabric interface, or other component integrated with the I/O subsystem 1722 , the processor 1720 , an SoC, and/or one or more other components of the computing device 1700 .
- the computing device 1700 may also include one or more peripheral devices 1732 .
- the peripheral devices 1732 may include any number of additional input/output devices, interface devices, and/or other peripheral devices.
- the peripheral devices 1732 may include a display, touch screen, graphics circuitry, keyboard, mouse, speaker system, microphone, network interface, and/or other input/output devices, interface devices, and/or peripheral devices.
- the resource manager server 1602 establishes an environment 1800 during operation.
- the illustrative environment 1800 includes a topology manager 1802 , a model constructor 1804 , a bandwidth limit determiner 1806 , a bandwidth limit programmer 1808 , and a utilization manager 1810 .
- the various components of the environment 1800 may be embodied as hardware, firmware, software, or a combination thereof.
- one or more of the components of the environment 1800 may be embodied as circuitry or collection of electrical devices (e.g., topology manager circuitry 1802 , model constructor circuitry 1804 , bandwidth limit determiner circuitry 1806 , bandwidth limit programmer circuitry 1808 , and/or utilization manager circuitry 1810 ).
- electrical devices e.g., topology manager circuitry 1802 , model constructor circuitry 1804 , bandwidth limit determiner circuitry 1806 , bandwidth limit programmer circuitry 1808 , and/or utilization manager circuitry 1810 ).
- one or more of the topology manager circuitry 1802 , the model constructor circuitry 1804 , the bandwidth limit determiner circuitry 1806 , the bandwidth limit programmer circuitry 1808 , and/or the utilization manager circuitry 1810 may form a portion of the processor 1720 , the I/O subsystem 1722 , the NIC 1730 , and/or other components of the resource manager server 1602 . Additionally, in some embodiments, one or more of the illustrative components may form a portion of another component and/or one or more of the illustrative components may be independent of one another.
- the topology manager 1802 is configured to discover the topology of the sleds coupled to a layer of switches that are communicatively coupled to the resource manager server 1602 .
- the model constructor 1804 is configured to construct a model of network connectivity between the plurality of sleds and the layer of switches based on the topology. Constructing the model may include identifying which sleds of the plurality of sleds are connected to a particular switch of the layer of switches.
- the bandwidth limit determiner 1806 is configured to determine an oversubscription of the network based on the model of network connectivity. The oversubscription is based on an available bandwidth for the layer of switches and a maximum bandwidth of the sleds. The bandwidth limit determiner 1806 may determine a network uplink oversubscription for the layer of switches or may determine a storage resource oversubscription of the sleds. The bandwidth limit determiner 1806 is further configured to determine a bandwidth limit for each sled based on the oversubscription. The bandwidth limit programmer 1808 is configured to program each sled with the corresponding bandwidth limit. The bandwidth limit programmer 1808 may communicate the bandwidth limit to the NIC 1730 of the corresponding sled.
- the utilization manager 1810 is configured to monitor a bandwidth utilization of the sleds. Monitoring the bandwidth utilization may include receiving telemetry data from the sleds that is indicative of the bandwidth utilized by each sled. The utilization manager 1810 is further configured to determine whether the network is congested based on the bandwidth utilization of the plurality of sleds. For example, determining whether the network is congested may include determining whether a queue depth of the network exceeds a predetermined queue depth limit for a predetermined amount of time. In some embodiments, determining whether the network is congested may include monitoring bandwidth per class of network traffic, such as NVMe over Ethernet traffic, field-programmable gate array (FPGA) over Ethernet traffic, storage traffic, and/or other traffic classes.
- FPGA field-programmable gate array
- Each traffic class may be independently monitored with its own queue depth controls. Further, bandwidth may be limited at the source or target, or in some embodiments based on source and target pair combinations.
- the utilization manager 1810 is further configured to modify a bandwidth limit in response to determining that the network is congested. The bandwidth limit may be reduced for each sled that is associated with a high input rate flow.
- a storage sled 1610 establishes an environment 1900 during operation. It should be understood that the environment 1900 may also be established by other sleds of the system 1600 .
- the illustrative environment 1900 includes a bandwidth limit manager 1904 , a bandwidth programmer 1906 , and a telemetry data manager 1908 .
- the various components of the environment 1900 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of the environment 1900 may be embodied as circuitry or collection of electrical devices (e.g., bandwidth limit manager circuitry 1904 , bandwidth programmer circuitry 1906 , and/or telemetry data manager circuitry 1908 ).
- one or more of the bandwidth limit manager circuitry 1904 , the bandwidth programmer circuitry 1906 , and/or the telemetry data manager circuitry 1908 may form a portion of the processor 1720 , the I/O subsystem 1722 , the NIC 1730 , and/or other components of the storage sled 1610 . Additionally, in some embodiments, one or more of the illustrative components may form a portion of another component and/or one or more of the illustrative components may be independent of one another.
- the bandwidth programmer 1906 is configured to receive a bandwidth limit for the sled from the resource manager server 1602 and to program the bandwidth limit to the NIC 1730 of the sled.
- the bandwidth limit manager 1904 is configured to enforce, by the NIC 1730 , the bandwidth limit in response to programming the bandwidth limit.
- the telemetry data manager 1908 is configured to send telemetry data indicative of utilization of the NIC 1730 to the resource manager server 1602 .
- the telemetry data may be sent by the NIC 1730 .
- the telemetry data may indicative of a NIC queue depth and/or or a network stack queue depth.
- the resource manager server 1602 may execute a method 2000 for bandwidth allocation. It should be appreciated that, in some embodiments, the operations of the method 2000 may be performed by one or more components of the environment 1800 of the resource manager server 1602 as shown in FIG. 18 .
- the method 2000 begins in block 2002 , in which the resource manager server 1602 discovers the network topology of the components of the system 1600 .
- the topology may be predetermined at design time of the system 1600 or, in some embodiments, may be discovered using a topology discovery protocol or other discovery technique.
- the resource manager server 1602 may discover sleds, racks, switches, and network connections of the system 1600 . For example, the resource manager server 1602 may identify that a sled is connected to a particular port of a switch. As another example, the resource manager server 1602 may identify that a port of a switch is connected to a particular port of an upstream switch.
- the resource manager server 1602 constructs a model of network connectivity between the components of the system 1600 .
- the model may identify network connections and the associated available bandwidth between sleds, switches, and other network elements of the system 1600 .
- the resource manager server 1602 determines oversubscription of the system 1600 based on the model of network connectivity. As described above, the system 1600 may be organized in layers, and each layer may have a maximum amount of available bandwidth or other resources. Oversubscription may exist if the total maximum bandwidth or other resource demand of a layer exceeds the available bandwidth or other resources of a higher layer. In some embodiments, in block 2010 , the resource manager server 1602 may determine network uplink oversubscription. For example, as shown in FIG. 16 , the sleds 1610 , 1612 , 1614 are connected to the switch 1606 .
- Oversubscription may exist if the maximum bandwidth used by the sleds 1610 , 1612 , 1614 in combination exceeds the available bandwidth of the uplink from the switch 1606 to the switch 1604 .
- oversubscription may exist if the maximum bandwidth used by the sleds 1616 , 1618 , 1620 exceeds the available bandwidth of the uplink from the switch 1608 to the switch 1604 .
- the resource manager server 1602 may determine storage resource oversubscription. For example, oversubscription may exist if demand for storage resources of a sled (e.g., the storage sled 1610 ) exceeds the available bandwidth or other resources of that sled.
- the resource manager server 1602 determines bandwidth limits for each sled in the system 1600 based on the oversubscription.
- the bandwidth limits may be determined in order to prevent or reduce network congestion in the system 1600 .
- the bandwidth limits for sleds 1610 , 1612 , 1614 may be set so that the combined bandwidth limits are less than or equal to the uplink bandwidth from the switch 1606 to the switch 1604 .
- the resource manager server 1602 programs each sled with the corresponding bandwidth limit. After being programmed, each sled enforces the bandwidth limits, as described further below in connection with FIG. 21 .
- the resource manager server 1602 may use any technique to program the sled.
- the resource manager server 1602 may program the NIC 1730 of the sled with the bandwidth limit. For example, the resource manager server 1602 may communicate out-of-band or otherwise communicate with the NIC 1730 without invoking the operating system or other software networking stack of the sled.
- the resource manager server 1602 may receive bandwidth telemetry from the sleds of the system 1600 .
- the bandwidth telemetry may indicate the current bandwidth usage of the sled and/or whether the associated network connection is congested.
- the bandwidth telemetry may indicate queue depth of the NIC 1730 , the associated switch port, and/or the networking stack of the sled.
- the resource manager server 1602 identifies network congestion based on the telemetry.
- the resource manager server 1602 may use any appropriate algorithm to identify dropped packets, increased latency, or otherwise identify the network congestion.
- the resource manager server 1602 may determine whether any queue depth in the system exceeds a predetermined threshold queue depth for longer than a predetermined time. For example, the resource manager server 1602 may analyze the queue depth of a NIC 1730 , a switch port, and/or a networking stack of a sled.
- the resource manager server 1602 determines whether congestion has been detected. If not, the method 2000 loops back to block 2020 to continue monitoring network utilization. If congestion is detected, the method 2000 advances to block 2028 .
- the resource manager server 1602 modifies one or more bandwidth limits to reduce or eliminate the congestion.
- the resource manager server 1602 may identify one or more high-input rate flows in the system 1600 . For example, one or more storage sleds 1610 generating NVMe over Ethernet data may generate high-input rate flows. The resource manager server 1602 may reduce the input rate bandwidth limit associated with the high-input rate flows. Additionally or alternatively, in some embodiments the resource manager server 1602 may generate one or more alerts concerning the congestion, and a network administrator may provide modified bandwidth limits. In some embodiments, alternate network routes may be possible. If alternate routes are possible, based on the congestion telemetry data, different bandwidth limits may be set for different routes to reduce the congestion rate. After modifying the bandwidth limits, the method 2000 loops back to block 2016 to program the sleds with the modified bandwidth limits and continue monitoring network utilization.
- a storage sled 1610 may execute a method 2100 for bandwidth allocation. It should be appreciated that, in some embodiments, the operations of the method 2100 may be performed by one or more components of the environment 1900 of the storage sled 1610 as shown in FIG. 19 .
- the method 2100 begins in block 2102 , in which the storage sled 1610 determines whether an update to a bandwidth limit has been received from the resource manager server 1602 . As described above in connection with FIG. 20 , the resource manager server 1602 may program the bandwidth limit to the storage sled 1610 in response to modeling network connectivity and determining an oversubscription of the system 1600 and/or in response to detecting network congestion based on telemetry data. If an update to the bandwidth limit has not been received, the method 2100 branches ahead to block 2108 , described below. If an update to the bandwidth limit has been received, the method 2100 advances to block 2104 .
- the storage sled 1610 programs one or more network interface controllers (NICs) 1330 of the storage sled with the new bandwidth limit.
- the NIC 1730 may throttle or otherwise limit bandwidth used by the storage sled 1610 to below the bandwidth limit.
- the storage sled 1610 may set a maximum input bandwidth for the NIC 1730 .
- the bandwidth limits may limit the amount of data (e.g., NVMe over Ethernet data) generated by the storage sled 1610 and submitted to the switch 1606 .
- bandwidth limits may be enforced by other components of the storage sled 1610 , such as an operating system, software networking stack, NVMe over Ethernet subsystem, or other component.
- the storage sled 1610 determines whether to send telemetry data to the resource manager server 1602 .
- the storage sled 1610 may be configured by an administrator to send telemetry data.
- the storage sled 1610 may send telemetry data in response to certain events, for example in response to detected network congestion. If the storage sled 1610 determines not to send telemetry data, the method 2100 loops back to block 2102 to continue monitoring for updated bandwidth limits. If the storage sled 1610 determines to send telemetry data, the method 2100 advances to block 2110 .
- the storage sled 1610 sends bandwidth telemetry data to the resource manager server 1602 .
- the bandwidth telemetry may indicate the current bandwidth usage of the sled and/or whether the associated network connection is congested.
- the bandwidth telemetry may indicate queue depth of the NIC 1730 , the associated switch port, and/or the network stack of the sled.
- the storage sled 1610 may retrieve the telemetry data from the NIC 1730 of the storage sled 1610 .
- an operating system, software networking stack, or other component of the storage sled 1610 may retrieve telemetry data from the NIC 1730 .
- the storage sled 1610 may send the telemetry data from the NIC 1730 to the resource manager server 1602 .
- the NIC 1730 may send the telemetry data out-of-band or otherwise without the involvement of the operating system, software networking stack, or other components of the storage sled 1610 .
- the method 2100 loops back to block 2102 to continue monitoring for updated bandwidth limits.
- An embodiment of the technologies disclosed herein may include any one or more, and any combination of, the examples described below.
- Example 1 includes a resource manager server for bandwidth allocation, the resource manager server comprising: one or more processors; and one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the resource manager server to: discover a topology of a plurality of sleds coupled to a layer of switches that are communicatively coupled to the resource manager server; construct a model of network connectivity between the plurality of sleds and the layer of switches based on the topology; determine an oversubscription of a network based on the model of network connectivity, wherein the oversubscription is based on an available bandwidth for the layer of switches and a maximum bandwidth of the plurality of sleds; determine a bandwidth limit for each sled of the plurality of sleds based on the oversubscription; and program each sled of the plurality of sleds with the corresponding bandwidth limit.
- the resource manager server comprising: one or more processors; and one or more memory devices having stored therein a plurality of instructions
- Example 2 includes the subject matter of Example 1, and wherein to construct the model of network connectivity comprises to identify which sleds of the plurality of sleds are connected to a particular switch of the layer of switches.
- Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to determine the oversubscription comprises to determine a network uplink oversubscription for the layer of switches.
- Example 4 includes the subject matter of any of Examples 1-3, and wherein to determine the oversubscription comprises to determine a storage resource oversubscription of the plurality of sleds.
- Example 5 includes the subject matter of any of Examples 1-4, and wherein to program the bandwidth limit for each sled comprises to communicate the bandwidth limit to a network interface controller of the corresponding sled.
- Example 6 includes the subject matter of any of Examples 1-5, and wherein the one or more memory devices have stored therein a plurality of instructions that, when executed by the one or more processors, further cause the resource manager server to: monitor a bandwidth utilization of the plurality of sleds; determine whether the network is congested based on the bandwidth utilization of the plurality of sleds; and modify a bandwidth limit in response to a determination that the network is congested.
- Example 7 includes the subject matter of any of Examples 1-6, and wherein to monitor the bandwidth utilization of the plurality of sleds comprises to receive telemetry data from the plurality of sleds indicative of the bandwidth utilized by each sled.
- Example 8 includes the subject matter of any of Examples 1-7, and wherein to determine whether the network is congested comprises to determine whether a queue depth of the network exceeds a predetermined queue depth limit for a predetermined amount of time.
- Example 9 includes the subject matter of any of Examples 1-8, and wherein the queue depth comprises a switch port queue depth, a network interface controller queue depth, or a network stack queue depth.
- Example 10 includes the subject matter of any of Examples 1-9, and wherein to modify the bandwidth limit comprises to: identify a first sled of the plurality of sleds associated with a high input rate flow; and reduce an input rate of the bandwidth limit for the first sled.
- Example 11 includes a sled for bandwidth allocation, the sled communicatively coupled to a layer of switches that are communicatively coupled to a resource manager server on a network, the sled comprising: one or more processors; and one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the sled to: receive a bandwidth limit for the sled from the resource manager server; program the bandwidth limit to a network interface controller of the sled; and enforce, by the network interface controller, the bandwidth limit in response to programming of the bandwidth limit.
- Example 12 includes the subject matter of Example 11, and wherein the one or more memory devices have stored therein a plurality of instructions that, when executed by the one or more processors, further cause the sled to send telemetry data indicative of a utilization of the network interface controller to the resource manager server of the network.
- Example 13 includes the subject matter of any of Examples 11 and 12, and wherein to send the telemetry data comprises to send the telemetry data by the network interface controller.
- Example 14 includes the subject matter of any of Examples 11-13, and wherein the telemetry data is indicative of a network interface controller queue depth, or a network stack queue depth.
- Example 15 includes a method for bandwidth allocation, the method comprising: discovering, by a resource manager server of a network, a topology of a plurality of sleds coupled to a layer of switches that are communicatively coupled to the resource manager server; constructing, by the resource manager server, a model of network connectivity between the plurality of sleds and the layer of switches based on the topology; determining, by the resource manager server, an oversubscription of the network based on the model of network connectivity, wherein the oversubscription is based on an available bandwidth for the layer of switches and a maximum bandwidth of the plurality of sleds; determining, by the resource manager server, a bandwidth limit for each sled of the plurality of sleds based on the oversubscription; and programming, by the resource manager server, each sled of the plurality of sleds with the corresponding bandwidth limit.
- Example 16 includes the subject matter of Example 15, and wherein constructing the model of network connectivity comprises identifying which sleds of the plurality of sleds are connected to a particular switch of the layer of switches.
- Example 17 includes the subject matter of any of Examples 15 and 16, and wherein determining the oversubscription comprises determining a network uplink oversubscription for the layer of switches.
- Example 18 includes the subject matter of any of Examples 15-17, and wherein determining the oversubscription comprises determining a storage resource oversubscription of the plurality of sleds.
- Example 19 includes the subject matter of any of Examples 15-18, and wherein programming the bandwidth limit for each sled comprises communicating the bandwidth limit to a network interface controller of the corresponding sled.
- Example 20 includes the subject matter of any of Examples 15-19, and further comprising: monitoring, by the resource manager server, a bandwidth utilization of the plurality of sleds; determining, by the resource manager server, whether the network is congested based on the bandwidth utilization of the plurality of sleds; and modifying, by the resource manager server, a bandwidth limit in response to determining that the network is congested.
- Example 21 includes the subject matter of any of Examples 15-20, and wherein monitoring the bandwidth utilization of the plurality of sleds comprises receiving telemetry data from the plurality of sleds indicative of the bandwidth utilized by each sled.
- Example 22 includes the subject matter of any of Examples 15-21, and wherein determining whether the network is congested comprises determining whether a queue depth of the network exceeds a predetermined queue depth limit for a predetermined amount of time.
- Example 23 includes the subject matter of any of Examples 15-22, and wherein the queue depth comprises a switch port queue depth, a network interface controller queue depth, or a network stack queue depth.
- Example 24 includes the subject matter of any of Examples 15-23, and wherein modifying the bandwidth limit comprises: identifying a first sled of the plurality of sleds associated with a high input rate flow; and reducing an input rate of the bandwidth limit for the first sled.
- Example 25 includes a method for bandwidth allocation, the method comprising: receiving, by a sled of a plurality of sleds communicatively coupled to a layer of switches that are communicatively coupled to a resource manager server in a network, a bandwidth limit for the sled from the resource manager server; programming, by the sled, the bandwidth limit to a network interface controller of the sled; and enforcing, by the network interface controller of the sled, the bandwidth limit in response to programming the bandwidth limit.
- Example 26 includes the subject matter of Example 25, and further comprising sending, by the sled, telemetry data indicative of a utilization of the network interface controller to the resource manager server of the network.
- Example 27 includes the subject matter of any of Examples 25 and 26, and wherein sending the telemetry data comprises sending the telemetry data by the network interface controller.
- Example 28 includes the subject matter of any of Examples 25-27, and wherein the telemetry data is indicative of a network interface controller queue depth, or a network stack queue depth.
- Example 29 includes a computing device comprising: a processor; and a memory having stored therein a plurality of instructions that when executed by the processor cause the computing device to perform the method of any of Examples 15-28.
- Example 30 includes one or more non-transitory, computer readable storage media comprising a plurality of instructions stored thereon that in response to being executed result in a computing device performing the method of any of Examples 15-28.
- Example 31 includes a computing device comprising means for performing the method of any of Examples 15-28.
- Example 32 includes a resource manager server for bandwidth allocation, the resource manager server comprising: topology manager circuitry to discover a topology of a plurality of sleds coupled to a layer of switches that are communicatively coupled to the resource manager server; model constructer circuitry to construct a model of network connectivity between the plurality of sleds and the layer of switches based on the topology; bandwidth limit determiner circuitry to (i) determine an oversubscription of a network based on the model of network connectivity, wherein the oversubscription is based on an available bandwidth for the layer of switches and a maximum bandwidth of the plurality of sleds, and (ii) determine a bandwidth limit for each sled of the plurality of sleds based on the oversubscription; and bandwidth limit programmer circuitry to program each sled of the plurality of sleds with the corresponding bandwidth limit.
- topology manager circuitry to discover a topology of a plurality of sleds coupled to a layer of switches that are communicatively coupled to
- Example 33 includes the subject matter of Example 32, and wherein to construct the model of network connectivity comprises to identify which sleds of the plurality of sleds are connected to a particular switch of the layer of switches.
- Example 34 includes the subject matter of any of Examples 32 and 33, and wherein to determine the oversubscription comprises to determine a network uplink oversubscription for the layer of switches.
- Example 35 includes the subject matter of any of Examples 32-34, and wherein to determine the oversubscription comprises to determine a storage resource oversubscription of the plurality of sleds.
- Example 36 includes the subject matter of any of Examples 32-35, and wherein to program the bandwidth limit for each sled comprises to communicate the bandwidth limit to a network interface controller of the corresponding sled.
- Example 37 includes the subject matter of any of Examples 32-36, and further comprising utilization manager circuitry to: monitor a bandwidth utilization of the plurality of sleds; determine whether the network is congested based on the bandwidth utilization of the plurality of sleds; and modify a bandwidth limit in response to a determination that the network is congested.
- Example 38 includes the subject matter of any of Examples 32-37, and wherein to monitor the bandwidth utilization of the plurality of sleds comprises to receive telemetry data from the plurality of sleds indicative of the bandwidth utilized by each sled.
- Example 39 includes the subject matter of any of Examples 32-38, and wherein to determine whether the network is congested comprises to determine whether a queue depth of the network exceeds a predetermined queue depth limit for a predetermined amount of time.
- Example 40 includes the subject matter of any of Examples 32-39, and wherein the queue depth comprises a switch port queue depth, a network interface controller queue depth, or a network stack queue depth.
- Example 41 includes the subject matter of any of Examples 32-40, and wherein to modify the bandwidth limit comprises to: identify a first sled of the plurality of sleds associated with a high input rate flow; and reduce an input rate of the bandwidth limit for the first sled.
- Example 42 includes a sled for bandwidth allocation, the sled communicatively coupled to a layer of switches that communicatively coupled to a resource manager server on a network, the sled comprising: bandwidth programmer circuitry to: (i) receive a bandwidth limit for the sled from the resource manager server, and (ii) program the bandwidth limit to a network interface controller of the sled; and bandwidth limit manager circuitry to enforce, by the network interface controller, the bandwidth limit in response to programming of the bandwidth limit.
- Example 43 includes the subject matter of Example 42, and further comprising telemetry data manager circuitry to send telemetry data indicative of a utilization of the network interface controller to the resource manager server of the network.
- Example 44 includes the subject matter of any of Examples 42 and 43, and wherein to send the telemetry data comprises to send the telemetry data by the network interface controller.
- Example 45 includes the subject matter of any of Examples 42-44, and wherein the telemetry data is indicative of a network interface controller queue depth, or a network stack queue depth.
- Example 46 includes a resource manager server for bandwidth allocation, the resource manager server comprising: means for discovering a topology of a plurality of sleds coupled to a layer of switches that are communicatively coupled to the resource manager server in a network; means for constructing a model of network connectivity between the plurality of sleds and the layer of switches based on the topology; means for determining an oversubscription of the network based on the model of network connectivity, wherein the oversubscription is based on an available bandwidth for the layer of switches and a maximum bandwidth of the plurality of sleds; means for determining a bandwidth limit for each sled of the plurality of sleds based on the oversubscription; and means for programming each sled of the plurality of sleds with the corresponding bandwidth limit.
- Example 47 includes the subject matter of Example 46, and wherein the means for constructing the model of network connectivity comprises means for identifying which sleds of the plurality of sleds are connected to a particular switch of the layer of switches.
- Example 48 includes the subject matter of any of Examples 46 and 47, and wherein the means for determining the oversubscription comprises means for determining a network uplink oversubscription for the layer of switches.
- Example 49 includes the subject matter of any of Examples 46-48, and wherein the means for determining the oversubscription comprises means for determining a storage resource oversubscription of the plurality of sleds.
- Example 50 includes the subject matter of any of Examples 46-49, and wherein the means for programming the bandwidth limit for each sled comprises circuitry for communicating the bandwidth limit to a network interface controller of the corresponding sled.
- Example 51 includes the subject matter of any of Examples 46-50, and further comprising: means for monitoring a bandwidth utilization of the plurality of sleds; means for determining whether the network is congested based on the bandwidth utilization of the plurality of sleds; and means for modifying a bandwidth limit in response to determining that the network is congested.
- Example 52 includes the subject matter of any of Examples 46-51, and wherein the means for monitoring the bandwidth utilization of the plurality of sleds comprises circuitry for receiving telemetry data from the plurality of sleds indicative of the bandwidth utilized by each sled.
- Example 53 includes the subject matter of any of Examples 46-52, and wherein the means for determining whether the network is congested comprises means for determining whether a queue depth of the network exceeds a predetermined queue depth limit for a predetermined amount of time.
- Example 54 includes the subject matter of any of Examples 46-53, and wherein the queue depth comprises a switch port queue depth, a network interface controller queue depth, or a network stack queue depth.
- Example 55 includes the subject matter of any of Examples 46-54, and wherein the means for modifying the bandwidth limit comprises: means for identifying a first sled of the plurality of sleds associated with a high input rate flow; and means for reducing an input rate of the bandwidth limit for the first sled.
- Example 56 includes a sled for bandwidth allocation, the sled communicatively coupled to a layer of switches that are communicatively coupled to a resource manager server on a network, the sled comprising: circuitry for receiving a bandwidth limit for the sled from the resource manager server; means for programming the bandwidth limit to a network interface controller of the sled; and means for enforcing, by the network interface controller of the sled, the bandwidth limit in response to programming the bandwidth limit.
- Example 57 includes the subject matter of Example 56, and further comprising means for sending telemetry data indicative of a utilization of the network interface controller to the resource manager server of the network.
- Example 58 includes the subject matter of any of Examples 56 and 57, and wherein the means for sending the telemetry data comprises means for sending the telemetry data by the network interface controller.
- Example 59 includes the subject matter of any of Examples 56-58, and wherein the telemetry data is indicative of a network interface controller queue depth, or a network stack queue depth.
Abstract
Description
- The present application claims the benefit Indian Provisional Patent Application No. 2017410306 32, filed Aug. 30, 2017, and U.S. Provisional Patent Application No. 62/584,401, filed Nov. 10, 2017.
- Datacenters and other large computer networks typically include multiple layers of switches. For example, servers may be installed in racks, and each server in a rack may be connected to a top-of-rack switch. Multiple top-of-rack switches may be connected to an upstream switch, and so on. Therefore, communicating between servers or other nodes in different racks may require traversing multiple switch layers. Traversing each layer of switches may introduce queuing latency.
- The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
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FIG. 1 is a simplified diagram of at least one embodiment of a data center for executing workloads with disaggregated resources; -
FIG. 2 is a simplified diagram of at least one embodiment of a pod of the data center ofFIG. 1 ; -
FIG. 3 is a perspective view of at least one embodiment of a rack that may be included in the pod ofFIG. 2 ; -
FIG. 4 is a side plan elevation view of the rack ofFIG. 3 ; -
FIG. 5 is a perspective view of the rack ofFIG. 3 having a sled mounted therein; -
FIG. 6 is a is a simplified block diagram of at least one embodiment of a top side of the sled ofFIG. 5 ; -
FIG. 7 is a simplified block diagram of at least one embodiment of a bottom side of the sled ofFIG. 6 ; -
FIG. 8 is a simplified block diagram of at least one embodiment of a compute sled usable in the data center ofFIG. 1 ; -
FIG. 9 is a top perspective view of at least one embodiment of the compute sled ofFIG. 8 ; -
FIG. 10 is a simplified block diagram of at least one embodiment of an accelerator sled usable in the data center ofFIG. 1 ; -
FIG. 11 is a top perspective view of at least one embodiment of the accelerator sled ofFIG. 10 ; -
FIG. 12 is a simplified block diagram of at least one embodiment of a storage sled usable in the data center ofFIG. 1 ; -
FIG. 13 is a top perspective view of at least one embodiment of the storage sled ofFIG. 12 ; -
FIG. 14 is a simplified block diagram of at least one embodiment of a memory sled usable in the data center ofFIG. 1 ; and -
FIG. 15 is a simplified block diagram of a system that may be established within the data center ofFIG. 1 to execute workloads with managed nodes composed of disaggregated resources. -
FIG. 16 is a simplified block diagram of an at least one embodiment of a system for bandwidth allocation; -
FIG. 17 is a simplified block diagram of at least one embodiment of a computing device ofFIG. 16 ; -
FIG. 18 is a simplified block diagram of at least one embodiment of an environment of the resource manager ofFIGS. 16 and 17 ; -
FIG. 19 is a simplified block diagram of at least one embodiment of an environment of a sled ofFIGS. 16 and 17 ; -
FIG. 20 is a simplified flow diagram of at least one embodiment of a method for bandwidth allocation that may be executed by the resource manager server ofFIGS. 16-18 ; and -
FIG. 21 is a simplified flow diagram of at least one embodiment of a method for bandwidth allocation that may be executed by the sled ofFIGS. 16-17 and 19 . - While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
- References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
- The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
- In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
- Referring now to
FIG. 1 , adata center 100 in which disaggregated resources may cooperatively execute one or more workloads (e.g., applications on behalf of customers) includesmultiple pods pod spine switches 150 that switch communications among pods (e.g., thepods data center 100. In some embodiments, the sleds may be connected with a fabric using Intel Omni-Path technology. As described in more detail herein, resources within sleds in thedata center 100 may be allocated to a group (referred to herein as a “managed node”) containing resources from one or more other sleds to be collectively utilized in the execution of a workload. The workload can execute as if the resources belonging to the managed node were located on the same sled. The resources in a managed node may even belong to sleds belonging to different racks, and even todifferent pods data center 100 provides more efficient resource usage over typical data centers comprised of hyperconverged servers containing compute, memory, storage and perhaps additional resources). As such, thedata center 100 may provide greater performance (e.g., throughput, operations per second, latency, etc.) than a typical data center that has the same number of resources. - Referring now to
FIG. 2 , thepod 110, in the illustrative embodiment, includes a set ofrows racks 240. Eachrack 240 may house multiple sleds (e.g., sixteen sleds) and provide power and data connections to the housed sleds, as described in more detail herein. In the illustrative embodiment, the racks in eachrow multiple pod switches pod switch 250 includes a set ofports 252 to which the sleds of the racks of thepod 110 are connected and another set ofports 254 that connect thepod 110 to thespine switches 150 to provide connectivity to other pods in thedata center 100. Similarly, thepod switch 260 includes a set ofports 262 to which the sleds of the racks of thepod 110 are connected and a set ofports 264 that connect thepod 110 to thespine switches 150. As such, the use of the pair ofswitches pod 110. For example, if either of theswitches pod 110 may still maintain data communication with the remainder of the data center 100 (e.g., sleds of other pods) through theother switch switches - It should be appreciated that each of the
other pods pod 110 shown in and described in regard toFIG. 2 (e.g., each pod may have rows of racks housing multiple sleds as described above). Additionally, while twopod switches pod - Referring now to
FIGS. 3-5 , eachillustrative rack 240 of thedata center 100 includes two elongated support posts 302, 304, which are arranged vertically. For example, the elongated support posts 302, 304 may extend upwardly from a floor of thedata center 100 when deployed. Therack 240 also includes one or morehorizontal pairs 310 of elongated support arms 312 (identified inFIG. 3 via a dashed ellipse) configured to support a sled of thedata center 100 as discussed below. Oneelongated support arm 312 of the pair ofelongated support arms 312 extends outwardly from theelongated support post 302 and the otherelongated support arm 312 extends outwardly from theelongated support post 304. - In the illustrative embodiments, each sled of the
data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, therack 240 is configured to receive the chassis-less sleds. For example, eachpair 310 ofelongated support arms 312 defines asled slot 320 of therack 240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrativeelongated support arm 312 includes acircuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled. Eachcircuit board guide 330 is secured to, or otherwise mounted to, atop side 332 of the correspondingelongated support arm 312. For example, in the illustrative embodiment, eachcircuit board guide 330 is mounted at a distal end of the correspondingelongated support arm 312 relative to the correspondingelongated support post circuit board guide 330 may be referenced in each Figure. - Each
circuit board guide 330 includes an inner wall that defines acircuit board slot 380 configured to receive the chassis-less circuit board substrate of asled 400 when thesled 400 is received in thecorresponding sled slot 320 of therack 240. To do so, as shown inFIG. 4 , a user (or robot) aligns the chassis-less circuit board substrate of anillustrative chassis-less sled 400 to asled slot 320. The user, or robot, may then slide the chassis-less circuit board substrate forward into thesled slot 320 such that eachside edge 414 of the chassis-less circuit board substrate is received in a correspondingcircuit board slot 380 of the circuit board guides 330 of thepair 310 ofelongated support arms 312 that define thecorresponding sled slot 320 as shown inFIG. 4 . By having robotically accessible and robotically manipulable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate. Furthermore, the sleds are configured to blindly mate with power and data communication cables in eachrack 240, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. As such, in some embodiments, thedata center 100 may operate (e.g., execute workloads, undergo maintenance and/or upgrades, etc.) without human involvement on the data center floor. In other embodiments, a human may facilitate one or more maintenance or upgrade operations in thedata center 100. - It should be appreciated that each
circuit board guide 330 is dual sided. That is, eachcircuit board guide 330 includes an inner wall that defines acircuit board slot 380 on each side of thecircuit board guide 330. In this way, eachcircuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to therack 240 to turn therack 240 into a two-rack solution that can hold twice asmany sled slots 320 as shown inFIG. 3 . Theillustrative rack 240 includes sevenpairs 310 ofelongated support arms 312 that define a corresponding sevensled slots 320, each configured to receive and support acorresponding sled 400 as discussed above. Of course, in other embodiments, therack 240 may include additional orfewer pairs 310 of elongated support arms 312 (i.e., additional or fewer sled slots 320). It should be appreciated that because thesled 400 is chassis-less, thesled 400 may have an overall height that is different than typical servers. As such, in some embodiments, the height of eachsled slot 320 may be shorter than the height of a typical server (e.g., shorter than a single rank unit, “1U”). That is, the vertical distance between eachpair 310 ofelongated support arms 312 may be less than a standard rack unit “1U.” Additionally, due to the relative decrease in height of thesled slots 320, the overall height of therack 240 in some embodiments may be shorter than the height of traditional rack enclosures. For example, in some embodiments, each of the elongated support posts 302, 304 may have a length of six feet or less. Again, in other embodiments, therack 240 may have different dimensions. Further, it should be appreciated that therack 240 does not include any walls, enclosures, or the like. Rather, therack 240 is an enclosure-less rack that is opened to the local environment. Of course, in some cases, an end plate may be attached to one of the elongated support posts 302, 304 in those situations in which therack 240 forms an end-of-row rack in thedata center 100. - In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts 302, 304. To facilitate such routing, each
elongated support post sled slot 320, power interconnects to provide power to eachsled slot 320, and/or other types of interconnects. - The
rack 240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with acorresponding sled slot 320 and is configured to mate with an optical data connector of acorresponding sled 400 when thesled 400 is received in thecorresponding sled slot 320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in thedata center 100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable enters the connector mechanism. Subsequently, the optical fiber inside the cable enters a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism. - The
illustrative rack 240 also includes afan array 370 coupled to the cross-support arms of therack 240. Thefan array 370 includes one or more rows of coolingfans 372, which are aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, thefan array 370 includes a row of coolingfans 372 for eachsled slot 320 of therack 240. As discussed above, eachsled 400 does not include any on-board cooling system in the illustrative embodiment and, as such, thefan array 370 provides cooling for eachsled 400 received in therack 240. Eachrack 240, in the illustrative embodiment, also includes a power supply associated with eachsled slot 320. Each power supply is secured to one of theelongated support arms 312 of thepair 310 ofelongated support arms 312 that define thecorresponding sled slot 320. For example, therack 240 may include a power supply coupled or secured to eachelongated support arm 312 extending from theelongated support post 302. Each power supply includes a power connector configured to mate with a power connector of thesled 400 when thesled 400 is received in thecorresponding sled slot 320. In the illustrative embodiment, thesled 400 does not include any on-board power supply and, as such, the power supplies provided in therack 240 supply power to correspondingsleds 400 when mounted to therack 240. - Referring now to
FIG. 6 , thesled 400, in the illustrative embodiment, is configured to be mounted in acorresponding rack 240 of thedata center 100 as discussed above. In some embodiments, eachsled 400 may be optimized or otherwise configured for performing particular tasks, such as compute tasks, acceleration tasks, data storage tasks, etc. For example, thesled 400 may be embodied as acompute sled 800 as discussed below in regard toFIGS. 8-9 , anaccelerator sled 1000 as discussed below in regard toFIGS. 10-11 , astorage sled 1200 as discussed below in regard toFIGS. 12-13 , or as a sled optimized or otherwise configured to perform other specialized tasks, such as amemory sled 1400, discussed below in regard toFIG. 14 . - As discussed above, the
illustrative sled 400 includes a chassis-lesscircuit board substrate 602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that thecircuit board substrate 602 is “chassis-less” in that thesled 400 does not include a housing or enclosure. Rather, the chassis-lesscircuit board substrate 602 is open to the local environment. The chassis-lesscircuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-lesscircuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-lesscircuit board substrate 602 in other embodiments. - As discussed in more detail below, the chassis-less
circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-lesscircuit board substrate 602. As discussed, the chassis-lesscircuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of thesled 400 by reducing those structures that may inhibit air flow. For example, because the chassis-lesscircuit board substrate 602 is not positioned in an individual housing or enclosure, there is no backplane (e.g., a backplate of the chassis) to the chassis-lesscircuit board substrate 602, which could inhibit air flow across the electrical components. Additionally, the chassis-lesscircuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-lesscircuit board substrate 602. For example, the illustrative chassis-lesscircuit board substrate 602 has awidth 604 that is greater than adepth 606 of the chassis-lesscircuit board substrate 602. In one particular embodiment, for example, the chassis-lesscircuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, anairflow path 608 that extends from afront edge 610 of the chassis-lesscircuit board substrate 602 toward arear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of thesled 400. Furthermore, although not illustrated inFIG. 6 , the various physical resources mounted to the chassis-lesscircuit board substrate 602 are mounted in corresponding locations such that no two substantively heat-producing electrical components shadow each other as discussed in more detail below. That is, no two electrical components, which produce appreciable heat during operation (i.e., greater than a nominal heat sufficient enough to adversely impact the cooling of another electrical component), are mounted to the chassis-lesscircuit board substrate 602 linearly in-line with each other along the direction of the airflow path 608 (i.e., along a direction extending from thefront edge 610 toward therear edge 612 of the chassis-less circuit board substrate 602). - As discussed above, the
illustrative sled 400 includes one or morephysical resources 620 mounted to atop side 650 of the chassis-lesscircuit board substrate 602. Although twophysical resources 620 are shown inFIG. 6 , it should be appreciated that thesled 400 may include one, two, or morephysical resources 620 in other embodiments. Thephysical resources 620 may be embodied as any type of processor, controller, or other compute circuit capable of performing various tasks such as compute functions and/or controlling the functions of thesled 400 depending on, for example, the type or intended functionality of thesled 400. For example, as discussed in more detail below, thephysical resources 620 may be embodied as high-performance processors in embodiments in which thesled 400 is embodied as a compute sled, as accelerator co-processors or circuits in embodiments in which thesled 400 is embodied as an accelerator sled, storage controllers in embodiments in which thesled 400 is embodied as a storage sled, or a set of memory devices in embodiments in which thesled 400 is embodied as a memory sled. - The
sled 400 also includes one or more additionalphysical resources 630 mounted to thetop side 650 of the chassis-lesscircuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of thesled 400, thephysical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments. - The
physical resources 620 are communicatively coupled to thephysical resources 630 via an input/output (I/O)subsystem 622. The I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with thephysical resources 620, thephysical resources 630, and/or other components of thesled 400. For example, the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDRS data bus. - In some embodiments, the
sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications. - The
sled 400 also includes apower connector 640 configured to mate with a corresponding power connector of therack 240 when thesled 400 is mounted in thecorresponding rack 240. Thesled 400 receives power from a power supply of therack 240 via thepower connector 640 to supply power to the various electrical components of thesled 400. That is, thesled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of thesled 400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-lesscircuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-lesscircuit board substrate 602 as discussed above. In some embodiments, power is provided to theprocessors 820 through vias directly under the processors 820 (e.g., through thebottom side 750 of the chassis-less circuit board substrate 602), providing an increased thermal budget, additional current and/or voltage, and better voltage control over typical boards. - In some embodiments, the
sled 400 may also include mountingfeatures 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in arack 240 by the robot. The mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp thesled 400 without damaging the chassis-lesscircuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads attached to the chassis-lesscircuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-lesscircuit board substrate 602. The particular number, shape, size, and/or make-up of the mountingfeature 642 may depend on the design of the robot configured to manage thesled 400. - Referring now to
FIG. 7 , in addition to thephysical resources 630 mounted on thetop side 650 of the chassis-lesscircuit board substrate 602, thesled 400 also includes one ormore memory devices 720 mounted to abottom side 750 of the chassis-lesscircuit board substrate 602. That is, the chassis-lesscircuit board substrate 602 is embodied as a double-sided circuit board. Thephysical resources 620 are communicatively coupled to thememory devices 720 via the I/O subsystem 622. For example, thephysical resources 620 and thememory devices 720 may be communicatively coupled by one or more vias extending through the chassis-lesscircuit board substrate 602. Eachphysical resource 620 may be communicatively coupled to a different set of one ormore memory devices 720 in some embodiments. Alternatively, in other embodiments, eachphysical resource 620 may be communicatively coupled to eachmemory devices 720. - The
memory devices 720 may be embodied as any type of memory device capable of storing data for thephysical resources 620 during operation of thesled 400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces. - In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
- Referring now to
FIG. 8 , in some embodiments, thesled 400 may be embodied as acompute sled 800. Thecompute sled 800 is optimized, or otherwise configured, to perform compute tasks. Of course, as discussed above, thecompute sled 800 may rely on other sleds, such as acceleration sleds and/or storage sleds, to perform such compute tasks. Thecompute sled 800 includes various physical resources (e.g., electrical components) similar to the physical resources of thesled 400, which have been identified inFIG. 8 using the same reference numbers. The description of such components provided above in regard toFIGS. 6 and 7 applies to the corresponding components of thecompute sled 800 and is not repeated herein for clarity of the description of thecompute sled 800. - In the
illustrative compute sled 800, thephysical resources 620 are embodied asprocessors 820. Although only twoprocessors 820 are shown inFIG. 8 , it should be appreciated that thecompute sled 800 may includeadditional processors 820 in other embodiments. Illustratively, theprocessors 820 are embodied as high-performance processors 820 and may be configured to operate at a relatively high power rating. Although theprocessors 820 generate additional heat operating at power ratings greater than typical processors (which operate at around 155-230 W), the enhanced thermal cooling characteristics of the chassis-lesscircuit board substrate 602 discussed above facilitate the higher power operation. For example, in the illustrative embodiment, theprocessors 820 are configured to operate at a power rating of at least 250 W. In some embodiments, theprocessors 820 may be configured to operate at a power rating of at least 350 W. - In some embodiments, the
compute sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of thesled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. - The
compute sled 800 also includes acommunication circuit 830. Theillustrative communication circuit 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). TheNIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, other devices that may be used by thecompute sled 800 to connect with another compute device (e.g., with other sleds 400). In some embodiments, theNIC 832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, theNIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to theNIC 832. In such embodiments, the local processor of theNIC 832 may be capable of performing one or more of the functions of theprocessors 820. Additionally or alternatively, in such embodiments, the local memory of theNIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels. - The
communication circuit 830 is communicatively coupled to anoptical data connector 834. Theoptical data connector 834 is configured to mate with a corresponding optical data connector of therack 240 when thecompute sled 800 is mounted in therack 240. Illustratively, theoptical data connector 834 includes a plurality of optical fibers which lead from a mating surface of theoptical data connector 834 to anoptical transceiver 836. Theoptical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of theoptical data connector 834 in the illustrative embodiment, theoptical transceiver 836 may form a portion of thecommunication circuit 830 in other embodiments. - In some embodiments, the
compute sled 800 may also include anexpansion connector 840. In such embodiments, theexpansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to thecompute sled 800. The additional physical resources may be used, for example, by theprocessors 820 during operation of thecompute sled 800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-lesscircuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits. - Referring now to
FIG. 9 , an illustrative embodiment of thecompute sled 800 is shown. As shown, theprocessors 820,communication circuit 830, andoptical data connector 834 are mounted to thetop side 650 of the chassis-lesscircuit board substrate 602. Any suitable attachment or mounting technology may be used to mount the physical resources of thecompute sled 800 to the chassis-lesscircuit board substrate 602. For example, the various physical resources may be mounted in corresponding sockets (e.g., a processor socket), holders, or brackets. In some cases, some of the electrical components may be directly mounted to the chassis-lesscircuit board substrate 602 via soldering or similar techniques. - As discussed above, the
individual processors 820 andcommunication circuit 830 are mounted to thetop side 650 of the chassis-lesscircuit board substrate 602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, theprocessors 820 andcommunication circuit 830 are mounted in corresponding locations on thetop side 650 of the chassis-lesscircuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of theairflow path 608. It should be appreciated that, although theoptical data connector 834 is in-line with thecommunication circuit 830, theoptical data connector 834 produces no or nominal heat during operation. - The
memory devices 720 of thecompute sled 800 are mounted to thebottom side 750 of the of the chassis-lesscircuit board substrate 602 as discussed above in regard to thesled 400. Although mounted to thebottom side 750, thememory devices 720 are communicatively coupled to theprocessors 820 located on thetop side 650 via the I/O subsystem 622. Because the chassis-lesscircuit board substrate 602 is embodied as a double-sided circuit board, thememory devices 720 and theprocessors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-lesscircuit board substrate 602. Of course, eachprocessor 820 may be communicatively coupled to a different set of one ormore memory devices 720 in some embodiments. Alternatively, in other embodiments, eachprocessor 820 may be communicatively coupled to eachmemory device 720. In some embodiments, thememory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-lesscircuit board substrate 602 and may interconnect with acorresponding processor 820 through a ball-grid array. - Each of the
processors 820 includes aheatsink 850 secured thereto. Due to the mounting of thememory devices 720 to thebottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of thesleds 400 in the corresponding rack 240), thetop side 650 of the chassis-lesscircuit board substrate 602 includes additional “free” area or space that facilitates the use ofheatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-lesscircuit board substrate 602, none of theprocessor heatsinks 850 include cooling fans attached thereto. That is, each of theheatsinks 850 is embodied as a fan-less heatsinks. - Referring now to
FIG. 10 , in some embodiments, thesled 400 may be embodied as anaccelerator sled 1000. Theaccelerator sled 1000 is optimized, or otherwise configured, to perform specialized compute tasks, such as machine learning, encryption, hashing, or other computational-intensive task. In some embodiments, for example, acompute sled 800 may offload tasks to theaccelerator sled 1000 during operation. Theaccelerator sled 1000 includes various components similar to components of thesled 400 and/or computesled 800, which have been identified inFIG. 10 using the same reference numbers. The description of such components provided above in regard toFIGS. 6, 7, and 8 apply to the corresponding components of theaccelerator sled 1000 and is not repeated herein for clarity of the description of theaccelerator sled 1000. - In the
illustrative accelerator sled 1000, thephysical resources 620 are embodied asaccelerator circuits 1020. Although only twoaccelerator circuits 1020 are shown inFIG. 10 , it should be appreciated that theaccelerator sled 1000 may includeadditional accelerator circuits 1020 in other embodiments. For example, as shown inFIG. 11 , theaccelerator sled 1000 may include fouraccelerator circuits 1020 in some embodiments. Theaccelerator circuits 1020 may be embodied as any type of processor, co-processor, compute circuit, or other device capable of performing compute or processing operations. For example, theaccelerator circuits 1020 may be embodied as, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits. - In some embodiments, the
accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, theaccelerator circuits 1020 may be daisy-chained with aprimary accelerator circuit 1020 connected to theNIC 832 andmemory 720 through the I/O subsystem 622 and asecondary accelerator circuit 1020 connected to theNIC 832 andmemory 720 through aprimary accelerator circuit 1020. - Referring now to
FIG. 11 , an illustrative embodiment of theaccelerator sled 1000 is shown. As discussed above, theaccelerator circuits 1020,communication circuit 830, andoptical data connector 834 are mounted to thetop side 650 of the chassis-lesscircuit board substrate 602. Again, theindividual accelerator circuits 1020 andcommunication circuit 830 are mounted to thetop side 650 of the chassis-lesscircuit board substrate 602 such that no two heat-producing, electrical components shadow each other as discussed above. Thememory devices 720 of theaccelerator sled 1000 are mounted to thebottom side 750 of the of the chassis-lesscircuit board substrate 602 as discussed above in regard to the sled 600. Although mounted to thebottom side 750, thememory devices 720 are communicatively coupled to theaccelerator circuits 1020 located on thetop side 650 via the I/O subsystem 622 (e.g., through vias). Further, each of theaccelerator circuits 1020 may include a heatsink 1070 that is larger than a traditional heatsink used in a server. As discussed above with reference to the heatsinks 870, the heatsinks 1070 may be larger than tradition heatsinks because of the “free” area provided by thememory devices 750 being located on thebottom side 750 of the chassis-lesscircuit board substrate 602 rather than on thetop side 650. - Referring now to
FIG. 12 , in some embodiments, thesled 400 may be embodied as astorage sled 1200. Thestorage sled 1200 is optimized, or otherwise configured, to store data in adata storage 1250 local to thestorage sled 1200. For example, during operation, acompute sled 800 or anaccelerator sled 1000 may store and retrieve data from thedata storage 1250 of thestorage sled 1200. Thestorage sled 1200 includes various components similar to components of thesled 400 and/or thecompute sled 800, which have been identified inFIG. 12 using the same reference numbers. The description of such components provided above in regard toFIGS. 6, 7 , and 8 apply to the corresponding components of thestorage sled 1200 and is not repeated herein for clarity of the description of thestorage sled 1200. - In the
illustrative storage sled 1200, thephysical resources 620 are embodied asstorage controllers 1220. Although only twostorage controllers 1220 are shown inFIG. 12 , it should be appreciated that thestorage sled 1200 may includeadditional storage controllers 1220 in other embodiments. Thestorage controllers 1220 may be embodied as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into thedata storage 1250 based on requests received via thecommunication circuit 830. In the illustrative embodiment, thestorage controllers 1220 are embodied as relatively low-power processors or controllers. For example, in some embodiments, thestorage controllers 1220 may be configured to operate at a power rating of about 75 watts. - In some embodiments, the
storage sled 1200 may also include a controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of thesled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. - Referring now to
FIG. 13 , an illustrative embodiment of thestorage sled 1200 is shown. In the illustrative embodiment, thedata storage 1250 is embodied as, or otherwise includes, astorage cage 1252 configured to house one or more solid state drives (SSDs) 1254. To do so, thestorage cage 1252 includes a number of mountingslots 1256, each of which is configured to receive a correspondingsolid state drive 1254. Each of the mountingslots 1256 includes a number of drive guides 1258 that cooperate to define anaccess opening 1260 of thecorresponding mounting slot 1256. Thestorage cage 1252 is secured to the chassis-lesscircuit board substrate 602 such that the access openings face away from (i.e., toward the front of) the chassis-lesscircuit board substrate 602. As such, solid state drives 1254 are accessible while thestorage sled 1200 is mounted in a corresponding rack 204. For example, asolid state drive 1254 may be swapped out of a rack 240 (e.g., via a robot) while thestorage sled 1200 remains mounted in thecorresponding rack 240. - The
storage cage 1252 illustratively includes sixteen mountingslots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, thestorage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in thestorage cage 1252, but may be mounted in thestorage cage 1252 in a different orientation in other embodiments. Eachsolid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above. - As shown in
FIG. 13 , thestorage controllers 1220, thecommunication circuit 830, and theoptical data connector 834 are illustratively mounted to thetop side 650 of the chassis-lesscircuit board substrate 602. Again, as discussed above, any suitable attachment or mounting technology may be used to mount the electrical components of thestorage sled 1200 to the chassis-lesscircuit board substrate 602 including, for example, sockets (e.g., a processor socket), holders, brackets, soldered connections, and/or other mounting or securing techniques. - As discussed above, the
individual storage controllers 1220 and thecommunication circuit 830 are mounted to thetop side 650 of the chassis-lesscircuit board substrate 602 such that no two heat-producing, electrical components shadow each other. For example, thestorage controllers 1220 and thecommunication circuit 830 are mounted in corresponding locations on thetop side 650 of the chassis-lesscircuit board substrate 602 such that no two of those electrical components are linearly in-line with other along the direction of theairflow path 608. - The
memory devices 720 of thestorage sled 1200 are mounted to thebottom side 750 of the of the chassis-lesscircuit board substrate 602 as discussed above in regard to thesled 400. Although mounted to thebottom side 750, thememory devices 720 are communicatively coupled to thestorage controllers 1220 located on thetop side 650 via the I/O subsystem 622. Again, because the chassis-lesscircuit board substrate 602 is embodied as a double-sided circuit board, thememory devices 720 and thestorage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-lesscircuit board substrate 602. Each of thestorage controllers 1220 includes a heatsink 1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-lesscircuit board substrate 602 of thestorage sled 1200, none of the heatsinks 1270 include cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink. - Referring now to
FIG. 14 , in some embodiments, thesled 400 may be embodied as amemory sled 1400. Thestorage sled 1400 is optimized, or otherwise configured, to provide other sleds 400 (e.g., compute sleds 800, accelerator sleds 1000, etc.) with access to a pool of memory (e.g., in two ormore sets memory sled 1200. For example, during operation, acompute sled 800 or anaccelerator sled 1000 may remotely write to and/or read from one or more of the memory sets 1430, 1432 of thememory sled 1200 using a logical address space that maps to physical addresses in the memory sets 1430, 1432. Thememory sled 1400 includes various components similar to components of thesled 400 and/or thecompute sled 800, which have been identified inFIG. 14 using the same reference numbers. The description of such components provided above in regard toFIGS. 6, 7, and 8 apply to the corresponding components of thememory sled 1400 and is not repeated herein for clarity of the description of thememory sled 1400. - In the
illustrative memory sled 1400, thephysical resources 620 are embodied asmemory controllers 1420. Although only twomemory controllers 1420 are shown inFIG. 14 , it should be appreciated that thememory sled 1400 may includeadditional memory controllers 1420 in other embodiments. Thememory controllers 1420 may be embodied as any type of processor, controller, or control circuit capable of controlling the writing and reading of data into the memory sets 1430, 1432 based on requests received via thecommunication circuit 830. In the illustrative embodiment, eachstorage controller 1220 is connected to acorresponding memory set memory devices 720 within the correspondingmemory set sled 400 that has sent a request to thememory sled 1400 to perform a memory access operation (e.g., read or write). - In some embodiments, the
memory sled 1400 may also include a controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of thesled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, amemory controller 1420 may access, through the controller-to-controller interconnect 1442, memory that is within the memory set 1432 associated with anothermemory controller 1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, thememory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to thememory set 1430, the next memory address is mapped to thememory set 1432, and the third address is mapped to thememory set 1430, etc.). The interleaving may be managed within thememory controllers 1420, or from CPU sockets (e.g., of the compute sled 800) across network links to the memory sets 1430, 1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device. - Further, in some embodiments, the
memory sled 1400 may be connected to one or more other sleds 400 (e.g., in thesame rack 240 or an adjacent rack 240) through a waveguide, using thewaveguide connector 1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 Ghz or 32 Ghz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430, 1432) to another sled (e.g., asled 400 in thesame rack 240 or anadjacent rack 240 as the memory sled 1400) without adding to the load on theoptical data connector 834. - Referring now to
FIG. 15 , a system for executing one or more workloads (e.g., applications) may be implemented in accordance with thedata center 100. In the illustrative embodiment, thesystem 1510 includes anorchestrator server 1520, which may be embodied as a managed node comprising a compute device (e.g., a compute sled 800) executing management software (e.g., a cloud operating environment, such as OpenStack) that is communicatively coupled tomultiple sleds 400 including a large number of compute sleds 1530 (e.g., each similar to the compute sled 800), memory sleds 1540 (e.g., each similar to the memory sled 1400), accelerator sleds 1550 (e.g., each similar to the memory sled 1000), and storage sleds 1560 (e.g., each similar to the storage sled 1200). One or more of thesleds node 1570, such as by theorchestrator server 1520, to collectively perform a workload (e.g., anapplication 1532 executed in a virtual machine or in a container). The managednode 1570 may be embodied as an assembly ofphysical resources 620, such asprocessors 820,memory resources 720,accelerator circuits 1020, ordata storage 1250, from the same ordifferent sleds 400. Further, the managed node may be established, defined, or “spun up” by theorchestrator server 1520 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. In the illustrative embodiment, theorchestrator server 1520 may selectively allocate and/or deallocatephysical resources 620 from thesleds 400 and/or add or remove one ormore sleds 400 from the managednode 1570 as a function of quality of service (QoS) targets (e.g., performance targets associated with a throughput, latency, instructions per second, etc.) associated with a service level agreement for the workload (e.g., the application 1532). In doing so, theorchestrator server 1520 may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in eachsled 400 of the managednode 1570 and compare the telemetry data to the quality of service targets to determine whether the quality of service targets are being satisfied. If the so, theorchestrator server 1520 may additionally determine whether one or more physical resources may be deallocated from the managednode 1570 while still satisfying the QoS targets, thereby freeing up those physical resources for use in another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not presently satisfied, theorchestrator server 1520 may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application 1532) while the workload is executing - Additionally, in some embodiments, the
orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) and pre-emptively identifying available resources in thedata center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, theorchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in thedata center 100. For example, theorchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, theorchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and thesled 400 on which the resource is located). - In some embodiments, the
orchestrator server 1520 may generate a map of heat generation in thedata center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from thesleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in thedata center 100. Additionally or alternatively, in some embodiments, theorchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within thedata center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. Theorchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in thedata center 100. - To reduce the computational load on the
orchestrator server 1520 and the data transfer load on the network, in some embodiments, theorchestrator server 1520 may send self- test information to thesleds 400 to enable eachsled 400 to locally (e.g., on the sled 400) determine whether telemetry data generated by thesled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Eachsled 400 may then report back a simplified result (e.g., yes or no) to theorchestrator server 1520, which theorchestrator server 1520 may utilize in determining the allocation of resources to managed nodes. - Referring now to
FIG. 16 , asystem 1600 for bandwidth allocation may be implemented in accordance with thedata center 100 described above with reference toFIGS. 1-15 . As shown, thesystem 1600 includes aresource manager server 1602 andmultiple sleds multiple switches resource manager server 1602 and thesleds sled 400 as described above in connection withFIGS. 1-15 or another sled of the data center. - The network elements of the
system 1600 are organized into a network topology. As shown, thesleds switch 1606, which may be embodied as a top-of-rack switch, middle-of-rack switch, end-of-row switch, or other switch device. Similarly, thesleds switch 1608. Theswitches switch 1604, which may be embodied as a data center domain switch or other upstream switch. Theresource manager server 1602 is illustrated as being connected to theupstream switch 1604, however, in other embodiments it may be connected to any other location in the network topology. Thus, as shown inFIG. 16 , theswitches - Additionally, although the
resource manager server 1602 is illustrated as a single server computing device, in some embodiments, theresource manager server 1602 may be embodied as a “virtual server” formed from multiple computing devices distributed across thesystem 1600 and/or operating in a public or private cloud. Accordingly, although theresource manager server 1602 is illustrated inFIG. 16 and described below as embodied as a single server computing device, it should be appreciated that theresource manager server 1602 may be embodied as multiple devices cooperating together to facilitate the functionality described below. - In use, as described further below, the
resource manager server 1602 may discover the network topology of thesystem 1600 and construct a model of resource oversubscription in thesystem 1600. Resource oversubscription may include network uplink oversubscription, storage resource oversubscription, or any other circumstance in which the aggregate bandwidth or other demand generated by the sleds exceeds the available bandwidth or other capacity of thesystem 1600. Theresource manager server 1602 may determine bandwidth limits for each sled or other network element of thesystem 1600 and program those bandwidth limits to the network elements. Each network element enforces the programmed bandwidth limits, which may reduce network congestion. By reducing congestion, thesystem 1600 may eliminate or reduce queuing latency for each layer of switches. For example, bandwidth limits for astorage sled 1610 may ensure that non-volatile memory express (NVMe) over Ethernet data traffic generated by the storage sled 1610 (and other storage sleds) does not exceed available upstream bandwidth. Accordingly, thesystem 1600 may improve network latency and reduce network congestion, without implementing expensive bandwidth reservation mechanisms at the switch level. - Referring now to
FIG. 17 , anillustrative computing device 1700 is shown. Thecomputing device 1700 may be theresource manager server 1602, asled 400, astorage sled accelerator sled 1000, amemory sled 1400, acompute sled FIG. 17 , thecomputing device 1700 illustratively includes aprocessor 1720, an input/output subsystem 1722, amemory 1724, adata storage device 1726, acommunication subsystem 1728, and/or other components and devices commonly found in asled 400, astorage sled accelerator sled 1000, amemory sled 1400, acompute sled computing device 1700 may include other or additional components, such as those commonly found in a server computer (e.g., various input/output devices), in other embodiments. Additionally, in some embodiments, one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component. For example, thememory 1724, or portions thereof, may be incorporated in theprocessor 1720 in some embodiments. - The
processor 1720 may be embodied as any type of processor capable of performing the functions described herein. For example, theprocessor 1720 may be embodied as a single or multi-core processor(s), digital signal processor, microcontroller, or other processor or processing/controlling circuit. Similarly, thememory 1724 may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. In operation, thememory 1724 may store various data and software used during operation of thecomputing device 1700 such operating systems, applications, programs, libraries, and drivers. Thememory 1724 is communicatively coupled to theprocessor 1720 via the I/O subsystem 1722, which may be embodied as circuitry and/or components to facilitate input/output operations with theprocessor 1720, thememory 1724, and other components of thecomputing device 1700. For example, the I/O subsystem 1722 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, sensor hubs, firmware devices, communication links (i.e., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.) and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem 1722 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with theprocessor 1720, thememory 1724, and other components of thecomputing device 1700, on a single integrated circuit chip. - The
data storage device 1726 may be embodied as any type of device or devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, non-volatile flash memory, or other data storage devices. Thecomputing device 1700 may also include acommunications subsystem 1728, which may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications between thecomputing device 1700 and other remote devices over a computer network (not shown). Thecommunications subsystem 1728 may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, InfiniBand®, Bluetooth®, Wi-Fi®, WiMAX, 3G, 4G LTE, etc.) to effect such communication. As shown, thecommunication subsystem 1728 may include a network interface controller (NIC) 1330. - The
illustrative communications subsystem 1728 includes a network interface controller (NIC) 1330. TheNIC 1730 may be embodied as one or more add-in-boards, daughtercards, controller chips, chipsets, circuits, or other devices that may be used by thecomputing device 1700 for network communications with remote devices. For example, theNIC 1730 may be embodied as an expansion card coupled to the I/O subsystem 1722 over an expansion bus such as PCI Express. As another example, in some embodiments theNIC 1730 may be embodied as a network controller, host fabric interface, or other component integrated with the I/O subsystem 1722, theprocessor 1720, an SoC, and/or one or more other components of thecomputing device 1700. - As shown, the
computing device 1700 may also include one or moreperipheral devices 1732. Theperipheral devices 1732 may include any number of additional input/output devices, interface devices, and/or other peripheral devices. For example, in some embodiments, theperipheral devices 1732 may include a display, touch screen, graphics circuitry, keyboard, mouse, speaker system, microphone, network interface, and/or other input/output devices, interface devices, and/or peripheral devices. - Referring now to
FIG. 18 , in an illustrative embodiment, theresource manager server 1602 establishes anenvironment 1800 during operation. Theillustrative environment 1800 includes atopology manager 1802, amodel constructor 1804, abandwidth limit determiner 1806, abandwidth limit programmer 1808, and autilization manager 1810. The various components of theenvironment 1800 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of theenvironment 1800 may be embodied as circuitry or collection of electrical devices (e.g.,topology manager circuitry 1802,model constructor circuitry 1804, bandwidthlimit determiner circuitry 1806, bandwidthlimit programmer circuitry 1808, and/or utilization manager circuitry 1810). It should be appreciated that, in such embodiments, one or more of thetopology manager circuitry 1802, themodel constructor circuitry 1804, the bandwidthlimit determiner circuitry 1806, the bandwidthlimit programmer circuitry 1808, and/or theutilization manager circuitry 1810 may form a portion of theprocessor 1720, the I/O subsystem 1722, theNIC 1730, and/or other components of theresource manager server 1602. Additionally, in some embodiments, one or more of the illustrative components may form a portion of another component and/or one or more of the illustrative components may be independent of one another. - The
topology manager 1802 is configured to discover the topology of the sleds coupled to a layer of switches that are communicatively coupled to theresource manager server 1602. Themodel constructor 1804 is configured to construct a model of network connectivity between the plurality of sleds and the layer of switches based on the topology. Constructing the model may include identifying which sleds of the plurality of sleds are connected to a particular switch of the layer of switches. - The
bandwidth limit determiner 1806 is configured to determine an oversubscription of the network based on the model of network connectivity. The oversubscription is based on an available bandwidth for the layer of switches and a maximum bandwidth of the sleds. Thebandwidth limit determiner 1806 may determine a network uplink oversubscription for the layer of switches or may determine a storage resource oversubscription of the sleds. Thebandwidth limit determiner 1806 is further configured to determine a bandwidth limit for each sled based on the oversubscription. Thebandwidth limit programmer 1808 is configured to program each sled with the corresponding bandwidth limit. Thebandwidth limit programmer 1808 may communicate the bandwidth limit to theNIC 1730 of the corresponding sled. - The
utilization manager 1810 is configured to monitor a bandwidth utilization of the sleds. Monitoring the bandwidth utilization may include receiving telemetry data from the sleds that is indicative of the bandwidth utilized by each sled. Theutilization manager 1810 is further configured to determine whether the network is congested based on the bandwidth utilization of the plurality of sleds. For example, determining whether the network is congested may include determining whether a queue depth of the network exceeds a predetermined queue depth limit for a predetermined amount of time. In some embodiments, determining whether the network is congested may include monitoring bandwidth per class of network traffic, such as NVMe over Ethernet traffic, field-programmable gate array (FPGA) over Ethernet traffic, storage traffic, and/or other traffic classes. Each traffic class may be independently monitored with its own queue depth controls. Further, bandwidth may be limited at the source or target, or in some embodiments based on source and target pair combinations. Theutilization manager 1810 is further configured to modify a bandwidth limit in response to determining that the network is congested. The bandwidth limit may be reduced for each sled that is associated with a high input rate flow. - Referring now to
FIG. 19 , in an illustrative embodiment, astorage sled 1610 establishes anenvironment 1900 during operation. It should be understood that theenvironment 1900 may also be established by other sleds of thesystem 1600. Theillustrative environment 1900 includes abandwidth limit manager 1904, abandwidth programmer 1906, and atelemetry data manager 1908. The various components of theenvironment 1900 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of theenvironment 1900 may be embodied as circuitry or collection of electrical devices (e.g., bandwidthlimit manager circuitry 1904,bandwidth programmer circuitry 1906, and/or telemetry data manager circuitry 1908). It should be appreciated that, in such embodiments, one or more of the bandwidthlimit manager circuitry 1904, thebandwidth programmer circuitry 1906, and/or the telemetrydata manager circuitry 1908 may form a portion of theprocessor 1720, the I/O subsystem 1722, theNIC 1730, and/or other components of thestorage sled 1610. Additionally, in some embodiments, one or more of the illustrative components may form a portion of another component and/or one or more of the illustrative components may be independent of one another. - The
bandwidth programmer 1906 is configured to receive a bandwidth limit for the sled from theresource manager server 1602 and to program the bandwidth limit to theNIC 1730 of the sled. Thebandwidth limit manager 1904 is configured to enforce, by theNIC 1730, the bandwidth limit in response to programming the bandwidth limit. - The
telemetry data manager 1908 is configured to send telemetry data indicative of utilization of theNIC 1730 to theresource manager server 1602. The telemetry data may be sent by theNIC 1730. The telemetry data may indicative of a NIC queue depth and/or or a network stack queue depth. - Referring now to
FIG. 20 , in use, theresource manager server 1602 may execute amethod 2000 for bandwidth allocation. It should be appreciated that, in some embodiments, the operations of themethod 2000 may be performed by one or more components of theenvironment 1800 of theresource manager server 1602 as shown inFIG. 18 . Themethod 2000 begins inblock 2002, in which theresource manager server 1602 discovers the network topology of the components of thesystem 1600. The topology may be predetermined at design time of thesystem 1600 or, in some embodiments, may be discovered using a topology discovery protocol or other discovery technique. In some embodiments, inblock 2004 theresource manager server 1602 may discover sleds, racks, switches, and network connections of thesystem 1600. For example, theresource manager server 1602 may identify that a sled is connected to a particular port of a switch. As another example, theresource manager server 1602 may identify that a port of a switch is connected to a particular port of an upstream switch. - In
block 2006, theresource manager server 1602 constructs a model of network connectivity between the components of thesystem 1600. The model may identify network connections and the associated available bandwidth between sleds, switches, and other network elements of thesystem 1600. - In
block 2008, theresource manager server 1602 determines oversubscription of thesystem 1600 based on the model of network connectivity. As described above, thesystem 1600 may be organized in layers, and each layer may have a maximum amount of available bandwidth or other resources. Oversubscription may exist if the total maximum bandwidth or other resource demand of a layer exceeds the available bandwidth or other resources of a higher layer. In some embodiments, inblock 2010, theresource manager server 1602 may determine network uplink oversubscription. For example, as shown inFIG. 16 , thesleds switch 1606. Oversubscription may exist if the maximum bandwidth used by thesleds switch 1606 to theswitch 1604. Similarly, oversubscription may exist if the maximum bandwidth used by thesleds switch 1608 to theswitch 1604. In some embodiments, in block 2012, theresource manager server 1602 may determine storage resource oversubscription. For example, oversubscription may exist if demand for storage resources of a sled (e.g., the storage sled 1610) exceeds the available bandwidth or other resources of that sled. - In block 2014, the
resource manager server 1602 determines bandwidth limits for each sled in thesystem 1600 based on the oversubscription. The bandwidth limits may be determined in order to prevent or reduce network congestion in thesystem 1600. For example, again referring toFIG. 16 , the bandwidth limits forsleds switch 1606 to theswitch 1604. - In
block 2016, theresource manager server 1602 programs each sled with the corresponding bandwidth limit. After being programmed, each sled enforces the bandwidth limits, as described further below in connection withFIG. 21 . Theresource manager server 1602 may use any technique to program the sled. In some embodiments, inblock 2018 theresource manager server 1602 may program theNIC 1730 of the sled with the bandwidth limit. For example, theresource manager server 1602 may communicate out-of-band or otherwise communicate with theNIC 1730 without invoking the operating system or other software networking stack of the sled. - In block 2020, the
resource manager server 1602 may receive bandwidth telemetry from the sleds of thesystem 1600. The bandwidth telemetry may indicate the current bandwidth usage of the sled and/or whether the associated network connection is congested. For example, the bandwidth telemetry may indicate queue depth of theNIC 1730, the associated switch port, and/or the networking stack of the sled. - In block 2022, the
resource manager server 1602 identifies network congestion based on the telemetry. Theresource manager server 1602 may use any appropriate algorithm to identify dropped packets, increased latency, or otherwise identify the network congestion. In some embodiments, inblock 2024, theresource manager server 1602 may determine whether any queue depth in the system exceeds a predetermined threshold queue depth for longer than a predetermined time. For example, theresource manager server 1602 may analyze the queue depth of aNIC 1730, a switch port, and/or a networking stack of a sled. Inblock 2026, theresource manager server 1602 determines whether congestion has been detected. If not, themethod 2000 loops back to block 2020 to continue monitoring network utilization. If congestion is detected, themethod 2000 advances to block 2028. - In
block 2028, theresource manager server 1602 modifies one or more bandwidth limits to reduce or eliminate the congestion. In some embodiments, in block 2030, theresource manager server 1602 may identify one or more high-input rate flows in thesystem 1600. For example, one ormore storage sleds 1610 generating NVMe over Ethernet data may generate high-input rate flows. Theresource manager server 1602 may reduce the input rate bandwidth limit associated with the high-input rate flows. Additionally or alternatively, in some embodiments theresource manager server 1602 may generate one or more alerts concerning the congestion, and a network administrator may provide modified bandwidth limits. In some embodiments, alternate network routes may be possible. If alternate routes are possible, based on the congestion telemetry data, different bandwidth limits may be set for different routes to reduce the congestion rate. After modifying the bandwidth limits, themethod 2000 loops back to block 2016 to program the sleds with the modified bandwidth limits and continue monitoring network utilization. - Referring now to
FIG. 21 , in use, astorage sled 1610 may execute amethod 2100 for bandwidth allocation. It should be appreciated that, in some embodiments, the operations of themethod 2100 may be performed by one or more components of theenvironment 1900 of thestorage sled 1610 as shown inFIG. 19 . Themethod 2100 begins inblock 2102, in which thestorage sled 1610 determines whether an update to a bandwidth limit has been received from theresource manager server 1602. As described above in connection withFIG. 20 , theresource manager server 1602 may program the bandwidth limit to thestorage sled 1610 in response to modeling network connectivity and determining an oversubscription of thesystem 1600 and/or in response to detecting network congestion based on telemetry data. If an update to the bandwidth limit has not been received, themethod 2100 branches ahead to block 2108, described below. If an update to the bandwidth limit has been received, themethod 2100 advances to block 2104. - In
block 2104, thestorage sled 1610 programs one or more network interface controllers (NICs) 1330 of the storage sled with the new bandwidth limit. After being programmed, theNIC 1730 may throttle or otherwise limit bandwidth used by thestorage sled 1610 to below the bandwidth limit. In particular, in some embodiments inblock 2106 thestorage sled 1610 may set a maximum input bandwidth for theNIC 1730. Thus, the bandwidth limits may limit the amount of data (e.g., NVMe over Ethernet data) generated by thestorage sled 1610 and submitted to theswitch 1606. Although illustrated as being enforced by theNIC 1730, it should be understood that in some embodiments, the bandwidth limits may be enforced by other components of thestorage sled 1610, such as an operating system, software networking stack, NVMe over Ethernet subsystem, or other component. - In
block 2108, thestorage sled 1610 determines whether to send telemetry data to theresource manager server 1602. For example, thestorage sled 1610 may be configured by an administrator to send telemetry data. In some embodiments, thestorage sled 1610 may send telemetry data in response to certain events, for example in response to detected network congestion. If thestorage sled 1610 determines not to send telemetry data, themethod 2100 loops back to block 2102 to continue monitoring for updated bandwidth limits. If thestorage sled 1610 determines to send telemetry data, themethod 2100 advances to block 2110. - In block 2110, the
storage sled 1610 sends bandwidth telemetry data to theresource manager server 1602. As described above, the bandwidth telemetry may indicate the current bandwidth usage of the sled and/or whether the associated network connection is congested. For example, the bandwidth telemetry may indicate queue depth of theNIC 1730, the associated switch port, and/or the network stack of the sled. In some embodiments, inblock 2112 thestorage sled 1610 may retrieve the telemetry data from theNIC 1730 of thestorage sled 1610. For example, an operating system, software networking stack, or other component of thestorage sled 1610 may retrieve telemetry data from theNIC 1730. In some embodiments, inblock 2114 thestorage sled 1610 may send the telemetry data from theNIC 1730 to theresource manager server 1602. TheNIC 1730 may send the telemetry data out-of-band or otherwise without the involvement of the operating system, software networking stack, or other components of thestorage sled 1610. After sending the telemetry data, themethod 2100 loops back to block 2102 to continue monitoring for updated bandwidth limits. - Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
- Example 1 includes a resource manager server for bandwidth allocation, the resource manager server comprising: one or more processors; and one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the resource manager server to: discover a topology of a plurality of sleds coupled to a layer of switches that are communicatively coupled to the resource manager server; construct a model of network connectivity between the plurality of sleds and the layer of switches based on the topology; determine an oversubscription of a network based on the model of network connectivity, wherein the oversubscription is based on an available bandwidth for the layer of switches and a maximum bandwidth of the plurality of sleds; determine a bandwidth limit for each sled of the plurality of sleds based on the oversubscription; and program each sled of the plurality of sleds with the corresponding bandwidth limit.
- Example 2 includes the subject matter of Example 1, and wherein to construct the model of network connectivity comprises to identify which sleds of the plurality of sleds are connected to a particular switch of the layer of switches.
- Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to determine the oversubscription comprises to determine a network uplink oversubscription for the layer of switches.
- Example 4 includes the subject matter of any of Examples 1-3, and wherein to determine the oversubscription comprises to determine a storage resource oversubscription of the plurality of sleds.
- Example 5 includes the subject matter of any of Examples 1-4, and wherein to program the bandwidth limit for each sled comprises to communicate the bandwidth limit to a network interface controller of the corresponding sled.
- Example 6 includes the subject matter of any of Examples 1-5, and wherein the one or more memory devices have stored therein a plurality of instructions that, when executed by the one or more processors, further cause the resource manager server to: monitor a bandwidth utilization of the plurality of sleds; determine whether the network is congested based on the bandwidth utilization of the plurality of sleds; and modify a bandwidth limit in response to a determination that the network is congested.
- Example 7 includes the subject matter of any of Examples 1-6, and wherein to monitor the bandwidth utilization of the plurality of sleds comprises to receive telemetry data from the plurality of sleds indicative of the bandwidth utilized by each sled.
- Example 8 includes the subject matter of any of Examples 1-7, and wherein to determine whether the network is congested comprises to determine whether a queue depth of the network exceeds a predetermined queue depth limit for a predetermined amount of time.
- Example 9 includes the subject matter of any of Examples 1-8, and wherein the queue depth comprises a switch port queue depth, a network interface controller queue depth, or a network stack queue depth.
- Example 10 includes the subject matter of any of Examples 1-9, and wherein to modify the bandwidth limit comprises to: identify a first sled of the plurality of sleds associated with a high input rate flow; and reduce an input rate of the bandwidth limit for the first sled.
- Example 11 includes a sled for bandwidth allocation, the sled communicatively coupled to a layer of switches that are communicatively coupled to a resource manager server on a network, the sled comprising: one or more processors; and one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the sled to: receive a bandwidth limit for the sled from the resource manager server; program the bandwidth limit to a network interface controller of the sled; and enforce, by the network interface controller, the bandwidth limit in response to programming of the bandwidth limit.
- Example 12 includes the subject matter of Example 11, and wherein the one or more memory devices have stored therein a plurality of instructions that, when executed by the one or more processors, further cause the sled to send telemetry data indicative of a utilization of the network interface controller to the resource manager server of the network.
- Example 13 includes the subject matter of any of Examples 11 and 12, and wherein to send the telemetry data comprises to send the telemetry data by the network interface controller.
- Example 14 includes the subject matter of any of Examples 11-13, and wherein the telemetry data is indicative of a network interface controller queue depth, or a network stack queue depth.
- Example 15 includes a method for bandwidth allocation, the method comprising: discovering, by a resource manager server of a network, a topology of a plurality of sleds coupled to a layer of switches that are communicatively coupled to the resource manager server; constructing, by the resource manager server, a model of network connectivity between the plurality of sleds and the layer of switches based on the topology; determining, by the resource manager server, an oversubscription of the network based on the model of network connectivity, wherein the oversubscription is based on an available bandwidth for the layer of switches and a maximum bandwidth of the plurality of sleds; determining, by the resource manager server, a bandwidth limit for each sled of the plurality of sleds based on the oversubscription; and programming, by the resource manager server, each sled of the plurality of sleds with the corresponding bandwidth limit.
- Example 16 includes the subject matter of Example 15, and wherein constructing the model of network connectivity comprises identifying which sleds of the plurality of sleds are connected to a particular switch of the layer of switches.
- Example 17 includes the subject matter of any of Examples 15 and 16, and wherein determining the oversubscription comprises determining a network uplink oversubscription for the layer of switches.
- Example 18 includes the subject matter of any of Examples 15-17, and wherein determining the oversubscription comprises determining a storage resource oversubscription of the plurality of sleds.
- Example 19 includes the subject matter of any of Examples 15-18, and wherein programming the bandwidth limit for each sled comprises communicating the bandwidth limit to a network interface controller of the corresponding sled.
- Example 20 includes the subject matter of any of Examples 15-19, and further comprising: monitoring, by the resource manager server, a bandwidth utilization of the plurality of sleds; determining, by the resource manager server, whether the network is congested based on the bandwidth utilization of the plurality of sleds; and modifying, by the resource manager server, a bandwidth limit in response to determining that the network is congested.
- Example 21 includes the subject matter of any of Examples 15-20, and wherein monitoring the bandwidth utilization of the plurality of sleds comprises receiving telemetry data from the plurality of sleds indicative of the bandwidth utilized by each sled.
- Example 22 includes the subject matter of any of Examples 15-21, and wherein determining whether the network is congested comprises determining whether a queue depth of the network exceeds a predetermined queue depth limit for a predetermined amount of time.
- Example 23 includes the subject matter of any of Examples 15-22, and wherein the queue depth comprises a switch port queue depth, a network interface controller queue depth, or a network stack queue depth.
- Example 24 includes the subject matter of any of Examples 15-23, and wherein modifying the bandwidth limit comprises: identifying a first sled of the plurality of sleds associated with a high input rate flow; and reducing an input rate of the bandwidth limit for the first sled.
- Example 25 includes a method for bandwidth allocation, the method comprising: receiving, by a sled of a plurality of sleds communicatively coupled to a layer of switches that are communicatively coupled to a resource manager server in a network, a bandwidth limit for the sled from the resource manager server; programming, by the sled, the bandwidth limit to a network interface controller of the sled; and enforcing, by the network interface controller of the sled, the bandwidth limit in response to programming the bandwidth limit.
- Example 26 includes the subject matter of Example 25, and further comprising sending, by the sled, telemetry data indicative of a utilization of the network interface controller to the resource manager server of the network.
- Example 27 includes the subject matter of any of Examples 25 and 26, and wherein sending the telemetry data comprises sending the telemetry data by the network interface controller.
- Example 28 includes the subject matter of any of Examples 25-27, and wherein the telemetry data is indicative of a network interface controller queue depth, or a network stack queue depth.
- Example 29 includes a computing device comprising: a processor; and a memory having stored therein a plurality of instructions that when executed by the processor cause the computing device to perform the method of any of Examples 15-28.
- Example 30 includes one or more non-transitory, computer readable storage media comprising a plurality of instructions stored thereon that in response to being executed result in a computing device performing the method of any of Examples 15-28.
- Example 31 includes a computing device comprising means for performing the method of any of Examples 15-28.
- Example 32 includes a resource manager server for bandwidth allocation, the resource manager server comprising: topology manager circuitry to discover a topology of a plurality of sleds coupled to a layer of switches that are communicatively coupled to the resource manager server; model constructer circuitry to construct a model of network connectivity between the plurality of sleds and the layer of switches based on the topology; bandwidth limit determiner circuitry to (i) determine an oversubscription of a network based on the model of network connectivity, wherein the oversubscription is based on an available bandwidth for the layer of switches and a maximum bandwidth of the plurality of sleds, and (ii) determine a bandwidth limit for each sled of the plurality of sleds based on the oversubscription; and bandwidth limit programmer circuitry to program each sled of the plurality of sleds with the corresponding bandwidth limit.
- Example 33 includes the subject matter of Example 32, and wherein to construct the model of network connectivity comprises to identify which sleds of the plurality of sleds are connected to a particular switch of the layer of switches.
- Example 34 includes the subject matter of any of Examples 32 and 33, and wherein to determine the oversubscription comprises to determine a network uplink oversubscription for the layer of switches.
- Example 35 includes the subject matter of any of Examples 32-34, and wherein to determine the oversubscription comprises to determine a storage resource oversubscription of the plurality of sleds.
- Example 36 includes the subject matter of any of Examples 32-35, and wherein to program the bandwidth limit for each sled comprises to communicate the bandwidth limit to a network interface controller of the corresponding sled.
- Example 37 includes the subject matter of any of Examples 32-36, and further comprising utilization manager circuitry to: monitor a bandwidth utilization of the plurality of sleds; determine whether the network is congested based on the bandwidth utilization of the plurality of sleds; and modify a bandwidth limit in response to a determination that the network is congested.
- Example 38 includes the subject matter of any of Examples 32-37, and wherein to monitor the bandwidth utilization of the plurality of sleds comprises to receive telemetry data from the plurality of sleds indicative of the bandwidth utilized by each sled.
- Example 39 includes the subject matter of any of Examples 32-38, and wherein to determine whether the network is congested comprises to determine whether a queue depth of the network exceeds a predetermined queue depth limit for a predetermined amount of time.
- Example 40 includes the subject matter of any of Examples 32-39, and wherein the queue depth comprises a switch port queue depth, a network interface controller queue depth, or a network stack queue depth.
- Example 41 includes the subject matter of any of Examples 32-40, and wherein to modify the bandwidth limit comprises to: identify a first sled of the plurality of sleds associated with a high input rate flow; and reduce an input rate of the bandwidth limit for the first sled.
- Example 42 includes a sled for bandwidth allocation, the sled communicatively coupled to a layer of switches that communicatively coupled to a resource manager server on a network, the sled comprising: bandwidth programmer circuitry to: (i) receive a bandwidth limit for the sled from the resource manager server, and (ii) program the bandwidth limit to a network interface controller of the sled; and bandwidth limit manager circuitry to enforce, by the network interface controller, the bandwidth limit in response to programming of the bandwidth limit.
- Example 43 includes the subject matter of Example 42, and further comprising telemetry data manager circuitry to send telemetry data indicative of a utilization of the network interface controller to the resource manager server of the network.
- Example 44 includes the subject matter of any of Examples 42 and 43, and wherein to send the telemetry data comprises to send the telemetry data by the network interface controller.
- Example 45 includes the subject matter of any of Examples 42-44, and wherein the telemetry data is indicative of a network interface controller queue depth, or a network stack queue depth.
- Example 46 includes a resource manager server for bandwidth allocation, the resource manager server comprising: means for discovering a topology of a plurality of sleds coupled to a layer of switches that are communicatively coupled to the resource manager server in a network; means for constructing a model of network connectivity between the plurality of sleds and the layer of switches based on the topology; means for determining an oversubscription of the network based on the model of network connectivity, wherein the oversubscription is based on an available bandwidth for the layer of switches and a maximum bandwidth of the plurality of sleds; means for determining a bandwidth limit for each sled of the plurality of sleds based on the oversubscription; and means for programming each sled of the plurality of sleds with the corresponding bandwidth limit.
- Example 47 includes the subject matter of Example 46, and wherein the means for constructing the model of network connectivity comprises means for identifying which sleds of the plurality of sleds are connected to a particular switch of the layer of switches.
- Example 48 includes the subject matter of any of Examples 46 and 47, and wherein the means for determining the oversubscription comprises means for determining a network uplink oversubscription for the layer of switches.
- Example 49 includes the subject matter of any of Examples 46-48, and wherein the means for determining the oversubscription comprises means for determining a storage resource oversubscription of the plurality of sleds.
- Example 50 includes the subject matter of any of Examples 46-49, and wherein the means for programming the bandwidth limit for each sled comprises circuitry for communicating the bandwidth limit to a network interface controller of the corresponding sled.
- Example 51 includes the subject matter of any of Examples 46-50, and further comprising: means for monitoring a bandwidth utilization of the plurality of sleds; means for determining whether the network is congested based on the bandwidth utilization of the plurality of sleds; and means for modifying a bandwidth limit in response to determining that the network is congested.
- Example 52 includes the subject matter of any of Examples 46-51, and wherein the means for monitoring the bandwidth utilization of the plurality of sleds comprises circuitry for receiving telemetry data from the plurality of sleds indicative of the bandwidth utilized by each sled.
- Example 53 includes the subject matter of any of Examples 46-52, and wherein the means for determining whether the network is congested comprises means for determining whether a queue depth of the network exceeds a predetermined queue depth limit for a predetermined amount of time.
- Example 54 includes the subject matter of any of Examples 46-53, and wherein the queue depth comprises a switch port queue depth, a network interface controller queue depth, or a network stack queue depth.
- Example 55 includes the subject matter of any of Examples 46-54, and wherein the means for modifying the bandwidth limit comprises: means for identifying a first sled of the plurality of sleds associated with a high input rate flow; and means for reducing an input rate of the bandwidth limit for the first sled.
- Example 56 includes a sled for bandwidth allocation, the sled communicatively coupled to a layer of switches that are communicatively coupled to a resource manager server on a network, the sled comprising: circuitry for receiving a bandwidth limit for the sled from the resource manager server; means for programming the bandwidth limit to a network interface controller of the sled; and means for enforcing, by the network interface controller of the sled, the bandwidth limit in response to programming the bandwidth limit.
- Example 57 includes the subject matter of Example 56, and further comprising means for sending telemetry data indicative of a utilization of the network interface controller to the resource manager server of the network.
- Example 58 includes the subject matter of any of Examples 56 and 57, and wherein the means for sending the telemetry data comprises means for sending the telemetry data by the network interface controller.
- Example 59 includes the subject matter of any of Examples 56-58, and wherein the telemetry data is indicative of a network interface controller queue depth, or a network stack queue depth.
Claims (25)
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US16/642,520 Abandoned US20200192710A1 (en) | 2017-08-30 | 2018-08-30 | Technologies for enabling and metering the utilization of features on demand |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190014049A1 (en) * | 2017-07-04 | 2019-01-10 | Vmware, Inc | Network resource management for hyper-converged infrastructures |
US10761726B2 (en) * | 2018-04-16 | 2020-09-01 | VWware, Inc. | Resource fairness control in distributed storage systems using congestion data |
US10785549B2 (en) | 2016-07-22 | 2020-09-22 | Intel Corporation | Technologies for switching network traffic in a data center |
US11122123B1 (en) | 2020-03-09 | 2021-09-14 | International Business Machines Corporation | Method for a network of storage devices |
US11137922B2 (en) | 2016-11-29 | 2021-10-05 | Intel Corporation | Technologies for providing accelerated functions as a service in a disaggregated architecture |
US20220150142A1 (en) * | 2019-03-28 | 2022-05-12 | Omron Corporation | Monitoring system, setting device, and monitoring method |
US20220272862A1 (en) * | 2021-02-19 | 2022-08-25 | CyberSecure IPS, LLC | Intelligent cable patching of racks to facilitate cable installation |
Families Citing this family (121)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9948724B2 (en) * | 2015-09-10 | 2018-04-17 | International Business Machines Corporation | Handling multi-pipe connections |
CN109891908A (en) * | 2016-11-29 | 2019-06-14 | 英特尔公司 | Technology for the interconnection of millimeter wave rack |
US10686895B2 (en) | 2017-01-30 | 2020-06-16 | Centurylink Intellectual Property Llc | Method and system for implementing dual network telemetry application programming interface (API) framework |
US10346315B2 (en) | 2017-05-26 | 2019-07-09 | Oracle International Corporation | Latchless, non-blocking dynamically resizable segmented hash index |
US11119835B2 (en) | 2017-08-30 | 2021-09-14 | Intel Corporation | Technologies for providing efficient reprovisioning in an accelerator device |
US11106427B2 (en) * | 2017-09-29 | 2021-08-31 | Intel Corporation | Memory filtering for disaggregate memory architectures |
US11650598B2 (en) * | 2017-12-30 | 2023-05-16 | Telescent Inc. | Automated physical network management system utilizing high resolution RFID, optical scans and mobile robotic actuator |
US10511690B1 (en) * | 2018-02-20 | 2019-12-17 | Intuit, Inc. | Method and apparatus for predicting experience degradation events in microservice-based applications |
WO2019190449A1 (en) * | 2018-03-26 | 2019-10-03 | Hewlett-Packard Development Company, L.P. | Generation of kernels based on physical states |
US11315013B2 (en) * | 2018-04-23 | 2022-04-26 | EMC IP Holding Company LLC | Implementing parameter server in networking infrastructure for high-performance computing |
US10599553B2 (en) * | 2018-04-27 | 2020-03-24 | International Business Machines Corporation | Managing cloud-based hardware accelerators |
US11221886B2 (en) | 2018-05-17 | 2022-01-11 | International Business Machines Corporation | Optimizing dynamical resource allocations for cache-friendly workloads in disaggregated data centers |
US10893096B2 (en) | 2018-05-17 | 2021-01-12 | International Business Machines Corporation | Optimizing dynamical resource allocations using a data heat map in disaggregated data centers |
US10841367B2 (en) | 2018-05-17 | 2020-11-17 | International Business Machines Corporation | Optimizing dynamical resource allocations for cache-dependent workloads in disaggregated data centers |
US10936374B2 (en) | 2018-05-17 | 2021-03-02 | International Business Machines Corporation | Optimizing dynamic resource allocations for memory-dependent workloads in disaggregated data centers |
US10977085B2 (en) | 2018-05-17 | 2021-04-13 | International Business Machines Corporation | Optimizing dynamical resource allocations in disaggregated data centers |
US10601903B2 (en) | 2018-05-17 | 2020-03-24 | International Business Machines Corporation | Optimizing dynamical resource allocations based on locality of resources in disaggregated data centers |
US11330042B2 (en) * | 2018-05-17 | 2022-05-10 | International Business Machines Corporation | Optimizing dynamic resource allocations for storage-dependent workloads in disaggregated data centers |
US10684887B2 (en) * | 2018-05-25 | 2020-06-16 | Vmware, Inc. | Live migration of a virtualized compute accelerator workload |
US10795713B2 (en) | 2018-05-25 | 2020-10-06 | Vmware, Inc. | Live migration of a virtualized compute accelerator workload |
US11042406B2 (en) | 2018-06-05 | 2021-06-22 | Intel Corporation | Technologies for providing predictive thermal management |
US11431648B2 (en) | 2018-06-11 | 2022-08-30 | Intel Corporation | Technologies for providing adaptive utilization of different interconnects for workloads |
US20190384376A1 (en) * | 2018-06-18 | 2019-12-19 | American Megatrends, Inc. | Intelligent allocation of scalable rack resources |
US11388835B1 (en) * | 2018-06-27 | 2022-07-12 | Amazon Technologies, Inc. | Placement of custom servers |
US11436113B2 (en) * | 2018-06-28 | 2022-09-06 | Twitter, Inc. | Method and system for maintaining storage device failure tolerance in a composable infrastructure |
US10977193B2 (en) | 2018-08-17 | 2021-04-13 | Oracle International Corporation | Remote direct memory operations (RDMOs) for transactional processing systems |
US11347678B2 (en) * | 2018-08-06 | 2022-05-31 | Oracle International Corporation | One-sided reliable remote direct memory operations |
US11188348B2 (en) * | 2018-08-31 | 2021-11-30 | International Business Machines Corporation | Hybrid computing device selection analysis |
US11182322B2 (en) | 2018-09-25 | 2021-11-23 | International Business Machines Corporation | Efficient component communication through resource rewiring in disaggregated datacenters |
US11163713B2 (en) | 2018-09-25 | 2021-11-02 | International Business Machines Corporation | Efficient component communication through protocol switching in disaggregated datacenters |
US11012423B2 (en) | 2018-09-25 | 2021-05-18 | International Business Machines Corporation | Maximizing resource utilization through efficient component communication in disaggregated datacenters |
US11650849B2 (en) * | 2018-09-25 | 2023-05-16 | International Business Machines Corporation | Efficient component communication through accelerator switching in disaggregated datacenters |
US11138044B2 (en) * | 2018-09-26 | 2021-10-05 | Micron Technology, Inc. | Memory pooling between selected memory resources |
US10901893B2 (en) * | 2018-09-28 | 2021-01-26 | International Business Machines Corporation | Memory bandwidth management for performance-sensitive IaaS |
WO2020072819A1 (en) * | 2018-10-03 | 2020-04-09 | Rigetti & Co, Inc. | Parcelled quantum resources |
US10962389B2 (en) * | 2018-10-03 | 2021-03-30 | International Business Machines Corporation | Machine status detection |
US10768990B2 (en) * | 2018-11-01 | 2020-09-08 | International Business Machines Corporation | Protecting an application by autonomously limiting processing to a determined hardware capacity |
US11055186B2 (en) * | 2018-11-27 | 2021-07-06 | Red Hat, Inc. | Managing related devices for virtual machines using robust passthrough device enumeration |
US10831975B2 (en) | 2018-11-29 | 2020-11-10 | International Business Machines Corporation | Debug boundaries in a hardware accelerator |
US10901918B2 (en) * | 2018-11-29 | 2021-01-26 | International Business Machines Corporation | Constructing flexibly-secure systems in a disaggregated environment |
US11275622B2 (en) * | 2018-11-29 | 2022-03-15 | International Business Machines Corporation | Utilizing accelerators to accelerate data analytic workloads in disaggregated systems |
US11048318B2 (en) * | 2018-12-06 | 2021-06-29 | Intel Corporation | Reducing microprocessor power with minimal performance impact by dynamically adapting runtime operating configurations using machine learning |
US10771344B2 (en) * | 2018-12-21 | 2020-09-08 | Servicenow, Inc. | Discovery of hyper-converged infrastructure devices |
US10970107B2 (en) * | 2018-12-21 | 2021-04-06 | Servicenow, Inc. | Discovery of hyper-converged infrastructure |
US11269593B2 (en) * | 2019-01-23 | 2022-03-08 | Sap Se | Global number range generation |
US11271804B2 (en) * | 2019-01-25 | 2022-03-08 | Dell Products L.P. | Hyper-converged infrastructure component expansion/replacement system |
US11429440B2 (en) * | 2019-02-04 | 2022-08-30 | Hewlett Packard Enterprise Development Lp | Intelligent orchestration of disaggregated applications based on class of service |
US10817221B2 (en) * | 2019-02-12 | 2020-10-27 | International Business Machines Corporation | Storage device with mandatory atomic-only access |
US10949101B2 (en) * | 2019-02-25 | 2021-03-16 | Micron Technology, Inc. | Storage device operation orchestration |
US11294992B2 (en) * | 2019-03-12 | 2022-04-05 | Xilinx, Inc. | Locking execution of cores to licensed programmable devices in a data center |
US11443018B2 (en) * | 2019-03-12 | 2022-09-13 | Xilinx, Inc. | Locking execution of cores to licensed programmable devices in a data center |
US11531869B1 (en) * | 2019-03-28 | 2022-12-20 | Xilinx, Inc. | Neural-network pooling |
US11243817B2 (en) * | 2019-03-29 | 2022-02-08 | Intel Corporation | Technologies for data migration between edge accelerators hosted on different edge locations |
US11089137B2 (en) * | 2019-04-02 | 2021-08-10 | International Business Machines Corporation | Dynamic data transmission |
US11055256B2 (en) * | 2019-04-02 | 2021-07-06 | Intel Corporation | Edge component computing system having integrated FaaS call handling capability |
EP3949326A1 (en) | 2019-04-05 | 2022-02-09 | Cisco Technology, Inc. | Discovering trustworthy devices using attestation and mutual attestation |
US11263122B2 (en) * | 2019-04-09 | 2022-03-01 | Vmware, Inc. | Implementing fine grain data coherency of a shared memory region |
US11416294B1 (en) * | 2019-04-17 | 2022-08-16 | Juniper Networks, Inc. | Task processing for management of data center resources |
US11003479B2 (en) * | 2019-04-29 | 2021-05-11 | Intel Corporation | Device, system and method to communicate a kernel binary via a network |
CN110053650B (en) * | 2019-05-06 | 2022-06-07 | 湖南中车时代通信信号有限公司 | Automatic train operation system, automatic train operation system architecture and module management method of automatic train operation system |
CN110203600A (en) * | 2019-06-06 | 2019-09-06 | 北京卫星环境工程研究所 | Suitable for spacecraft material be automatically stored and radio frequency |
US11481117B2 (en) * | 2019-06-17 | 2022-10-25 | Hewlett Packard Enterprise Development Lp | Storage volume clustering based on workload fingerprints |
US10877817B1 (en) * | 2019-06-28 | 2020-12-29 | Intel Corporation | Technologies for providing inter-kernel application programming interfaces for an accelerated architecture |
US10949362B2 (en) * | 2019-06-28 | 2021-03-16 | Intel Corporation | Technologies for facilitating remote memory requests in accelerator devices |
US20200409748A1 (en) * | 2019-06-28 | 2020-12-31 | Intel Corporation | Technologies for managing accelerator resources |
WO2021026094A1 (en) * | 2019-08-02 | 2021-02-11 | Jpmorgan Chase Bank, N.A. | Systems and methods for provisioning a new secondary identityiq instance to an existing identityiq instance |
US11082411B2 (en) * | 2019-08-06 | 2021-08-03 | Advanced New Technologies Co., Ltd. | RDMA-based data transmission method, network interface card, server and medium |
US10925166B1 (en) * | 2019-08-07 | 2021-02-16 | Quanta Computer Inc. | Protection fixture |
EP4019206A4 (en) * | 2019-08-22 | 2022-08-17 | NEC Corporation | Robot control system, robot control method, and recording medium |
US10999403B2 (en) | 2019-09-27 | 2021-05-04 | Red Hat, Inc. | Composable infrastructure provisioning and balancing |
CN110650609B (en) * | 2019-10-10 | 2020-12-01 | 珠海与非科技有限公司 | Cloud server of distributed storage |
CA3151195A1 (en) * | 2019-10-10 | 2021-04-15 | Channel One Holdings Inc. | Methods and systems for time-bounding execution of computing workflows |
US11200046B2 (en) * | 2019-10-22 | 2021-12-14 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Managing composable compute system infrastructure with support for decoupled firmware updates |
DE102020127704A1 (en) | 2019-10-29 | 2021-04-29 | Nvidia Corporation | TECHNIQUES FOR EFFICIENT TRANSFER OF DATA TO A PROCESSOR |
US11803380B2 (en) | 2019-10-29 | 2023-10-31 | Nvidia Corporation | High performance synchronization mechanisms for coordinating operations on a computer system |
CN112749121A (en) * | 2019-10-31 | 2021-05-04 | 中兴通讯股份有限公司 | Multi-chip interconnection system based on PCIE bus |
US11342004B2 (en) * | 2019-11-07 | 2022-05-24 | Quantum Corporation | System and method for rapid replacement of robotic media mover in automated media library |
US10747281B1 (en) * | 2019-11-19 | 2020-08-18 | International Business Machines Corporation | Mobile thermal balancing of data centers |
US11782810B2 (en) * | 2019-11-22 | 2023-10-10 | Dell Products, L.P. | Systems and methods for automated field replacement component configuration |
US11263105B2 (en) * | 2019-11-26 | 2022-03-01 | Lucid Software, Inc. | Visualization tool for components within a cloud infrastructure |
US11861219B2 (en) | 2019-12-12 | 2024-01-02 | Intel Corporation | Buffer to reduce write amplification of misaligned write operations |
US11789878B2 (en) | 2019-12-19 | 2023-10-17 | Intel Corporation | Adaptive fabric allocation for local and remote emerging memories based prediction schemes |
US11321259B2 (en) * | 2020-02-14 | 2022-05-03 | Sony Interactive Entertainment Inc. | Network architecture providing high speed storage access through a PCI express fabric between a compute node and a storage server |
US11636503B2 (en) * | 2020-02-26 | 2023-04-25 | At&T Intellectual Property I, L.P. | System and method for offering network slice as a service |
US11121941B1 (en) | 2020-03-12 | 2021-09-14 | Cisco Technology, Inc. | Monitoring communications to identify performance degradation |
US20210304025A1 (en) * | 2020-03-24 | 2021-09-30 | Facebook, Inc. | Dynamic quality of service management for deep learning training communication |
US11115497B2 (en) * | 2020-03-25 | 2021-09-07 | Intel Corporation | Technologies for providing advanced resource management in a disaggregated environment |
US11630696B2 (en) | 2020-03-30 | 2023-04-18 | International Business Machines Corporation | Messaging for a hardware acceleration system |
US11509079B2 (en) * | 2020-04-06 | 2022-11-22 | Hewlett Packard Enterprise Development Lp | Blind mate connections with different sets of datums |
US11177618B1 (en) * | 2020-05-14 | 2021-11-16 | Dell Products L.P. | Server blind-mate power and signal connector dock |
US11374808B2 (en) * | 2020-05-29 | 2022-06-28 | Corning Research & Development Corporation | Automated logging of patching operations via mixed reality based labeling |
US11295135B2 (en) * | 2020-05-29 | 2022-04-05 | Corning Research & Development Corporation | Asset tracking of communication equipment via mixed reality based labeling |
US11947971B2 (en) * | 2020-06-11 | 2024-04-02 | Hewlett Packard Enterprise Development Lp | Remote resource configuration mechanism |
US11687629B2 (en) * | 2020-06-12 | 2023-06-27 | Baidu Usa Llc | Method for data protection in a data processing cluster with authentication |
US11360789B2 (en) | 2020-07-06 | 2022-06-14 | International Business Machines Corporation | Configuration of hardware devices |
CN111824668B (en) * | 2020-07-08 | 2022-07-19 | 北京极智嘉科技股份有限公司 | Robot and robot-based container storage and retrieval method |
US11681557B2 (en) * | 2020-07-31 | 2023-06-20 | International Business Machines Corporation | Systems and methods for managing resources in a hyperconverged infrastructure cluster |
US20220046292A1 (en) | 2020-08-05 | 2022-02-10 | Avesha, Inc. | Networked system for real-time computer-aided augmentation of live input video stream |
US11314687B2 (en) * | 2020-09-24 | 2022-04-26 | Commvault Systems, Inc. | Container data mover for migrating data between distributed data storage systems integrated with application orchestrators |
US20210011787A1 (en) * | 2020-09-25 | 2021-01-14 | Francesc Guim Bernat | Technologies for scaling inter-kernel technologies for accelerator device kernels |
US11405451B2 (en) * | 2020-09-30 | 2022-08-02 | Jpmorgan Chase Bank, N.A. | Data pipeline architecture |
US11379402B2 (en) | 2020-10-20 | 2022-07-05 | Micron Technology, Inc. | Secondary device detection using a synchronous interface |
US20220129601A1 (en) * | 2020-10-26 | 2022-04-28 | Oracle International Corporation | Techniques for generating a configuration for electrically isolating fault domains in a data center |
US11803493B2 (en) * | 2020-11-30 | 2023-10-31 | Dell Products L.P. | Systems and methods for management controller co-processor host to variable subsystem proxy |
US20210092069A1 (en) * | 2020-12-10 | 2021-03-25 | Intel Corporation | Accelerating multi-node performance of machine learning workloads |
US11948014B2 (en) * | 2020-12-15 | 2024-04-02 | Google Llc | Multi-tenant control plane management on computing platform |
US11662934B2 (en) * | 2020-12-15 | 2023-05-30 | International Business Machines Corporation | Migration of a logical partition between mutually non-coherent host data processing systems |
US11645104B2 (en) * | 2020-12-22 | 2023-05-09 | Reliance Jio Infocomm Usa, Inc. | Intelligent data plane acceleration by offloading to distributed smart network interfaces |
US20210117334A1 (en) * | 2020-12-23 | 2021-04-22 | Intel Corporation | Memory controller to manage quality of service enforcement and migration between local and pooled memory |
US11445028B2 (en) | 2020-12-30 | 2022-09-13 | Dell Products L.P. | System and method for providing secure console access with multiple smart NICs using NC-SL and SPDM |
US11803216B2 (en) | 2021-02-03 | 2023-10-31 | Hewlett Packard Enterprise Development Lp | Contiguous plane infrastructure for computing systems |
US11503743B2 (en) * | 2021-03-12 | 2022-11-15 | Baidu Usa Llc | High availability fluid connector for liquid cooling |
US11470015B1 (en) * | 2021-03-22 | 2022-10-11 | Amazon Technologies, Inc. | Allocating workloads to heterogenous worker fleets |
US20220321403A1 (en) * | 2021-04-02 | 2022-10-06 | Nokia Solutions And Networks Oy | Programmable network segmentation for multi-tenant fpgas in cloud infrastructures |
US20220342688A1 (en) * | 2021-04-26 | 2022-10-27 | Dell Products L.P. | Systems and methods for migration of virtual computing resources using smart network interface controller acceleration |
US11805073B2 (en) | 2021-05-03 | 2023-10-31 | Avesha, Inc. | Controlling placement of workloads of an application within an application environment |
US11714775B2 (en) | 2021-05-10 | 2023-08-01 | Zenlayer Innovation LLC | Peripheral component interconnect (PCI) hosting device |
IT202100017564A1 (en) * | 2021-07-02 | 2023-01-02 | Fastweb S P A | Robotic apparatus to carry out maintenance operations on an electronic component |
US11863385B2 (en) * | 2022-01-21 | 2024-01-02 | International Business Machines Corporation | Optimizing container executions with network-attached hardware components of a composable disaggregated infrastructure |
US11921582B2 (en) | 2022-04-29 | 2024-03-05 | Microsoft Technology Licensing, Llc | Out of band method to change boot firmware configuration |
CN115052055B (en) * | 2022-08-17 | 2022-11-11 | 北京左江科技股份有限公司 | Network message checksum unloading method based on FPGA |
Family Cites Families (192)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2704350B1 (en) * | 1993-04-22 | 1995-06-02 | Bull Sa | Physical structure of a mass memory subsystem. |
JP3320344B2 (en) * | 1997-09-19 | 2002-09-03 | 富士通株式会社 | Cartridge transfer robot for library device and library device |
US6158000A (en) * | 1998-09-18 | 2000-12-05 | Compaq Computer Corporation | Shared memory initialization method for system having multiple processor capability |
US6230265B1 (en) * | 1998-09-30 | 2001-05-08 | International Business Machines Corporation | Method and system for configuring resources in a data processing system utilizing system power control information |
US7287096B2 (en) * | 2001-05-19 | 2007-10-23 | Texas Instruments Incorporated | Method for robust, flexible reconfiguration of transceive parameters for communication systems |
US7536715B2 (en) * | 2001-05-25 | 2009-05-19 | Secure Computing Corporation | Distributed firewall system and method |
US6901580B2 (en) * | 2001-06-22 | 2005-05-31 | Intel Corporation | Configuration parameter sequencing and sequencer |
US7415723B2 (en) * | 2002-06-11 | 2008-08-19 | Pandya Ashish A | Distributed network security system and a hardware processor therefor |
US7408876B1 (en) * | 2002-07-02 | 2008-08-05 | Extreme Networks | Method and apparatus for providing quality of service across a switched backplane between egress queue managers |
US20040073834A1 (en) * | 2002-10-10 | 2004-04-15 | Kermaani Kaamel M. | System and method for expanding the management redundancy of computer systems |
US7386889B2 (en) * | 2002-11-18 | 2008-06-10 | Trusted Network Technologies, Inc. | System and method for intrusion prevention in a communications network |
US7031154B2 (en) * | 2003-04-30 | 2006-04-18 | Hewlett-Packard Development Company, L.P. | Louvered rack |
US7238104B1 (en) * | 2003-05-02 | 2007-07-03 | Foundry Networks, Inc. | System and method for venting air from a computer casing |
US7146511B2 (en) * | 2003-10-07 | 2006-12-05 | Hewlett-Packard Development Company, L.P. | Rack equipment application performance modification system and method |
US20050132084A1 (en) * | 2003-12-10 | 2005-06-16 | Heung-For Cheng | Method and apparatus for providing server local SMBIOS table through out-of-band communication |
US7809836B2 (en) | 2004-04-07 | 2010-10-05 | Intel Corporation | System and method for automating bios firmware image recovery using a non-host processor and platform policy to select a donor system |
US7552217B2 (en) | 2004-04-07 | 2009-06-23 | Intel Corporation | System and method for Automatic firmware image recovery for server management operational code |
US7421535B2 (en) * | 2004-05-10 | 2008-09-02 | International Business Machines Corporation | Method for demoting tracks from cache |
JP4335760B2 (en) * | 2004-07-08 | 2009-09-30 | 富士通株式会社 | Rack mount storage unit and rack mount disk array device |
US7685319B2 (en) * | 2004-09-28 | 2010-03-23 | Cray Canada Corporation | Low latency communication via memory windows |
CN101542453A (en) * | 2005-01-05 | 2009-09-23 | 极端数据公司 | Systems and methods for providing co-processors to computing systems |
US20110016214A1 (en) * | 2009-07-15 | 2011-01-20 | Cluster Resources, Inc. | System and method of brokering cloud computing resources |
US7634584B2 (en) * | 2005-04-27 | 2009-12-15 | Solarflare Communications, Inc. | Packet validation in virtual network interface architecture |
US9135074B2 (en) * | 2005-05-19 | 2015-09-15 | Hewlett-Packard Development Company, L.P. | Evaluating performance of workload manager based on QoS to representative workload and usage efficiency of shared resource for plurality of minCPU and maxCPU allocation values |
US8799980B2 (en) * | 2005-11-16 | 2014-08-05 | Juniper Networks, Inc. | Enforcement of network device configuration policies within a computing environment |
TW200720941A (en) * | 2005-11-18 | 2007-06-01 | Inventec Corp | Host computer memory configuration data remote access method and system |
US7493419B2 (en) * | 2005-12-13 | 2009-02-17 | International Business Machines Corporation | Input/output workload fingerprinting for input/output schedulers |
US8713551B2 (en) * | 2006-01-03 | 2014-04-29 | International Business Machines Corporation | Apparatus, system, and method for non-interruptively updating firmware on a redundant hardware controller |
US20070271560A1 (en) * | 2006-05-18 | 2007-11-22 | Microsoft Corporation | Deploying virtual machine to host based on workload characterizations |
US7472211B2 (en) * | 2006-07-28 | 2008-12-30 | International Business Machines Corporation | Blade server switch module using out-of-band signaling to detect the physical location of an active drive enclosure device |
US8098658B1 (en) * | 2006-08-01 | 2012-01-17 | Hewett-Packard Development Company, L.P. | Power-based networking resource allocation |
US8010565B2 (en) * | 2006-10-16 | 2011-08-30 | Dell Products L.P. | Enterprise rack management method, apparatus and media |
US8068351B2 (en) * | 2006-11-10 | 2011-11-29 | Oracle America, Inc. | Cable management system |
US20090089564A1 (en) * | 2006-12-06 | 2009-04-02 | Brickell Ernie F | Protecting a Branch Instruction from Side Channel Vulnerabilities |
US8112524B2 (en) * | 2007-01-15 | 2012-02-07 | International Business Machines Corporation | Recommending moving resources in a partitioned computer |
US7738900B1 (en) | 2007-02-15 | 2010-06-15 | Nextel Communications Inc. | Systems and methods of group distribution for latency sensitive applications |
US8140719B2 (en) * | 2007-06-21 | 2012-03-20 | Sea Micro, Inc. | Dis-aggregated and distributed data-center architecture using a direct interconnect fabric |
CN101431432A (en) * | 2007-11-06 | 2009-05-13 | 联想(北京)有限公司 | Blade server |
US8078865B2 (en) * | 2007-11-20 | 2011-12-13 | Dell Products L.P. | Systems and methods for configuring out-of-band bios settings |
US8214467B2 (en) * | 2007-12-14 | 2012-07-03 | International Business Machines Corporation | Migrating port-specific operating parameters during blade server failover |
EP2223211A4 (en) * | 2007-12-17 | 2011-08-17 | Nokia Corp | Accessory configuration and management |
US8645965B2 (en) * | 2007-12-31 | 2014-02-04 | Intel Corporation | Supporting metered clients with manycore through time-limited partitioning |
US8225159B1 (en) * | 2008-04-25 | 2012-07-17 | Netapp, Inc. | Method and system for implementing power savings features on storage devices within a storage subsystem |
US8166263B2 (en) * | 2008-07-03 | 2012-04-24 | Commvault Systems, Inc. | Continuous data protection over intermittent connections, such as continuous data backup for laptops or wireless devices |
US20100125695A1 (en) * | 2008-11-15 | 2010-05-20 | Nanostar Corporation | Non-volatile memory storage system |
US20100091458A1 (en) * | 2008-10-15 | 2010-04-15 | Mosier Jr David W | Electronics chassis with angled card cage |
US8954977B2 (en) * | 2008-12-09 | 2015-02-10 | Intel Corporation | Software-based thread remapping for power savings |
US8798045B1 (en) * | 2008-12-29 | 2014-08-05 | Juniper Networks, Inc. | Control plane architecture for switch fabrics |
US20100229175A1 (en) * | 2009-03-05 | 2010-09-09 | International Business Machines Corporation | Moving Resources In a Computing Environment Having Multiple Logically-Partitioned Computer Systems |
WO2010108165A1 (en) * | 2009-03-20 | 2010-09-23 | The Trustees Of Princeton University | Systems and methods for network acceleration and efficient indexing for caching file systems |
US8321870B2 (en) * | 2009-08-14 | 2012-11-27 | General Electric Company | Method and system for distributed computation having sub-task processing and sub-solution redistribution |
US20110055838A1 (en) * | 2009-08-28 | 2011-03-03 | Moyes William A | Optimized thread scheduling via hardware performance monitoring |
JP5056987B2 (en) * | 2009-10-16 | 2012-10-24 | 富士通株式会社 | Electronic equipment |
CN101706802B (en) * | 2009-11-24 | 2013-06-05 | 成都市华为赛门铁克科技有限公司 | Method, device and sever for writing, modifying and restoring data |
US9129052B2 (en) * | 2009-12-03 | 2015-09-08 | International Business Machines Corporation | Metering resource usage in a cloud computing environment |
CN102135923A (en) * | 2010-01-21 | 2011-07-27 | 鸿富锦精密工业(深圳)有限公司 | Method for integrating operating system into BIOS (Basic Input/Output System) chip and method for starting operating system |
US8638553B1 (en) * | 2010-03-31 | 2014-01-28 | Amazon Technologies, Inc. | Rack system cooling with inclined computing devices |
US8601297B1 (en) * | 2010-06-18 | 2013-12-03 | Google Inc. | Systems and methods for energy proportional multiprocessor networks |
US8171142B2 (en) * | 2010-06-30 | 2012-05-01 | Vmware, Inc. | Data center inventory management using smart racks |
IT1401647B1 (en) * | 2010-07-09 | 2013-08-02 | Campatents B V | METHOD FOR MONITORING CHANGES OF CONFIGURATION OF A MONITORING DEVICE FOR AN AUTOMATIC MACHINE |
US8259450B2 (en) * | 2010-07-21 | 2012-09-04 | Birchbridge Incorporated | Mobile universal hardware platform |
WO2012016031A1 (en) * | 2010-07-28 | 2012-02-02 | Par Systems, Inc. | Robotic storage and retrieval systems |
US8824222B2 (en) * | 2010-08-13 | 2014-09-02 | Rambus Inc. | Fast-wake memory |
US8914805B2 (en) * | 2010-08-31 | 2014-12-16 | International Business Machines Corporation | Rescheduling workload in a hybrid computing environment |
US8489939B2 (en) * | 2010-10-25 | 2013-07-16 | At&T Intellectual Property I, L.P. | Dynamically allocating multitier applications based upon application requirements and performance and reliability of resources |
WO2012057546A2 (en) * | 2010-10-28 | 2012-05-03 | 엘지전자 주식회사 | Method and apparatus for transceiving a data frame in a wireless lan system |
US8838286B2 (en) * | 2010-11-04 | 2014-09-16 | Dell Products L.P. | Rack-level modular server and storage framework |
US8762668B2 (en) * | 2010-11-18 | 2014-06-24 | Hitachi, Ltd. | Multipath switching over multiple storage systems |
US9563479B2 (en) * | 2010-11-30 | 2017-02-07 | Red Hat, Inc. | Brokering optimized resource supply costs in host cloud-based network using predictive workloads |
CN102693181A (en) * | 2011-03-25 | 2012-09-26 | 鸿富锦精密工业(深圳)有限公司 | Firmware update-write system and method |
US9405550B2 (en) * | 2011-03-31 | 2016-08-02 | International Business Machines Corporation | Methods for the transmission of accelerator commands and corresponding command structure to remote hardware accelerator engines over an interconnect link |
US20120303322A1 (en) * | 2011-05-23 | 2012-11-29 | Rego Charles W | Incorporating memory and io cycle information into compute usage determinations |
CN103748560A (en) * | 2011-07-01 | 2014-04-23 | 惠普发展公司,有限责任合伙企业 | Method of and system for managing computing resources |
US9317336B2 (en) * | 2011-07-27 | 2016-04-19 | Alcatel Lucent | Method and apparatus for assignment of virtual resources within a cloud environment |
US8713257B2 (en) * | 2011-08-26 | 2014-04-29 | Lsi Corporation | Method and system for shared high speed cache in SAS switches |
US8755176B2 (en) * | 2011-10-12 | 2014-06-17 | Xyratex Technology Limited | Data storage system, an energy module and a method of providing back-up power to a data storage system |
US9237107B2 (en) * | 2011-11-15 | 2016-01-12 | New Jersey Institute Of Technology | Fair quantized congestion notification (FQCN) to mitigate transport control protocol (TCP) throughput collapse in data center networks |
US20140304713A1 (en) * | 2011-11-23 | 2014-10-09 | Telefonaktiebolaget L M Ericsson (pulb) | Method and apparatus for distributed processing tasks |
DE102011119693A1 (en) * | 2011-11-29 | 2013-05-29 | Universität Heidelberg | System, computer-implemented method and computer program product for direct communication between hardware accelerators in a computer cluster |
US20130185729A1 (en) * | 2012-01-13 | 2013-07-18 | Rutgers, The State University Of New Jersey | Accelerating resource allocation in virtualized environments using workload classes and/or workload signatures |
US8732291B2 (en) * | 2012-01-13 | 2014-05-20 | Accenture Global Services Limited | Performance interference model for managing consolidated workloads in QOS-aware clouds |
US9336061B2 (en) * | 2012-01-14 | 2016-05-10 | International Business Machines Corporation | Integrated metering of service usage for hybrid clouds |
US9367360B2 (en) * | 2012-01-30 | 2016-06-14 | Microsoft Technology Licensing, Llc | Deploying a hardware inventory as a cloud-computing stamp |
TWI462017B (en) * | 2012-02-24 | 2014-11-21 | Wistron Corp | Server deployment system and method for updating data |
US9749413B2 (en) * | 2012-05-29 | 2017-08-29 | Intel Corporation | Peer-to-peer interrupt signaling between devices coupled via interconnects |
JP5983045B2 (en) * | 2012-05-30 | 2016-08-31 | 富士通株式会社 | Library device |
CN102694863B (en) * | 2012-05-30 | 2015-08-26 | 电子科技大学 | Based on the implementation method of the distributed memory system of adjustment of load and System Fault Tolerance |
US8832268B1 (en) * | 2012-08-16 | 2014-09-09 | Amazon Technologies, Inc. | Notification and resolution of infrastructure issues |
US9792004B2 (en) * | 2012-10-08 | 2017-10-17 | Fisher-Rosemount Systems, Inc. | Derived and linked definitions with override |
US9202040B2 (en) | 2012-10-10 | 2015-12-01 | Globalfoundries Inc. | Chip authentication using multi-domain intrinsic identifiers |
US9047417B2 (en) * | 2012-10-29 | 2015-06-02 | Intel Corporation | NUMA aware network interface |
US20140185225A1 (en) * | 2012-12-28 | 2014-07-03 | Joel Wineland | Advanced Datacenter Designs |
US9130824B2 (en) | 2013-01-08 | 2015-09-08 | American Megatrends, Inc. | Chassis management implementation by management instance on baseboard management controller managing multiple computer nodes |
US9609782B2 (en) * | 2013-01-15 | 2017-03-28 | Intel Corporation | Rack assembly structure |
US9201837B2 (en) * | 2013-03-13 | 2015-12-01 | Futurewei Technologies, Inc. | Disaggregated server architecture for data centers |
US9582010B2 (en) * | 2013-03-14 | 2017-02-28 | Rackspace Us, Inc. | System and method of rack management |
US9634958B2 (en) * | 2013-04-02 | 2017-04-25 | Amazon Technologies, Inc. | Burst capacity for user-defined pools |
US9104562B2 (en) * | 2013-04-05 | 2015-08-11 | International Business Machines Corporation | Enabling communication over cross-coupled links between independently managed compute and storage networks |
CN103281351B (en) * | 2013-04-19 | 2016-12-28 | 武汉方寸科技有限公司 | A kind of high-effect Remote Sensing Data Processing and the cloud service platform of analysis |
US20140317267A1 (en) * | 2013-04-22 | 2014-10-23 | Advanced Micro Devices, Inc. | High-Density Server Management Controller |
US20140337496A1 (en) * | 2013-05-13 | 2014-11-13 | Advanced Micro Devices, Inc. | Embedded Management Controller for High-Density Servers |
CN103294521B (en) * | 2013-05-30 | 2016-08-10 | 天津大学 | A kind of method reducing data center's traffic load and energy consumption |
US9436600B2 (en) * | 2013-06-11 | 2016-09-06 | Svic No. 28 New Technology Business Investment L.L.P. | Non-volatile memory storage for multi-channel memory system |
US20150033222A1 (en) | 2013-07-25 | 2015-01-29 | Cavium, Inc. | Network Interface Card with Virtual Switch and Traffic Flow Policy Enforcement |
US10069686B2 (en) * | 2013-09-05 | 2018-09-04 | Pismo Labs Technology Limited | Methods and systems for managing a device through a manual information input module |
US9306861B2 (en) * | 2013-09-26 | 2016-04-05 | Red Hat Israel, Ltd. | Automatic promiscuous forwarding for a bridge |
US9413713B2 (en) * | 2013-12-05 | 2016-08-09 | Cisco Technology, Inc. | Detection of a misconfigured duplicate IP address in a distributed data center network fabric |
US9792243B2 (en) * | 2013-12-26 | 2017-10-17 | Intel Corporation | Computer architecture to provide flexibility and/or scalability |
US9705798B1 (en) * | 2014-01-07 | 2017-07-11 | Google Inc. | Systems and methods for routing data through data centers using an indirect generalized hypercube network |
US9444695B2 (en) * | 2014-01-30 | 2016-09-13 | Xerox Corporation | Methods and systems for scheduling a task |
BR112016017483A2 (en) * | 2014-02-27 | 2017-08-08 | Intel Corp | RACK CONTROLLER AND DATA CENTER MANAGEMENT METHOD |
US10120727B2 (en) * | 2014-02-27 | 2018-11-06 | Intel Corporation | Techniques to allocate configurable computing resources |
US9363926B1 (en) * | 2014-03-17 | 2016-06-07 | Amazon Technologies, Inc. | Modular mass storage system with staggered backplanes |
US9925492B2 (en) * | 2014-03-24 | 2018-03-27 | Mellanox Technologies, Ltd. | Remote transactional memory |
US10218645B2 (en) * | 2014-04-08 | 2019-02-26 | Mellanox Technologies, Ltd. | Low-latency processing in a network node |
US9503391B2 (en) * | 2014-04-11 | 2016-11-22 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and system for network function placement |
US9544233B2 (en) * | 2014-04-28 | 2017-01-10 | New Jersey Institute Of Technology | Congestion management for datacenter network |
US9081828B1 (en) * | 2014-04-30 | 2015-07-14 | Igneous Systems, Inc. | Network addressable storage controller with storage drive profile comparison |
TWI510933B (en) * | 2014-05-13 | 2015-12-01 | Acer Inc | Method for remotely accessing data and local apparatus using the method |
CN109067833B (en) * | 2014-05-22 | 2021-06-22 | 华为技术有限公司 | Node interconnection device, resource control node and server system |
US9477279B1 (en) * | 2014-06-02 | 2016-10-25 | Datadirect Networks, Inc. | Data storage system with active power management and method for monitoring and dynamical control of power sharing between devices in data storage system |
US9602351B2 (en) * | 2014-06-06 | 2017-03-21 | Microsoft Technology Licensing, Llc | Proactive handling of network faults |
US9684575B2 (en) * | 2014-06-23 | 2017-06-20 | Liqid Inc. | Failover handling in modular switched fabric for data storage systems |
US10382279B2 (en) * | 2014-06-30 | 2019-08-13 | Emc Corporation | Dynamically composed compute nodes comprising disaggregated components |
US10122605B2 (en) * | 2014-07-09 | 2018-11-06 | Cisco Technology, Inc | Annotation of network activity through different phases of execution |
US9892079B2 (en) * | 2014-07-25 | 2018-02-13 | Rajiv Ganth | Unified converged network, storage and compute system |
US9262144B1 (en) * | 2014-08-20 | 2016-02-16 | International Business Machines Corporation | Deploying virtual machine instances of a pattern to regions of a hierarchical tier using placement policies and constraints |
US9684531B2 (en) * | 2014-08-21 | 2017-06-20 | International Business Machines Corporation | Combining blade servers based on workload characteristics |
CN104168332A (en) * | 2014-09-01 | 2014-11-26 | 广东电网公司信息中心 | Load balance and node state monitoring method in high performance computing |
US9858104B2 (en) * | 2014-09-24 | 2018-01-02 | Pluribus Networks, Inc. | Connecting fabrics via switch-to-switch tunneling transparent to network servers |
US10630767B1 (en) * | 2014-09-30 | 2020-04-21 | Amazon Technologies, Inc. | Hardware grouping based computing resource allocation |
US10061599B1 (en) * | 2014-10-16 | 2018-08-28 | American Megatrends, Inc. | Bus enumeration acceleration |
US9098451B1 (en) * | 2014-11-21 | 2015-08-04 | Igneous Systems, Inc. | Shingled repair set for writing data |
US9886306B2 (en) * | 2014-11-21 | 2018-02-06 | International Business Machines Corporation | Cross-platform scheduling with long-term fairness and platform-specific optimization |
WO2016090485A1 (en) * | 2014-12-09 | 2016-06-16 | Cirba Ip Inc. | System and method for routing computing workloads based on proximity |
US20160173600A1 (en) | 2014-12-15 | 2016-06-16 | Cisco Technology, Inc. | Programmable processing engine for a virtual interface controller |
US10057186B2 (en) * | 2015-01-09 | 2018-08-21 | International Business Machines Corporation | Service broker for computational offloading and improved resource utilization |
EP3046028B1 (en) * | 2015-01-15 | 2020-02-19 | Alcatel Lucent | Load-balancing and scaling of cloud resources by migrating a data session |
US10114692B2 (en) * | 2015-01-27 | 2018-10-30 | Quantum Corporation | High/low energy zone data storage |
US10234930B2 (en) * | 2015-02-13 | 2019-03-19 | Intel Corporation | Performing power management in a multicore processor |
JP2016167143A (en) * | 2015-03-09 | 2016-09-15 | 富士通株式会社 | Information processing system and control method of the same |
US9276900B1 (en) * | 2015-03-19 | 2016-03-01 | Igneous Systems, Inc. | Network bootstrapping for a distributed storage system |
US10848408B2 (en) * | 2015-03-26 | 2020-11-24 | Vmware, Inc. | Methods and apparatus to control computing resource utilization of monitoring agents |
US10606651B2 (en) * | 2015-04-17 | 2020-03-31 | Microsoft Technology Licensing, Llc | Free form expression accelerator with thread length-based thread assignment to clustered soft processor cores that share a functional circuit |
US10019388B2 (en) * | 2015-04-28 | 2018-07-10 | Liqid Inc. | Enhanced initialization for data storage assemblies |
US9910664B2 (en) * | 2015-05-04 | 2018-03-06 | American Megatrends, Inc. | System and method of online firmware update for baseboard management controller (BMC) devices |
US20160335209A1 (en) * | 2015-05-11 | 2016-11-17 | Quanta Computer Inc. | High-speed data transmission using pcie protocol |
US9696781B2 (en) * | 2015-05-28 | 2017-07-04 | Cisco Technology, Inc. | Automated power control for reducing power usage in communications networks |
US11203486B2 (en) * | 2015-06-02 | 2021-12-21 | Alert Innovation Inc. | Order fulfillment system |
US9792248B2 (en) * | 2015-06-02 | 2017-10-17 | Microsoft Technology Licensing, Llc | Fast read/write between networked computers via RDMA-based RPC requests |
US9606836B2 (en) * | 2015-06-09 | 2017-03-28 | Microsoft Technology Licensing, Llc | Independently networkable hardware accelerators for increased workflow optimization |
CN204887839U (en) * | 2015-07-23 | 2015-12-16 | 中兴通讯股份有限公司 | Veneer module level water cooling system |
US10055218B2 (en) * | 2015-08-11 | 2018-08-21 | Quanta Computer Inc. | System and method for adding and storing groups of firmware default settings |
US10348574B2 (en) * | 2015-08-17 | 2019-07-09 | Vmware, Inc. | Hardware management systems for disaggregated rack architectures in virtual server rack deployments |
US10736239B2 (en) * | 2015-09-22 | 2020-08-04 | Z-Impact, Inc. | High performance computing rack and storage system with forced cooling |
US10387209B2 (en) * | 2015-09-28 | 2019-08-20 | International Business Machines Corporation | Dynamic transparent provisioning of resources for application specific resources |
US10162793B1 (en) * | 2015-09-29 | 2018-12-25 | Amazon Technologies, Inc. | Storage adapter device for communicating with network storage |
US9888607B2 (en) * | 2015-09-30 | 2018-02-06 | Seagate Technology Llc | Self-biasing storage device sled |
US10216643B2 (en) * | 2015-11-23 | 2019-02-26 | International Business Machines Corporation | Optimizing page table manipulations |
US9811347B2 (en) * | 2015-12-14 | 2017-11-07 | Dell Products, L.P. | Managing dependencies for human interface infrastructure (HII) devices |
US10028401B2 (en) * | 2015-12-18 | 2018-07-17 | Microsoft Technology Licensing, Llc | Sidewall-accessible dense storage rack |
US20170180220A1 (en) * | 2015-12-18 | 2017-06-22 | Intel Corporation | Techniques to Generate Workload Performance Fingerprints for Cloud Infrastructure Elements |
US10452467B2 (en) | 2016-01-28 | 2019-10-22 | Intel Corporation | Automatic model-based computing environment performance monitoring |
US10581711B2 (en) * | 2016-01-28 | 2020-03-03 | Oracle International Corporation | System and method for policing network traffic flows using a ternary content addressable memory in a high performance computing environment |
WO2017146618A1 (en) * | 2016-02-23 | 2017-08-31 | Telefonaktiebolaget Lm Ericsson (Publ) | Methods and modules relating to allocation of host machines |
US20170257970A1 (en) * | 2016-03-04 | 2017-09-07 | Radisys Corporation | Rack having uniform bays and an optical interconnect system for shelf-level, modular deployment of sleds enclosing information technology equipment |
US9811281B2 (en) * | 2016-04-07 | 2017-11-07 | International Business Machines Corporation | Multi-tenant memory service for memory pool architectures |
US10701141B2 (en) * | 2016-06-30 | 2020-06-30 | International Business Machines Corporation | Managing software licenses in a disaggregated environment |
US11706895B2 (en) * | 2016-07-19 | 2023-07-18 | Pure Storage, Inc. | Independent scaling of compute resources and storage resources in a storage system |
US10234833B2 (en) * | 2016-07-22 | 2019-03-19 | Intel Corporation | Technologies for predicting power usage of a data center |
US10034407B2 (en) | 2016-07-22 | 2018-07-24 | Intel Corporation | Storage sled for a data center |
US20180034908A1 (en) * | 2016-07-27 | 2018-02-01 | Alibaba Group Holding Limited | Disaggregated storage and computation system |
US10365852B2 (en) * | 2016-07-29 | 2019-07-30 | Vmware, Inc. | Resumable replica resynchronization |
US10193997B2 (en) | 2016-08-05 | 2019-01-29 | Dell Products L.P. | Encoded URI references in restful requests to facilitate proxy aggregation |
US10127107B2 (en) * | 2016-08-14 | 2018-11-13 | Nxp Usa, Inc. | Method for performing data transaction that selectively enables memory bank cuts and memory device therefor |
US10108560B1 (en) * | 2016-09-14 | 2018-10-23 | Evol1-Ip, Llc | Ethernet-leveraged hyper-converged infrastructure |
US10303458B2 (en) * | 2016-09-29 | 2019-05-28 | Hewlett Packard Enterprise Development Lp | Multi-platform installer |
US10776342B2 (en) * | 2016-11-18 | 2020-09-15 | Tuxena, Inc. | Systems and methods for recovering lost clusters from a mounted volume |
US10726131B2 (en) * | 2016-11-21 | 2020-07-28 | Facebook, Inc. | Systems and methods for mitigation of permanent denial of service attacks |
CN109891908A (en) * | 2016-11-29 | 2019-06-14 | 英特尔公司 | Technology for the interconnection of millimeter wave rack |
US20180150256A1 (en) * | 2016-11-29 | 2018-05-31 | Intel Corporation | Technologies for data deduplication in disaggregated architectures |
US10503671B2 (en) * | 2016-12-29 | 2019-12-10 | Oath Inc. | Controlling access to a shared resource |
US10282549B2 (en) * | 2017-03-07 | 2019-05-07 | Hewlett Packard Enterprise Development Lp | Modifying service operating system of baseboard management controller |
CN110769959B (en) * | 2017-03-08 | 2022-03-29 | Bwxt核能股份有限公司 | Apparatus and method for blind bolt repair |
US20180288152A1 (en) * | 2017-04-01 | 2018-10-04 | Anjaneya R. Chagam Reddy | Storage dynamic accessibility mechanism method and apparatus |
US10331581B2 (en) * | 2017-04-10 | 2019-06-25 | Hewlett Packard Enterprise Development Lp | Virtual channel and resource assignment |
US10355939B2 (en) * | 2017-04-13 | 2019-07-16 | International Business Machines Corporation | Scalable data center network topology on distributed switch |
US10467052B2 (en) * | 2017-05-01 | 2019-11-05 | Red Hat, Inc. | Cluster topology aware container scheduling for efficient data transfer |
US10303615B2 (en) * | 2017-06-16 | 2019-05-28 | Hewlett Packard Enterprise Development Lp | Matching pointers across levels of a memory hierarchy |
US20190166032A1 (en) * | 2017-11-30 | 2019-05-30 | American Megatrends, Inc. | Utilization based dynamic provisioning of rack computing resources |
US10447273B1 (en) * | 2018-09-11 | 2019-10-15 | Advanced Micro Devices, Inc. | Dynamic virtualized field-programmable gate array resource control for performance and reliability |
US11201818B2 (en) * | 2019-04-04 | 2021-12-14 | Cisco Technology, Inc. | System and method of providing policy selection in a network |
-
2017
- 2017-12-21 US US15/850,325 patent/US20190068466A1/en not_active Abandoned
- 2017-12-29 US US15/858,288 patent/US20190068521A1/en not_active Abandoned
- 2017-12-29 US US15/858,549 patent/US20190065401A1/en not_active Abandoned
- 2017-12-29 US US15/858,316 patent/US20190065260A1/en not_active Abandoned
- 2017-12-29 US US15/858,542 patent/US11748172B2/en active Active
- 2017-12-29 US US15/858,557 patent/US20190065083A1/en not_active Abandoned
- 2017-12-29 US US15/858,748 patent/US11614979B2/en active Active
- 2017-12-29 US US15/858,305 patent/US20190068464A1/en not_active Abandoned
- 2017-12-29 US US15/858,286 patent/US20190068523A1/en not_active Abandoned
- 2017-12-30 US US15/859,385 patent/US20190065281A1/en not_active Abandoned
- 2017-12-30 US US15/859,364 patent/US11392425B2/en active Active
- 2017-12-30 US US15/859,366 patent/US20190065261A1/en not_active Abandoned
- 2017-12-30 US US15/859,368 patent/US11422867B2/en active Active
- 2017-12-30 US US15/859,388 patent/US20190065231A1/en not_active Abandoned
- 2017-12-30 US US15/859,394 patent/US11467885B2/en active Active
- 2017-12-30 US US15/859,363 patent/US20190068444A1/en not_active Abandoned
-
2018
- 2018-03-09 US US15/916,394 patent/US20190065415A1/en not_active Abandoned
- 2018-03-23 US US15/933,855 patent/US11030017B2/en active Active
- 2018-03-30 US US15/942,101 patent/US11416309B2/en active Active
- 2018-03-30 US US15/942,108 patent/US20190067848A1/en not_active Abandoned
- 2018-06-29 US US16/022,962 patent/US11055149B2/en active Active
- 2018-06-29 US US16/023,803 patent/US10888016B2/en active Active
- 2018-07-27 CN CN201810845565.8A patent/CN109426316A/en active Pending
- 2018-07-27 CN CN201810843475.5A patent/CN109428841A/en active Pending
- 2018-07-30 WO PCT/US2018/044363 patent/WO2019045928A1/en active Application Filing
- 2018-07-30 WO PCT/US2018/044366 patent/WO2019045930A1/en unknown
- 2018-07-30 WO PCT/US2018/044365 patent/WO2019045929A1/en active Application Filing
- 2018-07-30 DE DE112018004798.9T patent/DE112018004798T5/en active Pending
- 2018-07-30 EP EP18852427.6A patent/EP3676708A4/en active Pending
- 2018-08-30 US US16/642,523 patent/US20200257566A1/en not_active Abandoned
- 2018-08-30 US US16/642,520 patent/US20200192710A1/en not_active Abandoned
- 2018-08-30 CN CN201811005041.4A patent/CN109426646A/en active Pending
- 2018-08-30 CN CN201811004869.8A patent/CN109426633A/en active Pending
- 2018-08-30 CN CN201811004916.9A patent/CN109426630A/en active Pending
- 2018-08-30 CN CN201811004878.7A patent/CN109426568A/en active Pending
- 2018-08-30 WO PCT/US2018/048946 patent/WO2019046639A1/en active Application Filing
- 2018-08-30 CN CN201811002563.9A patent/CN109428843A/en active Pending
- 2018-08-30 CN CN201811001590.4A patent/CN109428889A/en active Pending
- 2018-08-30 WO PCT/US2018/048917 patent/WO2019046620A1/en active Application Filing
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11595277B2 (en) | 2016-07-22 | 2023-02-28 | Intel Corporation | Technologies for switching network traffic in a data center |
US10785549B2 (en) | 2016-07-22 | 2020-09-22 | Intel Corporation | Technologies for switching network traffic in a data center |
US10802229B2 (en) | 2016-07-22 | 2020-10-13 | Intel Corporation | Technologies for switching network traffic in a data center |
US10791384B2 (en) | 2016-07-22 | 2020-09-29 | Intel Corporation | Technologies for switching network traffic in a data center |
US11128553B2 (en) | 2016-07-22 | 2021-09-21 | Intel Corporation | Technologies for switching network traffic in a data center |
US11137922B2 (en) | 2016-11-29 | 2021-10-05 | Intel Corporation | Technologies for providing accelerated functions as a service in a disaggregated architecture |
US11907557B2 (en) | 2016-11-29 | 2024-02-20 | Intel Corporation | Technologies for dividing work across accelerator devices |
US20190014049A1 (en) * | 2017-07-04 | 2019-01-10 | Vmware, Inc | Network resource management for hyper-converged infrastructures |
US10574580B2 (en) * | 2017-07-04 | 2020-02-25 | Vmware, Inc. | Network resource management for hyper-converged infrastructures |
US11265253B2 (en) | 2017-07-04 | 2022-03-01 | Vmware, Inc. | Network resource management for hyperconverged infrastructures |
US10761726B2 (en) * | 2018-04-16 | 2020-09-01 | VWware, Inc. | Resource fairness control in distributed storage systems using congestion data |
US20220150142A1 (en) * | 2019-03-28 | 2022-05-12 | Omron Corporation | Monitoring system, setting device, and monitoring method |
US11695660B2 (en) * | 2019-03-28 | 2023-07-04 | Omron Corporation | Monitoring system, setting device, and monitoring method |
US11122123B1 (en) | 2020-03-09 | 2021-09-14 | International Business Machines Corporation | Method for a network of storage devices |
US20220272862A1 (en) * | 2021-02-19 | 2022-08-25 | CyberSecure IPS, LLC | Intelligent cable patching of racks to facilitate cable installation |
US11785735B2 (en) * | 2021-02-19 | 2023-10-10 | CyberSecure IPS, LLC | Intelligent cable patching of racks to facilitate cable installation |
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