US20190035623A1 - Integrated system and method for source/drain engineering - Google Patents
Integrated system and method for source/drain engineering Download PDFInfo
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- US20190035623A1 US20190035623A1 US16/148,430 US201816148430A US2019035623A1 US 20190035623 A1 US20190035623 A1 US 20190035623A1 US 201816148430 A US201816148430 A US 201816148430A US 2019035623 A1 US2019035623 A1 US 2019035623A1
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- source
- drain region
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000007789 gas Substances 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 150000003839 salts Chemical class 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 238000010926 purge Methods 0.000 claims abstract description 6
- 239000000203 mixture Substances 0.000 claims description 27
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 5
- 239000000460 chlorine Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 229910052801 chlorine Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 3
- 239000006227 byproduct Substances 0.000 claims 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 19
- 238000004140 cleaning Methods 0.000 abstract description 8
- 238000002360 preparation method Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 239000011261 inert gas Substances 0.000 abstract description 5
- 239000000356 contaminant Substances 0.000 description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical class [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910021480 group 4 element Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 241000237074 Centris Species 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005108 dry cleaning Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 150000004679 hydroxides Chemical class 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- Implementations of the present disclosure generally relate to the manufacture of semiconductor devices. More specifically, implementations described herein relate to methods for source/drain engineering.
- Integrated circuits are formed in and on silicon and other semiconductor substrates.
- substrates are made by growing an ingot from a bath of molten silicon, and then sawing the solidified ingot into multiple substrates.
- An epitaxial silicon layer may then be formed on the monocrystalline silicon substrate to form a defect-free silicon layer that may be doped or undoped.
- Semiconductor devices, such as transistors, are manufactured from the epitaxial silicon layer. The electrical properties of the formed epitaxial silicon layer will generally be better than the properties of the monocrystalline silicon substrate.
- Group IV elements may be advantageous in certain applications for forming silicon-based devices.
- Group IV elements may serve as a source/drain region in sub-10 nm Fin Field Effect Transistor (FinFET) devices due to the low contact resistance, superior electron mobility and lower operation voltage.
- FinFET Fin Field Effect Transistor
- Surfaces of the monocrystalline silicon and the epitaxial silicon layer are susceptible to contamination when exposed to typical fabrication facility ambient conditions, and there might be a few atomic layers of damaged Si from previous process steps.
- a native oxide layer may form on the monocrystalline silicon surface prior to deposition of the epitaxial layer.
- contaminants present in the ambient environment may deposit on the monocrystalline surface and may come from previous process steps.
- the presence of a native oxide layer or contaminants on the monocrystalline silicon surface negatively affects the quality of an epitaxial layer subsequently formed on the monocrystalline surface. While present cleaning methods remove some of the native oxides and contaminants from the monocrystalline silicon surface, some contaminants may
- Implementations described herein generally provide a method of processing a workpiece.
- the method of processing the workpiece includes disposing the workpiece in a processing volume.
- the workpiece includes a substrate.
- the substrate includes a source/drain region disposed on the substrate.
- the method of disposing a workpiece also includes establishing a low pressure processing environment in the processing volume.
- the method of disposing a workpiece also includes maintaining the low pressure processing environment while delivering a first gas containing to the processing volume, depositing a salt on the workpiece, heating the substrate to greater than 90° C., purging the processing volume with a second inert gas, and recessing the source/drain regions.
- FIG. 1 is a flow diagram illustrating operations of a method according to one implementation described herein.
- FIGS. 2A-2C illustrate a schematic, cross-sectional view of a device structure depicting stages of fabrication in accordance with the method of FIG. 1 .
- Implementations of the present disclosure generally relate to methods for forming semiconductor devices. More specifically, methods are described for sub-10 nm cleaning and recessing substrates in preparation for precise Group IV source/drain growth in FinFET devices.
- FIG. 1 is a flow diagram illustrating a method 100 for cleaning and recessing substrates in preparation for precise source/drain deposition comprising Group IV elements on a silicon substrate.
- FIGS. 2A-2C depict stages of fabrication of a device structure in accordance with the method 100 of FIG. 1 . The method 100 is described below in accordance with operations of cleaning and recessing a substrate as illustrated in FIGS. 2A-2C .
- a workpiece including a substrate 202 with a device 200 that has a source/drain region formed on the substrate, is disposed in a processing volume at step 25 .
- the device may have sub-10 nm trenches 218 , 220 .
- the processing volume may be contained within a processing chamber.
- the workpiece is shown in FIG. 2 , and may be pre-cleaned prior to performing the method 100 .
- the pre-cleaning may include any conventional wet or dry cleaning method.
- the workpiece has a device 200 that includes a dielectric material 204 disposed on a substrate 202 , a pre source/drain region 216 , a fin layer 210 disposed on the pre source/drain region 216 , a dummy gate 208 , and contaminants 206 .
- the pre source/drain region 216 may be disposed on the substrate 202 and within the dielectric material 204 .
- the dummy gate 208 may be disposed on the fin layer 210 .
- the contaminants 206 may be disposed on the pre source/drain region 216 and the fin layer 210 .
- the substrate 202 may be a silicon-containing substrate.
- the substrate 202 may further comprise germanium (Ge), carbon (C), boron (B), phosphorous (P), or other materials that may be co-grown, doped and/or associated with silicon materials.
- the substrate 202 may be part of a device, such as a fin shaped field effect transistor (FinFET) device.
- FinFET fin shaped field effect transistor
- the FinFET device may be sized for the 10 nm node.
- the dielectric material 204 may comprise one or more of silicon oxide (SiO), silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials that may be used to form a dielectric material.
- the dielectric material 204 may be deposited by various deposition processes. For example, the dielectric material 204 may be deposited by a chemical vapor deposition (CVD) process, which may be plasma enhanced.
- the contaminants 206 may include native oxide and dangling silicon bonds saturated with hydrogen such as SiO 2 or GeO 2 .
- the dummy gate 208 may comprise silicon nitride (SiN).
- the pre source/drain region 216 may comprise silicon and may further comprise germanium (Ge), carbon (C), boron (B), phosphorous (P), or other materials that may be co-grown, doped and/or associated with silicon materials.
- the workpiece including the device 200 , may be placed in an inductively coupled plasma (ICP) plasma reactor chamber.
- ICP inductively coupled plasma
- Suitable chambers include the CENTRIS® or MESA® chamber available from Applied Materials, Inc. of Santa Clara, Calif. Chambers available from other manufacturers may also be used to practice implementations described herein.
- a low pressure processing environment may be established within the chamber at step 50 of FIG. 1 .
- the low pressure processing environment may be maintained (at step 75 of FIG. 1 ) while each of the operations of method 100 proceed.
- a first gas may be delivered over the workpiece, including substrate 202 in the processing volume.
- the first gas may be a hydrogen argon (H 2 Ar) gas mixture.
- the first gas may be inert.
- the ion energy is controlled with low RF source power between 200-800 watts or plasma pulsing.
- the hydrogen gas may be flowed at a rate of between 10-500 sccm, and the argon may be flowed at a rate of between 300-1000 sccm.
- the pressure of the processing volume may be maintained between 5 mT to 50 mT.
- the temperature of the processing volume may be between 20° C. and 40° C., and the ion energy may be less than 50 electronvolt (eV).
- the first gas mixture producing the low energy ions may advantageously penetrate the native oxide contaminants 206 located within trenches 218 , 220 to break silicon-oxygen bonds in preparation for subsequent removal and activate the sub-oxide (SiO) disposed underneath.
- the hydrogen ions or radicals within the first gas mixture react with the native oxide to form volatile hydroxides.
- the dry clean gas mixture may be able to penetrate the small sub-10 nm trenches and contaminants efficiently to provide for a higher throughput without damaging the device 200 .
- a salt is deposited on the pre source/drain region 216 .
- a NH 3 /NF 3 /Ar gas mixture is delivered to the processing volume to react with the generated plasma and form a NH 4 F salt.
- the NH 4 F salt is deposited on the pre source/drain region 216 .
- the workpiece is heated to greater than 90° C. In one implementation, the workpiece is heated to greater than 90° C. for greater than 1 minute. Heating the workpiece may remove the contaminants 206 to expose a clean silicon surface 222 , as shown in FIG. 2B .
- the NH 4 F salt may react with and remove the native oxide contaminants 206 from the pre source/drain region 216 and fin layer 210 .
- the NH 4 F salt may expose the underlying silicon surface 222 in the pre source/drain region 216 without damaging the underlying silicon surface.
- the NH 3 /NF 3 /Ar gas mixture is delivered to the processing volume which is maintained at a pressure of 200-900 mT.
- the continuous mode RF power may be maintained between 200-400 watts.
- the argon is flowed at a rate of 500-1200 sccm, the ammonia (NH 3 ) is flowed at a rate of 10-100 sccm, and the NF 3 is flowed at a rate of 5-20 sccm.
- the processing volume and gas lines are purged using a second inert gas mixture.
- the second inert gas may be a H 2 /Ar plasma mixture.
- the second inert gas mixture advantageously removes any residual ammonia (NH 3 ) inside the chamber and gas line providing for a clean surface in preparation for subsequent processing operations.
- the pre source/drain region 216 is recessed by etching.
- the fin layer 210 may also be recessed.
- the width of the fin layer 210 is reduced about between 1-2 nm.
- Suitable methods of etching the pre source/drain region 216 or the fin layer 210 or a combination of both include any suitable etching process, such as anisotropic dry etching.
- argon (Ar), hydrogen (H), and/or chlorine (CI) may be used as precursors to produce an etchant plasma for etching the fin layer 210 .
- a H 2 /Cl 2 /Ar plasma is used for etching the pre source/drain region 216 .
- the plasma mixture may function to volatilize the pre source/drain region 216 such that a portion may be removed.
- the pre source/drain region 216 is etched 1-2 nm or at a rate between 0.5 nm/min-3 nm/min.
- the plasma ion energy is less than 20 eV with plasma pulsing
- the pressure of the processing volume may be maintained between 5-50 mTorr
- the temperature is between 30° C.-50° C.
- the RF power is between 500-600 watts.
- This step may use very low ion energy which is controlled by RF source pulsing without bias power.
- the argon may be flowed at a rate between 100-500 sccm
- the hydrogen may be flowed at a rate between 50-300 sccm
- the chlorine may be flowed at a rate between 10-100 sccm.
- the ratio of Cl:H:Ar may be between 1:5:10 to 1:3:5.
- the low energy H 2 /Cl 2 /Ar plasma pulsing provides for precise control in the nm scale while reducing silicon-silicon lattice damage.
- the integrated clean and recess process provides for a source/drain region free of carbon and oxide contaminants while reducing the silicon-silicon lattice damage in preparation for subsequent processing.
- a source/drain extension 212 may be deposited over the cleaned and recessed pre source/drain region 216 .
- the source/drain extension 212 is silicon arsenide (SiAs).
- a source/drain layer 214 may be deposited on the source/drain extension 212 .
- the source/drain layer 214 is silicon phosphide (SiP).
- the integrated clean and recess process prepares the device 200 for subsequent processing while maintaining a low pressure environment. More specifically, the resulting source/drain region may be free of contaminants and/or defects, may has a desired shape, and may be prepared for subsequent epitaxial growth.
- the device 200 may undergo additional processing steps within the same cluster tool. Use of a single apparatus containing various processing chambers allows for the various operations of the method 100 of FIG. 1 to occur while maintaining a low pressure environment. More specifically, the low pressure environment need not be broken during transfer to an epitaxial chamber for source/drain extension 212 and source/drain layer 214 growth.
- additional processing may include replacing the dummy gate 208 with a metal gate.
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Abstract
Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
Description
- This application is a continuation of U.S. patent application Ser. No. 15/890,117 filed on Feb. 6, 2018, which is a continuation of U.S. patent application Ser. No. 15/417,496, filed on Jan. 27, 2017, which claims priority to Provisional Patent Application Ser. No. 62/395,765, filed Sep. 16, 2016, and Provisional Patent Application Ser. No. 62/423,082, filed on Nov. 16, 2016, all of which are herein incorporated by reference.
- Implementations of the present disclosure generally relate to the manufacture of semiconductor devices. More specifically, implementations described herein relate to methods for source/drain engineering.
- Integrated circuits are formed in and on silicon and other semiconductor substrates. In the case of single crystal silicon, substrates are made by growing an ingot from a bath of molten silicon, and then sawing the solidified ingot into multiple substrates. An epitaxial silicon layer may then be formed on the monocrystalline silicon substrate to form a defect-free silicon layer that may be doped or undoped. Semiconductor devices, such as transistors, are manufactured from the epitaxial silicon layer. The electrical properties of the formed epitaxial silicon layer will generally be better than the properties of the monocrystalline silicon substrate.
- Group IV elements may be advantageous in certain applications for forming silicon-based devices. For example, Group IV elements may serve as a source/drain region in sub-10 nm Fin Field Effect Transistor (FinFET) devices due to the low contact resistance, superior electron mobility and lower operation voltage. However, there are major challenges in preparing a substrate for Group IV source/drain growth. Surfaces of the monocrystalline silicon and the epitaxial silicon layer are susceptible to contamination when exposed to typical fabrication facility ambient conditions, and there might be a few atomic layers of damaged Si from previous process steps. For example, a native oxide layer may form on the monocrystalline silicon surface prior to deposition of the epitaxial layer. Additionally, contaminants present in the ambient environment may deposit on the monocrystalline surface and may come from previous process steps. The presence of a native oxide layer or contaminants on the monocrystalline silicon surface negatively affects the quality of an epitaxial layer subsequently formed on the monocrystalline surface. While present cleaning methods remove some of the native oxides and contaminants from the monocrystalline silicon surface, some contaminants may still remain.
- Therefore, there is a need for a method for integrated cleaning a substrate surface and subsequent recessing prior to performing an epitaxial deposition process.
- Implementations described herein generally provide a method of processing a workpiece. The method of processing the workpiece includes disposing the workpiece in a processing volume. The workpiece includes a substrate. The substrate includes a source/drain region disposed on the substrate. The method of disposing a workpiece also includes establishing a low pressure processing environment in the processing volume. The method of disposing a workpiece also includes maintaining the low pressure processing environment while delivering a first gas containing to the processing volume, depositing a salt on the workpiece, heating the substrate to greater than 90° C., purging the processing volume with a second inert gas, and recessing the source/drain regions.
- So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary implementations and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective implementations.
-
FIG. 1 is a flow diagram illustrating operations of a method according to one implementation described herein. -
FIGS. 2A-2C illustrate a schematic, cross-sectional view of a device structure depicting stages of fabrication in accordance with the method ofFIG. 1 . - To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one implementation may be beneficially incorporated in other implementations without further recitation.
- Implementations of the present disclosure generally relate to methods for forming semiconductor devices. More specifically, methods are described for sub-10 nm cleaning and recessing substrates in preparation for precise Group IV source/drain growth in FinFET devices.
-
FIG. 1 is a flow diagram illustrating amethod 100 for cleaning and recessing substrates in preparation for precise source/drain deposition comprising Group IV elements on a silicon substrate.FIGS. 2A-2C depict stages of fabrication of a device structure in accordance with themethod 100 ofFIG. 1 . Themethod 100 is described below in accordance with operations of cleaning and recessing a substrate as illustrated inFIGS. 2A-2C . - As illustrated in
FIG. 1 , a workpiece, including asubstrate 202 with adevice 200 that has a source/drain region formed on the substrate, is disposed in a processing volume atstep 25. For example, the device may havesub-10 nm trenches FIG. 2 , and may be pre-cleaned prior to performing themethod 100. The pre-cleaning may include any conventional wet or dry cleaning method. - As shown in
FIG. 2A , the workpiece has adevice 200 that includes adielectric material 204 disposed on asubstrate 202, a pre source/drain region 216, afin layer 210 disposed on the pre source/drain region 216, adummy gate 208, andcontaminants 206. In one implementation, the pre source/drain region 216 may be disposed on thesubstrate 202 and within thedielectric material 204. Thedummy gate 208 may be disposed on thefin layer 210. Thecontaminants 206 may be disposed on the pre source/drain region 216 and thefin layer 210. Thesubstrate 202 may be a silicon-containing substrate. Thesubstrate 202 may further comprise germanium (Ge), carbon (C), boron (B), phosphorous (P), or other materials that may be co-grown, doped and/or associated with silicon materials. Thesubstrate 202 may be part of a device, such as a fin shaped field effect transistor (FinFET) device. In one implementation, the FinFET device may be sized for the 10 nm node. - The
dielectric material 204, such as a shallow trench isolation (STI) oxide, may comprise one or more of silicon oxide (SiO), silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials that may be used to form a dielectric material. Thedielectric material 204 may be deposited by various deposition processes. For example, thedielectric material 204 may be deposited by a chemical vapor deposition (CVD) process, which may be plasma enhanced. Thecontaminants 206 may include native oxide and dangling silicon bonds saturated with hydrogen such as SiO2 or GeO2. Thedummy gate 208 may comprise silicon nitride (SiN). The pre source/drain region 216 may comprise silicon and may further comprise germanium (Ge), carbon (C), boron (B), phosphorous (P), or other materials that may be co-grown, doped and/or associated with silicon materials. - The workpiece, including the
device 200, may be placed in an inductively coupled plasma (ICP) plasma reactor chamber. Suitable chambers include the CENTRIS® or MESA® chamber available from Applied Materials, Inc. of Santa Clara, Calif. Chambers available from other manufacturers may also be used to practice implementations described herein. A low pressure processing environment may be established within the chamber atstep 50 ofFIG. 1 . The low pressure processing environment may be maintained (atstep 75 ofFIG. 1 ) while each of the operations ofmethod 100 proceed. Atoperation 110 ofFIG. 1 , a first gas may be delivered over the workpiece, includingsubstrate 202 in the processing volume. The first gas may be a hydrogen argon (H2Ar) gas mixture. The first gas may be inert. In one implementation, the ion energy is controlled with low RF source power between 200-800 watts or plasma pulsing. The hydrogen gas may be flowed at a rate of between 10-500 sccm, and the argon may be flowed at a rate of between 300-1000 sccm. While the first gas is delivered, the pressure of the processing volume may be maintained between 5 mT to 50 mT. The temperature of the processing volume may be between 20° C. and 40° C., and the ion energy may be less than 50 electronvolt (eV). The first gas mixture producing the low energy ions may advantageously penetrate thenative oxide contaminants 206 located withintrenches device 200. - At
operation 120 ofFIG. 1 , while a higher pressure environment is maintained, a salt is deposited on the pre source/drain region 216. In one implementation, a NH3/NF3/Ar gas mixture is delivered to the processing volume to react with the generated plasma and form a NH4F salt. The NH4F salt is deposited on the pre source/drain region 216. Atoperation 130, the workpiece is heated to greater than 90° C. In one implementation, the workpiece is heated to greater than 90° C. for greater than 1 minute. Heating the workpiece may remove thecontaminants 206 to expose aclean silicon surface 222, as shown inFIG. 2B . In one implementation, the NH4F salt may react with and remove thenative oxide contaminants 206 from the pre source/drain region 216 andfin layer 210. The NH4F salt may expose theunderlying silicon surface 222 in the pre source/drain region 216 without damaging the underlying silicon surface. In one implementation, the NH3/NF3/Ar gas mixture is delivered to the processing volume which is maintained at a pressure of 200-900 mT. The continuous mode RF power may be maintained between 200-400 watts. The argon is flowed at a rate of 500-1200 sccm, the ammonia (NH3) is flowed at a rate of 10-100 sccm, and the NF3 is flowed at a rate of 5-20 sccm. - At
operation 140, while the low pressure environment is maintained, the processing volume and gas lines are purged using a second inert gas mixture. The second inert gas may be a H2/Ar plasma mixture. The second inert gas mixture advantageously removes any residual ammonia (NH3) inside the chamber and gas line providing for a clean surface in preparation for subsequent processing operations. - As shown in
FIG. 1 , atoperation 150, while the low pressure environment is maintained, the pre source/drain region 216 is recessed by etching. In one implementation, thefin layer 210 may also be recessed. In one implementation, the width of thefin layer 210 is reduced about between 1-2 nm. Suitable methods of etching the pre source/drain region 216 or thefin layer 210 or a combination of both include any suitable etching process, such as anisotropic dry etching. In one implementation, argon (Ar), hydrogen (H), and/or chlorine (CI) may be used as precursors to produce an etchant plasma for etching thefin layer 210. In another implementation, a H2/Cl2/Ar plasma is used for etching the pre source/drain region 216. The plasma mixture may function to volatilize the pre source/drain region 216 such that a portion may be removed. In one implementation, the pre source/drain region 216 is etched 1-2 nm or at a rate between 0.5 nm/min-3 nm/min. In one implementation, the plasma ion energy is less than 20 eV with plasma pulsing, the pressure of the processing volume may be maintained between 5-50 mTorr, the temperature is between 30° C.-50° C., and the RF power is between 500-600 watts. This step may use very low ion energy which is controlled by RF source pulsing without bias power. The argon may be flowed at a rate between 100-500 sccm, the hydrogen may be flowed at a rate between 50-300 sccm, and the chlorine may be flowed at a rate between 10-100 sccm. In one implementation, the ratio of Cl:H:Ar may be between 1:5:10 to 1:3:5. The low energy H2/Cl2/Ar plasma pulsing provides for precise control in the nm scale while reducing silicon-silicon lattice damage. The integrated clean and recess process provides for a source/drain region free of carbon and oxide contaminants while reducing the silicon-silicon lattice damage in preparation for subsequent processing. - As shown in
FIG. 2C , a source/drain extension 212 may be deposited over the cleaned and recessed pre source/drain region 216. In one implementation, the source/drain extension 212 is silicon arsenide (SiAs). A source/drain layer 214 may be deposited on the source/drain extension 212. In one implementation, the source/drain layer 214 is silicon phosphide (SiP). - The integrated clean and recess process prepares the
device 200 for subsequent processing while maintaining a low pressure environment. More specifically, the resulting source/drain region may be free of contaminants and/or defects, may has a desired shape, and may be prepared for subsequent epitaxial growth. Thedevice 200 may undergo additional processing steps within the same cluster tool. Use of a single apparatus containing various processing chambers allows for the various operations of themethod 100 ofFIG. 1 to occur while maintaining a low pressure environment. More specifically, the low pressure environment need not be broken during transfer to an epitaxial chamber for source/drain extension 212 and source/drain layer 214 growth. In one implementation, additional processing may include replacing thedummy gate 208 with a metal gate. - Thus, methods described for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices are provided. Benefits of this disclosure include precise fin size control in devices, such as sub-10 nm FinFET devices, and increased overall device yield.
- While the foregoing is directed to implementations of the present disclosure, other and further implementations of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (21)
1. A method of processing a workpiece, comprising:
flowing a first gas mixture into a processing chamber;
forming a first plasma from the first gas mixture;
exposing the workpiece to the first plasma, wherein the workpiece comprises:
a substrate comprising a source/drain region; and
a fin layer extending from a surface of the source/drain region; and
depositing a salt on one or more surfaces of the source/drain region and the fin layer.
2. The method of claim 1 , wherein the first gas mixture comprises NH3 and NF3.
3. The method of claim 1 , wherein source/drain region is disposed between a plurality of dielectric material features.
4. The method of claim 1 , further comprising:
flowing a second gas mixture into the processing chamber before flowing the first gas mixture, the second gas mixture comprising hydrogen gas and argon gas;
forming a second plasma of the second gas mixture; and
exposing the workpiece to the second plasma before exposing the workpiece to the first plasma.
5. The method of claim 1 , wherein the fin layer comprises silicon.
6. The method of claim 1 , further comprising:
heating the workpiece to about 90° C. or more; and
purging the processing chamber of the first gas mixture by flowing a purge gas mixture thereinto.
7. The method of claim 6 , wherein heating the workpiece to about 90° C. or more removes the salt or reaction byproducts of the salt from the one or more surfaces of the source/drain region and the fin layer.
8. The method of claim 7 , wherein depositing the salt and removing the salt or reaction byproducts of the salt cleans one or both of a native oxide or contaminates disposed on the one or more surfaces of the source/drain region and the fin layer.
9. The method of claim 8 , wherein the workpiece further comprises a dielectric material layer disposed on the fin layer.
10. The method of claim 9 , wherein the dielectric material layer is a dummy gate.
11. The method of claim 6 , further comprising:
flowing an etchant gas mixture into the processing chamber;
forming an etching plasma from the etchant gas mixture; and
exposing the workpiece to the etching plasma to reduce a width of the fin layer.
12. The method of claim 11 , wherein exposing the workpiece to the etching plasma reduces the width of the fin layer by up to about 2 nm.
13. The method of claim 11 , wherein the etchant gas mixture comprises chlorine.
14. The method of claim 1 , further comprising:
depositing an Si:As layer on one or more surfaces of the source/drain region.
15. The method of claim 14 , further comprising:
depositing an Si:P layer on one or more surfaces of the source/drain region.
16. A method of processing a substrate, comprising:
flowing a first processing gas mixture comprising NH3 and NF3 into a processing chamber;
forming a first plasma from the first processing gas mixture;
exposing the substrate to the first plasma, wherein the substrate comprises:
a source/drain region disposed between a plurality of dielectric material features; and
a fin layer extending from a surface of the source/drain region;
depositing a salt on one or more surfaces of the source/drain region and the fin layer; and
removing one or both of the salt or reaction byproducts of the salt from the one or more surfaces of the source/drain region and the fin layer, comprising:
heating the substrate to 90° C. or more; and
purging the processing chamber of the first processing gas mixture by flowing a purging gas thereinto.
17. The method of claim 16 , wherein depositing the salt on the one or more surfaces of the source/drain region and the fin layer and removing one or both of the salt or reaction byproducts of the salt and the one or more surfaces of the source/drain region and the fin layer includes removing a native oxide layer formed on the one or more surfaces of the source/drain region and the fin layer.
18. The method of claim 16 , further comprising:
flowing a second processing gas mixture comprising H2 and Cl2 into the processing chamber;
forming a second plasma from the second processing gas mixture; and
exposing the substrate to the second plasma.
19. The method of claim 18 , wherein exposing the substrate to the second plasma removes a material thickness of up to about 2 nm from the one or more surfaces of the source/drain region and the fin layer.
20. The method of claim 19 , further comprising:
depositing an Si:P layer on one or more surfaces of the source/drain region.
21. The method of claim 5 , wherein the fin layer further comprises at least one of germanium, carbon, boron, and phosphorous.
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US16/148,430 US20190035623A1 (en) | 2016-09-16 | 2018-10-01 | Integrated system and method for source/drain engineering |
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US11355620B2 (en) * | 2018-10-31 | 2022-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming same |
US11177346B2 (en) | 2019-01-07 | 2021-11-16 | Samsung Electronics Co., Ltd. | Semiconductor device |
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US20180174825A1 (en) | 2018-06-21 |
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US10090147B2 (en) | 2018-10-02 |
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WO2018052475A1 (en) | 2018-03-22 |
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