US20190019915A1 - Method of manufacturing a 3 color led integrated si cmos driver wafer using die to wafer bonding approach - Google Patents
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
- H01L31/1844—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
- H01L31/1848—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P comprising nitride compounds, e.g. InGaN, InGaAlN
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
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- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
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Abstract
Description
- The present disclosure relates to light-emitting diodes (LEDs). The present disclosure is particularly applicable to semiconductor-based LEDs.
- Red, green, and blue (RGB) color LED integration on silicon (Si) complementary metal-oxide-semiconductor (CMOS) wafers are highly desirable for producing low power and high brightness micro displays for use in augmented reality (AR), virtual reality (VR), video projection, and military applications. Known processes for integrating 3 color LEDs on Si CMOS driver circuits include transfer methods using pick & place, die-to-die bonding using micro-bump technology, and 3 color LED layer transfer on glass substrates and Si wafers (LED metallization after layer transfer). However, the known processes suffer from light re-absorption issues leading to poor color efficiency as well as substrate and color die material constraints.
- A need therefore exists for methodology enabling RGB LED integration with a Si CMOS driver wafer without poor color efficiency or material constraints and the resulting device.
- An aspect of the present disclosure is method of forming an integrated RGB LED and Si CMOS driver wafer.
- Another aspect of the present disclosure is an integrated RGB LED and Si CMOS driver wafer.
- Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
- According to the present disclosure, some technical effects may be achieved in part by a method including: providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal transparent conductive oxide (TCO) layer over each first and second color die and on a side surface of each second color die and oxide; forming a plasma-enhanced chemical vapor deposition (PECVD) oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.
- Aspects of the present disclosure include each first and second color die and the CMOS wafer being a known good die (KGD). Other aspects include each first color die including two LEDs and each second color die including one LED or each first color die including the one LED and each second color die including the two LEDs. Further aspects include wherein each first or second color die includes the two LEDs, each first or second color die further includes blue and green, green and red, or blue and red indium gallium nitride (InGaN) LEDs laterally separated within an oxide layer, a gallium nitride (GaN) buffer layer, and a substrate. Another aspect includes wherein each first or second color die includes the one LED and the one LED is red, each first or second color die includes an aluminum indium gallium phosphide (AlInGaP) LED within the oxide layer, a gallium phosphide (GaP) buffer layer, and the substrate. Further aspects include wherein each first or second color die includes the one LED and the one LED is blue or green, each first or second color die further includes an InGaN LED within the oxide layer, the GaN buffer layer, and the substrate. Other aspects include bonding and electrically connecting each first and corresponding second color die by: filling a first trench formed between each pair of adjacent first color dice with the first oxide; planarizing the first oxide down to the substrate of the first color dice; planarizing the substrate of the first color dice and first oxide down to the GaN or GaP buffer layer of the first color dice; etching a contact hole through the GaN or GaP buffer and oxide layers of each first color die for each LED of each second color die; forming a conformal nitride liner on sidewalls of each contact hole; filling each contact hole with a metal; planarizing the metal down to the GaN or GaP buffer layer of the first color dice; and connecting each LED of each second color die to a corresponding metal contact. Further aspects include removing the portion of each second color die by: planarizing the substrate of the second color dice and second oxide down to the GaN or GaP buffer layer of the second color dice; forming a mask over the two LEDs or one LED of each second color die and oxide and a portion of the GaN or GaP buffer and oxide layers on opposite sides of the one LED or two LEDs; and etching an exposed portion of the GaN or GaP buffer and oxide layers down to the GaN or GaP buffer layer of the first color dice. Additional aspects include the substrate being Si, sapphire, or silicon carbide (SiC).
- Another aspect of the present disclosure is a device including: a plurality of first color die over a CMOS wafer, each first color die laterally separated with a first oxide and electrically connected to the CMOS wafer; one or two metal contacts through each first color die down to the CMOS wafer; a second color die and an adjacent second oxide above each first color die and oxide, respectively, each second color die bonded to a first color die and electrically connected to the CMOS wafer through the bonded first color die; a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; and a planar PECVD layer over the CMOS wafer.
- Aspects of the device include each first color die including two LEDs and each second color die including one LED or each first color die including the one LED and each second color die including the two LEDs. Other aspects include wherein each first or second color die includes the two LEDs, each first and second color die further includes blue and green, green and red, or blue and red InGaN LEDs laterally separated within an oxide layer, a GaN buffer layer, and a substrate. Further aspects include wherein each first or second color die includes the one LED and the one LED is red, each first and second color die further includes an AlInGaP LED within the oxide layer, a GaP buffer layer, and the substrate. Other aspects include wherein each first or second color die includes the one LED and the one LED is blue or green, each first and second color die further includes an InGaN LED within the oxide layer, the GaN buffer layer, and the substrate. Another aspect includes the GaN or GaP buffer and oxide layers of each second die not covering an LED of a bonded first die. Additional aspects include a third color die and an adjacent third oxide above each second color die and oxide, respectively, each third color die bonded to a second color die and electrically connected to the CMOS wafer through the bonded second color die; and a conformal TCO layer over each third color die and on a side surface of each third color die and oxide. Other aspects include wherein the first, second, and third color dice each including blue, green, or red LEDs, and none of the first and second, first and third, or second and third color dice including a same color LED. Further aspects include wherein each first, second, or third die includes the blue or green LED, each first, second, or third die further includes a blue or green InGaN LED within an oxide layer, a GaN buffer layer, and a substrate, and wherein each first, second, or third die includes the red LED, each first, second, or third die further includes a red AlInGaP LED within an oxide layer, a GaP buffer layer, and a substrate. Another aspect includes the substrate being Si, sapphire, or SiC. Additional aspects include the GaN or GaP buffer and oxide layers of each of the third color die not covering an LED of each of the first and second color dice. Other aspects include each first, second, and third color die and the CMOS wafer being a KGD. Further aspects include the first, second, and third oxide being spin-on glass or low-temperature plasma-enhanced chemical vapor deposition oxide (LT-PECVD).
- A further aspect of the present disclosure is a method including: providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; providing a third color die above each second color die, each third color die being separated from each other with a third oxide, bonded to a second color die, and electrically connected to the CMOS wafer through the bonded second color die; removing a portion of each second and each third color die to expose a portion of each first and second color die, respectively; forming a conformal TCO layer over each first, second, and third color die and on a side surface of each second and third color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.
- Aspects of the present disclosure include each first, second, and third color die and the CMOS wafer being a KGD. Other aspects include the first, second, and third color dice each including blue, green, or red LEDs, and none of the first and second, first and third, or second and third color dice comprise a same color LED. Further aspects include wherein each first, second, and third color die includes the blue or green LED, each first, second, and third color die further includes the blue or green InGaN LED within an oxide layer, a GaN buffer layer, and a substrate. Another aspect includes wherein each first, second, or third color die includes the red LED, each first, second, or third color die further includes a red AlInGaP LED within an oxide layer, a GaP buffer layer, and a substrate. Other aspects include bonding and electrically connecting each first and corresponding second color die by: filling a first trench formed between each pair of adjacent first color dice with the first oxide; planarizing the first oxide down to the substrate of the first color dice; planarizing the substrate of the first color dice and first oxide down to the GaN or GaP buffer layer of the first color dice; etching two contact holes laterally separated through the GaN or GaP buffer and oxide layers of each first color die; forming a conformal nitride liner on sidewalls of each of the two contact holes; filling the two contact holes with a metal; planarizing the metal down to the GaN or GaP buffer layer of the first color dice; and connecting the blue, green, or red LED of each second color die to one of the two metal contacts.
- Further aspects include bonding and electrically connecting each second and corresponding third color die by: filing a second trench formed between each pair of adjacent second color dice with the second oxide; planarizing the second oxide down to the substrate of the second color dice; planarizing the substrate of the second color dice and second oxide down to the GaN or GaP buffer layer of the second color dice; etching a contact hole through the GaN of GaP buffer and oxide layers of each second color die over an open metal contact of the two metal contacts; forming a conformal nitride liner on sidewalls of the contact hole; filing the contact hole with a metal; planarizing the metal down to the GaN or GaP buffer layer of the second color dice; and connecting the blue, green, or red LED of each third color die to the metal contact. Another aspect includes removing the portion of each second and each third color die by: planarizing the substrate of the third color dice and oxide down the GaN or GaP buffer layer of the third color dice; forming a first mask over the blue, green, or red LED of each third color die and oxide and a portion of the GaN or GaP buffer and oxide layers on opposite sides of the blue, green, or red LED; etching an exposed portion of the GaN or GaP buffer and oxide layers of the third color dice down to the GaN or GaP buffer layer of the second color dice; forming a second mask over the blue, green, or red LED of each third and second color die and third oxide, the portion of the GaN and GaP buffer and oxide layers, and a portion of the GaN or GaP buffer and oxide layers on opposite sides of the blue, green, or red LED of each second color die; and etching an exposed portion of the GaN or GaP buffer and oxide layers of the second color die down to the GaN or GaP buffer of the first color dice. Further aspects include the substrate being silicon Si, sapphire, or SiC.
- Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
- The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
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FIGS. 1 through 11 schematically illustrate cross-sectional views of a process flow for forming an integrated RGB LED and Si CMOS driver wafer, in accordance with an exemplary embodiment; -
FIGS. 12 through 22 schematically illustrate cross-sectional views of a process flow for forming an integrated RGB LED and Si CMOS driver wafer, in accordance with another exemplary embodiment; and -
FIGS. 23 through 38 schematically illustrate cross-sectional views of a process flow for forming an integrated RGB LED and Si CMOS driver wafer, in accordance with a further exemplary embodiment. - In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
- The present disclosure addresses and solves the current problems of color inefficiency, substrate size, substrate and color die material constraints, high costs, and low yields attendant upon integrating RGB color LEDs on the same CMOS driver wafer. The problems are solved, inter alia, by bonding one or two color LED dice formed of the same or different materials on a Si CMOS driver wafer using only known good LED dice on known good Si CMOS dice.
- Methodology in accordance with embodiments of the present disclosure includes providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer. A second color die is provided above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die. A portion of each second color die is removed to expose a portion of each bonded first color die and a TCO layer is formed over each first and second color die and on a side surface of each second color die and oxide. A PECVD oxide layer is formed over the CMOS wafer and planarized.
- Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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FIGS. 1 through 11 schematically illustrate cross-sectional views of a process flow for forming an integrated RGB LED and Si CMOS driver wafer, in accordance with an exemplary embodiment. Adverting toFIG. 1 , a plurality of laterally separated color die 101, e.g., color die 103 and 105, are each bonded to aCMOS wafer 107 that includes asubstrate 109, source/drain (S/D)regions 111,gates 113, shallow trench isolation (STI)structures 115, and anoxide layer 117. Each color die 101 and theCMOS wafer 107 are KGD and thesubstrate 109 may be formed, e.g., of Si or a non-Si material, e.g., sapphire. Each color die 101 is laterally separated by atrench 119 and includes the laterally separatedLEDs oxide layer 125, aGaN buffer layer 127, and asubstrate 129, e.g., formed of Si, sapphire, or SiC. EachLED CMOS wafer 107 via ametal contact 131 within theoxide layer 117 and theLEDs LEDs - The
trench 119 is then filled with anoxide 201, e.g., formed of spin-on glass or LT-PECVD, and theoxide 201 is planarized, e.g., by chemical mechanical polishing (CMP), down to thesubstrate 129, as depicted inFIG. 2 . Adverting toFIG. 3 , theoxide 201 and thesubstrate 129 are planarized, e.g., by CMP, down to theGaN buffer layer 127, forming theoxide 201′. A contact hole (not shown for illustrative convenience) is then formed through the GaN buffer andoxide layers conformal nitride liner 401 is formed on the sidewalls of each contact hole; each contact hole is filled with ametal 403, e.g., copper (Cu), tungsten (W), or aluminum (Al); and themetal 403 is planarized, e.g., by CMP, down to theGaN buffer layer 127, as depicted inFIG. 4 . - Adverting to
FIG. 5 , a plurality of color die 501, e.g., color die 503 and 505, are each bonded to acolor die 101, e.g., color die 103 and 105, respectively. Like each color die 101, each color die 501 is a KGD and is laterally separated from each other color die 501 by atrench 507. Each color die 501 includes oneLED 509 within anoxide layer 511, a GaN orGaP buffer layer 513, and asubstrate 515, e.g., formed of Si, sapphire, or SiC, and eachLED 509 is electrically connected to theCMOS wafer 107 via themetal contacts LED 509 is red, each color die 501 includes anAlInGaP LED 509 and aGaP buffer layer 513, but in the instance where theLED 509 is blue or green, each color die 501 includes anInGaN LED 509 and aGaN buffer layer 513. By way of example, and not by way of limitation, theLED 509 is red in this instance and, therefore, each color die 501 includes anAlInGaP LED 509 and aGaP buffer layer 513. - Next, the
trench 507 is filled with anoxide 601, e.g., formed of spin-on glass or LT-PECVD, and theoxide 601 is planarized, e.g., by CMP, down to thesubstrate 515, as depicted inFIG. 6 . Adverting toFIG. 7 , theoxide 601 and thesubstrate 515 are planarized, e.g., by CMP, down to the GaP orGaN buffer layer 513, forming theoxide 601′. A portion of each color die 501 is then removed to expose a portion of each bonded color die 101 below, as depicted inFIG. 8 . The portion of each color die 501 may be removed, e.g., by forming a mask (not shown for illustrative convenience) over eachLED 509, theoxide 601′, and portions of the GaP orGaN buffer layer 513 andoxide layer 511 on opposite sides of theLED 509. The exposed portion of the GaP orGaN buffer layer 513 andoxide layer 511 is then etched, e.g., by a dry etch or an inductively coupled plasma (ICP) etch, down to theGaN buffer layer 127 of each color die 101, forming the GaP orGaN buffer layer 513′ and theoxide layer 511′. - Adverting to
FIG. 9 , aconformal TCO layer 901 is formed, e.g., to a thickness of 100 nm to 150 nm, over the each color die 101 and 501. A portion of theTCO layer 901 may then be removed over theoxide 601′ to make the subsequent dicing of the bondeddice TCO layer 901′, as depicted inFIG. 10 . Adverting toFIG. 11 , aPECVD oxide layer 1101 is formed over theCMOS wafer 107, for example, to a thickness of 0.5 μm to 1 μm, e.g., at least above an upper surface of theTCO layer 901′, and then planarized, e.g., by CMP, to complete the rest of the packaging process. Alternatively, thePECVD oxide layer 1101 may be formed over theCMOS wafer 107 without first removing a portion of theTCO layer 901. -
FIGS. 12 through 22 schematically illustrate cross-sectional views of a process flow for forming an integrated RGB LED and Si CMOS driver wafer, in accordance with another exemplary embodiment. The process steps ofFIGS. 12 through 22 are similar to the process steps ofFIGS. 1 through 11 , except each bottom color die in the bonded stack includes only 1 LED and each top color die includes two LEDs. Adverting toFIG. 12 , a plurality of laterally separated color die 1201, e.g., color die 1203 and 1205, are bonded to theCMOS wafer 107 ofFIG. 1 . Similar to the color die 101 ofFIG. 1 , each color die 1201 is a KGD and is laterally separated from each other color die 1201 by atrench 1207. Also similar to each color die 501 ofFIG. 5 , each color die 1201 includes one LED 1209 within anoxide layer 1211, a GaN orGaP buffer layer 1213, and asubstrate 1215, e.g., formed of Si, sapphire, or SiC, and each LED 1209 is electrically connected to theCMOS wafer 107 via ametal contact 131. In the instance where the LED 1209 is red, each color die 1201 includes an AlInGaP LED 1209 and aGaP buffer layer 1213, but in the instance where the LED 1209 is blue or green, each color die 1201 includes an InGaN LED 1209 and aGaN buffer layer 1213. By way of example, and not by way of limitation, the LED 1209 is red in this instance and, therefore, each color die 501 includes an AlInGaP LED 1209 and aGaP buffer layer 1213. - Next, the
trench 1207 is filled with anoxide 1301, e.g., formed of spin-on glass or LT-PECVD, and theoxide 1301 is planarized, e.g., by CMP, down to thesubstrate 1215, as depicted inFIG. 13 . Adverting toFIG. 14 , theoxide 1301 and thesubstrate 1215 are planarized, e.g., by CMP, down to the GaP orGaN buffer layer 1213, forming theoxide 1301′. Two contact holes (not shown for illustrative convenience) are then formed through the GaP or GaN buffer andoxide layers conformal nitride liner 1501 is formed on the sidewalls of each contact hole; each contact hole is filled with ametal 1503, e.g., Cu, W, or Al; and themetal 1503 is planarized, e.g., by CMP, down to the GaP orGaN buffer layer 1213, as depicted inFIG. 15 . - Adverting to
FIG. 16 , a plurality of color die 1601, e.g., color die 1603 and 1605, are each bonded to acolor die 1201, e.g., color die 1203 and 1205, respectively. Like color die 1201, each color die 1601 is a KGD and is laterally separated from each other color die 1601 by atrench 1607. Similar to the color die 101 ofFIG. 1 , each color die 1601 includes two laterally separatedLEDs oxide layer 1613, aGaN buffer layer 1615, and asubstrate 1617, e.g., formed of Si, sapphire, or SiC. Similar to theLEDs FIG. 1 , theLEDs LEDs - Next, the
trench 1607 is filled with anoxide 1701, e.g., formed of spin-on glass or LT-PECVD, and theoxide 1701 is planarized, e.g., by CMP, down to thesubstrate 1617, as depicted inFIG. 17 . Adverting toFIG. 18 , theoxide 1701 and thesubstrate 1617 are then planarized, e.g., by CMP, down to theGaN buffer layer 1615, forming theoxide 1701′. A portion of each color die 1601 is then removed to expose a portion of each bonded color die 1201 below, as depicted inFIG. 19 . The portion of each color die 1601 may be removed, e.g., by forming a mask (not shown for illustrative convenience) over theLEDs oxide 1701′, and portions of theGaN buffer layer 1615 andoxide layer 1613 on opposite sides of theLEDs GaN buffer layer 1615 andoxide layer 1611 is then etched, e.g., by a dry etch or an ICP etch, down to the GaP orGaN buffer layer 1213 of each color die 1201, forming the GaN buffer andoxide layers 1615′ and 1613′, respectively. - Adverting to
FIG. 20 , aconformal TCO layer 2001 is formed, e.g., to a thickness of 100 nm to 150 nm, over each color die 1201 and 1601. A portion of theTCO layer 2001 may then be removed over theoxide 1701′ to make the subsequent dicing of the bonded color dies 1601 and 1201 easier, thereby forming theTCO layer 2001′, as depicted inFIG. 21 . Adverting toFIG. 22 , aPECVD oxide layer 2201 is formed over theCMOS wafer 107, for example, to a thickness of 0.5 μm to 1 μm, e.g., at least above an upper surface of theTCO layer 2201′, and then planarized, e.g., by CMP, to complete the rest of the packaging process. Alternatively, thePECVD oxide layer 2201 may be formed over theCMOS wafer 107 without first removing a portion of theTCO layer 2201. -
FIGS. 23 through 38 schematically illustrate cross-sectional views of a process flow for forming an integrated RGB LED and Si CMOS driver wafer, in accordance with a further exemplary embodiment. The process steps ofFIGS. 23 through 38 are also similar to the process steps ofFIGS. 1 through 11 andFIGS. 12 through 22 , except each stacked color die in this instance includes only 1 LED. Adverting toFIG. 23 , a plurality of laterally separated color die 2301, e.g., color die 2303 and 2305, are bonded to theCMOS wafer 107 ofFIG. 1 , which again includes asubstrate 109, S/D regions 111,gates 113,STI structures 115, and anoxide layer 117. Similar to color die 101 ofFIG. 1 , each color die 2301 is a KGD and is laterally separated by atrench 2307. Similar to color die 1201 ofFIG. 12 , each color die 2301 includes oneLED 2309 within anoxide layer 2311, a GaN orGaP buffer layer 2313, and asubstrate 2315, e.g., formed of Si, sapphire, or SiC, and eachLED 2309 is electrically connected to theCMOS wafer 107 via ametal contact 131. In the instance where theLED 2309 is blue or green, each color die 2301 includes an InGaN LED 1209 and aGaN buffer layer 2313, but in the instance where theLED 2309 is red, each color die 2301 includes anAlInGaP LED 2309 and aGaP buffer layer 2313. By way of example, and not by way of limitation, theLED 2309 is blue in this instance and, therefore, each color die 2301 includes anInGaN LED 2309 and aGaN buffer layer 2313. - Next, the
trench 2307 is filled with anoxide 2401, e.g., formed of spin-on glass or LT-PECVD, and theoxide 2401 is planarized, e.g., by CMP, down to thesubstrate 2315, as depicted inFIG. 24 . Adverting toFIG. 25 , theoxide 2401 and thesubstrate 2315 are planarized, e.g., by CMP, down to the GaN orGaP buffer layer 2313, forming theoxide 2401′. Two contact holes (not shown for illustrative convenience) are then formed through the GaN or GaP buffer andoxide layers conformal nitride liner 2601 is formed on the sidewalls of each contact hole; each contact hole is filled with ametal 2603, e.g., Cu, W, or Al; and themetal 2603 is planarized, e.g., by CMP, down to the GaN orGaP buffer layer 2313, as depicted inFIG. 26 . - Adverting to
FIG. 27 , a plurality of color die 2701, e.g., color die 2703 and 2705, are each bonded to acolor die 2301, e.g., color die 2303 and 2305, respectively. Each color die 2701 is also a KGD and is laterally separated by atrench 2707. Similar to each color die 2301, each color die 2701 includes oneLED 2709 within anoxide layer 2711, a GaN orGaP buffer layer 2713, and asubstrate 2715, e.g., formed of Si, sapphire, or SiC, and eachLED 2709 is electrically connected to theCMOS wafer 107 via ametal contact 2603 and ametal contact 131. In the instance where theLED 2709 is blue or green, each color die 2701 includes anInGaN LED 2709 and aGaN buffer layer 2713, but in the instance where theLED 2709 is red, each color die 2701 includes anAlInGaP LED 2709 and aGaP buffer layer 2713. By way of example, and not by way of limitation, theLED 2709 is green in this instance and, therefore, each color die 2701 includes anInGaN LED 2709 and aGaN buffer layer 2713. - Next, the
trench 2707 is filled with anoxide 2801, e.g., formed of spin-on glass or LT-PECVD, and theoxide 2801 is planarized, e.g., by CMP, down to thesubstrate 2715, as depicted inFIG. 28 . Adverting toFIG. 29 , theoxide 2801 and thesubstrate 2715 are planarized, e.g., by CMP, down to the GaN orGaP buffer layer 2713, forming theoxide 2801′. A contact hole (not shown for illustrative convenience) is then formed through the GaN or GaP buffer andoxide layers available metal contact 2603; aconformal nitride liner 3001 is formed on the sidewalls of each contact hole; each contact hole is filled with ametal 3003, e.g., Cu, W, or Al; and themetal 3003 is planarized, e.g., by CMP, down to the GaN orGaP buffer layer 2713, as depicted inFIG. 30 . - Adverting to
FIG. 31 , a plurality of color die 3101, e.g., color die 3103 and 3105, are each bonded to acolor die 2701, e.g., color die 2703 and 2705, respectively. Each color die 3101 is also a KGD and is laterally separated by atrench 3107. Similar to each color die 2701, each color die 3101 includes oneLED 3109 within anoxide layer 3111, a GaN orGaP buffer layer 3113, and asubstrate 3115, e.g., formed of Si, sapphire, or SiC, and eachLED 3109 is electrically connected to theCMOS wafer 107 via themetal contacts LED 3109 is red, each color die 3101 includes anAlInGaP LED 3109 and aGaP buffer layer 3113, but in the instance where theLED 3109 is blue or green, each color die 3101 includes anInGaN LED 3109 and aGaN buffer layer 3113. By way of example, and not by way of limitation, theLED 3109 is red in this instance and, therefore, each color die 3101 includes anAlInGaP LED 3109 and aGaP buffer layer 3113. - Next, the
trench 3107 is filled with anoxide 3201, e.g., formed of spin-on glass or LT-PECVD, and theoxide 3201 is planarized, e.g., by CMP, down to thesubstrate 3115, as depicted inFIG. 32 . Adverting toFIG. 33 , theoxide 3201 and thesubstrate 3115 are then planarized, e.g., by CMP, down to the GaP orGaN buffer layer 3113, forming theoxide 3201′. - Adverting to
FIG. 34 , a portion of each color die 3101 is removed to expose a portion of each bonded color die 2701 below. The portion of each color die 3101 may be removed, e.g., by forming a mask (not shown for illustrative convenience) over theLED 3109 of each color die 3101, theoxide 3201′, and portions of the GaP or GaN buffer andoxide layers LED 3109. The exposed portion of the GaP orGaN buffer layer 3113 andoxide layer 3111 is then etched, e.g., by a dry etch or an ICP etch, down to the GaN orGaP buffer layer 2713 of each color die 2701, forming the GaP or GaN buffer andoxide layers 3113′ and 3111′, respectively. - A second mask (not shown for illustrative convenience) may then be formed over the
LEDs oxide 3201′, the GaP orGaN buffer layer 3113′ andoxide layer 3111′, and portions of the GaP or GaN buffer andoxide layers LED 2709. The exposed portion of the GaP orGaN buffer layer 2713 andoxide layer 2711 is then etched, e.g., by a dry etch or an ICP etch, down to the GaN orGaP buffer layer 2313 of each color die 2301, forming the GaN or GaP buffer andoxide layers 2713′ and 2711′, respectively, as depicted inFIG. 35 . - Adverting to
FIG. 36 , aconformal TCO layer 3601 is formed, e.g., to a thickness of 100 nm to 150 nm, over each color die 2301, 2701, and 3101 and theoxide 3201′ as well as the side surfaces of theoxides 3201′ and 2801′. A portion of theTCO layer 3601 may then be removed over theoxide 3201′ to make the subsequent dicing of the bonded dies 3101, 2701, and 2301 easier, thereby forming theTCO layer 3601′, as depicted inFIG. 37 . Adverting toFIG. 38 , aPECVD oxide layer 3801 is formed over theCMOS wafer 107, e.g., to a thickness of 0.5 μm to 1 μm, e.g., at least above an upper surface of theTCO layer 3601′, and then planarized, e.g., by CMP, to complete the rest of the packaging process. Alternatively, thePECVD oxide layer 3801 may be formed over theCMOS wafer 107 without first removing a portion of theTCO layer 3601. - The embodiments of the present disclosure can achieve several technical effects including enabling the use of LEDs made in parallel on smaller substrates, the use of both Si and non-Si substrates, the achievement of lower costs, and the ability to stack and bond different color die materials to maximize color efficiency as well as producing high yielding micro displays by using only known good LED dice on known good Si CMOS wafers. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of semiconductor devices including semiconductor-based LEDs.
- In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
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US6730937B2 (en) | 2000-12-26 | 2004-05-04 | Industrial Technology Research Institute | High resolution and brightness full-color LED display manufactured using CMP technique |
US7492338B2 (en) * | 2003-10-28 | 2009-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
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US8058663B2 (en) | 2007-09-26 | 2011-11-15 | Iii-N Technology, Inc. | Micro-emitter array based full-color micro-display |
US7915080B2 (en) * | 2008-12-19 | 2011-03-29 | Texas Instruments Incorporated | Bonding IC die to TSV wafers |
US8642363B2 (en) | 2009-12-09 | 2014-02-04 | Nano And Advanced Materials Institute Limited | Monolithic full-color LED micro-display on an active matrix panel manufactured using flip-chip technology |
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US9583525B2 (en) | 2015-06-02 | 2017-02-28 | Semiconductor Components Industries, Llc | Die stacked image sensors and related methods |
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