US20180277620A1

US20180277620A1 - Densely stacked metal-insulator-metal capacitor and method of forming the same

Info

Publication number: US20180277620A1
Application number: US15/470,554
Authority: US
Inventors: Effendi Leobandung
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2017-03-27
Filing date: 2017-03-27
Publication date: 2018-09-27
Anticipated expiration: 2037-03-27
Also published as: US10103218B1

Abstract

A metal-insulator-metal capacitor (MIM cap) includes a dielectric layer disposed over a substrate three contacts. A stacked structure of first and second metal layers separated by high-k dielectrics is disposed over the substrate and contacts. Three vias are formed through the structure to expose each of the three contacts. Selective etching is used to create gaps between the various metal layers at the location of the vias and these gaps are filled with an insulator. The vias are then filled with metal and the MIM cap is constructed such that the metal of the first via is electrically connected to the second metal layers and the metal of the second via is electrically connected to the first metal layers.

Description

BACKGROUND

The present invention relates to metal-insulator-metal (MIM) capacitors and, more specifically, to densely stacked MIM capacitors (caps) and methods of forming the same.
Recently, advances have been made in combining metal circuit elements to semiconductor integrated circuits (ICs). These metal circuit elements may provide superior characteristics to circuit elements formed entirely by semiconductors. The use of MIM caps in advanced chips may significantly reduce noise.
As ICs do not offer a lot of surface area upon which metal circuit elements may be formed, it may be desirable to stack multiple MIM layers. However, fabrication of such devices may require many processing steps, such as repeated patterning and etching steps, thereby increasing the complexity and cost associated with the fabrication.

SUMMARY

A metal-insulator-metal capacitor includes a first contact, a second contact, and a third contact, each disposed within a substrate. A first dielectric layer is disposed over the substrate and the first, second, and third contacts. A stacked structure is disposed over the first dielectric layer. The stacked structure includes a repeating pattern of a second metal layer, a first metal layer, and a high-k dielectric disposed between the second metal layer and the first metal layer. A second dielectric layer is disposed over the stacked structure. A first via exposes the first contact through the first dielectric layer, the stacked structure, and the second dielectric layer. The first via is filled with metal. A second via exposes the second contact through the first dielectric layer, the stacked structure, and the second dielectric layer. The second via is filled with metal. A third via exposes the third contact through the first dielectric layer, the stacked structure, and the second dielectric layer. The third via is filled with metal. The second metal layer of each repeating pattern of the stacked structure is connected to the metal filling the first via, insulated from the metal filling the second via, and insulated from the metal filling the third via. The first metal layer of each repeating pattern of the stacked structure is insulated from the metal filling the first via, connected to the metal filling the second via, and insulated from the metal filling the third via.
A method for forming a metal-insulator-metal capacitor includes disposing a first dielectric layer on a substrate having a first contact, a second contact, and a third contact disposed therein. A stacked structure is disposed over the first dielectric layer. The stacked structure includes a repeating pattern of a second metal layer, a first metal layer, and a high-k dielectric disposed between the second metal layer and the first metal layer. A second dielectric layer is disposed over the stacked structure. A first via is created through the second dielectric layer, the stacked structure, and the first dielectric layer to expose the first contact. A second via is created through the second dielectric layer, the stacked structure, and the first dielectric layer to expose the second contact. A third via is created through the second dielectric layer, the stacked structure, and the first dielectric layer to expose the third contact. The first metal layers of the stacked structure are selectively etched through the first via and the third via to create ring-shaped voids. The ring-shaped voids of the first via and the third via are filled with an insulator. The second metal layers of the stacked structure are selectively etched through the second via and the third via to create ring-shaped voids. The ring-shaped voids of the second via and the third via are filled with an insulator. The first via, the second via, and the third via are filled with a metal.
A method for forming a metal-insulator-metal capacitor includes disposing a first dielectric layer on a substrate having a first contact, a second contact, and a third contact disposed therein. A first second-metal layer is disposed over the first dielectric layer. A first high-k dielectric layer is disposed over the first second-metal layer. A first first-metal layer is disposed over the first high-k dielectric layer. A second high-k dielectric layer is disposed over the first first-metal layer. A second second-metal layer is disposed over the second high-k dielectric layer. A third high-k dielectric layer is disposed over the second second-metal layer. A second first-metal layer is disposed over the third high-k dielectric layer. A second dielectric layer is disposed over the second first-metal layer. A first via is created through the first dialectic, the first second-metal layer, the first high-k dielectric layer, the first first-metal layer, the second high-k dielectric layer, the second second-metal layer, the third high-k dielectric layer, the second first-metal layer, and the second dielectric layer exposing the first contact. A second via is created through the first dialectic, the first second-metal layer, the first high-k dielectric layer, the first first-metal layer, the second high-k dielectric layer, the second second-metal layer, the third high-k dielectric layer, the second first-metal layer, and the second dielectric layer exposing the second contact. A third via is created through the first dialectic, the first second-metal layer, the first high-k dielectric layer, the first first-metal layer, the second high-k dielectric layer, the second second-metal layer, the third high-k dielectric layer, the second first-metal layer, and the second dielectric layer exposing the third contact. The first and second first-metal layers are selectively etched through the first via and the third via to remove a portion of the first and second first-metal layers through the first via and the third via. The removed portion of the first and second first-metal layers are filled with an insulator though the first via and the third via. The first and second second-metal layers are selectively etched through the second via and the third via to remove a portion of the first and second second-metal layers through the second via and the third via. The removed portion of the first and second second-metal layers are filled with an insulator though the second via and the third via. The first via, the second via, and the third via are filled with a metal.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

A more complete appreciation of the present invention and many of the attendant aspects thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 is a diagram illustrating an existing MIM cap structure;

FIG. 2 is a flow chart illustrating a method for fabricating a densely stacked MIM cap structure in accordance with exemplary embodiments of the present invention; and

FIGS. 3A-3I are diagrams illustrating various processing steps for fabricating a densely stacked MIM cap structure in accordance with exemplary embodiments of the present invention.

DETAILED DESCRIPTION

In describing exemplary embodiments of the present invention illustrated in the drawings, specific terminology is employed for sake of clarity. However, the present invention is not intended to be limited to the illustrations or any specific terminology, and it is to be understood that each element includes all equivalents.
Exemplary embodiments of the present invention pertain to a novel structure of a densely stacked metal-insulator-metal (MIM) capacitor (cap) and various methods for fabricating the MIM cap.
Existing MIM cap structures, such as that illustrated in FIG. 1 may have two metal contacts 11 and 12 that are formed on or within a semiconductor wafer 10. Electrodes may be formed, for example, including two top electrodes 13 and 17, as well as a middle electrode 15. Dielectric layers 14 and 16 may be formed between the electrodes and together, the electrodes and dielectric layers may form the MIM cap structure.
To fabricate such a structure, generally, the first top electrode 17 and the first dielectric layer 16 may be deposited, patterned, and etched. Then the middle electrode 15 and the second dielectric 14 may be deposited, patterned, and etched. Finally, the second top electrode 13 may be deposited, patterned, and etched. Accordingly, many patterning and etching steps are performed, particularly where there are more electrode and dielectric layers than are shown in this figure.
Exemplary embodiments of the present invention may provide a densely stacked structure, where there are few patterning and etching steps, for example, only two masks might be needed, regardless of the number of electrode and dielectric layers within the structure. FIG. 2 is a flow chart illustrating a method for fabricating a densely stacked MIM cap in accordance with exemplary embodiments of the present invention, and FIGS. 3A though 3I are schematic diagrams showing the structure in various processing stages in accordance with exemplary embodiments of the present invention.
Referring to FIG. 2 and FIG. 3A, the process may begin with a back end of line (BEOL) structure (Step S20) which may include a wafer or substrate 31 and various contacts such as a driving voltage (Vdd) contact 32, a ground (Gnd) contact 33, and an input/output (I/O) contact 34. The BEOL structure may be a far back end structure, which may be a higher-level structure where layers tend to be thicker.
Next, as may be seen in FIG. 3B, the desired layers may be deposited upon the BEOL structure (Step S21). The deposited layers may include a first dielectric layer 35 a and a second dielectric layer 35 b, with a repeating set of layers sandwiched between the dielectric layers 35 a. The repeating set of layers may include a first metal 38, a second metal 36, and a high-k dielectric layer 37 disposed therebetween.
While four repetitions of the set of layers are shown, it is to be understood that any desired number of repetitions may be used, for example, there may be only a single set of the first metal 38, second metal 36, and the high-k dielectric 37 disposed therebetween. However, there may alternatively be a plurality of repetitions, such as 2 repetitions, 3 repetitions, 4 repetitions (as shown), or more than 4 repetitions.
Additional repetitions may enlarge the structure and add to fabrication costs, however, additional repetitions may lead to lager capacitors. Thus, the demands of the integrated circuit design may determine how many repetitions to fabricate.
As mentioned above, each repetition may include a first metal 38, a second metal 36, and a high-k dielectric 37 disposed therebetween. As used herein, the term “high-k dielectric” is intended to mean a material with a greater dielectric constant than that of silicon dioxide. Examples of suitable high-k dielectric materials include, but are not limited to: hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide. The high-k dielectric layers 37 may be deposited using atomic layer deposition. The thickness of each high-k dielectric layer 37 may be within the range of 1-10 mm.
The first metal layers 38 and the second metal layers 36 may each be formed of copper, a copper alloy, or any other suitable electrically conductive metal. Each of these layers may have a thickness of 10-50 nm. The MIM cap is formed by each set of first and second metal layers with the high-k dielectric disposed therebetween.
In the exemplary structure shown, a first second-metal layer 36 a is disposed over the first dielectric layer 35 a. A first high-k dielectric layer 37 a is disposed over the first second-metal layer 36 a. A first first-metal layer 38 a is disposed over the first high-k dielectric layer 37 a. A second high-k dielectric layer 37 b is disposed over the first first-metal layer 38 a. A second second-metal layer 36 b is disposed over the second high-k dielectric layer 37 b. A third high-k dielectric layer 37 c is disposed over the second second-metal layer 36 b. A second first-metal layer 38 b is disposed over the third high-k dielectric layer 37 c. A fourth high-k dielectric layer 37 d is disposed over the second first-metal layer 38 b. A third second-metal layer 36 c is disposed over the fourth high-k dielectric layer 37 d. A fifth high-k dielectric layer 37 e is disposed over the third second-metal layer 36 c. A third first-metal layer 38 c is disposed over the fifth high-k dielectric layer 37 e. A sixth high-k dielectric layer 37 f is disposed over the third first-metal layer 38 c. A fourth second-metal layer 36 d is disposed over the sixth high-k dielectric layer 37 f. A seventh high-k dielectric layer 37 g is disposed over the fourth second-metal layer 36 d. A fourth first-metal layer 38 d is disposed over the seventh high-k dielectric layer 37 g. A second dielectric layer 35 b is disposed over the fourth first-metal layer 38 d.
It is to be understood that the first and second dielectric layers 35 a and 35 b may be formed of a substance, such as silicon dioxide, which is different than the high-k dielectric layers 37, however, any dielectric may do.
Next, as can be seen in FIG. 3C, vias may be formed within the stacked structure to expose each of the contacts, including the Vdd contact 32, the Gnd contact 33, and the I/O contact 34 (Step S22). These vias may be formed, for example, by etching.
Next, as can be seen in FIG. 3D, the vias of the Vdd contact 32 and the I/O contact 34 may be patterned and further etched, for example, using an isotropic etching technique, to selectively etch into the first metal layers 38 (Step S23) creating a ring-shaped void at each first metal layer 38.
As can be seen from FIG. 3E, an insulator may then be deposited within each of the vias of the Vdd contact 32, the Gnd contact 33, and the I/O contact 34 (Step S24). This insulator may serve to fill the ring-shaped voids made by etching the first metal layers 38 within the vias of the Vdd contact 32 and the I/O contact 34. The via of the Gnd contact 33 may receive a coating of the deposited insulator.
Next, as can be seen from FIG. 3F, the deposited insulator may then be anisotopically etched so as to remove the insulator from each of the vias but to leave the insulator within the ring-shaped voids (Step S25).
As can be seen from FIG. 3G, steps similar to steps S23, S24, and S25 may be performed for the second metal layers 36 (rather than for the first metal layers 38) and for the Gnd contact 33 via and the I/O contact 34 via (rather than for the Vdd contact 32 via and the I/O contact 34 via). In this way, the second metal layers 36 may be selectively etched isotopically so as to create ring-shaped voids at each of the second metal layers about the vias for the Gnd contact 33 and the I/O contact 34 (Step S26). Then, as can be seen in FIG. 3H, insulator may be deposited in each via so as to fill the ring-shaped voids in the second metal layers 36 for the vias of the Gnd contact 33 and the I/O contact 34 and then anisotopic etching may be performed to remove the insulator, but leaving the insulator in the ring-shaped voids (Step S27).
As can be seen from FIG. 3I, each of the vias may be filled with a metal such as copper (Step S28). This may be performed in three steps: the first step being to deposit a liner to line each via, the second step being to fill the lined vias with a metal such as copper, and the third step being to planarize the top surface of the structure. Thereafter, the remainder of the BEOL processing may be completed so that an integrated circuit (IC) may be formed to make use of the MIM cap so created (Step S29), for example, on a back end thereof.
As shown in FIG. 3I, the final structure has all second metal layers 36 connected with the metal-filled via of the Vdd contact 32, and all first metal layers 38 insulated from the metal-filled via of the Vdd contact 32 by insulating rings. Concurrently, all first metal layers 38 are connected with the metal-filled via of the Gnd contact 33, and all second metal layers 36 are insulated from the metal-filled via of the Gnd contact 33 by insulating rings. Concurrently, all first and second metal layers 38 and 36 are insulated from the metal-filled via of the I/O contact 34 by insulating rings.
Exemplary embodiments described herein are illustrative, and many variations can be introduced without departing from the spirit of the invention or from the scope of the appended claims. For example, elements and/or features of different exemplary embodiments may be combined with each other and/or substituted for each other within the scope of this invention and appended claims.

Claims

What is claimed is:

1. A metal-insulator-metal capacitor, comprising:

a first contact, a second contact, and a third contact, each disposed within a substrate;

a first dielectric layer disposed over the substrate and the first, second, and third contacts;

a stacked structure disposed over the first dielectric layer, the stacked structure including repeating pattern of a second metal layer, a first metal layer, and a high-k dielectric disposed between the second metal layer and the first metal layer;

a second dielectric layer disposed over the stacked structure;

a first via exposing the first contact through the first dielectric layer, the stacked structure, and the second dielectric layer, the first via being filled with metal;

a second via exposing the second contact through the first dielectric layer, the stacked structure, and the second dielectric layer, the second via being filled with metal; and

a third via exposing the third contact through the first dielectric layer, the stacked structure, and the second dielectric layer, the third via being filled with metal,

wherein the second metal layer of each repeating pattern of the stacked structure is connected to the metal filling the first via, insulated from the metal filling the second via, and insulated from the metal filling the third via, and

wherein the first metal layer of each repeating pattern of the stacked structure is insulated from the metal filling the first via, connected to the metal filling the second via, and insulated from the metal filling the third via.

2. The metal-insulator-metal capacitor of claim 1, wherein the high-k dielectric layer of each repeating pattern of the stacked structure makes contact with the metal filling the first via, makes contact with the metal filling the second via, and makes contact with the metal filling the third via.

3. The metal-insulator-metal capacitor of claim 1, wherein the first contact is a driving voltage contact, the second contact is a ground voltage contact, and the third contact is an input/output contact.

4. The metal-insulator-metal capacitor of claim 1, wherein the first and second dielectric layers include silicon oxide and the high-k dielectric layer of each repeating pattern of the stacked structure is a dielectric having a dielectric constant greater than that of silicon oxide.

5. The metal-insulator-metal capacitor of claim 1, wherein the repeating pattern of the stacked structure is repeated at least two times.

6. The metal-insulator-metal capacitor of claim 1, wherein the repeating pattern of the stacked structure is repeated at least four times.

7. The metal-insulator-metal capacitor of claim 1, wherein both the first metal layer and the second metal layer of the repeating pattern of the stacked structure include copper.

8. The metal-insulator-metal capacitor of claim 1, wherein the first metal layer of the repeating pattern of the stacked structure have different etching susceptibilities than the second metal layer of the repeating pattern of the stacked structure.

9. A method for forming a metal-insulator-metal capacitor, comprising:

disposing a first dielectric layer on a substrate having a first contact, a second contact, and a third contact disposed therein;

disposing a stacked structure over the first dielectric layer, the stacked structure including repeating pattern of a second metal layer, a first metal layer, and a high-k dielectric disposed between the second metal layer and the first metal layer;

disposing a second dielectric layer over the stacked structure;

creating a first via through the second dielectric layer, the stacked structure, and the first dielectric layer to expose the first contact;

creating a second via through the second dielectric layer, the stacked structure, and the first dielectric layer to expose the second contact;

creating a third via through the second dielectric layer, the stacked structure, and the first dielectric layer to expose the third contact;

selectively etching the first metal layers of the stacked structure through the first via and the third via to create ring-shaped voids;

filling the ring-shaped voids of the first via and the third via with an insulator;

selectively etching the second metal layers of the stacked structure through the second via and the third via to create ring-shaped voids;

filling the ring-shaped voids of the second via and the third via with an insulator; and

filling the first via, the second via, and the third via with a metal.

10. The method for forming a metal-insulator-metal capacitor of claim 9, wherein the first contact is a driving voltage contact, the second contact is a ground voltage contact, and the third contact is an input/output contact.

11. The method for forming a metal-insulator-metal capacitor of claim 9, wherein the first and second dielectric layers include silicon oxide and the high-k dielectric layer of each repeating pattern of the stacked structure is a dielectric having a dielectric constant greater than that of silicon oxide.

12. The method for forming a metal-insulator-metal capacitor of claim 9, wherein the repeating pattern of the stacked structure is repeated at least two times.

13. The method for forming a metal-insulator-metal capacitor of claim 9, wherein the repeating pattern of the stacked structure is repeated at least four times.

14. The method for forming a metal-insulator-metal capacitor of claim 9, wherein the selective etching of the first metal layers of the stacked structure through the first via and the third via is isotropic etching and the selective etching of the second metal layers of the stacked structure through the second via and the third via is isotropic etching.

15. The method for forming a metal-insulator-metal capacitor of claim 9, wherein the filling of the ring-shaped voids of each via includes:

depositing the insulator in the corresponding via; and

performing anisotropic etching on the insulator in the corresponding via to remove the insulator from everywhere in the corresponding via except for in the ring-shaped voids.

16. The method for forming a metal-insulator-metal capacitor of claim 9, wherein the filling of the first via, second via, and third via with the metal includes:

depositing a liner in each via;

filling each lined via with the metal; and

planarizing the metal from the top of each via.

17. A method for thrilling a metal-insulator-metal capacitor, comprising:

disposing a first second-metal layer over the first dielectric layer;

disposing a first high-k dielectric layer over the first second-metal layer;

disposing a first first-metal layer over the first high-k dielectric layer;

disposing a second high-k dielectric layer over the first first-metal layer;

disposing a second second-metal layer over the second high-k dielectric layer;

disposing a third high-k dielectric layer over the second second-metal layer;

disposing a second first-metal layer over the third high-k dielectric layer;

disposing a second dielectric layer over the second first-metal layer;

creating a first via through the first dialectic, the first second-metal layer, the first high-k dielectric layer, the first first-metal layer, the second high-k dielectric layer, the second second-metal layer, the third high-k dielectric layer, the second first-metal layer, and the second dielectric layer exposing the first contact;

creating a second via through the first dialectic, the first second-metal layer, the first high-k dielectric layer, the first first-metal layer, the second high-k dielectric layer, the second second-metal layer, the third high-k dielectric layer, the second first-metal layer, and the second dielectric layer exposing the second contact;

creating a third via through the first dialectic, the first second-metal layer, the first high-k dielectric layer, the first first-metal layer, the second high-k dielectric layer, the second second-metal layer, the third high-k dielectric layer, the second first-metal layer, and the second dielectric layer exposing the third contact;

selectively etching the first and second first-metal layers through the first via and the third via to remove a portion of the first and second first-metal layers through the first via and the third via;

filling the removed portion of the first and second first-metal layers with an insulator though the first via and the third via;

selectively etching the first and second second-metal layers through the second via and the third via to remove a portion of the first and second second-metal layers through the second via and the third via;

filling the removed portion of the first and second second-metal layers with an insulator though the second via and the third via; and

filling the first via, the second via, and the third via with a metal.

18. The method for forming a metal-insulator-metal capacitor of claim 17, wherein the first contact is a driving voltage contact, the second contact is a ground voltage contact, and the third contact is an input/output contact.

19. The method for forming a metal-insulator-metal capacitor of claim 17, wherein the selective etching of the first and second second-metal layers through the first via and the third via is isotropic etching and the selective etching of the first and second first-metal layers through the second via and the third via is isotropic etching.

20. The method for forming a metal-insulator-metal capacitor of claim 17, wherein the filling the removed portion of the first and second second/first-metal layers with an insulator though the first/second via and the third via, include:

depositing the insulator in the corresponding via; and

performing anisotropic etching on the insulator in the corresponding via to remove the insulator from everywhere in the corresponding via except for in the removed portions.