US20180226421A1 - Method of forming split-gate, twin-bit non-volatile memory cell - Google Patents
Method of forming split-gate, twin-bit non-volatile memory cell Download PDFInfo
- Publication number
- US20180226421A1 US20180226421A1 US15/945,659 US201815945659A US2018226421A1 US 20180226421 A1 US20180226421 A1 US 20180226421A1 US 201815945659 A US201815945659 A US 201815945659A US 2018226421 A1 US2018226421 A1 US 2018226421A1
- Authority
- US
- United States
- Prior art keywords
- insulation
- polysilicon
- block
- forming
- blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 25
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 99
- 229920005591 polysilicon Polymers 0.000 claims description 99
- 238000009413 insulation Methods 0.000 claims description 91
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 238000005137 deposition process Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 6
- 239000012774 insulation material Substances 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 23
- 239000010410 layer Substances 0.000 description 76
- 229920002120 photoresistant polymer Polymers 0.000 description 33
- 150000004767 nitrides Chemical class 0.000 description 11
- 230000000873 masking effect Effects 0.000 description 10
- 230000008878 coupling Effects 0.000 description 9
- 238000010168 coupling process Methods 0.000 description 9
- 238000005859 coupling reaction Methods 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 239000007943 implant Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H01L27/11521—
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Definitions
- the present invention relates to non-volatile memory arrays.
- split gate non-volatile flash memory cells are well known.
- U.S. Pat. No. 6,747,310 discloses such memory cells having source and drain regions defining a channel region there between, a select gate over one portion of the channel regions, a floating gate over the other portion of the channel region, and an erase gate over the source region.
- the memory cells are formed in pairs that share a common source region and common erase gate, with each memory cell having its own channel region in the substrate extending between the source and drain regions (i.e. there are two separate channel regions for each pair of memory cells).
- the lines connecting all the control gates for memory cells in a given column run vertically. The same is true for the lines connecting the erase gates and the select gates, and the source lines.
- the bit lines connecting drain regions for each row of memory cells run horizontally.
- Each memory cell stores a single bit of information (based on the programming state of the floating gate). Given the number of electrodes for each cell (source, drain, select gate, control gate and erase gate), and two separate channel regions for each pair of memory calls, configuring and forming the architecture and array layout with all the various lines connected to these electrodes can be overly complex and difficult to implement, especially as critical dimensions continue to shrink.
- a method of forming a pair of non-volatile memory cells includes forming a first insulation layer on a semiconductor substrate, forming a first polysilicon layer on the first insulation layer in a first polysilicon deposition process, forming spaced apart first and second insulation blocks on the first polysilicon layer, the first insulation block having a first side facing the second insulation block and a second side facing away from the second insulation block, and the second insulation block having a first side facing the first insulation block and a second side facing away from the first insulation block, removing a portion of the first polysilicon layer disposed between the first and second insulation blocks while maintaining portions of the first polysilicon layer disposed underneath the first and second insulation blocks and adjacent the second sides of the first and second insulation blocks, removing the portions of the first polysilicon layer adjacent the second sides of the first and second insulation blocks while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the first and second insulation blocks, forming a first drain region in the substrate and
- the first polysilicon block is disposed between the first and second insulation blocks, the second polysilicon block is disposed over the first drain region, and the third polysilicon block is disposed over the second drain region.
- the substrate includes a continuous channel region extending between the first and second drain regions.
- a method of forming a pair of non-volatile memory cells includes forming a first insulation layer on a semiconductor substrate, forming a first polysilicon layer on the first insulation layer in a first polysilicon deposition process, forming an insulation layer stack on the first polysilicon layer, forming a second polysilicon layer on the insulation layer stack, forming spaced apart first and second insulation blocks on the second polysilicon layer, the first insulation block having a first side facing the second insulation block and a second side facing away from the second insulation block, and the second insulation block having a first side facing the first insulation block and a second side facing away from the first insulation block, removing portions of the second polysilicon layer, the insulation layer stack and the first polysilicon layer disposed between the first and second insulation blocks and adjacent the second sides of the first and second insulation blocks, while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the first and second insulation blocks, forming a first drain region in the substrate and adjacent the second side of the first insulation block, forming
- the first polysilicon block is disposed between the first and second insulation blocks, the second polysilicon block is disposed over the first drain region, and the third polysilicon block is disposed over the second drain region.
- the substrate includes a continuous channel region extending between the first and second drain regions.
- FIGS. 1A-1H are side cross section views showing the steps in forming the 2 bit memory cell of the present invention.
- FIG. 2 is a side cross section view showing an alternate embodiment of the 2 bit memory cell of the present invention.
- FIGS. 3A-3C are side cross section views showing the steps in forming an alternate embodiment of the 2 bit memory cell of the present invention.
- FIGS. 4A-4D are side cross section views showing the steps in forming an alternate embodiment of the 2 bit memory cell of the present invention.
- FIGS. 5A-5D are side cross section views showing the steps in forming an alternate embodiment of the 2 bit memory cell of the present invention.
- FIGS. 6A-6D are side cross section views showing the steps in forming an alternate embodiment of the 2 bit memory cell of the present invention.
- FIG. 7 is a side cross section view showing an alternate embodiment of the 2 bit memory cell of the present invention.
- FIG. 8 is a plan view showing control circuitry used to operate an array of 2-bit memory cells of the present invention.
- the present invention is a memory cell design, architecture and method of manufacture of a split-gate, two bit memory cell design.
- FIGS. 1A-1H there are shown cross-sectional views of the steps in the process to make a 2-bit memory cell (while only the formation of a single 2-bit memory cell is shown in the figures, it should be understood that an array of such memory cells are formed concurrently).
- the process begins by forming a layer of silicon dioxide (oxide) 12 on a substrate 10 of P type single crystalline silicon. Thereafter a layer 14 of polysilicon (or amorphous silicon) is formed on the layer 12 of silicon dioxide.
- insulating stack 11 (ONO, oxide-nitride-oxide) is formed on layer 14 , and a layer 13 of polysilicon (or amorphous silicon) is formed on the layer 11 .
- Another insulating layer 16 e.g. silicon nitride—“nitride”) is formed on poly layer 13 , as shown in FIG. 1A .
- Photoresist material (not shown) is coated on the structure, and a photolithography masking step is performed exposing selected portions of the photoresist material.
- the photoresist is developed such that portions of the photoresist are removed.
- the structure is etched. Specifically, nitride layer 16 , poly layer 13 and insulating layer stack 11 are anisotropically etched (using poly layer 14 as an etch stop), leaving pairs of nitride blocks 16 and poly blocks 13 as shown in FIG. 1B (after the photoresist is removed).
- the space between nitride blocks 16 and poly blocks 13 is termed herein the “inner region,” and the spaces outside of the pair of nitride blocks 16 and poly blocks 13 are termed herein the “outer regions.”
- Photoresist material 18 is coated on the structure, and is patterned using masking and develop steps, to cover the outer regions, but leaving the inner region exposed. An anisotropic poly etch is then used to remove the portion of poly layer 14 in the inner region.
- a WLVT implantation is used to implant the substrate in the inner region, as illustrated in FIG. 1C .
- spacers 20 are then formed on the sides of the structure. Formation of spacers is well known in the art, and involves the deposition of a material over the contour of a structure, followed by an anisotropic etch process, whereby the material is removed from horizontal surfaces of the structure, while the material remains largely intact on vertically oriented surfaces of the structure (with a rounded upper surface). Spacers 20 can be oxide or oxide-nitride.
- FIG. 1D Photoresist material 22 is coated on the structure, and is patterned using masking and develop steps, to cover the inner region, but leaving the outer regions exposed. A poly etch is then used to remove the exposed portions of poly layer 14 in the outer regions.
- An implant process e.g. implantation and anneal
- an oxide layer is formed over the structure, including oxide layer 26 along the sides and top of the structures.
- a photoresist coating and photolithography masking step is used to cover the structure with photoresist except for the inner region.
- An oxide anisotropic etch e.g. dry anisotropic etch
- an oxide layer 15 is grown over the structure in the inner region, which thickens oxide layer 12 over the substrate 10 in the outer regions, as shown in FIG. 1F .
- a polysilicon deposition and etch back is used to form a layer of polysilicon in the inner and outer regions.
- a photoresist coating and photolithography masking, and polysilicon etch, are used to define the outer edges of the polysilicon layer in the outer regions.
- the resulting structure is shown in FIG. 1G (after photoresist removal), which results in poly block 28 in the inner region and poly blocks 30 in the outer regions.
- poly block 28 can be replaced with a metal block for improved conductivity as follows.
- a photoresist coating and masking process are used to cover the structure with photoresist except for the inner region.
- Poly and oxide etches are used to remove the poly block 28 and the oxide layers 15 and 26 from the inner region.
- An insulation layer 32 is formed on the substrate and exposed structure sidewalls in the inner region.
- Layer 32 is preferably a high K material (i.e. having a dielectric constant K greater than that of oxide, such as HfO2, ZrO2, TiO2, etc.).
- a metal deposition and etch back are then used to form a block of metal material 34 in the inner region (i.e. on and alongside the high K insulation layer 32 ).
- CMP is used to planarize the top surfaces.
- the resulting structure is shown in FIG. 1H (after photoresist removal).
- the poly block between the floating gates 14 (which is the word line gate) can remain as a poly block, or can be replaced by a metal block insulated with a high K material as described above.
- the final 2-bit memory cell structure is shown in FIG. 2 , where a continuous channel region 36 is defined in the substrate between the two bit line (drain) regions 24 A and 24 B.
- a first floating gate 14 A is disposed over and insulated from a first portion of the channel region 36 (for controlling the conductivity thereof).
- a first coupling gate 13 A is disposed over and insulated from the first floating gate 14 A (for coupling the voltage on the floating gate 14 A).
- a word line gate 34 is disposed over and insulated from a second portion of the channel region 36 (for controlling the conductivity thereof).
- a second floating gate 14 B is disposed over and insulated from a third portion of the channel region 36 (for controlling the conductivity thereof).
- a second coupling gate 13 B is disposed over and insulated from the second floating gate 14 B (for coupling the voltage on floating gate 14 B).
- a first erase gate 30 A is disposed over and insulated from the first drain region 24 A, and disposed adjacent to and insulated from the first floating gate 14 A.
- a second erase gate 30 B is disposed over and insulated from the second drain region 24 B, and disposed adjacent to and insulated from the second floating gate 14 B.
- Programming floating gate 14 A with electrons stores the first bit (i.e., bit 1 ), and programming floating gate 14 B with electrons stores the second bit (i.e., bit 2 ).
- Table 1 illustrates exemplary operational voltages for program, read and erase operations of the two-bit memory cell.
- a voltage of 1V is applied to the word line gate 34 which turns on the underlying channel portion.
- Voltage 4.5V is applied to coupling gate 13 B which is capacitively coupled to floating gate 14 B to turn on the underlying channel portion.
- Voltage 4.5V is applied to bit line 24 A and ⁇ 1 uA on bit line 24 B. Electrons travel from bit line 24 B toward bit line 24 A, and inject themselves onto floating gate 14 A because of the positive voltage capacitively coupled thereto by erase gate 30 A.
- Floating gate 14 B is similarly programmed.
- a voltage of 8.5 volts is applied to the erase gates 30 A and 30 B, and a negative voltage of ⁇ 7V is applied to the coupling gate 13 A and 13 B, which causes electrons to tunnel through the insulation from the floating gates 14 to the erase gates 30 .
- Vcc is applied to word line 34 which turns on the underlying channel portion.
- a voltage of 1V is applied to the bit line 24 B and zero volts applied to bit line 24 A.
- a 4.5V voltage is applied to coupling gate 13 B, which is capacitively coupled to floating gate 14 B (turning on the underlying channel region portion).
- Current will flow through the channel if floating gate 14 A is erased (i.e., erased state will have a positive voltage on floating gate 14 A and therefore the underlying channel region portion is turned on), and current will not flow through the channel if floating gate 14 A is programmed (i.e. is programmed with electrons sufficient to prevent turning on the underlying channel region portion).
- Floating gate 14 B is similarly read.
- FIGS. 3A-3C illustrate an alternate embodiment for forming the 2-bit memory cell, which starts with the structure in FIG. 1D .
- a sacrificial oxide spacer 25 is formed.
- a photoresist coating and photolithography masking step is used to cover the inner region with photoresist 22 .
- a poly etch is then used to remove the exposed portions of poly layer 14 in the outer regions.
- An implant process e.g. implantation and anneal
- an oxide wet etch is performed to remove spacer 25 in the outer regions, as shown in FIG. 3A .
- oxide 26 is formed such that oxide layer 26 includes a stepped contour 26 a .
- a photoresist coating and photolithography masking step is used to cover the structure with photoresist except for the inner region.
- An oxide anisotropic etch is then used to remove the oxide over the substrate 10 .
- an oxide layer 15 is grown over the structure in the inner region, which thickens oxide layer 12 over the substrate 10 in the outer regions, as shown in FIG. 3B .
- the remaining processing steps described above with respect to FIGS. 1G and 1H are performed, resulting in the structure shown in FIG. 3C .
- the erase gates 30 have a notch 31 facing a corner of the floating gate 14 for enhanced erase operation performance.
- FIGS. 4A to 4D illustrate another embodiment for forming the 2-bit memory cell, which starts with the structure of FIG. 1B , as shown in FIG. 4A .
- a poly etch is used to remove the exposed poly layer 14 portions in the inner and the outer regions, instead of just in the inner region, leaving poly blocks 14 .
- Spacers 42 e.g. oxide or oxide-nitride
- Photo resist 44 is formed covering the inner region, and spacers 42 facing the outer regions are removed.
- An implant is then used form drain regions 46 , as illustrated in FIG. 4C .
- oxide 48 is formed on the structure, which removes exposed portions of oxide layer 12 on the substrate.
- a photoresist coating and photolithography masking process is used to open the inner region, but leave the outer regions covered by photoresist.
- a oxide anisotropic etch is then used to remove the oxide 12 over the substrate 10 in the inner region.
- an oxide layer 50 (e.g. by thermal oxidation) is grown in the inner region, which thickens oxide layer 12 over the substrate 10 in the outer regions.
- a polysilicon deposition and etch back or CMP is used to form a layer of polysilicon in the inner and outer regions.
- a photoresist coating and photolithography masking, and polysilicon etch, are used to define the outer edges of the polysilicon layer in the outer regions.
- the resulting structure is shown in FIG. 4D (after photoresist removal), which results in poly block 52 in the inner region and poly blocks 54 in the outer regions.
- poly block 52 and oxide 48 and 50 in the inner region could be replaced with a high K insulator and metal block as described above.
- the advantages of this embodiment include that the floating gate poly blocks 14 are defined with a single poly etch, and the insulation between the floating gate and the word line gate 52 on one side and the erase gate 54 on the other side can be independently varied (i.e. by the inclusion of spacer 42 on just one side of the floating gate).
- FIGS. 5A-5D illustrate another embodiment for forming the 2-bit memory cell, which begins with the structure of FIG. 1A .
- a photolithography and nitride etch process are used to form a trench 76 in the nitride layer 16 .
- Oxide spacers 78 are formed on the trench sidewalls by oxide deposition and etch, as shown in FIG. 5A .
- a poly etch is performed to remove the exposed portion of poly layer 14 in trench 76 .
- a WLVT implantation is used to implant the substrate under trench 76 .
- An oxide deposition and etch is used to form spacers 80 along the exposed sides of poly layer 14 , as shown in FIG. 5B .
- a nitride etch is used to remove nitride layer 16 .
- a poly etch is used to remove exposed portions of poly layer 14 .
- Photoresist is coated on the structure and selectively removed except for trench 76 , and an implant process is used to form drain regions 82 , as illustrated in FIG. 5C (after photoresist removal).
- Oxide layer 84 is formed on the exposed ends of poly layer 14 and exposed substrate in trench 76 (e.g. thermal oxide).
- a poly deposition and etch are performed to form poly block (word line gate) 86 in trench 76 , and poly blocks (erase gates) 88 along the outer sides of floating gate blocks 14 , as illustrated in FIG. 5D .
- FIGS. 6A-6D illustrate an alternate embodiment of the process of FIGS. 5A-5D , wherein before spacers 78 are formed, a poly slope etch is performed so that the upper surface of poly layer 14 slopes downwardly as it extends away from nitride layer 16 , as shown in FIG. 6A .
- ONO layer 11 is formed over the structure, and poly layer 13 is formed on ONO layer by poly deposition and etch back, as shown in FIG. 6B .
- Spacers 78 are then formed on poly layer 13 , as shown in FIG. 6C .
- the remaining processing steps described above with respect to FIGS. 5B to 5D are then performed, resulting in each floating gate having an upwardly sloping surface terminating in a sharper edge that faces the notch of the erase gate, as shown in FIG. 6D .
- FIG. 7 illustrates an alternate embodiment for the 2 bit memory cell of FIG. 1H , where the memory cell does not include a coupling gate. Formation of the memory cell of FIG. 7 is similar to that disclosed with respect to FIGS. 1A-1H , except omitting the formation of the ONO layer 11 and second poly layer 13 before the formation of nitride layer 16 (see FIG. 1A ).
- the operational voltages for the 2 bit memory cell of FIG. 7 are illustrated in Table 2 below:
- Control circuitry 96 preferably (but not necessarily) formed on the same substrate 10 (as shown in FIG. 8 ) is configured program, read and erase an array 98 of the 2-bit memory cells described herein by applying the voltages of Table 1 or Table 2.
- adjacent includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between)
- mounted to includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between)
- electrically coupled includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
- forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
Abstract
Description
- This application is a divisional of U.S. patent application Ser. No. 15/476,663, filed Mar. 31, 2017, which claims the benefit of Chinese Patent Application No. 201610285454.7 filed on Apr. 29, 2016.
- The present invention relates to non-volatile memory arrays.
- Split gate non-volatile flash memory cells are well known. For example, U.S. Pat. No. 6,747,310 discloses such memory cells having source and drain regions defining a channel region there between, a select gate over one portion of the channel regions, a floating gate over the other portion of the channel region, and an erase gate over the source region. The memory cells are formed in pairs that share a common source region and common erase gate, with each memory cell having its own channel region in the substrate extending between the source and drain regions (i.e. there are two separate channel regions for each pair of memory cells). The lines connecting all the control gates for memory cells in a given column run vertically. The same is true for the lines connecting the erase gates and the select gates, and the source lines. The bit lines connecting drain regions for each row of memory cells run horizontally.
- Each memory cell stores a single bit of information (based on the programming state of the floating gate). Given the number of electrodes for each cell (source, drain, select gate, control gate and erase gate), and two separate channel regions for each pair of memory calls, configuring and forming the architecture and array layout with all the various lines connected to these electrodes can be overly complex and difficult to implement, especially as critical dimensions continue to shrink.
- One solution is to eliminate the source region, and have both memory cells share a single continuous channel region and a common word line gate, and disclosed in U.S. Pat. No. 8,780,625. However, there are performance limitations with this configuration because, among other things, it lacks erase gates.
- The aforementioned problems and needs are addressed by a method of forming a pair of non-volatile memory cells includes forming a first insulation layer on a semiconductor substrate, forming a first polysilicon layer on the first insulation layer in a first polysilicon deposition process, forming spaced apart first and second insulation blocks on the first polysilicon layer, the first insulation block having a first side facing the second insulation block and a second side facing away from the second insulation block, and the second insulation block having a first side facing the first insulation block and a second side facing away from the first insulation block, removing a portion of the first polysilicon layer disposed between the first and second insulation blocks while maintaining portions of the first polysilicon layer disposed underneath the first and second insulation blocks and adjacent the second sides of the first and second insulation blocks, removing the portions of the first polysilicon layer adjacent the second sides of the first and second insulation blocks while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the first and second insulation blocks, forming a first drain region in the substrate and adjacent the second side of the first insulation block, forming a second drain region in the substrate and adjacent the second side of the second insulation block, forming a second polysilicon layer over the substrate and the first and second insulation blocks in a second polysilicon deposition process, and removing portions of the second polysilicon layer while maintaining a first polysilicon block, a second polysilicon block and a third polysilicon block of the second polysilicon layer. The first polysilicon block is disposed between the first and second insulation blocks, the second polysilicon block is disposed over the first drain region, and the third polysilicon block is disposed over the second drain region. The substrate includes a continuous channel region extending between the first and second drain regions.
- A method of forming a pair of non-volatile memory cells includes forming a first insulation layer on a semiconductor substrate, forming a first polysilicon layer on the first insulation layer in a first polysilicon deposition process, forming an insulation layer stack on the first polysilicon layer, forming a second polysilicon layer on the insulation layer stack, forming spaced apart first and second insulation blocks on the second polysilicon layer, the first insulation block having a first side facing the second insulation block and a second side facing away from the second insulation block, and the second insulation block having a first side facing the first insulation block and a second side facing away from the first insulation block, removing portions of the second polysilicon layer, the insulation layer stack and the first polysilicon layer disposed between the first and second insulation blocks and adjacent the second sides of the first and second insulation blocks, while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the first and second insulation blocks, forming a first drain region in the substrate and adjacent the second side of the first insulation block, forming a second drain region in the substrate and adjacent the second side of the second insulation block, forming a third polysilicon layer over the substrate and the first and second insulation blocks in a second polysilicon deposition process, and removing portions of the third polysilicon layer while maintaining a first polysilicon block, a second polysilicon block and a third polysilicon block of the third polysilicon layer. The first polysilicon block is disposed between the first and second insulation blocks, the second polysilicon block is disposed over the first drain region, and the third polysilicon block is disposed over the second drain region. The substrate includes a continuous channel region extending between the first and second drain regions.
- Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
-
FIGS. 1A-1H are side cross section views showing the steps in forming the 2 bit memory cell of the present invention. -
FIG. 2 is a side cross section view showing an alternate embodiment of the 2 bit memory cell of the present invention. -
FIGS. 3A-3C are side cross section views showing the steps in forming an alternate embodiment of the 2 bit memory cell of the present invention. -
FIGS. 4A-4D are side cross section views showing the steps in forming an alternate embodiment of the 2 bit memory cell of the present invention. -
FIGS. 5A-5D are side cross section views showing the steps in forming an alternate embodiment of the 2 bit memory cell of the present invention. -
FIGS. 6A-6D are side cross section views showing the steps in forming an alternate embodiment of the 2 bit memory cell of the present invention. -
FIG. 7 is a side cross section view showing an alternate embodiment of the 2 bit memory cell of the present invention. -
FIG. 8 is a plan view showing control circuitry used to operate an array of 2-bit memory cells of the present invention. - The present invention is a memory cell design, architecture and method of manufacture of a split-gate, two bit memory cell design. Referring to
FIGS. 1A-1H , there are shown cross-sectional views of the steps in the process to make a 2-bit memory cell (while only the formation of a single 2-bit memory cell is shown in the figures, it should be understood that an array of such memory cells are formed concurrently). The process begins by forming a layer of silicon dioxide (oxide) 12 on asubstrate 10 of P type single crystalline silicon. Thereafter alayer 14 of polysilicon (or amorphous silicon) is formed on thelayer 12 of silicon dioxide. Then insulating stack 11 (ONO, oxide-nitride-oxide) is formed onlayer 14, and alayer 13 of polysilicon (or amorphous silicon) is formed on thelayer 11. Another insulating layer 16 (e.g. silicon nitride—“nitride”) is formed onpoly layer 13, as shown inFIG. 1A . - Photoresist material (not shown) is coated on the structure, and a photolithography masking step is performed exposing selected portions of the photoresist material. The photoresist is developed such that portions of the photoresist are removed. Using the remaining photoresist as a mask, the structure is etched. Specifically,
nitride layer 16,poly layer 13 andinsulating layer stack 11 are anisotropically etched (usingpoly layer 14 as an etch stop), leaving pairs ofnitride blocks 16 andpoly blocks 13 as shown inFIG. 1B (after the photoresist is removed). The space betweennitride blocks 16 andpoly blocks 13 is termed herein the “inner region,” and the spaces outside of the pair ofnitride blocks 16 andpoly blocks 13 are termed herein the “outer regions.”Photoresist material 18 is coated on the structure, and is patterned using masking and develop steps, to cover the outer regions, but leaving the inner region exposed. An anisotropic poly etch is then used to remove the portion ofpoly layer 14 in the inner region. A WLVT implantation is used to implant the substrate in the inner region, as illustrated inFIG. 1C . - After removal of
photoresist 18,spacers 20 are then formed on the sides of the structure. Formation of spacers is well known in the art, and involves the deposition of a material over the contour of a structure, followed by an anisotropic etch process, whereby the material is removed from horizontal surfaces of the structure, while the material remains largely intact on vertically oriented surfaces of the structure (with a rounded upper surface).Spacers 20 can be oxide or oxide-nitride. The resultant structure is shown inFIG. 1D .Photoresist material 22 is coated on the structure, and is patterned using masking and develop steps, to cover the inner region, but leaving the outer regions exposed. A poly etch is then used to remove the exposed portions ofpoly layer 14 in the outer regions. An implant process (e.g. implantation and anneal) is then performed to form drain regions (bit lines—BL) 24 in the substrate in the outer regions, as shown inFIG. 1E . - After removal of
photoresist 22, an oxide layer is formed over the structure, includingoxide layer 26 along the sides and top of the structures. A photoresist coating and photolithography masking step is used to cover the structure with photoresist except for the inner region. An oxide anisotropic etch (e.g. dry anisotropic etch) is then used to remove the oxide over thesubstrate 10. After removal of photoresist, anoxide layer 15 is grown over the structure in the inner region, which thickensoxide layer 12 over thesubstrate 10 in the outer regions, as shown inFIG. 1F . A polysilicon deposition and etch back is used to form a layer of polysilicon in the inner and outer regions. A photoresist coating and photolithography masking, and polysilicon etch, are used to define the outer edges of the polysilicon layer in the outer regions. The resulting structure is shown inFIG. 1G (after photoresist removal), which results inpoly block 28 in the inner region and poly blocks 30 in the outer regions. - Optionally,
poly block 28 can be replaced with a metal block for improved conductivity as follows. A photoresist coating and masking process are used to cover the structure with photoresist except for the inner region. Poly and oxide etches are used to remove thepoly block 28 and the oxide layers 15 and 26 from the inner region. Aninsulation layer 32 is formed on the substrate and exposed structure sidewalls in the inner region.Layer 32 is preferably a high K material (i.e. having a dielectric constant K greater than that of oxide, such as HfO2, ZrO2, TiO2, etc.). A metal deposition and etch back are then used to form a block ofmetal material 34 in the inner region (i.e. on and alongside the high K insulation layer 32). Preferably, CMP is used to planarize the top surfaces. The resulting structure is shown inFIG. 1H (after photoresist removal). It should be noted that for all of the embodiments herein, the poly block between the floating gates 14 (which is the word line gate) can remain as a poly block, or can be replaced by a metal block insulated with a high K material as described above. - The final 2-bit memory cell structure is shown in
FIG. 2 , where acontinuous channel region 36 is defined in the substrate between the two bit line (drain)regions gate 14A is disposed over and insulated from a first portion of the channel region 36 (for controlling the conductivity thereof). Afirst coupling gate 13A is disposed over and insulated from the first floatinggate 14A (for coupling the voltage on the floatinggate 14A). Aword line gate 34 is disposed over and insulated from a second portion of the channel region 36 (for controlling the conductivity thereof). A second floatinggate 14B is disposed over and insulated from a third portion of the channel region 36 (for controlling the conductivity thereof). Asecond coupling gate 13B is disposed over and insulated from the second floatinggate 14B (for coupling the voltage on floatinggate 14B). A first erasegate 30A is disposed over and insulated from thefirst drain region 24A, and disposed adjacent to and insulated from the first floatinggate 14A. A second erasegate 30B is disposed over and insulated from thesecond drain region 24B, and disposed adjacent to and insulated from the second floatinggate 14B.Programming floating gate 14A with electrons stores the first bit (i.e., bit 1), andprogramming floating gate 14B with electrons stores the second bit (i.e., bit 2). - Table 1 below illustrates exemplary operational voltages for program, read and erase operations of the two-bit memory cell.
-
TABLE 1 EG EG WL CG CG BL BL 30A 30B 28 13A 13B 24A 24B Program 4.5 V 0 1 V 10.5 V 4.5 V 4.5 V −1 uA bit 1 Program 0 4.5 V 1 V 4.5 V 10.5 V −1 uA 4.5 V bit 2 Read 0 0 Vcc 0 4.5 V 0 1 V bit 1 Read 0 0 Vcc 4.5 V 0 1 V 0 bit 2 Erase 8.5 V 8.5 V 0 −7 V −7 V 0 0 both bits
Toprogram floating gate 14A, voltage 4.5V is applied to erasegate 30A and voltage 10.5V is applied tocoupling gate 13A which are capacitively coupled to floatinggate 14A. A voltage of 1V is applied to theword line gate 34 which turns on the underlying channel portion. Voltage 4.5V is applied tocoupling gate 13B which is capacitively coupled to floatinggate 14B to turn on the underlying channel portion. Voltage 4.5V is applied tobit line 24A and −1 uA onbit line 24B. Electrons travel frombit line 24B towardbit line 24A, and inject themselves onto floatinggate 14A because of the positive voltage capacitively coupled thereto by erasegate 30A. Floatinggate 14B is similarly programmed. - To erase the floating
gates gates coupling gate gates 14 to the erasegates 30. - To read floating
gate 14A, Vcc is applied toword line 34 which turns on the underlying channel portion. A voltage of 1V is applied to thebit line 24B and zero volts applied tobit line 24A. A 4.5V voltage is applied tocoupling gate 13B, which is capacitively coupled to floatinggate 14B (turning on the underlying channel region portion). Current will flow through the channel if floatinggate 14A is erased (i.e., erased state will have a positive voltage on floatinggate 14A and therefore the underlying channel region portion is turned on), and current will not flow through the channel if floatinggate 14A is programmed (i.e. is programmed with electrons sufficient to prevent turning on the underlying channel region portion). Floatinggate 14B is similarly read. -
FIGS. 3A-3C illustrate an alternate embodiment for forming the 2-bit memory cell, which starts with the structure inFIG. 1D . Asacrificial oxide spacer 25 is formed. A photoresist coating and photolithography masking step is used to cover the inner region withphotoresist 22. A poly etch is then used to remove the exposed portions ofpoly layer 14 in the outer regions. An implant process (e.g. implantation and anneal) is then performed to form drain regions (bit lines—BL) 24 in the substrate in the outer regions. Thereafter, an oxide wet etch is performed to removespacer 25 in the outer regions, as shown inFIG. 3A . After removal ofphotoresist 22,oxide 26 is formed such thatoxide layer 26 includes a steppedcontour 26 a. A photoresist coating and photolithography masking step is used to cover the structure with photoresist except for the inner region. An oxide anisotropic etch is then used to remove the oxide over thesubstrate 10. After removal of photoresist, anoxide layer 15 is grown over the structure in the inner region, which thickensoxide layer 12 over thesubstrate 10 in the outer regions, as shown inFIG. 3B . The remaining processing steps described above with respect toFIGS. 1G and 1H are performed, resulting in the structure shown inFIG. 3C . The erasegates 30 have anotch 31 facing a corner of the floatinggate 14 for enhanced erase operation performance. -
FIGS. 4A to 4D illustrate another embodiment for forming the 2-bit memory cell, which starts with the structure ofFIG. 1B , as shown inFIG. 4A . A poly etch is used to remove the exposedpoly layer 14 portions in the inner and the outer regions, instead of just in the inner region, leaving poly blocks 14. Spacers 42 (e.g. oxide or oxide-nitride) are formed along the sides of the structure, and a WLVT implantation is used to implant the substrate in the inner region, as shown inFIG. 4B . Photo resist 44 is formed covering the inner region, andspacers 42 facing the outer regions are removed. An implant is then usedform drain regions 46, as illustrated inFIG. 4C . - After removal of
photoresist 44,oxide 48 is formed on the structure, which removes exposed portions ofoxide layer 12 on the substrate. A photoresist coating and photolithography masking process is used to open the inner region, but leave the outer regions covered by photoresist. A oxide anisotropic etch is then used to remove theoxide 12 over thesubstrate 10 in the inner region. After removal of the photoresist, an oxide layer 50 (e.g. by thermal oxidation) is grown in the inner region, which thickensoxide layer 12 over thesubstrate 10 in the outer regions. A polysilicon deposition and etch back or CMP is used to form a layer of polysilicon in the inner and outer regions. A photoresist coating and photolithography masking, and polysilicon etch, are used to define the outer edges of the polysilicon layer in the outer regions. The resulting structure is shown inFIG. 4D (after photoresist removal), which results inpoly block 52 in the inner region and poly blocks 54 in the outer regions. Optionally,poly block 52 andoxide word line gate 52 on one side and the erasegate 54 on the other side can be independently varied (i.e. by the inclusion ofspacer 42 on just one side of the floating gate). -
FIGS. 5A-5D illustrate another embodiment for forming the 2-bit memory cell, which begins with the structure ofFIG. 1A . A photolithography and nitride etch process are used to form atrench 76 in thenitride layer 16.Oxide spacers 78 are formed on the trench sidewalls by oxide deposition and etch, as shown inFIG. 5A . A poly etch is performed to remove the exposed portion ofpoly layer 14 intrench 76. A WLVT implantation is used to implant the substrate undertrench 76. An oxide deposition and etch is used to formspacers 80 along the exposed sides ofpoly layer 14, as shown inFIG. 5B . A nitride etch is used to removenitride layer 16. A poly etch is used to remove exposed portions ofpoly layer 14. Photoresist is coated on the structure and selectively removed except fortrench 76, and an implant process is used to formdrain regions 82, as illustrated inFIG. 5C (after photoresist removal).Oxide layer 84 is formed on the exposed ends ofpoly layer 14 and exposed substrate in trench 76 (e.g. thermal oxide). A poly deposition and etch are performed to form poly block (word line gate) 86 intrench 76, and poly blocks (erase gates) 88 along the outer sides of floating gate blocks 14, as illustrated inFIG. 5D . -
FIGS. 6A-6D illustrate an alternate embodiment of the process ofFIGS. 5A-5D , wherein before spacers 78 are formed, a poly slope etch is performed so that the upper surface ofpoly layer 14 slopes downwardly as it extends away fromnitride layer 16, as shown inFIG. 6A .ONO layer 11 is formed over the structure, andpoly layer 13 is formed on ONO layer by poly deposition and etch back, as shown inFIG. 6B .Spacers 78 are then formed onpoly layer 13, as shown inFIG. 6C . The remaining processing steps described above with respect toFIGS. 5B to 5D are then performed, resulting in each floating gate having an upwardly sloping surface terminating in a sharper edge that faces the notch of the erase gate, as shown inFIG. 6D . -
FIG. 7 illustrates an alternate embodiment for the 2 bit memory cell ofFIG. 1H , where the memory cell does not include a coupling gate. Formation of the memory cell ofFIG. 7 is similar to that disclosed with respect toFIGS. 1A-1H , except omitting the formation of theONO layer 11 andsecond poly layer 13 before the formation of nitride layer 16 (seeFIG. 1A ). The operational voltages for the 2 bit memory cell ofFIG. 7 are illustrated in Table 2 below: -
TABLE 2 EG 30AEG 30BWL 34 BL 24ABL 24B Program bit 1 HV1 0 1 V HV2 −1 uA Program bit 2 0 HV1 1 V −1 uA HV2 Read bit 1 0 Vegr Vcc 0 Vblr Read bit 2 Vegr 0 Vcc Vblr 0 Erase both bits 11.5 V 11.5 V 0 0 0 -
Control circuitry 96 preferably (but not necessarily) formed on the same substrate 10 (as shown inFIG. 8 ) is configured program, read and erase anarray 98 of the 2-bit memory cells described herein by applying the voltages of Table 1 or Table 2. - It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the memory cell array of the present invention. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.
- It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed there between) and “indirectly on” (intermediate materials, elements or space disposed there between). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/945,659 US10056398B1 (en) | 2016-04-29 | 2018-04-04 | Method of forming split-gate, twin-bit non-volatile memory cell |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610285454.7 | 2016-04-29 | ||
CN201610285454 | 2016-04-29 | ||
CN201610285454.7A CN107342288B (en) | 2016-04-29 | 2016-04-29 | Split gate type dual bit non-volatile memory cell |
US15/476,663 US9972632B2 (en) | 2016-04-29 | 2017-03-31 | Split-gate, twin-bit non-volatile memory cell |
US15/945,659 US10056398B1 (en) | 2016-04-29 | 2018-04-04 | Method of forming split-gate, twin-bit non-volatile memory cell |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/476,663 Division US9972632B2 (en) | 2016-04-29 | 2017-03-31 | Split-gate, twin-bit non-volatile memory cell |
Publications (2)
Publication Number | Publication Date |
---|---|
US20180226421A1 true US20180226421A1 (en) | 2018-08-09 |
US10056398B1 US10056398B1 (en) | 2018-08-21 |
Family
ID=60159057
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/476,663 Active US9972632B2 (en) | 2016-04-29 | 2017-03-31 | Split-gate, twin-bit non-volatile memory cell |
US15/945,659 Active US10056398B1 (en) | 2016-04-29 | 2018-04-04 | Method of forming split-gate, twin-bit non-volatile memory cell |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/476,663 Active US9972632B2 (en) | 2016-04-29 | 2017-03-31 | Split-gate, twin-bit non-volatile memory cell |
Country Status (7)
Country | Link |
---|---|
US (2) | US9972632B2 (en) |
EP (2) | EP3982394B1 (en) |
JP (1) | JP6656412B2 (en) |
KR (1) | KR101992590B1 (en) |
CN (1) | CN107342288B (en) |
TW (1) | TWI632669B (en) |
WO (1) | WO2017189179A1 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107305892B (en) * | 2016-04-20 | 2020-10-02 | 硅存储技术公司 | Method of forming tri-gate non-volatile flash memory cell pairs using two polysilicon deposition steps |
CN108847388B (en) * | 2018-06-19 | 2020-10-27 | 上海华力微电子有限公司 | Floating gate isolation etching process under split gate structure |
CN112185815A (en) * | 2019-07-04 | 2021-01-05 | 硅存储技术公司 | Method of forming split gate flash memory cells with spacer defined floating gates and discretely formed polysilicon gates |
US11183572B2 (en) * | 2020-04-20 | 2021-11-23 | Taiwan Semiconductor Manufacturing Company Limited | Flash memory device including a buried floating gate and a buried erase gate and methods of forming the same |
CN114335186A (en) | 2020-09-30 | 2022-04-12 | 硅存储技术股份有限公司 | Split-gate non-volatile memory cell with erase gate disposed over word line gate and method of making the same |
CN114335185A (en) | 2020-09-30 | 2022-04-12 | 硅存储技术股份有限公司 | Split-gate dual bit non-volatile memory cell with erase gate disposed over word line gate and method of making the same |
CN115083912A (en) | 2021-03-11 | 2022-09-20 | 硅存储技术股份有限公司 | Split gate memory cell with improved control gate capacitive coupling and method of making same |
KR20230119016A (en) * | 2021-03-11 | 2023-08-14 | 실리콘 스토리지 테크놀로지 인크 | Split Gate Flash Memory Cell with Improved Control Gate Capacitive Coupling, and Method of Making The Same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160163722A1 (en) * | 2014-12-04 | 2016-06-09 | United Microelectronics Corp. | Non-volatile memory cell and method of manufacturing the same |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100488583B1 (en) * | 1997-12-31 | 2005-12-08 | 삼성전자주식회사 | Dual bit split gate flash memory device and method for driving the same |
JP4222675B2 (en) * | 1999-03-29 | 2009-02-12 | 三洋電機株式会社 | Nonvolatile semiconductor memory device |
US6151248A (en) * | 1999-06-30 | 2000-11-21 | Sandisk Corporation | Dual floating gate EEPROM cell array with steering gates shared by adjacent cells |
US6894343B2 (en) | 2001-05-18 | 2005-05-17 | Sandisk Corporation | Floating gate memory cells utilizing substrate trenches to scale down their size |
US6747310B2 (en) | 2002-10-07 | 2004-06-08 | Actrans System Inc. | Flash memory cells with separated self-aligned select and erase gates, and process of fabrication |
US6930348B2 (en) * | 2003-06-24 | 2005-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual bit split gate flash memory |
US20050012137A1 (en) | 2003-07-18 | 2005-01-20 | Amitay Levi | Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing |
US7169667B2 (en) * | 2003-07-30 | 2007-01-30 | Promos Technologies Inc. | Nonvolatile memory cell with multiple floating gates formed after the select gate |
US7046552B2 (en) | 2004-03-17 | 2006-05-16 | Actrans System Incorporation, Usa | Flash memory with enhanced program and erase coupling and process of fabricating the same |
US6992929B2 (en) * | 2004-03-17 | 2006-01-31 | Actrans System Incorporation, Usa | Self-aligned split-gate NAND flash memory and fabrication process |
US7518912B2 (en) * | 2006-08-25 | 2009-04-14 | Powerchip Semiconductor Corp. | Multi-level non-volatile memory |
US20090039410A1 (en) * | 2007-08-06 | 2009-02-12 | Xian Liu | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
US7800159B2 (en) * | 2007-10-24 | 2010-09-21 | Silicon Storage Technology, Inc. | Array of contactless non-volatile memory cells |
US8325521B2 (en) * | 2010-10-08 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and inhibited operation of flash memory with split gate |
CN102637455A (en) | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | Memory array |
CN102956643A (en) * | 2011-08-24 | 2013-03-06 | 硅存储技术公司 | Non-volatile floating gate storage unit manufacturing method and storage unit manufactured by same |
CN102969346B (en) * | 2011-08-31 | 2016-08-10 | 硅存储技术公司 | There is band and improve floating boom and the Nonvolatile memery unit of coupling grid of coupling ratio |
JP6114534B2 (en) | 2012-11-07 | 2017-04-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
US9123822B2 (en) * | 2013-08-02 | 2015-09-01 | Silicon Storage Technology, Inc. | Split gate non-volatile flash memory cell having a silicon-metal floating gate and method of making same |
US10312248B2 (en) * | 2014-11-12 | 2019-06-04 | Silicon Storage Technology, Inc. | Virtual ground non-volatile memory array |
US9793279B2 (en) | 2015-07-10 | 2017-10-17 | Silicon Storage Technology, Inc. | Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing |
-
2016
- 2016-04-29 CN CN201610285454.7A patent/CN107342288B/en active Active
-
2017
- 2017-03-31 US US15/476,663 patent/US9972632B2/en active Active
- 2017-04-03 EP EP21205392.0A patent/EP3982394B1/en active Active
- 2017-04-03 EP EP17790086.7A patent/EP3449486B1/en active Active
- 2017-04-03 JP JP2018555757A patent/JP6656412B2/en active Active
- 2017-04-03 WO PCT/US2017/025683 patent/WO2017189179A1/en active Application Filing
- 2017-04-03 KR KR1020187034585A patent/KR101992590B1/en active IP Right Grant
- 2017-04-11 TW TW106112012A patent/TWI632669B/en active
-
2018
- 2018-04-04 US US15/945,659 patent/US10056398B1/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160163722A1 (en) * | 2014-12-04 | 2016-06-09 | United Microelectronics Corp. | Non-volatile memory cell and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
EP3449486A4 (en) | 2020-04-15 |
CN107342288A (en) | 2017-11-10 |
US9972632B2 (en) | 2018-05-15 |
JP6656412B2 (en) | 2020-03-04 |
CN107342288B (en) | 2020-08-04 |
KR101992590B1 (en) | 2019-06-24 |
TW201740543A (en) | 2017-11-16 |
KR20180132950A (en) | 2018-12-12 |
EP3449486A1 (en) | 2019-03-06 |
TWI632669B (en) | 2018-08-11 |
US10056398B1 (en) | 2018-08-21 |
US20170317093A1 (en) | 2017-11-02 |
JP2019515495A (en) | 2019-06-06 |
EP3449486B1 (en) | 2022-01-26 |
EP3982394B1 (en) | 2024-02-14 |
EP3982394A1 (en) | 2022-04-13 |
WO2017189179A1 (en) | 2017-11-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10056398B1 (en) | Method of forming split-gate, twin-bit non-volatile memory cell | |
US8114740B2 (en) | Profile of flash memory cells | |
US10312246B2 (en) | Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling | |
US10418451B1 (en) | Split-gate flash memory cell with varying insulation gate oxides, and method of forming same | |
KR102305705B1 (en) | A method of fabricating a split gate flash memory cell having an erase gate | |
JP5348824B2 (en) | NROM device and manufacturing method thereof | |
CN113169175A (en) | Split-gate nonvolatile memory unit with fin field effect transistor structure, HKMG memory and logic gate and preparation method thereof | |
US11404545B2 (en) | Method of forming split-gate flash memory cell with spacer defined floating gate and discretely formed polysilicon gates | |
US11621335B2 (en) | Method of making split-gate non-volatile memory cells with erase gates disposed over word line gates | |
US11315635B2 (en) | Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same | |
US9882033B2 (en) | Method of manufacturing a non-volatile memory cell and array having a trapping charge layer in a trench | |
KR100595118B1 (en) | Nonvolatile memory cell and method of forming and operating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT, DELAWARE Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INC.;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:053311/0305 Effective date: 20200327 |
|
AS | Assignment |
Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: MICROCHIP TECHNOLOGY INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: MICROSEMI CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INC.;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:052856/0909 Effective date: 20200529 Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, MINNESOTA Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INC.;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:053468/0705 Effective date: 20200529 |
|
AS | Assignment |
Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT, MINNESOTA Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:055671/0612 Effective date: 20201217 |
|
AS | Assignment |
Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT, MINNESOTA Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:057935/0474 Effective date: 20210528 |
|
AS | Assignment |
Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT, MINNESOTA Free format text: GRANT OF SECURITY INTEREST IN PATENT RIGHTS;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:058214/0625 Effective date: 20211117 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059263/0001 Effective date: 20220218 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059263/0001 Effective date: 20220218 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059263/0001 Effective date: 20220218 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059263/0001 Effective date: 20220218 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059263/0001 Effective date: 20220218 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059358/0335 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059358/0335 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059358/0335 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059358/0335 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059358/0335 Effective date: 20220228 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 |