US20180226403A1 - Insulating layer next to fin structure and method of removing fin structure - Google Patents
Insulating layer next to fin structure and method of removing fin structure Download PDFInfo
- Publication number
- US20180226403A1 US20180226403A1 US15/445,928 US201715445928A US2018226403A1 US 20180226403 A1 US20180226403 A1 US 20180226403A1 US 201715445928 A US201715445928 A US 201715445928A US 2018226403 A1 US2018226403 A1 US 2018226403A1
- Authority
- US
- United States
- Prior art keywords
- fin structure
- etching process
- substrate
- fin structures
- fin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 36
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000012670 alkaline solution Substances 0.000 description 4
- 239000006117 anti-reflective coating Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- 239000003929 acidic solution Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
Definitions
- the present invention relates to a method of removing a fin structure, and more particularly to a method of removing a fin structure by two different etching processes.
- Transistors such as metal oxide semiconductor field-effect transistors (MOSFETs)
- MOSFETs metal oxide semiconductor field-effect transistors
- Some semiconductor devices such as high performance processor devices, can include millions of transistors. For such devices, scaling down the size of the transistors to thus increase transistor density has traditionally been a high priority in the semiconductor manufacturing industry. This scaling down process provides the benefits of increased production efficiency and lowered associated costs.
- an insulating layer is provided next to a fin structure.
- the insulating layer includes a substrate, a first fin structure extending and protruding from the substrate, a recess embedded in the substrate and adjacent to the first fin structure, and an insulating layer disposed on the substrate, which contacts the first fin structure and fills in the recess.
- a method of removing a fin structure includes the steps of providing a substrate, and providing a fin structure extending from the substrate.
- a mask layer is disposed on a top surface of the fin structure, and an organic dielectric layer covers the substrate, the fin structure and the mask layer. Later, the organic dielectric layer is patterned so an opening is formed on the organic dielectric layer, wherein the mask layer is exposed by the opening. Subsequently, a first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Finally, a second etching process is performed to remove the fin structure.
- FIG. 1 to FIG. 5 depict a method of removing a fin structure according to a preferred embodiment of the present invention, wherein:
- FIG. 1 depicts a stage of providing a substrate with numerous fin structures
- FIG. 2 is a fabricating stage following FIG. 1 ;
- FIG. 3 is a fabricating stage following FIG. 2 ;
- FIG. 4 is a fabricating stage following FIG. 3 ;
- FIG. 5 is a fabricating stage following FIG. 4 .
- FIG. 6 depicts an insulating layer next to a fin structure.
- FIG. 8 depicts a recess in a triangular profile.
- fin structures in different regions will often be arranged in different densities. In other words, fin structures are closer to each other in a high density region, and are farther from each other in a low density region.
- the fabricating steps of fin structures include etching the substrate. If, however, fin structures in the high density region and in the low density region are formed by a single etching step, the shape of the resultant fin structures will not match the original design due to the loading effect.
- the method of the present invention specially forms fin structures with the same density in all regions. Later, redundant fin structures in the low density region are removed by two different etching processes. In detail, a dry etching process is utilized to remove a mask layer on the fin structure and then a wet etching process removes the entire fin structure. In some circumstances, part of the fin structure is removed in the dry etching process along with the mask layer. If the redundant fin structures are removed by only the dry etching process, an organic dielectric layer covering wanted fin structures adjacent to the redundant fin structures will be removed entirely before the dry etching process is over, causing the wanted fin structures to undergo a dry etch as they are not protected by the organic dielectric layer. By using the two step etching process of the present invention, the wanted fin structures will not be damaged during the removal of the redundant fin structures.
- FIG. 1 to FIG. 5 depict a method of removing a fin structure according to a preferred embodiment of the present invention.
- a substrate 10 is provided.
- the substrate 10 the present invention may be a bulk silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate or a silicon carbide substrate.
- At least a fin structure 12 extends and protrudes from the substrate 10 .
- the number of fin structures 12 may be single or plural, and is exemplified as four in the present invention.
- the fin structures 12 are further divided into two first fin structures 14 and two second fin structures 16 based on whether the fin structures 12 will be removed or not, wherein the first fin structures 14 will be preserved, and the second fin structures 16 will be removed.
- the first fin structures 14 and the second fin structures 16 are disposed alternately.
- the number of the first fin structures 14 and the second fin structures 16 can be altered based on different requirements.
- the first fin structures 14 and the second fin structures 16 are the same in their material and structure. Therefore, only the material and structure of the second fin structures 16 will be described in the following description.
- the material of each of the second fin structures 16 is the same as the material of the substrate 10 . For example, if the substrate 10 is made of silicon, the second fin structures 16 are made of silicon as well.
- Each second fin structure 16 includes a top surface 18 .
- the top surface 18 is the highest surface of the second fin structure 16 with respect to the top surface of the substrate 10 .
- a mask layer 20 is disposed on and contacts the top surface 18 of each of the second fin structures 16 .
- a mask layer 20 is also disposed on each of the first fin structures 14 .
- the mask layer 20 may be made of single or multiple materials.
- the mask layer 20 may include silicon nitride, silicon oxide or silicon oxynitride.
- the mask layer 20 is formed by a silicon oxide layer 22 and a silicon nitride layer 24 .
- the silicon oxide layer 22 is below the silicon nitride layer 24 .
- a recess 26 is disposed between the first fin structure 14 and the second fin structure 16 next to the first fin structure 14 .
- a height H of each of the second fin structures 16 is preferably 1200 angstroms.
- a width W of the recess 26 is preferably smaller than 20 nanometers.
- An organic dielectric layer 28 is formed to entirely cover the substrate 10 , the first fin structures 14 and the second fin structures 16 , wherein the organic dielectric layer 28 fills up the recess 26 .
- the organic dielectric layer 28 may contains carbon, hydrogen, and oxygen, but does not contain silicon.
- the organic dielectric layer 28 is preferably made of homogeneous and non-photosensitive material.
- the organic dielectric layer 28 can be formed on the substrate 10 , the first fin structures 14 , and the second fin structures 16 by a spin coating process. In this way, the organic dielectric layer 28 can entirely fill up the recess 26 and have a flat top surface.
- a silicon-containing bottom anti-reflective coating 30 and a photoresist layer 32 are formed to cover the organic dielectric layer 28 . Later, the photoresist layer 32 is patterned to form at least one opening 34 within the photoresist layer 32 . In this embodiment, the number of openings 34 is exemplified as two. As shown in FIG. 2 , the silicon-containing bottom anti-reflective coating 30 and the organic dielectric layer 32 are patterned by taking the photoresist layer 32 as a mask to form at least one opening 36 on the organic dielectric layer 28 .
- the photoresist layer 32 serves as the mask when patterning the silicon-containing bottom anti-reflective coating 30 and the organic dielectric layer 32 , the number of openings 36 should be the same as the number of openings 34 .
- the mask layer 20 on each of the second fin structures 16 is exposed through the corresponding opening 36 . Therefore, one mask layer 20 is exposed through one opening 36 .
- the organic dielectric layer 28 can be patterned by a dry etching process. During the dry etching process, the photoresist layer 32 and the silicon-containing bottom anti-reflective coating 30 are consumed entirely.
- the etchant in the dry etching process can be hydrogen bromide, chlorine gas or fluorine-containing gas.
- a first etching process 38 is performed by taking the organic dielectric layer 28 as a mask to entirely remove the exposed mask layers 20 .
- the first etching process 38 is preferably an anisotropic etching process such as a dry etching process.
- the etchant used in the first etching process 38 may be a fluorine-containing gas.
- the second fin structures 16 are exposed through the openings 36 .
- the first etching process 38 can continue to etch the second fin structures 16 . This is shown in FIG. 7 . For example, one third of the height H of each of the second fin structures 16 can be removed.
- FIG. 4 continues from FIG. 3 .
- a second etching process 40 is performed to entirely remove the second fin structures 16 by taking the organic dielectric layer 28 as a mask.
- the second etching process 40 continues to etch part of the substrate 10 to form a recess 42 in the substrate 10 .
- the second etching process 40 stops at the point that the second fin structures 16 are entirely removed. Therefore, no recess will be formed in the substrate 10 .
- Subsequent figures and processes show the recess 42 is formed in the substrate 10 as an example.
- the second etching process 40 is preferably an isotropic etching process such as a wet etching process or an isotropic dry etching process. If the second etching process 40 is a wet etching process, the etchant can be an alkaline solution or an acidic solution. If an alkaline solution is used, the substrate 10 will be etched along the lattice direction by the alkaline solution to form the recess 42 in a hexagonal profile (as shown in FIG. 4 ) or to form a recess 142 in a triangular profile (as shown in FIG. 8 ).
- the etchant can be an alkaline solution or an acidic solution. If an alkaline solution is used, the substrate 10 will be etched along the lattice direction by the alkaline solution to form the recess 42 in a hexagonal profile (as shown in FIG. 4 ) or to form a recess 142 in a triangular profile (as shown in FIG. 8 ).
- the substrate 10 will not be etched along the lattice direction.
- the recess will not form a hexagonal profile or a triangular profile.
- the alkaline solution may be tetramethylammonium hydroxide (TMAH). It is noteworthy that the organic dielectric layer 28 still covers the substrate 10 while the second fin structures 16 are removed.
- the organic dielectric layer 28 is completely removed.
- an insulating layer (not shown) is formed to cover the substrate 10 and the first fin structures 14 , and to fill in the recess 42 .
- the insulating layer is preferably silicon oxide. Later, the insulating layer is etched back to a predetermined height to form an insulating layer 44 .
- the insulating layer 44 serves as a shallow trench isolation (STI) at both sides of each of the first fin structures 14 .
- the shallow trench isolation fills up the recess 42 .
- a gate dielectric layer, and a gate electrode can be formed to cross the first fin structures 14 . Later, source/drain doping regions can be formed at two sides of the gate electrode in the first fin structures 14 . Based on different requirements, the mask layer 20 on the first fin structures 14 can be removed before forming the gate dielectric layer.
- the position of the first fin structures 14 and the second fin structures 16 can be altered based on different requirements.
- the number of the first fin structures 14 , the number of the second fin structures 16 , and the total number of the first fin structures 14 and the second fin structures 16 can also be altered.
- the number of the recesses 42 is equal to the number of second fin structures 16 .
- FIG. 6 depicts an insulating layer next to a fin structure.
- the insulating layer includes a substrate 10 .
- a first fin structure 14 extends and protrudes from the substrate 10 .
- the material of the first fin structure 14 is the same as the material of the substrate 10 .
- the substrate 10 is made of silicon
- the first fin structure 14 is made of silicon as well.
- a recess 42 is embedded in the substrate 10 .
- the recess 42 is adjacent to the first fin structure 14 .
- the recess 42 has a hexagonal profile or a triangular profile.
- An insulating layer 44 is disposed on the substrate 10 , contacts the first fin structure 14 and fills in the recess 42 .
- Another first fin structure 14 extends and protrudes from the substrate 10 .
- the recess 42 is disposed between the two first fin structures 14 .
- the insulating layer 44 contacts both of the first fin structures 14 .
- the insulating layer 44 includes silicon oxide.
- a mask layer 20 covers each of the first fin structures 44 .
- the mask layer 20 includes silicon oxide layer 22 and silicon nitride layer 24 disposed from bottom to top.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- The present invention relates to a method of removing a fin structure, and more particularly to a method of removing a fin structure by two different etching processes.
- Transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), are the core building block of the vast majority of semiconductor devices. Some semiconductor devices, such as high performance processor devices, can include millions of transistors. For such devices, scaling down the size of the transistors to thus increase transistor density has traditionally been a high priority in the semiconductor manufacturing industry. This scaling down process provides the benefits of increased production efficiency and lowered associated costs.
- Such scaling down, however, has also increased the complexity of processing and manufacturing ICs. For the advantages of scaling down to be fully realized, developments in IC processing and manufacturing are needed. A three dimensional transistor, such as a fin-type field-effect transistor (FinFET), has been introduced to replace a planar transistor. Existing FinFET devices and methods of fabricating FinFET devices, although adequate for their intended purposes, have not been entirely satisfactory in all respects. For example, forming fin structures with different densities raise challenges in FinFET process development. In view of the above, it would be an advantage in the art to provide a better method to form fin structures with different densities.
- In one embodiment, an insulating layer is provided next to a fin structure. The insulating layer includes a substrate, a first fin structure extending and protruding from the substrate, a recess embedded in the substrate and adjacent to the first fin structure, and an insulating layer disposed on the substrate, which contacts the first fin structure and fills in the recess.
- In another embodiment, a method of removing a fin structure includes the steps of providing a substrate, and providing a fin structure extending from the substrate. A mask layer is disposed on a top surface of the fin structure, and an organic dielectric layer covers the substrate, the fin structure and the mask layer. Later, the organic dielectric layer is patterned so an opening is formed on the organic dielectric layer, wherein the mask layer is exposed by the opening. Subsequently, a first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Finally, a second etching process is performed to remove the fin structure.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 toFIG. 5 depict a method of removing a fin structure according to a preferred embodiment of the present invention, wherein: -
FIG. 1 depicts a stage of providing a substrate with numerous fin structures; -
FIG. 2 is a fabricating stage followingFIG. 1 ; -
FIG. 3 is a fabricating stage followingFIG. 2 ; -
FIG. 4 is a fabricating stage followingFIG. 3 ; -
FIG. 5 is a fabricating stage followingFIG. 4 . -
FIG. 6 depicts an insulating layer next to a fin structure. -
FIG. 7 depicts a method of removing a fin structure according to another preferred embodiment of the present invention. -
FIG. 8 depicts a recess in a triangular profile. - Based on different product requirements, fin structures in different regions will often be arranged in different densities. In other words, fin structures are closer to each other in a high density region, and are farther from each other in a low density region. The fabricating steps of fin structures include etching the substrate. If, however, fin structures in the high density region and in the low density region are formed by a single etching step, the shape of the resultant fin structures will not match the original design due to the loading effect.
- To avoid this loading effect, the method of the present invention specially forms fin structures with the same density in all regions. Later, redundant fin structures in the low density region are removed by two different etching processes. In detail, a dry etching process is utilized to remove a mask layer on the fin structure and then a wet etching process removes the entire fin structure. In some circumstances, part of the fin structure is removed in the dry etching process along with the mask layer. If the redundant fin structures are removed by only the dry etching process, an organic dielectric layer covering wanted fin structures adjacent to the redundant fin structures will be removed entirely before the dry etching process is over, causing the wanted fin structures to undergo a dry etch as they are not protected by the organic dielectric layer. By using the two step etching process of the present invention, the wanted fin structures will not be damaged during the removal of the redundant fin structures.
-
FIG. 1 toFIG. 5 depict a method of removing a fin structure according to a preferred embodiment of the present invention. As shown inFIG. 1 , asubstrate 10 is provided. Thesubstrate 10 the present invention may be a bulk silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate or a silicon carbide substrate. At least afin structure 12 extends and protrudes from thesubstrate 10. The number offin structures 12 may be single or plural, and is exemplified as four in the present invention. Thefin structures 12 are further divided into twofirst fin structures 14 and twosecond fin structures 16 based on whether thefin structures 12 will be removed or not, wherein thefirst fin structures 14 will be preserved, and thesecond fin structures 16 will be removed. Thefirst fin structures 14 and thesecond fin structures 16 are disposed alternately. The number of thefirst fin structures 14 and thesecond fin structures 16 can be altered based on different requirements. Thefirst fin structures 14 and thesecond fin structures 16 are the same in their material and structure. Therefore, only the material and structure of thesecond fin structures 16 will be described in the following description. The material of each of thesecond fin structures 16 is the same as the material of thesubstrate 10. For example, if thesubstrate 10 is made of silicon, thesecond fin structures 16 are made of silicon as well. Eachsecond fin structure 16 includes atop surface 18. Thetop surface 18 is the highest surface of thesecond fin structure 16 with respect to the top surface of thesubstrate 10. Amask layer 20 is disposed on and contacts thetop surface 18 of each of thesecond fin structures 16. Amask layer 20 is also disposed on each of thefirst fin structures 14. Themask layer 20 may be made of single or multiple materials. Themask layer 20 may include silicon nitride, silicon oxide or silicon oxynitride. In this embodiment, themask layer 20 is formed by asilicon oxide layer 22 and asilicon nitride layer 24. Thesilicon oxide layer 22 is below thesilicon nitride layer 24. Furthermore, arecess 26 is disposed between thefirst fin structure 14 and thesecond fin structure 16 next to thefirst fin structure 14. A height H of each of thesecond fin structures 16 is preferably 1200 angstroms. A width W of therecess 26 is preferably smaller than 20 nanometers. Anorganic dielectric layer 28 is formed to entirely cover thesubstrate 10, thefirst fin structures 14 and thesecond fin structures 16, wherein theorganic dielectric layer 28 fills up therecess 26. Theorganic dielectric layer 28 may contains carbon, hydrogen, and oxygen, but does not contain silicon. Theorganic dielectric layer 28 is preferably made of homogeneous and non-photosensitive material. Because of the property of theorganic dielectric layer 28, theorganic dielectric layer 28 can be formed on thesubstrate 10, thefirst fin structures 14, and thesecond fin structures 16 by a spin coating process. In this way, theorganic dielectric layer 28 can entirely fill up therecess 26 and have a flat top surface. - A silicon-containing bottom
anti-reflective coating 30 and aphotoresist layer 32 are formed to cover theorganic dielectric layer 28. Later, thephotoresist layer 32 is patterned to form at least oneopening 34 within thephotoresist layer 32. In this embodiment, the number ofopenings 34 is exemplified as two. As shown inFIG. 2 , the silicon-containing bottomanti-reflective coating 30 and theorganic dielectric layer 32 are patterned by taking thephotoresist layer 32 as a mask to form at least oneopening 36 on theorganic dielectric layer 28. Because thephotoresist layer 32 serves as the mask when patterning the silicon-containing bottomanti-reflective coating 30 and theorganic dielectric layer 32, the number ofopenings 36 should be the same as the number ofopenings 34. Themask layer 20 on each of thesecond fin structures 16 is exposed through thecorresponding opening 36. Therefore, onemask layer 20 is exposed through oneopening 36. Theorganic dielectric layer 28 can be patterned by a dry etching process. During the dry etching process, thephotoresist layer 32 and the silicon-containing bottomanti-reflective coating 30 are consumed entirely. The etchant in the dry etching process can be hydrogen bromide, chlorine gas or fluorine-containing gas. - As shown in
FIG. 3 , afirst etching process 38 is performed by taking theorganic dielectric layer 28 as a mask to entirely remove the exposed mask layers 20. Thefirst etching process 38 is preferably an anisotropic etching process such as a dry etching process. The etchant used in thefirst etching process 38 may be a fluorine-containing gas. After removing the mask layers 20, thesecond fin structures 16 are exposed through theopenings 36. According to another preferred embodiment of the present invention, after removing the mask layers 20 entirely, thefirst etching process 38 can continue to etch thesecond fin structures 16. This is shown inFIG. 7 . For example, one third of the height H of each of thesecond fin structures 16 can be removed. -
FIG. 4 continues fromFIG. 3 . As shown inFIG. 4 , asecond etching process 40 is performed to entirely remove thesecond fin structures 16 by taking theorganic dielectric layer 28 as a mask. After removing thesecond fin structures 16, thesecond etching process 40 continues to etch part of thesubstrate 10 to form arecess 42 in thesubstrate 10. According to another preferred embodiment of the present invention, thesecond etching process 40 stops at the point that thesecond fin structures 16 are entirely removed. Therefore, no recess will be formed in thesubstrate 10. Subsequent figures and processes show therecess 42 is formed in thesubstrate 10 as an example. Thesecond etching process 40 is preferably an isotropic etching process such as a wet etching process or an isotropic dry etching process. If thesecond etching process 40 is a wet etching process, the etchant can be an alkaline solution or an acidic solution. If an alkaline solution is used, thesubstrate 10 will be etched along the lattice direction by the alkaline solution to form therecess 42 in a hexagonal profile (as shown inFIG. 4 ) or to form arecess 142 in a triangular profile (as shown inFIG. 8 ). If, however, an acidic solution is used or an isotropic dry etching process is used, thesubstrate 10 will not be etched along the lattice direction. The recess will not form a hexagonal profile or a triangular profile. The alkaline solution may be tetramethylammonium hydroxide (TMAH). It is noteworthy that theorganic dielectric layer 28 still covers thesubstrate 10 while thesecond fin structures 16 are removed. - As shown in
FIG. 5 , theorganic dielectric layer 28 is completely removed. At this point, the method of removing a fin structure of the present invention is completed. As shown inFIG. 6 , an insulating layer (not shown) is formed to cover thesubstrate 10 and thefirst fin structures 14, and to fill in therecess 42. The insulating layer is preferably silicon oxide. Later, the insulating layer is etched back to a predetermined height to form an insulatinglayer 44. The insulatinglayer 44 serves as a shallow trench isolation (STI) at both sides of each of thefirst fin structures 14. The shallow trench isolation fills up therecess 42. After that, a gate dielectric layer, and a gate electrode can be formed to cross thefirst fin structures 14. Later, source/drain doping regions can be formed at two sides of the gate electrode in thefirst fin structures 14. Based on different requirements, themask layer 20 on thefirst fin structures 14 can be removed before forming the gate dielectric layer. - The position of the
first fin structures 14 and thesecond fin structures 16 can be altered based on different requirements. The number of thefirst fin structures 14, the number of thesecond fin structures 16, and the total number of thefirst fin structures 14 and thesecond fin structures 16 can also be altered. For example, there can be twofirst fin structures 14 arranged in sequence followed by twosecond fin structures 16 arranged in sequence That is, there will be tworecesses 42 side by side with no fin structure disposed between the tworecesses 42 after the etching processes. In another case, there can be twofirst fin structures 14 and onesecond fin structure 16. In this way, onesecond fin structure 16 will be removed, while the twofirst fin structures 14 remain. In addition, the number of therecesses 42 is equal to the number ofsecond fin structures 16. -
FIG. 6 depicts an insulating layer next to a fin structure. As shown inFIG. 6 , the insulating layer includes asubstrate 10. Afirst fin structure 14 extends and protrudes from thesubstrate 10. The material of thefirst fin structure 14 is the same as the material of thesubstrate 10. For example, if thesubstrate 10 is made of silicon, thefirst fin structure 14 is made of silicon as well. Arecess 42 is embedded in thesubstrate 10. Therecess 42 is adjacent to thefirst fin structure 14. Therecess 42 has a hexagonal profile or a triangular profile. An insulatinglayer 44 is disposed on thesubstrate 10, contacts thefirst fin structure 14 and fills in therecess 42. Anotherfirst fin structure 14 extends and protrudes from thesubstrate 10. Therecess 42 is disposed between the twofirst fin structures 14. The insulatinglayer 44 contacts both of thefirst fin structures 14. The insulatinglayer 44 includes silicon oxide. Amask layer 20 covers each of thefirst fin structures 44. Themask layer 20 includessilicon oxide layer 22 andsilicon nitride layer 24 disposed from bottom to top. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (12)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710070806.1A CN108417631B (en) | 2017-02-09 | 2017-02-09 | Insulating layer beside fin-shaped structure and method for removing fin-shaped structure |
CN201710070806.1 | 2017-02-09 | ||
CN201710070806 | 2017-02-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20180226403A1 true US20180226403A1 (en) | 2018-08-09 |
US10276443B2 US10276443B2 (en) | 2019-04-30 |
Family
ID=63037374
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/445,928 Active 2037-03-09 US10276443B2 (en) | 2017-02-09 | 2017-02-28 | Insulating layer next to fin structure and method of removing fin structure |
Country Status (2)
Country | Link |
---|---|
US (1) | US10276443B2 (en) |
CN (1) | CN108417631B (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180358306A1 (en) * | 2016-07-29 | 2018-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy Fin Etch to Form Recesses in Substrate |
US10566444B2 (en) * | 2017-12-21 | 2020-02-18 | International Business Machines Corporation | Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance |
US20200135898A1 (en) * | 2018-10-30 | 2020-04-30 | International Business Machines Corporation | Hard mask replenishment for etching processes |
US20210217625A1 (en) * | 2020-01-09 | 2021-07-15 | Samsung Electronics Co., Ltd. | Methods of cutting a fine pattern, methods of forming active patterns using the same, and methods of manufacturing a semiconductor device using the same |
US11133224B2 (en) * | 2019-09-27 | 2021-09-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and method for forming the same |
US11211478B2 (en) * | 2020-02-28 | 2021-12-28 | Semiconductor Manufacturing (Shanghai) International Corporation | Semiconductor structure and method for forming same |
US20230066097A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Active region cut process |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11189614B2 (en) * | 2018-03-16 | 2021-11-30 | Intel Corporation | Process etch with reduced loading effect |
US10818556B2 (en) * | 2018-12-17 | 2020-10-27 | United Microelectronics Corp. | Method for forming a semiconductor structure |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050230348A1 (en) * | 2004-04-14 | 2005-10-20 | Nec Lcd Technologies, Ltd. | Method for forming organic mask and method for forming pattern using said organic mask |
US20130277759A1 (en) * | 2012-04-20 | 2013-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Fin Structures and Methods for Forming the Same |
US8617996B1 (en) * | 2013-01-10 | 2013-12-31 | Globalfoundries Inc. | Fin removal method |
US20150206954A1 (en) * | 2014-01-23 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method Of Making a FinFET Device |
US20160268142A1 (en) * | 2015-03-09 | 2016-09-15 | United Microelectronics Corp. | Manufacturing method of patterned structure of semiconductor device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW432610B (en) * | 1998-07-24 | 2001-05-01 | United Microelectronics Corp | Manufacturing method for shallow trench isolation area |
KR20070001456A (en) * | 2005-06-29 | 2007-01-04 | 주식회사 하이닉스반도체 | Method for manufacturing saddle type transistor |
US8598675B2 (en) * | 2011-02-10 | 2013-12-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structure profile for gap filling |
US8658536B1 (en) | 2012-09-05 | 2014-02-25 | Globalfoundries Inc. | Selective fin cut process |
US9070710B2 (en) * | 2013-06-07 | 2015-06-30 | United Microelectronics Corp. | Semiconductor process |
CN105374871B (en) | 2014-08-22 | 2020-05-19 | 联华电子股份有限公司 | Fin structure and forming method thereof |
CN106252391B (en) * | 2015-06-09 | 2021-02-19 | 联华电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
-
2017
- 2017-02-09 CN CN201710070806.1A patent/CN108417631B/en active Active
- 2017-02-28 US US15/445,928 patent/US10276443B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050230348A1 (en) * | 2004-04-14 | 2005-10-20 | Nec Lcd Technologies, Ltd. | Method for forming organic mask and method for forming pattern using said organic mask |
US20130277759A1 (en) * | 2012-04-20 | 2013-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Fin Structures and Methods for Forming the Same |
US8617996B1 (en) * | 2013-01-10 | 2013-12-31 | Globalfoundries Inc. | Fin removal method |
US20150206954A1 (en) * | 2014-01-23 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method Of Making a FinFET Device |
US20160268142A1 (en) * | 2015-03-09 | 2016-09-15 | United Microelectronics Corp. | Manufacturing method of patterned structure of semiconductor device |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180358306A1 (en) * | 2016-07-29 | 2018-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy Fin Etch to Form Recesses in Substrate |
US10679950B2 (en) * | 2016-07-29 | 2020-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming recesses in substrates by etching dummy Fins |
US10861800B2 (en) | 2016-07-29 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure having a crown-shaped semiconductor strip and an isolation region recessed in the substrate |
US11488912B2 (en) | 2016-07-29 | 2022-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming recesses in a substrate by etching dummy fins |
US10566444B2 (en) * | 2017-12-21 | 2020-02-18 | International Business Machines Corporation | Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance |
US20200135898A1 (en) * | 2018-10-30 | 2020-04-30 | International Business Machines Corporation | Hard mask replenishment for etching processes |
US11133224B2 (en) * | 2019-09-27 | 2021-09-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and method for forming the same |
US20210217625A1 (en) * | 2020-01-09 | 2021-07-15 | Samsung Electronics Co., Ltd. | Methods of cutting a fine pattern, methods of forming active patterns using the same, and methods of manufacturing a semiconductor device using the same |
US11842899B2 (en) * | 2020-01-09 | 2023-12-12 | Samsung Electronics Co., Ltd. | Methods of cutting a fine pattern, methods of forming active patterns using the same, and methods of manufacturing a semiconductor device using the same |
US11211478B2 (en) * | 2020-02-28 | 2021-12-28 | Semiconductor Manufacturing (Shanghai) International Corporation | Semiconductor structure and method for forming same |
US20230066097A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Active region cut process |
Also Published As
Publication number | Publication date |
---|---|
US10276443B2 (en) | 2019-04-30 |
CN108417631A (en) | 2018-08-17 |
CN108417631B (en) | 2022-06-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10276443B2 (en) | Insulating layer next to fin structure and method of removing fin structure | |
US8609480B2 (en) | Methods of forming isolation structures on FinFET semiconductor devices | |
TWI509736B (en) | Finfets having dielectric punch-through stoppers | |
CN108735813B (en) | Semiconductor structure and forming method thereof | |
US8936986B2 (en) | Methods of forming finfet devices with a shared gate structure | |
US8741701B2 (en) | Fin structure formation including partial spacer removal | |
TW201735352A (en) | Semiconductor device and method of forming the same | |
CN107346759B (en) | Semiconductor structure and manufacturing method thereof | |
US10332877B2 (en) | Semiconductor device and manufacturing method thereof | |
CN107785315B (en) | Method for forming semiconductor structure | |
US20180005894A1 (en) | Semiconductor structure having contact holes between sidewall spacers | |
US20180061714A1 (en) | Semiconductor structure and fabrication method thereof | |
CN106158628B (en) | Semiconductor structure and manufacturing process thereof | |
US9721804B1 (en) | Semiconductor device and method for fabricating the same | |
CN107978563B (en) | Semiconductor device, preparation method and electronic device | |
CN109887845B (en) | Semiconductor device and method of forming the same | |
CN107731917B (en) | Method for forming semiconductor structure | |
CN107689330B (en) | Semiconductor device, preparation method and electronic device | |
US9748333B2 (en) | Semiconductor structure including dummy structure and semiconductor pattern structure including dummy structure | |
US10460997B2 (en) | Manufacturing method of semiconductor device | |
CN111599684B (en) | Fin manufacturing method, fin field effect transistor and fin structure | |
CN111446286B (en) | Semiconductor structure and forming method thereof | |
CN111508842B (en) | Semiconductor device and method of forming the same | |
CN111430241B (en) | Semiconductor structure and forming method thereof | |
CN111463276B (en) | Semiconductor structure and forming method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, SHIN-CHI;CHEN, CHIH-CHUNG;LIU, AN-CHI;AND OTHERS;REEL/FRAME:041405/0808 Effective date: 20170221 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |