US20180190713A1 - Magnetic Memory Device with Grid-Shaped Common Source Plate, System, and Method of Fabrication - Google Patents
Magnetic Memory Device with Grid-Shaped Common Source Plate, System, and Method of Fabrication Download PDFInfo
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- US20180190713A1 US20180190713A1 US15/399,509 US201715399509A US2018190713A1 US 20180190713 A1 US20180190713 A1 US 20180190713A1 US 201715399509 A US201715399509 A US 201715399509A US 2018190713 A1 US2018190713 A1 US 2018190713A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- H01L27/222—
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
Definitions
- Embodiments disclosed herein relate to magnetic memory devices and electronic systems including a magnetic memory device. More specifically, embodiments disclosed herein relate to semiconductor structures and magnetic cell array structures for magnetic memory devices (e.g., Magnetic Random Access Memory (MRAM) devices), to electronic systems including such magnetic memory devices, and to methods of forming such magnetic memory devices.
- MRAM Magnetic Random Access Memory
- MRAM is a non-volatile computer memory technology based on magnetoresistance.
- One type of MRAM cell is a spin torque transfer MRAM (STT-MRAM) cell, which includes a magnetic cell core supported by a substrate.
- STT-MRAM spin torque transfer MRAM
- a known STT-MRAM cell 10 generally includes at least two magnetic regions, for example, a “fixed region” 12 (also known in the art as a “pinned region”) and a “free region” 14 , with a non-magnetic region 16 between the fixed region 12 and the free region 14 .
- the fixed region 12 , free region 14 , and non-magnetic region 16 form a magnetic tunnel junction region (MTJ) of the STT-MRAM cell 10 .
- MTJ magnetic tunnel junction region
- the STT-MRAM cell 10 may also include a first electrode 18 electrically coupled to the fixed region 12 and a second electrode 20 electrically coupled to the free region 14 .
- the fixed region 12 and the free region 14 may exhibit magnetic orientations that are either horizontally oriented (“in-plane”) as shown in FIG. 1 by arrows, or perpendicularly oriented (“out-of-plane”) relative to the width of the regions.
- the fixed region 12 includes a magnetic material that has a substantially fixed magnetic orientation (e.g., a non-switchable magnetic orientation during normal operation).
- the free region 14 includes a magnetic material that has a magnetic orientation that may be switched, during operation of the cell, between a “parallel” configuration and an “anti-parallel” configuration.
- the magnetic orientations of the fixed region and the free region are directed in the same direction (e.g., north and north, east and east, south and south, or west and west, respectively).
- the magnetic orientations of the fixed region 12 and the free region 14 are directed in opposite directions (e.g., north and south, east and west, south and north, or west and east, respectively).
- the STT-MRAM cell 10 exhibits a lower electrical resistance across the magnetoresistive elements (e.g., the fixed region 12 and free region 14 ). This state of low electrical resistance may be defined as a “0” logic state of the STT-MRAM cell 10 .
- the STT-MRAM cell 10 exhibits a higher electrical resistance across the magnetoresistive elements. This state of high electrical resistance may be defined as a “1” logic state of the STT-MRAM cell 10 .
- Switching of the magnetic orientation of the free region 14 may be accomplished by passing a programming current through the STT-MRAM cell 10 and the fixed region 12 and free region 12 therein.
- the fixed region 12 polarizes the electron spin of the programming current, and torque is created as the spin-polarized current passes through the cell 10 .
- the spin-polarized electron current exerts torque on the free region 14 .
- J c critical switching current density
- the resulting high or low electrical resistance states across the magnetoresistive elements enable the read and write operations of the STT-MRAM cell.
- the magnetic orientation of the free region 14 is usually desired to be maintained, during a “storage” stage, until the STT-MRAM cell 10 is to be rewritten to a different configuration (i.e., to a different logic state). Accordingly, the STT-MRAM cell 10 is non-volatile and holds its logic state even in the absence of applied power.
- High density cell array layouts are desired to obtain STT-MRAM devices with high data storage capabilities.
- STT-MRAM conventionally requires higher current to read and/or write logic states compared to other non-volatile memory, such as NAND Flash memory.
- Several publications describe efforts to achieve high density cell array layout and/or to reduce the current required to read and/or write logic states in STT-MRAM devices.
- U.S. Patent Application Publication No. 2007/0279963 to Kenji Tsuchida et al. filed Feb. 9, 2007, titled “Semiconductor Memory” (hereinafter “the '963 Publication”) describes an STT-MRAM cell layout with a dual-access trench.
- the '963 Publication describes a conventional layout that achieves a cell size of 12F 2 , where F is a smallest feature size (e.g., width of a line, trench, or other feature).
- F is a smallest feature size (e.g., width of a line, trench, or other feature).
- the '963 Publication describes staggering the cells to achieve a smaller 8F 2 cell size.
- FIG. 1 is a simplified schematic side view of a known STT-MRAM cell.
- FIG. 2A is a simplified schematic top view of a linear array of STT-MRAM cells.
- FIG. 2B is a cross sectional electrical circuit diagram taken along and through a bit line of the linear array of FIG. 2A .
- FIG. 2C is a schematic cross sectional diagram taken along and through a source power line of the linear array of FIG. 2A .
- FIG. 3A is a simplified schematic top view of an array of magnetic cells according to an embodiment of the present disclosure.
- FIG. 3B is a cross sectional electrical circuit diagram taken along and through a bit line of the array of FIG. 3A .
- FIG. 3C is a schematic cross sectional diagram taken along and through a source power line of the array of FIG. 3A .
- FIG. 4A shows a representation of a linear array of magnetic cells to illustrate resistive properties of the linear array.
- FIG. 4B shows a representation of an array of magnetic cells according to an embodiment of the present disclosure to illustrate resistive properties of the array.
- FIG. 5 is a simplified schematic top view of the array of magnetic cells according to the embodiment of FIG. 3A .
- FIG. 6A shows a cross-sectional view of the array of magnetic cells taken from line A-A of FIG. 5 .
- FIG. 6B shows a cross-sectional view of the array of magnetic cells taken from line B-B of FIG. 5 .
- FIG. 6C shows a cross-sectional view of a peripheral region of a semiconductor device including the array of magnetic cells.
- FIGS. 7 through 14 show a method of forming an array of magnetic memory cells according to an embodiment of the present disclosure.
- FIG. 15 shows a schematic block diagram of an electronic system according to an embodiment of the present disclosure.
- the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one skilled in the art would understand that the given parameter, property, or condition is met with a small degree of variance, such as within acceptable manufacturing tolerances.
- a parameter that is substantially met may be at least about 90% met, at least about 95% met, or even at least about 99% met.
- any relational term such as “first,” “second,” “over,” “top,” “bottom,” “overlying,” “underlying,” etc., is used for clarity and convenience in understanding the disclosure and accompanying drawings and does not connote or depend on any specific preference, orientation, or order, except where the context clearly indicates otherwise.
- the term “forming” means and includes any method of creating, building, depositing, and/or patterning a material.
- forming may be accomplished by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, co-sputtering, spin-coating, diffusing, depositing, growing, or any other technique known in the art of semiconductor fabrication.
- Material may be formed and/or patterned into various shapes and configurations using known techniques, such as isotropic etching, anisotropic etching, chemical-mechanical polishing (CMP), ablating, etc.
- the technique for forming the material may be selected by a person of ordinary skill in the art.
- a magnetic memory cell array structure may include a common source plate providing electrical access to the sources of all magnetic memory cells in the array.
- the common source plate may include linear portions that extend in two directions that are at a first angle to bit lines and at a second angle to word lines of the array.
- the common source plate may be characterized as a plate of conductive material having cutouts through which bit contacts for MTJs respectively extend.
- the MTJs of the magnetic memory cell array may be staggered, in that the MTJs of one column or row may be offset from MTJs of an immediately adjacent column or row.
- the common source plate may electrically connect to magnetic memory cells in two transverse directions (e.g., a row direction and a column direction).
- Magnetic memory (e.g., STT-MRAM) devices including the disclosed magnetic memory cell arrays with common source plates may exhibit improved (i.e., lower) electrical current requirements and may enable use of higher resistivity materials as source line material, compared to magnetic cell arrays with conventional linear source lines.
- FIGS. 2A-2C and the accompanying description thereof in this specification are provided to enhance an understanding by one of ordinary skill in the art of embodiments of the present disclosure, and are not admitted by the applicant as prior art for any purpose.
- FIG. 2A illustrates a linear array 100 of STT-MRAM cells 101 including MTJs 102 shown by shaded circles in FIG. 2A .
- FIG. 2B is a cross sectional electrical circuit diagram taken along and through a bit line 104 of the linear array 100 of FIG. 2A .
- FIG. 2C is a schematic cross sectional diagram taken along and through a source power line 113 of the linear array 100 of FIG. 2A .
- Certain elements shown in FIG. 2A are shown as transparent to more dearly illustrate structures that are overlying or underlying each other.
- the linear array 100 may include structures for operation of a device or system including the linear array 100 to electrically access and select, read from, write to, and/or erase data stored in the MTJs 102 , such as data/sense lines (e.g., bit lines) 104 , access lines (e.g., word lines) 106 , source lines 108 , source contacts 110 (shown as shaded boxes in FIG. 2A ), source line power contacts 111 (shown as shaded triangles in FIG. 2A ), source power lines 113 (shown in dashed lines in FIG. 2A ), and as well as other contacts, conductive lines, active areas, isolation trenches, substrates, dielectric materials, and layers that are not shown in FIG.
- data/sense lines e.g., bit lines
- access lines e.g., word lines
- source lines 108 source contacts 110 (shown as shaded boxes in FIG. 2A )
- source line power contacts 111 shown as shaded triangles in FIG. 2A
- the MTJs 102 of the linear array 100 may be aligned in a column direction (e.g., vertically from the perspective of FIG. 2A ) parallel to the word lines 106 and in a row direction (e.g., horizontally from the perspective of FIG. 2A ) perpendicular to the column direction and parallel to the bit lines 104 .
- the bit lines 104 are electrically conductive materials that may extend along (e.g., over) and may be electrically coupled to MTJs 102 aligned in the row direction.
- the word lines 106 may be formed in access trenches formed in a semiconductor substrate underlying the MTJs 102 and may include an electrically conductive gate material and a gate dielectric material, forming an access transistor for each respective MTJ 102 .
- the word lines 106 may extend along (e.g., under and parallel to) MTJs 102 aligned in the column direction. In the configuration shown in FIG. 2A , two word lines 106 may be operably coupled to each column of MTJs 102 , such that the linear array 100 is a so-called “dual-channel” array of STT-MRAM cells 101 .
- the source lines 108 may also extend along (e.g., parallel to) MTJs 102 aligned in the column direction, such as between two adjacent columns of MTJs 102 .
- the source contacts 110 may operably couple the source lines 108 to two word lines 106 of adjacent columns of MTJs 102 .
- the source contacts 110 are not electrically coupled to the bit lines 104 , other than the indirect connection through the word lines 106 and MTJs 102 . Accordingly, the source lines 108 and source contacts 110 may be shared between two adjacent columns of MTJs 102 .
- Source line power contacts 111 may be coupled to end portions of the source lines 108 , which, in turn, may be coupled to one or more source power lines 113 for applying a voltage to the source lines 108 .
- an STT-MRAM cell 101 including an MTJ 102 of the linear array 100 is selected to be programmed
- a programming current is applied to the STT-MRAM cell 101 , and the current is spin-polarized by the fixed region of the MTJ 102 and exerts a torque on the free region of the MTJ 102 , which switches the magnetization of the free region to “write to” or “program” the MTJ 102 .
- a current is used to detect a resistance state of the MTJ 102 .
- peripheral read/write circuitry may generate a write current (i.e., a programming current) to the bit line 104 and the source line 108 operably coupled to the MTJ 102 of the particular STT-MRAM cell 101 .
- the polarity of the voltage between the bit line 104 and the source line 108 determines the switch (or maintenance) in magnetic orientation of the free region in the MTJ 102 .
- the free region is magnetized according to the spin polarity of the programming current and the programmed logic state is written to the MTJ 102 .
- the peripheral read/write circuitry To read data from the MTJ 102 , the peripheral read/write circuitry generates a read voltage to the bit line 104 and the source line 108 through the MTJ 102 and the word lines 106 operably coupled to the MTJ 102 .
- the programmed state of the STT-MRAM cell 101 relates to the electrical resistance across the MTJ 102 , which may be determined by a potential difference (i.e., voltage) between the bit line 104 and the source line 108 .
- a high resistance across the MTJ 102 may be read as a logic state of “1,” and a low resistance across the MTJ 102 may be read as a logic state of “0,” for example.
- FIG. 3A illustrates an array 200 of magnetic memory cells 201 including MTJs 202 shown by shaded circles in FIG. 3A .
- FIG. 3B is a cross sectional electrical circuit diagram taken along and through a bit line 204 of the array 200 of FIG. 3A .
- FIG. 3C is a cross sectional electrical circuit diagram taken along and through a source power line of the array 200 of FIG. 3A . Certain elements shown in FIG. 3A are shown as transparent to more dearly illustrate structures that are overlying or underlying each other.
- the array 200 may include structures for operation of a device or system including the array 200 to electrically access and select, read from, write to, and/or erase data stored in the MTJs 202 , such as data/sense lines (e.g., bit lines) 204 , access lines (e.g., word lines) 206 , a common source plate 208 , source contacts 210 (shown as shaded boxes in FIG. 3A ), source contacts 211 (shown as shaded triangles in FIG. 3A ), source power lines 213 (shown in dashed lines in FIG. 3A ), and as well as other contacts, conductive lines, active areas, isolation trenches, substrates, dielectric materials, and layers that are not shown in FIG. 3A for clarity but that are known to one of ordinary skill in the art.
- a column direction of the array 200 may be parallel to the word lines 206 .
- a row direction of the array 200 may be perpendicular to the column direction and parallel to the bit lines 204 .
- the MTJs 202 in the array 200 may be staggered, such that MTJs 202 in one column are offset (i.e., not aligned in a row direction) from MTJs 202 in an immediately adjacent column. Similarly, MTJs 202 in one row are offset (i.e., not aligned in a column direction) from MTJs 202 in an immediately adjacent row.
- the MTJs 202 of the array 200 may be aligned in one or more directions at an angle to the column direction (i.e., a direction parallel to the word lines 206 ) and to the row direction (i.e., a direction parallel to the bit lines 204 ).
- the MTJs 202 may be aligned in a first angled direction 212 at an angle of between about 35 degrees and about 55 degrees, such as about 45 degrees, from the column direction and at a complementary angle from the row direction.
- the MTJs 202 may also be aligned in a second angled direction 214 at an angle of between about 35 degrees and about 55 degrees, such as about 45 degrees, from the row direction and at a complementary angle from the column direction.
- Each of the magnetic memory cells 201 of the array 200 may have a cell size of about 8F 2 .
- the feature size F may be the same in the column and row directions or may be different in the column and row directions.
- the bit lines 204 are electrically conductive materials that may extend along (e.g., over) and may be electrically coupled to MTJs 202 aligned in the row direction, being MTJs 202 in every other column.
- the word lines 206 may be formed in access trenches formed in a semiconductor substrate underlying the MTJs 202 and may include an electrically conductive gate material and a gate dielectric material, forming an access transistor for each respective MTJ 202 .
- the word lines 206 may extend along (e.g., under and parallel to) MTJs 202 aligned in the column direction, being MTJs 202 in every other column. Similar to the configuration described above in connection with FIG. 2A , two word lines 206 of the array 200 illustrated in FIG.
- 3A may be operably coupled to each column of MTJs 202 , such that the array 200 is a dual-channel array of magnetic memory cells 201 .
- the dual-channel arrangement in comparison to a so-called “single-channel” arrangement in which a single word line is operably coupled to each column of cells, may result in an increase of gate width, and therefore current drivability, by connection of two selection transistors in parallel to each MTJ 202 .
- Some conventional STT-MRAM memory cells with dual channels may have a cell size of about 12F 2 .
- the layout of the cells 201 of the present disclosure may result in a cell size of about 8F 2 .
- certain word lines 206 may be unselected by applying a negative voltage to the word lines 206 .
- the common source plate 208 may be electrically coupled to all of the magnetic memory cells 201 of all columns and rows of the array 200 .
- the common source plate 208 may include linear portions that extend in the first direction 212 and linear portions that extend in the second direction 214 , as illustrated in FIG. 3A .
- the common source plate 208 may be characterized as a plate of conductive material having cutouts 216 through which the staggered MTJs 202 respectively extend.
- the cutouts 216 may be generally rectangular as shown in FIG. 3A , or may have another shape, such as a trapezoid shape, a circle shape, or a parallelogram shape, for example.
- Source line power contacts 211 may be coupled to end portions of the common source plate 208 , which, in turn, may be coupled to one or more source power lines 213 for applying a voltage to the common source plate 208 .
- FIG. 4A illustrates resistive properties of the source lines 108 of the linear array 100 shown in FIG. 2A
- FIG. 4B illustrates resistive properties of the common source plate 208 shown in FIG. 3A
- Contacts 111 ( FIG. 2A ) for applying voltage to the source lines 108 may be positioned at end portion of the source lines 108 , such as at a top and bottom of the source line 108 as illustrated in FIG. 4A
- contacts 211 FIG. 3A
- a maximum resistance of the common source plate 208 may be reduced compared to a maximum resistance of the source line 108 . As shown in FIG.
- a maximum resistance of each source line 108 may be estimated by considering the source line 108 as a linear series of resistors (illustrated as rectangles) between each source contact 110 .
- a maximum electrical resistance through the source line 108 at a source contact 110 in a column of N cells may be about R*N/2, where R is a resistance of a segment of the source line 108 between adjacent source contacts 110 .
- a maximum resistance of the common source plate 208 may be estimated by computer simulation by considering the common source plate 208 as a two-dimensional grid of resistors (illustrated as rectangles) with a source contact 210 at each grid intersection between the resistors.
- a maximum electrical resistance through the common source plate 208 at a source contact 210 in a column of N cells may be estimated as about R, where R is a resistance of a segment of the common source plate 208 between adjacent source contacts 210 .
- the common source plate 208 may exhibit a significantly reduced resistance compared to linear source lines 108 .
- the reduced resistance of the common source plate 208 may enable a reduced current to be applied to a source of each magnetic memory cell 201 .
- a nominal resistance of a material selected for the common source plate 208 is less significant than in materials selected for the linear source lines 108 of the linear array 100 . Accordingly, conductive materials having relatively higher resistance may be selected for the common source plate 208 compared to materials selected for linear source lines 108 .
- a copper source line 108 or common source plate 208 may have a resistance of about 2.45-3.93 ⁇ per cell 101 , 201 assuming a line width of between about 21 nm and about 23 nm and a line height of about 55 nm.
- a tungsten source line 108 may have a resistance of about 13.38-17.47 ⁇ per cell 101 assuming a line width of between about 21 nm and about 23 nm and a line height of about 30 nm.
- a tungsten common source plate 208 may have a resistance of about 18.93-21.47 ⁇ per cell 201 assuming a line width of between about 21 nm and about 23 nm and a line height of about 30 nm. Based on these assumptions, an estimated maximum resistance through the source line 108 or through the common source plate 208 is identified in Table 1 below.
- the minimum line width of the common source plate 208 is a minimum width thereof between adjacent cells 201 .
- an acceptable maximum external resistance value for dual-channel arrangements may be about 1000 ⁇ or less to achieve sufficient current for writing data to the cells 101 , 201 , such as when a diameter of the MTJs 102 , 202 is about 20-30 nm and the MTJs 102 , 202 have a magnetic field oriented perpendicular to a substrate. Accordingly, tungsten may not be a viable option for the source lines 108 having 256 to 512 bits (e.g., cells) per column in the array 100 illustrated in FIG. 2A .
- Tungsten may only be available for higher line widths and lower bits per column, such as at least about 22 nm line width and 128 bits or less per column, since smaller line widths and/or higher bits per column made from tungsten exhibit maximum resistance values more than 1000 ⁇ .
- source lines 108 may not be feasible with 1,024 bits per column regardless of whether copper or tungsten is selected for the source lines 108 since the maximum resistance is greater than 1000 ⁇ using either material.
- resistance values may be well below the 1000 ⁇ threshold (e.g., about 20 ⁇ or less) for all line widths between about 21 nm and about 23 nm and for all quantities between 128 and 1,024 bits per column using either copper or tungsten for the common source plate 208 .
- the common source plate 208 configuration enables the use of different materials (e.g., materials having higher nominal resistance), arrays 200 having a higher number of bits (e.g., cells) per column, and/or source lines having a smaller line width and/or height.
- Tungsten may have advantages over copper when employed as a source material in manufacturability, reduction of impurities and contamination of adjacent features, smaller line height, and cost, for example.
- conductive materials may also be used as a material for the common source plate 208 .
- copper, tungsten, titanium, tantalum, aluminum, silver, gold, conductive silicides thereof, conductive nitrides thereof, or combinations thereof may be selected and used for the common source plate 208 .
- FIG. 5 illustrates the array 200 of FIG. 3A , with section lines A-A and B-B identified.
- the section line A-A extends through a row of MTJs 202 and source contacts 210 and along a bit line 204 .
- the section line B-B extends through a column of MTJs 202 and source contacts 210 and parallel to word lines 206 .
- FIGS. 6A-6C illustrate cross-sectional views of the array 200 of FIG. 5 .
- FIG. 6A shows a cross-sectional view of the array 200 through section line A-A of FIG. 5 .
- FIG. 6B shows a cross-sectional view of the array 200 through section line B-B of FIG. 5 .
- FIG. 6C shows a cross-sectional view of a peripheral portion 250 of a memory device including the array 200 .
- the word lines 206 may be formed on or in a semiconductor substrate 220 .
- the semiconductor substrate 220 may be a conventional silicon substrate or other bulk substrate including semiconductor material.
- the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates or silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si 1-x Ge x , where x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), among others.
- SOI silicon-on-insulator
- SOS silicon-on-sapphire
- SOOG silicon-on-glass
- the word lines 206 may be formed of one or more conductive materials, such as a tungsten material at least partially surrounded by a titanium nitride material. Portions (e.g., lower portions) of the word lines 206 may be electrically isolated from the surrounding semiconductor substrate 220 by a dielectric material, such as a silicon dioxide material. An upper portion of the word lines 206 may include, for example, a conductive metal silicide material, such as tungsten silicide. A dielectric gate material may be positioned over the word lines 206 .
- the word lines 206 may extend in the column direction (i.e., into-and-out of the page when viewed in the perspective of FIG.
- Shallow trench isolation (STI) regions 222 of a dielectric material may be positioned in the semiconductor substrate 220 to electrically isolate adjacent magnetic memory cells 201 from each other. Portions of the semiconductor substrate 220 between the word lines 206 of adjacent cells 201 may define a semiconductor source region 224 . Portions of the semiconductor substrate 220 between the word lines 206 of a single cell 201 may define a semiconductor drain region 226 .
- STI shallow trench isolation
- the semiconductor source region 224 may act as a drain, while the semiconductor drain region 226 may act as a source. Accordingly, the nomenclature for the semiconductor source region 224 and the semiconductor drain region 226 is used for convenience and clarity in understanding this disclosure, but it is to be understood that the functions thereof may be switched during certain operations.
- One or more dielectric materials 228 may be positioned over the semiconductor substrate 220 and word lines 206 .
- Conductive source contacts 210 (including lower source contact portions 210 A and upper source contact portions 210 B) and conductive cell contacts 232 may extend from the semiconductor substrate 220 through the one or more dielectric materials 228 .
- the common source plate 208 may be positioned over and electrically coupled to the source contacts 210 . As discussed above, the common source plate 208 may be configured as a grid of conductive material that is operably coupled to adjacent cells 201 in both the row direction and the column direction.
- a conductive bit contact 234 (including lower bit contact portion 234 A, upper bit contact portion 234 B, and MTJ lower electrode material 234 C) may be positioned over and electrically coupled to each of the cell contacts 232 .
- the bit contact 234 may include one or more conductive materials.
- the lower bit contact portion 234 A and the upper bit contact portion 234 B may each include a tungsten material at least partially surrounded by a titanium nitride material.
- the MTJ lower electrode material 234 C may include a titanium nitride material and a tantalum material over the titanium nitride material.
- other conductive materials may be used for the bit contact 234 , as selected by one of ordinary skill in the art.
- the MTJs 202 may be respectively positioned over and may be electrically coupled to the bit contacts 234 .
- the MTJs 202 may include a fixed magnetic region and a switchable magnetic region separated by a non-magnetic region, as discussed above.
- the fixed and switchable magnetic regions may have a magnetic orientation that is substantially parallel to the semiconductor substrate 220 (i.e., horizontally from the perspective of FIGS. 6A and 6B ) or, alternatively, may have a magnetic orientation that is substantially perpendicular to the semiconductor substrate 220 (e.g., vertically from the perspective of FIGS. 6A and 6B ).
- the bit lines 204 may be positioned over and electrically coupled to the MTJs 202 .
- the bit lines 204 may extend in the row direction.
- the bit lines 204 may include one or more conductive materials, such as copper, tungsten, titanium, tantalum, conductive nitrides thereof, conductive silicides thereof, or combinations thereof, for example.
- the peripheral portion 250 of a device including the array 200 of magnetic memory cells 201 may include, for example, read/write circuitry, a bit line reference, and an amplifier on or over the semiconductor substrate 220 .
- the read/write circuitry may include access transistors 252 and peripheral conductive lines 254 .
- Peripheral isolation trenches 256 filled with a dielectric material e.g., silicon dioxide may be positioned in the semiconductor substrate 220 to electrically isolate adjacent access transistors 252 .
- the peripheral conductive lines 254 may include copper, tungsten, or a combination of copper and tungsten.
- an upper portion of the peripheral conductive lines 254 may include copper and a lower portion of the peripheral conductive lines 254 may include tungsten.
- both the upper portion and the lower portion of the peripheral conductive lines 254 may include copper, or both the upper portion and the lower portion may include tungsten.
- the peripheral conductive lines 254 may operably connect the access transistors 252 of the peripheral portion 250 to the magnetic memory cells 201 ( FIGS. 6A and 6B ) of the array 200 .
- a magnetic memory device includes an array of magnetic memory cells.
- Each of the magnetic memory cells of the array may include a semiconductor substrate, at least one access line extending in a column direction in or on the semiconductor substrate, and a bit contact operably coupled to the at least one access line on a drain side of the at least one access line.
- a magnetic tunnel junction region may be electrically coupled to the bit contact.
- At least one data/sense line may be electrically coupled to the magnetic tunnel junction region and may extend in a row direction transverse to the column direction.
- At least one source contact may be operably coupled to the at least one access line on a source side of the at least one access line.
- a common source plate may be electrically coupled to the at least one source contact. The common source plate may electrically couple the at least one source contact of each of the magnetic memory cells of the array to the at least one source contact of adjacent magnetic memory cells of the array in both the column direction and the row direction.
- FIGS. 7 through 14 show a method of forming an array 300 of magnetic memory cells 301 according to an embodiment of the present disclosure.
- a semiconductor substrate 320 may be provided.
- Dielectric STI regions and access line trenches 305 may be formed in the semiconductor substrate 320 .
- the access line trenches 305 may be at least partially filled with one or more conductive materials to form access lines 306 (e.g., word lines).
- the access line trenches 305 may be lined with a conformal dielectric material (e.g., silicon dioxide) and an outer conductive material, such as titanium nitride, may be conformally formed over inner surfaces of the dielectric material within the access line trenches 305 .
- a conformal dielectric material e.g., silicon dioxide
- an outer conductive material such as titanium nitride
- the remaining portion of the access line trenches 305 may be filled with an inner conductive material, such as tungsten.
- An upper portion of the conductive material within the access line trenches 305 may be converted to a metal silicide material, such as tungsten silicide, by diffusing silicon into the conductive material, to form the word lines 306 .
- a gate dielectric material 307 and a first interlayer dielectric material 328 A may be formed over the semiconductor substrate 320 and word lines 306 .
- the gate dielectric material 307 may be a silicon dioxide material.
- the first interlayer dielectric material 328 A may be one or more dielectric materials such as oxides (e.g., silicon dioxide) and/or nitrides (e.g., silicon nitride).
- holes 309 may be formed through the first interlayer dielectric material 328 A and gate dielectric material 307 between adjacent word lines 306 , to expose the semiconductor substrate 320 .
- the holes 309 may be filled with one or more conductive materials to form lower source contact portions 310 A and lower bit contact portions 334 A.
- the one or more conductive materials may include, for example, an outer conformal layer of titanium nitride and an inner tungsten material. Excess conductive materials, if any, may be removed from over the first interlayer dielectric material 328 A, such as by a chemical-mechanical polishing (“CMP”) process.
- CMP chemical-mechanical polishing
- a second interlayer dielectric material 328 B may be formed over the first interlayer dielectric material 328 A, lower source contact portions 310 A, and lower bit contact portions 334 A.
- Source contact holes 311 may be formed through the second interlayer dielectric material 328 B and over the lower source contact portions 310 A to expose the lower source contact portions 310 A.
- One or more conductive materials may be formed in the source contact holes 311 to form upper source contact portions 310 B.
- an outer conformal layer of titanium nitride and an inner tungsten material may be used to form the upper source contact portions 310 B. Excess conductive materials, if any, may be removed from over the second interlayer dielectric material 328 B, such as by a CMP process.
- the lower and upper source contact portions 310 A, 310 B may define source contacts 310 .
- a common source plate 308 may be formed over and in contact with the source contacts 310 , and over the second interlayer dielectric material 328 A.
- the common source plate 308 may be patterned to result in a structure similar to the common source plate 208 described above with reference to FIG. 3A . Accordingly, cutouts 316 may be formed over the lower bit contact portions 334 A, but the common source plate 308 may operably connect adjacent source contacts 310 to each other in both column and row directions.
- the common source plate 308 may include a conductive material, such as copper, tungsten, titanium, tantalum, aluminum, gold, conductive silicides thereof, conductive nitrides thereof, or combinations thereof.
- a dielectric mask material 317 may be formed over the conductive material of the common source plate 308 and may be used for patterning the common source plate 308 .
- upper bit contact portions 334 B may be formed over the lower bit contact portions 334 A and through the cutouts 316 in the common source plate 308 .
- the upper bit contact portions 334 B may be formed using a so-called “self-alignment contact” process, as follows.
- a dielectric spacer material 318 such as a silicon nitride material, may be formed over the dielectric mask material 317 and/or the common source plate 308 . Portions of the dielectric spacer material 318 may be removed from horizontal surfaces, such as by using an anisotropic etch process, while other portions of the dielectric spacer material 318 may remain over vertical surfaces, such as along inner side walls of the cutouts 316 .
- a sacrificial dielectric material such as silicon dioxide, having different etch properties than the dielectric spacer material 318 may be formed over the structure.
- a top surface of the structure may be planarized, such as by a CMP process. Remaining portions of the sacrificial dielectric material (e.g., portions within the cutouts 316 and between the remaining dielectric spacer materials) may be removed, as well as an underlying portion of the second interlayer dielectric material 328 B. This removal process may expose the lower bit contact portions 334 A through the cutouts 316 .
- One or more conductive materials may be formed in the cutouts 316 and in contact with the lower bit contact portions 334 A to form upper bit contact portions 334 B, which may extend through the second interlayer dielectric material 328 B and through the cutouts 316 in the common source plate 308 between the dielectric spacer materials 318 .
- the one or more conductive materials may be, for example, an outer layer of titanium nitride and an inner portion of tungsten. Excess conductive materials, if any, may be removed from over the structure, such as by a CMP process, to result in a structure like that shown in FIG. 12 .
- the process described with reference to FIGS. 10 through 12 is a process in which the common source plate 308 is formed prior to the upper bit contact portions 334 B.
- the disclosure is not so limited. Rather, the disclosure also includes processes in which the upper bit contact portions 334 B are formed over the lower bit contact portions 334 A, after which the upper source contact portions 310 B and the common source plate 308 are formed and operably coupled to the lower source contact portions 310 A. Given the processes described above, one of ordinary skill in the art is capable of forming the upper bit contact portions 334 B prior to the common source plate 308 , as desired.
- an MTJ lower electrode material 334 C may be formed over the upper bit contact portion 334 B, for improved adhesion and electrical properties of the MTJs 302 to be formed thereover.
- the MTJ lower electrode material 334 C may include one or more conductive materials, such as a titanium nitride material formed over and in contact with the upper bit contact portion 334 B, and a tantalum material formed over and in contact with the titanium nitride material.
- a titanium nitride material formed over and in contact with the upper bit contact portion 334 B
- tantalum material formed over and in contact with the titanium nitride material.
- the MTJs 302 may be formed over and in contact with the MTJ lower electrode material 334 C.
- the MTJs 302 may be formed as known in the art, such as to have the structure shown in FIG. 1 . However, other MTJs 302 are known and capable of implementation with embodiments of this disclosure, as known by one of ordinary skill in the art.
- the MTJ lower electrode material 334 C and MTJs 302 may be formed in and through an upper interlayer dielectric material 319 , which may include one or more dielectric materials (e.g., silicon dioxide and silicon nitride).
- the lower bit contact portions 334 A, upper bit contact portions 334 B, and MTJ lower electrode materials 334 C may together define bit contacts 334 .
- data/sense lines 304 may be formed over the MTJs 302 .
- MTJs 302 that are aligned in a row direction may be electrically coupled to the same bit line 304 .
- the bit lines 304 may include one or more conductive materials, such as copper, tungsten, titanium, tantalum, aluminum, gold, conductive silicides thereof, conductive nitrides thereof, or combinations thereof.
- Each magnetic memory cell 301 of the array 300 may include an MTJ 302 , a bit contact 334 , at least one word line 306 (e.g., two word lines 306 ), at least one source contact 310 , and a portion of the common source plate 308 .
- the array 300 may, in plan view, have a similar configuration as the array 200 shown in FIG. 3A , for example.
- an array of magnetic memory cells may be formed.
- Each of the magnetic memory cells of the array may be formed by forming at least one access line extending in a column direction in or on a semiconductor substrate.
- a bit contact may be formed and operably coupled to the at least one access line on a drain side of the at least one access line.
- a magnetic tunnel junction region may be formed and electrically coupled to the bit contact.
- At least one data/sense line may be formed and electrically coupled to the magnetic tunnel junction region and may extend in a row direction transverse to the column direction.
- At least one source contact may be formed and operably coupled to the at least one access line on a source side of the at least one access line.
- a common source plate may be formed and electrically coupled to the at least one source contact. The common source plate may be patterned to electrically couple the at least one source contacts of adjacent magnetic memory cells of the array in both the column direction and the row direction.
- Embodiments of the disclosure may be implemented in STT-MRAM devices as well as other magnetic memory devices. Indeed, one of ordinary skill in the art may implement embodiments of the disclosure in a number of different semiconductor devices, example embodiments of which have been described herein.
- FIG. 15 is a schematic block diagram of an electronic system 400 according to an embodiment of the present disclosure.
- the electronic system 400 includes a processor 410 operably coupled with a memory device 420 , one or more input devices 430 , and one or more output devices 440 .
- the electronic system 400 may be a consumer electronic device, such as a desktop computer, a laptop computer, a tablet computer, an electronic reader, a smart phone, or other type of communication device, as well as any type of computing system incorporating non-volatile storage.
- the memory device 420 may be or include a magnetic memory device (e.g., one or more of the magnetic memory devices 200 , 300 ) that includes a common source plate (e.g., one or more of the common source plates 208 , 308 ) as discussed above.
- a magnetic memory device e.g., one or more of the magnetic memory devices 200 , 300
- a common source plate e.g., one or more of the common source plates 208 , 308
- the present disclosure includes electronic systems that include a magnetic memory device.
- the electronic systems may include at least one processor, at least one input device and at least one output device operably coupled to the at least one processor, and at least one magnetic memory device operably coupled to the at least one processor.
- the magnetic memory device may include an array of magnetic memory cells including conductive word lines in or on a semiconductor substrate, conductive bit lines, and magnetic tunnel junction regions each operably coupled to and between one of the conductive bit lines and, through a conductive bit contact, two of the conductive word lines.
- the conductive word lines may extend in a column direction and the conductive bit lines may extend in a row direction transverse to the column direction.
- a common source plate may be operably coupled to each of the conductive word lines through a conductive source contact and to each of the magnetic memory cells of the array.
Abstract
Description
- Embodiments disclosed herein relate to magnetic memory devices and electronic systems including a magnetic memory device. More specifically, embodiments disclosed herein relate to semiconductor structures and magnetic cell array structures for magnetic memory devices (e.g., Magnetic Random Access Memory (MRAM) devices), to electronic systems including such magnetic memory devices, and to methods of forming such magnetic memory devices.
- MRAM is a non-volatile computer memory technology based on magnetoresistance. One type of MRAM cell is a spin torque transfer MRAM (STT-MRAM) cell, which includes a magnetic cell core supported by a substrate. As shown in
FIG. 1 , a known STT-MRAM cell 10 generally includes at least two magnetic regions, for example, a “fixed region” 12 (also known in the art as a “pinned region”) and a “free region” 14, with anon-magnetic region 16 between thefixed region 12 and thefree region 14. Thefixed region 12,free region 14, andnon-magnetic region 16 form a magnetic tunnel junction region (MTJ) of the STT-MRAM cell 10. The STT-MRAM cell 10 may also include afirst electrode 18 electrically coupled to thefixed region 12 and asecond electrode 20 electrically coupled to thefree region 14. Thefixed region 12 and thefree region 14 may exhibit magnetic orientations that are either horizontally oriented (“in-plane”) as shown inFIG. 1 by arrows, or perpendicularly oriented (“out-of-plane”) relative to the width of the regions. Thefixed region 12 includes a magnetic material that has a substantially fixed magnetic orientation (e.g., a non-switchable magnetic orientation during normal operation). Thefree region 14, on the other hand, includes a magnetic material that has a magnetic orientation that may be switched, during operation of the cell, between a “parallel” configuration and an “anti-parallel” configuration. In the parallel configuration, the magnetic orientations of the fixed region and the free region are directed in the same direction (e.g., north and north, east and east, south and south, or west and west, respectively). In the “anti-parallel” configuration, the magnetic orientations of thefixed region 12 and thefree region 14 are directed in opposite directions (e.g., north and south, east and west, south and north, or west and east, respectively). In the parallel configuration, the STT-MRAM cell 10 exhibits a lower electrical resistance across the magnetoresistive elements (e.g., thefixed region 12 and free region 14). This state of low electrical resistance may be defined as a “0” logic state of the STT-MRAM cell 10. In the anti-parallel configuration, the STT-MRAM cell 10 exhibits a higher electrical resistance across the magnetoresistive elements. This state of high electrical resistance may be defined as a “1” logic state of the STT-MRAM cell 10. - Switching of the magnetic orientation of the
free region 14 may be accomplished by passing a programming current through the STT-MRAM cell 10 and thefixed region 12 andfree region 12 therein. Thefixed region 12 polarizes the electron spin of the programming current, and torque is created as the spin-polarized current passes through thecell 10. The spin-polarized electron current exerts torque on thefree region 14. When the torque of the spin-polarized electron current passing through thecell 10 is greater than a critical switching current density (Jc) of thefree region 14, the direction of the magnetic orientation of thefree region 14 is switched. Thus, the programming current can be used to alter the electrical resistance across the magnetic fixed andfree regions free region 14 to achieve the parallel configuration or the anti-parallel configuration associated with a desired logic state, the magnetic orientation of thefree region 14 is usually desired to be maintained, during a “storage” stage, until the STT-MRAM cell 10 is to be rewritten to a different configuration (i.e., to a different logic state). Accordingly, the STT-MRAM cell 10 is non-volatile and holds its logic state even in the absence of applied power. - High density cell array layouts are desired to obtain STT-MRAM devices with high data storage capabilities. However, STT-MRAM conventionally requires higher current to read and/or write logic states compared to other non-volatile memory, such as NAND Flash memory. Several publications describe efforts to achieve high density cell array layout and/or to reduce the current required to read and/or write logic states in STT-MRAM devices. For example, U.S. Patent Application Publication No. 2007/0279963 to Kenji Tsuchida et al., filed Feb. 9, 2007, titled “Semiconductor Memory” (hereinafter “the '963 Publication”) describes an STT-MRAM cell layout with a dual-access trench. The '963 Publication describes a conventional layout that achieves a cell size of 12F2, where F is a smallest feature size (e.g., width of a line, trench, or other feature). The '963 Publication describes staggering the cells to achieve a smaller 8F2 cell size. The article by Bo Zhao et al. titled “Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices,” published in the Proceedings of the Design, Automation & Test in Europe Conference & Exhibition held Mar. 12-16, 2012 (hereinafter “Zhao”), describes a source line that is parallel to a word line direction and that is used as a source for all cells along the source line. Zhao also describes a cell arrangement to achieve a 6F2 cell size.
-
FIG. 1 is a simplified schematic side view of a known STT-MRAM cell. -
FIG. 2A is a simplified schematic top view of a linear array of STT-MRAM cells.FIG. 2B is a cross sectional electrical circuit diagram taken along and through a bit line of the linear array ofFIG. 2A .FIG. 2C is a schematic cross sectional diagram taken along and through a source power line of the linear array ofFIG. 2A . -
FIG. 3A is a simplified schematic top view of an array of magnetic cells according to an embodiment of the present disclosure.FIG. 3B is a cross sectional electrical circuit diagram taken along and through a bit line of the array ofFIG. 3A .FIG. 3C is a schematic cross sectional diagram taken along and through a source power line of the array ofFIG. 3A . -
FIG. 4A shows a representation of a linear array of magnetic cells to illustrate resistive properties of the linear array. -
FIG. 4B shows a representation of an array of magnetic cells according to an embodiment of the present disclosure to illustrate resistive properties of the array. -
FIG. 5 is a simplified schematic top view of the array of magnetic cells according to the embodiment ofFIG. 3A . -
FIG. 6A shows a cross-sectional view of the array of magnetic cells taken from line A-A ofFIG. 5 . -
FIG. 6B shows a cross-sectional view of the array of magnetic cells taken from line B-B ofFIG. 5 . -
FIG. 6C shows a cross-sectional view of a peripheral region of a semiconductor device including the array of magnetic cells. -
FIGS. 7 through 14 show a method of forming an array of magnetic memory cells according to an embodiment of the present disclosure. -
FIG. 15 shows a schematic block diagram of an electronic system according to an embodiment of the present disclosure. - The illustrations included herewith are not meant to be actual views of any particular systems or structures, but are merely idealized representations that are employed to describe embodiments of the present disclosure. Elements and features common between figures may retain the same numerical designation.
- The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without employing these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques and material types employed in the semiconductor industry. In addition, the description provided herein does not form a complete process flow for manufacturing semiconductor devices, magnetic cell array structures, or magnetic memory cells, and the semiconductor devices, magnetic cell array structures, and memory cells described below do not form a complete semiconductor device, magnetic cell structure, or magnetic memory cell. Only those process acts and structures necessary for one of ordinary skill in the art to understand the embodiments described herein are described in detail below. Additional acts to form a complete semiconductor device and a memory cell array may be performed by conventional techniques.
- As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one skilled in the art would understand that the given parameter, property, or condition is met with a small degree of variance, such as within acceptable manufacturing tolerances. For example, a parameter that is substantially met may be at least about 90% met, at least about 95% met, or even at least about 99% met.
- As used herein, any relational term, such as “first,” “second,” “over,” “top,” “bottom,” “overlying,” “underlying,” etc., is used for clarity and convenience in understanding the disclosure and accompanying drawings and does not connote or depend on any specific preference, orientation, or order, except where the context clearly indicates otherwise.
- As used herein, the terms “vertical” and “horizontal” merely refer to a drawing figure as oriented on the drawing sheet, and in no way are limiting of orientation of a PCM device or any portion thereof.
- As used herein, the term “forming” means and includes any method of creating, building, depositing, and/or patterning a material. For example, forming may be accomplished by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, co-sputtering, spin-coating, diffusing, depositing, growing, or any other technique known in the art of semiconductor fabrication. Material may be formed and/or patterned into various shapes and configurations using known techniques, such as isotropic etching, anisotropic etching, chemical-mechanical polishing (CMP), ablating, etc. Depending on the specific material to be formed, the technique for forming the material may be selected by a person of ordinary skill in the art.
- According to some embodiments, a magnetic memory cell array structure may include a common source plate providing electrical access to the sources of all magnetic memory cells in the array. The common source plate may include linear portions that extend in two directions that are at a first angle to bit lines and at a second angle to word lines of the array. In other words, the common source plate may be characterized as a plate of conductive material having cutouts through which bit contacts for MTJs respectively extend. The MTJs of the magnetic memory cell array may be staggered, in that the MTJs of one column or row may be offset from MTJs of an immediately adjacent column or row. Thus, the common source plate may electrically connect to magnetic memory cells in two transverse directions (e.g., a row direction and a column direction). Magnetic memory (e.g., STT-MRAM) devices including the disclosed magnetic memory cell arrays with common source plates may exhibit improved (i.e., lower) electrical current requirements and may enable use of higher resistivity materials as source line material, compared to magnetic cell arrays with conventional linear source lines.
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FIGS. 2A-2C and the accompanying description thereof in this specification are provided to enhance an understanding by one of ordinary skill in the art of embodiments of the present disclosure, and are not admitted by the applicant as prior art for any purpose. -
FIG. 2A illustrates alinear array 100 of STT-MRAM cells 101 includingMTJs 102 shown by shaded circles inFIG. 2A .FIG. 2B is a cross sectional electrical circuit diagram taken along and through abit line 104 of thelinear array 100 ofFIG. 2A .FIG. 2C is a schematic cross sectional diagram taken along and through asource power line 113 of thelinear array 100 ofFIG. 2A . Certain elements shown inFIG. 2A are shown as transparent to more dearly illustrate structures that are overlying or underlying each other. Thelinear array 100 may include structures for operation of a device or system including thelinear array 100 to electrically access and select, read from, write to, and/or erase data stored in theMTJs 102, such as data/sense lines (e.g., bit lines) 104, access lines (e.g., word lines) 106, source lines 108, source contacts 110 (shown as shaded boxes inFIG. 2A ), source line power contacts 111 (shown as shaded triangles inFIG. 2A ), source power lines 113 (shown in dashed lines inFIG. 2A ), and as well as other contacts, conductive lines, active areas, isolation trenches, substrates, dielectric materials, and layers that are not shown inFIG. 2A for clarity but that are known to one of ordinary skill in the art. TheMTJs 102 of thelinear array 100 may be aligned in a column direction (e.g., vertically from the perspective ofFIG. 2A ) parallel to the word lines 106 and in a row direction (e.g., horizontally from the perspective ofFIG. 2A ) perpendicular to the column direction and parallel to the bit lines 104. - The bit lines 104 are electrically conductive materials that may extend along (e.g., over) and may be electrically coupled to
MTJs 102 aligned in the row direction. The word lines 106 may be formed in access trenches formed in a semiconductor substrate underlying theMTJs 102 and may include an electrically conductive gate material and a gate dielectric material, forming an access transistor for eachrespective MTJ 102. The word lines 106 may extend along (e.g., under and parallel to)MTJs 102 aligned in the column direction. In the configuration shown inFIG. 2A , twoword lines 106 may be operably coupled to each column ofMTJs 102, such that thelinear array 100 is a so-called “dual-channel” array of STT-MRAM cells 101. - The source lines 108 may also extend along (e.g., parallel to)
MTJs 102 aligned in the column direction, such as between two adjacent columns ofMTJs 102. Thesource contacts 110 may operably couple the source lines 108 to twoword lines 106 of adjacent columns ofMTJs 102. Thesource contacts 110 are not electrically coupled to thebit lines 104, other than the indirect connection through the word lines 106 andMTJs 102. Accordingly, the source lines 108 andsource contacts 110 may be shared between two adjacent columns ofMTJs 102. Sourceline power contacts 111 may be coupled to end portions of the source lines 108, which, in turn, may be coupled to one or moresource power lines 113 for applying a voltage to the source lines 108. - In use and operation, when an STT-
MRAM cell 101 including anMTJ 102 of thelinear array 100 is selected to be programmed, a programming current is applied to the STT-MRAM cell 101, and the current is spin-polarized by the fixed region of theMTJ 102 and exerts a torque on the free region of theMTJ 102, which switches the magnetization of the free region to “write to” or “program” theMTJ 102. In a read operation of the STT-MRAM cell 101, a current is used to detect a resistance state of theMTJ 102. - To initiate programming of a particular STT-
MRAM cell 101, peripheral read/write circuitry may generate a write current (i.e., a programming current) to thebit line 104 and thesource line 108 operably coupled to theMTJ 102 of the particular STT-MRAM cell 101. The polarity of the voltage between thebit line 104 and thesource line 108 determines the switch (or maintenance) in magnetic orientation of the free region in theMTJ 102. By changing the magnetic orientation of the free region with the spin polarity, the free region is magnetized according to the spin polarity of the programming current and the programmed logic state is written to theMTJ 102. - To read data from the
MTJ 102, the peripheral read/write circuitry generates a read voltage to thebit line 104 and thesource line 108 through theMTJ 102 and theword lines 106 operably coupled to theMTJ 102. The programmed state of the STT-MRAM cell 101 relates to the electrical resistance across theMTJ 102, which may be determined by a potential difference (i.e., voltage) between thebit line 104 and thesource line 108. A high resistance across theMTJ 102 may be read as a logic state of “1,” and a low resistance across theMTJ 102 may be read as a logic state of “0,” for example. -
FIG. 3A illustrates anarray 200 ofmagnetic memory cells 201 includingMTJs 202 shown by shaded circles inFIG. 3A .FIG. 3B is a cross sectional electrical circuit diagram taken along and through abit line 204 of thearray 200 ofFIG. 3A .FIG. 3C is a cross sectional electrical circuit diagram taken along and through a source power line of thearray 200 ofFIG. 3A . Certain elements shown inFIG. 3A are shown as transparent to more dearly illustrate structures that are overlying or underlying each other. Thearray 200 may include structures for operation of a device or system including thearray 200 to electrically access and select, read from, write to, and/or erase data stored in theMTJs 202, such as data/sense lines (e.g., bit lines) 204, access lines (e.g., word lines) 206, acommon source plate 208, source contacts 210 (shown as shaded boxes inFIG. 3A ), source contacts 211 (shown as shaded triangles inFIG. 3A ), source power lines 213 (shown in dashed lines inFIG. 3A ), and as well as other contacts, conductive lines, active areas, isolation trenches, substrates, dielectric materials, and layers that are not shown inFIG. 3A for clarity but that are known to one of ordinary skill in the art. A column direction of thearray 200 may be parallel to the word lines 206. A row direction of thearray 200 may be perpendicular to the column direction and parallel to the bit lines 204. - The
MTJs 202 in thearray 200 may be staggered, such thatMTJs 202 in one column are offset (i.e., not aligned in a row direction) fromMTJs 202 in an immediately adjacent column. Similarly,MTJs 202 in one row are offset (i.e., not aligned in a column direction) fromMTJs 202 in an immediately adjacent row. TheMTJs 202 of thearray 200 may be aligned in one or more directions at an angle to the column direction (i.e., a direction parallel to the word lines 206) and to the row direction (i.e., a direction parallel to the bit lines 204). By way of example and not limitation, theMTJs 202 may be aligned in a firstangled direction 212 at an angle of between about 35 degrees and about 55 degrees, such as about 45 degrees, from the column direction and at a complementary angle from the row direction. TheMTJs 202 may also be aligned in a secondangled direction 214 at an angle of between about 35 degrees and about 55 degrees, such as about 45 degrees, from the row direction and at a complementary angle from the column direction. Each of themagnetic memory cells 201 of thearray 200 may have a cell size of about 8F2. The feature size F may be the same in the column and row directions or may be different in the column and row directions. - The bit lines 204 are electrically conductive materials that may extend along (e.g., over) and may be electrically coupled to
MTJs 202 aligned in the row direction, beingMTJs 202 in every other column. The word lines 206 may be formed in access trenches formed in a semiconductor substrate underlying theMTJs 202 and may include an electrically conductive gate material and a gate dielectric material, forming an access transistor for eachrespective MTJ 202. The word lines 206 may extend along (e.g., under and parallel to)MTJs 202 aligned in the column direction, beingMTJs 202 in every other column. Similar to the configuration described above in connection withFIG. 2A , twoword lines 206 of thearray 200 illustrated inFIG. 3A may be operably coupled to each column ofMTJs 202, such that thearray 200 is a dual-channel array ofmagnetic memory cells 201. The dual-channel arrangement, in comparison to a so-called “single-channel” arrangement in which a single word line is operably coupled to each column of cells, may result in an increase of gate width, and therefore current drivability, by connection of two selection transistors in parallel to eachMTJ 202. Some conventional STT-MRAM memory cells with dual channels may have a cell size of about 12F2. However, the layout of thecells 201 of the present disclosure may result in a cell size of about 8F2. In operation,certain word lines 206 may be unselected by applying a negative voltage to the word lines 206. - The
common source plate 208 may be electrically coupled to all of themagnetic memory cells 201 of all columns and rows of thearray 200. Thecommon source plate 208 may include linear portions that extend in thefirst direction 212 and linear portions that extend in thesecond direction 214, as illustrated inFIG. 3A . In other words, thecommon source plate 208 may be characterized as a plate of conductivematerial having cutouts 216 through which the staggeredMTJs 202 respectively extend. Thecutouts 216 may be generally rectangular as shown inFIG. 3A , or may have another shape, such as a trapezoid shape, a circle shape, or a parallelogram shape, for example. Sourceline power contacts 211 may be coupled to end portions of thecommon source plate 208, which, in turn, may be coupled to one or moresource power lines 213 for applying a voltage to thecommon source plate 208. -
FIG. 4A illustrates resistive properties of the source lines 108 of thelinear array 100 shown inFIG. 2A andFIG. 4B illustrates resistive properties of thecommon source plate 208 shown inFIG. 3A . Contacts 111 (FIG. 2A ) for applying voltage to the source lines 108 may be positioned at end portion of the source lines 108, such as at a top and bottom of thesource line 108 as illustrated inFIG. 4A . Similarly, contacts 211 (FIG. 3A ) for applying voltage to thecommon source plate 208 may be positioned at end portions of thecommon source plate 208. A maximum resistance of thecommon source plate 208 may be reduced compared to a maximum resistance of thesource line 108. As shown inFIG. 4A , a maximum resistance of eachsource line 108 may be estimated by considering thesource line 108 as a linear series of resistors (illustrated as rectangles) between eachsource contact 110. A maximum electrical resistance through thesource line 108 at asource contact 110 in a column of N cells may be about R*N/2, where R is a resistance of a segment of thesource line 108 betweenadjacent source contacts 110. - As shown in
FIG. 4B , a maximum resistance of thecommon source plate 208 may be estimated by computer simulation by considering thecommon source plate 208 as a two-dimensional grid of resistors (illustrated as rectangles) with asource contact 210 at each grid intersection between the resistors. A maximum electrical resistance through thecommon source plate 208 at asource contact 210 in a column of N cells may be estimated as about R, where R is a resistance of a segment of thecommon source plate 208 betweenadjacent source contacts 210. Thus, where the number N of cells in a column is greater than 2, thecommon source plate 208 may exhibit a significantly reduced resistance compared to linear source lines 108. The reduced resistance of thecommon source plate 208 may enable a reduced current to be applied to a source of eachmagnetic memory cell 201. - In addition, since the resistance of the
common source plate 208 to access any givencell 201 in thearray 200 is not significantly dependent on the number of cells in thearray 200, a nominal resistance of a material selected for thecommon source plate 208 is less significant than in materials selected for thelinear source lines 108 of thelinear array 100. Accordingly, conductive materials having relatively higher resistance may be selected for thecommon source plate 208 compared to materials selected for linear source lines 108. - By way of example and not limitation, a
copper source line 108 orcommon source plate 208 may have a resistance of about 2.45-3.93Ω percell tungsten source line 108 may have a resistance of about 13.38-17.47Ω percell 101 assuming a line width of between about 21 nm and about 23 nm and a line height of about 30 nm. A tungstencommon source plate 208 may have a resistance of about 18.93-21.47Ω percell 201 assuming a line width of between about 21 nm and about 23 nm and a line height of about 30 nm. Based on these assumptions, an estimated maximum resistance through thesource line 108 or through thecommon source plate 208 is identified in Table 1 below. The minimum line width of thecommon source plate 208 is a minimum width thereof betweenadjacent cells 201. -
TABLE 1 Maximum Maximum Maximum Maximum Resistance Resistance Resistance Resistance (Ω) for 128 (Ω) for 256 (Ω) for 512 (Ω) for 1,024 Source Material and Minimum Bits Per Bits Per Bits Per Bits Per Type Line Height Line Width Column Column Column Column Source Copper, 23 nm 160 310 630 1260 Line 10855 nm 22 nm 180 350 700 1400 line height 21 nm 210 410 820 1640 Tungsten, 23 nm 860 1710 3430 6850 30 nm 22 nm 950 1910 3810 7620 line height 21 nm 1120 2240 4470 8940 Common Copper, 23 nm 3.5 3.5 3.5 3.5 Source 55 nm 22 nm 3.6 3.6 3.6 3.6 Plate 208line height 21 nm 3.9 3.9 3.9 3.9 Tungsten, 23 nm 13.4 13.4 13.4 13.4 30 nm 22 nm 14.9 14.9 14.9 14.9 line height 21 nm 17.5 17.5 17.5 17.5 - By way of example, an acceptable maximum external resistance value for dual-channel arrangements may be about 1000Ω or less to achieve sufficient current for writing data to the
cells MTJs MTJs array 100 illustrated inFIG. 2A . Tungsten may only be available for higher line widths and lower bits per column, such as at least about 22 nm line width and 128 bits or less per column, since smaller line widths and/or higher bits per column made from tungsten exhibit maximum resistance values more than 1000Ω. Moreover, source lines 108 may not be feasible with 1,024 bits per column regardless of whether copper or tungsten is selected for the source lines 108 since the maximum resistance is greater than 1000Ω using either material. - On the other hand, when an
array 200 having a common source plate 208 (FIG. 3A ) is used, rather than alinear array 100 having source lines 108 (FIG. 2A ) as described above, resistance values may be well below the 1000Ω threshold (e.g., about 20Ω or less) for all line widths between about 21 nm and about 23 nm and for all quantities between 128 and 1,024 bits per column using either copper or tungsten for thecommon source plate 208. Thus, thecommon source plate 208 configuration enables the use of different materials (e.g., materials having higher nominal resistance),arrays 200 having a higher number of bits (e.g., cells) per column, and/or source lines having a smaller line width and/or height. Tungsten may have advantages over copper when employed as a source material in manufacturability, reduction of impurities and contamination of adjacent features, smaller line height, and cost, for example. - Although copper and tungsten are analyzed and discussed above as a comparative example and to show certain advantages of the common source plate configuration, additional conductive materials may also be used as a material for the
common source plate 208. For example, copper, tungsten, titanium, tantalum, aluminum, silver, gold, conductive silicides thereof, conductive nitrides thereof, or combinations thereof may be selected and used for thecommon source plate 208. -
FIG. 5 illustrates thearray 200 ofFIG. 3A , with section lines A-A and B-B identified. The section line A-A extends through a row ofMTJs 202 andsource contacts 210 and along abit line 204. The section line B-B extends through a column ofMTJs 202 andsource contacts 210 and parallel to word lines 206. -
FIGS. 6A-6C illustrate cross-sectional views of thearray 200 ofFIG. 5 .FIG. 6A shows a cross-sectional view of thearray 200 through section line A-A ofFIG. 5 .FIG. 6B shows a cross-sectional view of thearray 200 through section line B-B ofFIG. 5 .FIG. 6C shows a cross-sectional view of aperipheral portion 250 of a memory device including thearray 200. - Referring to
FIGS. 6A and 6B , the word lines 206 may be formed on or in asemiconductor substrate 220. Thesemiconductor substrate 220 may be a conventional silicon substrate or other bulk substrate including semiconductor material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates or silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si1-xGex, where x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), among others. Furthermore, when reference is made to a “substrate” in this description, previous process stages may have been utilized to form material, regions, or junctions in the base semiconductor structure or foundation. - By way of example and not limitation, the word lines 206 may be formed of one or more conductive materials, such as a tungsten material at least partially surrounded by a titanium nitride material. Portions (e.g., lower portions) of the word lines 206 may be electrically isolated from the surrounding
semiconductor substrate 220 by a dielectric material, such as a silicon dioxide material. An upper portion of the word lines 206 may include, for example, a conductive metal silicide material, such as tungsten silicide. A dielectric gate material may be positioned over the word lines 206. The word lines 206 may extend in the column direction (i.e., into-and-out of the page when viewed in the perspective ofFIG. 6A , left-and-right when viewed in the perspective ofFIG. 6B ), with twoword lines 206 present in eachmagnetic memory cell 201. Shallow trench isolation (STI)regions 222 of a dielectric material may be positioned in thesemiconductor substrate 220 to electrically isolate adjacentmagnetic memory cells 201 from each other. Portions of thesemiconductor substrate 220 between the word lines 206 ofadjacent cells 201 may define asemiconductor source region 224. Portions of thesemiconductor substrate 220 between the word lines 206 of asingle cell 201 may define asemiconductor drain region 226. In certain operations (e.g., writing data from a “1” state to a “0” state), thesemiconductor source region 224 may act as a drain, while thesemiconductor drain region 226 may act as a source. Accordingly, the nomenclature for thesemiconductor source region 224 and thesemiconductor drain region 226 is used for convenience and clarity in understanding this disclosure, but it is to be understood that the functions thereof may be switched during certain operations. - One or more
dielectric materials 228 may be positioned over thesemiconductor substrate 220 and word lines 206. Conductive source contacts 210 (including lowersource contact portions 210A and uppersource contact portions 210B) and conductive cell contacts 232 may extend from thesemiconductor substrate 220 through the one or moredielectric materials 228. Thecommon source plate 208 may be positioned over and electrically coupled to thesource contacts 210. As discussed above, thecommon source plate 208 may be configured as a grid of conductive material that is operably coupled toadjacent cells 201 in both the row direction and the column direction. A conductive bit contact 234 (including lowerbit contact portion 234A, upperbit contact portion 234B, and MTJlower electrode material 234C) may be positioned over and electrically coupled to each of the cell contacts 232. Thebit contact 234 may include one or more conductive materials. By way of non-limiting example, the lowerbit contact portion 234A and the upperbit contact portion 234B may each include a tungsten material at least partially surrounded by a titanium nitride material. The MTJlower electrode material 234C may include a titanium nitride material and a tantalum material over the titanium nitride material. In some embodiments, other conductive materials may be used for thebit contact 234, as selected by one of ordinary skill in the art. - The
MTJs 202 may be respectively positioned over and may be electrically coupled to thebit contacts 234. TheMTJs 202 may include a fixed magnetic region and a switchable magnetic region separated by a non-magnetic region, as discussed above. The fixed and switchable magnetic regions may have a magnetic orientation that is substantially parallel to the semiconductor substrate 220 (i.e., horizontally from the perspective ofFIGS. 6A and 6B ) or, alternatively, may have a magnetic orientation that is substantially perpendicular to the semiconductor substrate 220 (e.g., vertically from the perspective ofFIGS. 6A and 6B ). - The bit lines 204 may be positioned over and electrically coupled to the
MTJs 202. The bit lines 204 may extend in the row direction. The bit lines 204 may include one or more conductive materials, such as copper, tungsten, titanium, tantalum, conductive nitrides thereof, conductive silicides thereof, or combinations thereof, for example. - Referring to
FIG. 6C , theperipheral portion 250 of a device including thearray 200 of magnetic memory cells 201 (FIGS. 6A and 6B ) may include, for example, read/write circuitry, a bit line reference, and an amplifier on or over thesemiconductor substrate 220. The read/write circuitry may includeaccess transistors 252 and peripheralconductive lines 254.Peripheral isolation trenches 256 filled with a dielectric material (e.g., silicon dioxide) may be positioned in thesemiconductor substrate 220 to electrically isolateadjacent access transistors 252. - By way of example and not limitation, the peripheral
conductive lines 254 may include copper, tungsten, or a combination of copper and tungsten. In some embodiments, an upper portion of the peripheralconductive lines 254 may include copper and a lower portion of the peripheralconductive lines 254 may include tungsten. In some embodiments, both the upper portion and the lower portion of the peripheralconductive lines 254 may include copper, or both the upper portion and the lower portion may include tungsten. The peripheralconductive lines 254 may operably connect theaccess transistors 252 of theperipheral portion 250 to the magnetic memory cells 201 (FIGS. 6A and 6B ) of thearray 200. - Accordingly, a magnetic memory device is disclosed that includes an array of magnetic memory cells. Each of the magnetic memory cells of the array may include a semiconductor substrate, at least one access line extending in a column direction in or on the semiconductor substrate, and a bit contact operably coupled to the at least one access line on a drain side of the at least one access line. A magnetic tunnel junction region may be electrically coupled to the bit contact. At least one data/sense line may be electrically coupled to the magnetic tunnel junction region and may extend in a row direction transverse to the column direction. At least one source contact may be operably coupled to the at least one access line on a source side of the at least one access line. A common source plate may be electrically coupled to the at least one source contact. The common source plate may electrically couple the at least one source contact of each of the magnetic memory cells of the array to the at least one source contact of adjacent magnetic memory cells of the array in both the column direction and the row direction.
-
FIGS. 7 through 14 show a method of forming anarray 300 ofmagnetic memory cells 301 according to an embodiment of the present disclosure. Referring toFIG. 7 , asemiconductor substrate 320 may be provided. Dielectric STI regions and accessline trenches 305 may be formed in thesemiconductor substrate 320. Theaccess line trenches 305 may be at least partially filled with one or more conductive materials to form access lines 306 (e.g., word lines). For example, theaccess line trenches 305 may be lined with a conformal dielectric material (e.g., silicon dioxide) and an outer conductive material, such as titanium nitride, may be conformally formed over inner surfaces of the dielectric material within theaccess line trenches 305. The remaining portion of theaccess line trenches 305 may be filled with an inner conductive material, such as tungsten. An upper portion of the conductive material within theaccess line trenches 305 may be converted to a metal silicide material, such as tungsten silicide, by diffusing silicon into the conductive material, to form the word lines 306. - Referring to
FIG. 8 , agate dielectric material 307 and a firstinterlayer dielectric material 328A may be formed over thesemiconductor substrate 320 and word lines 306. For example, thegate dielectric material 307 may be a silicon dioxide material. The firstinterlayer dielectric material 328A may be one or more dielectric materials such as oxides (e.g., silicon dioxide) and/or nitrides (e.g., silicon nitride). - Referring to
FIG. 9 , holes 309 may be formed through the firstinterlayer dielectric material 328A and gatedielectric material 307 betweenadjacent word lines 306, to expose thesemiconductor substrate 320. Theholes 309 may be filled with one or more conductive materials to form lowersource contact portions 310A and lowerbit contact portions 334A. The one or more conductive materials may include, for example, an outer conformal layer of titanium nitride and an inner tungsten material. Excess conductive materials, if any, may be removed from over the firstinterlayer dielectric material 328A, such as by a chemical-mechanical polishing (“CMP”) process. - Referring to
FIG. 10 , a secondinterlayer dielectric material 328B may be formed over the firstinterlayer dielectric material 328A, lowersource contact portions 310A, and lowerbit contact portions 334A. Source contact holes 311 may be formed through the secondinterlayer dielectric material 328B and over the lowersource contact portions 310A to expose the lowersource contact portions 310A. One or more conductive materials may be formed in the source contact holes 311 to form uppersource contact portions 310B. For example, an outer conformal layer of titanium nitride and an inner tungsten material may be used to form the uppersource contact portions 310B. Excess conductive materials, if any, may be removed from over the secondinterlayer dielectric material 328B, such as by a CMP process. The lower and uppersource contact portions source contacts 310. - Referring to
FIG. 11 , acommon source plate 308 may be formed over and in contact with thesource contacts 310, and over the secondinterlayer dielectric material 328A. Thecommon source plate 308 may be patterned to result in a structure similar to thecommon source plate 208 described above with reference toFIG. 3A . Accordingly,cutouts 316 may be formed over the lowerbit contact portions 334A, but thecommon source plate 308 may operably connectadjacent source contacts 310 to each other in both column and row directions. Thecommon source plate 308 may include a conductive material, such as copper, tungsten, titanium, tantalum, aluminum, gold, conductive silicides thereof, conductive nitrides thereof, or combinations thereof. Adielectric mask material 317 may be formed over the conductive material of thecommon source plate 308 and may be used for patterning thecommon source plate 308. - Referring to
FIG. 12 , upperbit contact portions 334B may be formed over the lowerbit contact portions 334A and through thecutouts 316 in thecommon source plate 308. The upperbit contact portions 334B may be formed using a so-called “self-alignment contact” process, as follows. Adielectric spacer material 318, such as a silicon nitride material, may be formed over thedielectric mask material 317 and/or thecommon source plate 308. Portions of thedielectric spacer material 318 may be removed from horizontal surfaces, such as by using an anisotropic etch process, while other portions of thedielectric spacer material 318 may remain over vertical surfaces, such as along inner side walls of thecutouts 316. A sacrificial dielectric material, such as silicon dioxide, having different etch properties than thedielectric spacer material 318 may be formed over the structure. A top surface of the structure may be planarized, such as by a CMP process. Remaining portions of the sacrificial dielectric material (e.g., portions within thecutouts 316 and between the remaining dielectric spacer materials) may be removed, as well as an underlying portion of the secondinterlayer dielectric material 328B. This removal process may expose the lowerbit contact portions 334A through thecutouts 316. One or more conductive materials may be formed in thecutouts 316 and in contact with the lowerbit contact portions 334A to form upperbit contact portions 334B, which may extend through the secondinterlayer dielectric material 328B and through thecutouts 316 in thecommon source plate 308 between thedielectric spacer materials 318. The one or more conductive materials may be, for example, an outer layer of titanium nitride and an inner portion of tungsten. Excess conductive materials, if any, may be removed from over the structure, such as by a CMP process, to result in a structure like that shown inFIG. 12 . - The process described with reference to
FIGS. 10 through 12 is a process in which thecommon source plate 308 is formed prior to the upperbit contact portions 334B. However, the disclosure is not so limited. Rather, the disclosure also includes processes in which the upperbit contact portions 334B are formed over the lowerbit contact portions 334A, after which the uppersource contact portions 310B and thecommon source plate 308 are formed and operably coupled to the lowersource contact portions 310A. Given the processes described above, one of ordinary skill in the art is capable of forming the upperbit contact portions 334B prior to thecommon source plate 308, as desired. - Referring to
FIG. 13 , an MTJlower electrode material 334C may be formed over the upperbit contact portion 334B, for improved adhesion and electrical properties of theMTJs 302 to be formed thereover. The MTJlower electrode material 334C may include one or more conductive materials, such as a titanium nitride material formed over and in contact with the upperbit contact portion 334B, and a tantalum material formed over and in contact with the titanium nitride material. However, one of ordinary skill in the art is capable of selecting the appropriate material(s) for the MTJlower electrode material 334C considering the material and electrical properties of theMTJs 302. TheMTJs 302 may be formed over and in contact with the MTJlower electrode material 334C. TheMTJs 302 may be formed as known in the art, such as to have the structure shown inFIG. 1 . However,other MTJs 302 are known and capable of implementation with embodiments of this disclosure, as known by one of ordinary skill in the art. The MTJlower electrode material 334C andMTJs 302 may be formed in and through an upperinterlayer dielectric material 319, which may include one or more dielectric materials (e.g., silicon dioxide and silicon nitride). The lowerbit contact portions 334A, upperbit contact portions 334B, and MTJlower electrode materials 334C may together definebit contacts 334. - Referring to
FIG. 14 , data/sense lines 304 (e.g., bit lines) may be formed over theMTJs 302.MTJs 302 that are aligned in a row direction may be electrically coupled to thesame bit line 304. The bit lines 304 may include one or more conductive materials, such as copper, tungsten, titanium, tantalum, aluminum, gold, conductive silicides thereof, conductive nitrides thereof, or combinations thereof. Eachmagnetic memory cell 301 of thearray 300 may include anMTJ 302, abit contact 334, at least one word line 306 (e.g., two word lines 306), at least onesource contact 310, and a portion of thecommon source plate 308. Thearray 300 may, in plan view, have a similar configuration as thearray 200 shown inFIG. 3A , for example. - Accordingly, the present disclosure includes methods of fabricating magnetic memory devices. In accordance with such methods, an array of magnetic memory cells may be formed. Each of the magnetic memory cells of the array may be formed by forming at least one access line extending in a column direction in or on a semiconductor substrate. A bit contact may be formed and operably coupled to the at least one access line on a drain side of the at least one access line. A magnetic tunnel junction region may be formed and electrically coupled to the bit contact. At least one data/sense line may be formed and electrically coupled to the magnetic tunnel junction region and may extend in a row direction transverse to the column direction. At least one source contact may be formed and operably coupled to the at least one access line on a source side of the at least one access line. A common source plate may be formed and electrically coupled to the at least one source contact. The common source plate may be patterned to electrically couple the at least one source contacts of adjacent magnetic memory cells of the array in both the column direction and the row direction.
- Embodiments of the disclosure may be implemented in STT-MRAM devices as well as other magnetic memory devices. Indeed, one of ordinary skill in the art may implement embodiments of the disclosure in a number of different semiconductor devices, example embodiments of which have been described herein.
-
FIG. 15 is a schematic block diagram of anelectronic system 400 according to an embodiment of the present disclosure. Theelectronic system 400 includes aprocessor 410 operably coupled with amemory device 420, one ormore input devices 430, and one ormore output devices 440. Theelectronic system 400 may be a consumer electronic device, such as a desktop computer, a laptop computer, a tablet computer, an electronic reader, a smart phone, or other type of communication device, as well as any type of computing system incorporating non-volatile storage. Thememory device 420 may be or include a magnetic memory device (e.g., one or more of themagnetic memory devices 200, 300) that includes a common source plate (e.g., one or more of thecommon source plates 208, 308) as discussed above. - Accordingly, the present disclosure includes electronic systems that include a magnetic memory device. The electronic systems may include at least one processor, at least one input device and at least one output device operably coupled to the at least one processor, and at least one magnetic memory device operably coupled to the at least one processor. The magnetic memory device may include an array of magnetic memory cells including conductive word lines in or on a semiconductor substrate, conductive bit lines, and magnetic tunnel junction regions each operably coupled to and between one of the conductive bit lines and, through a conductive bit contact, two of the conductive word lines. The conductive word lines may extend in a column direction and the conductive bit lines may extend in a row direction transverse to the column direction. A common source plate may be operably coupled to each of the conductive word lines through a conductive source contact and to each of the magnetic memory cells of the array.
- While certain illustrative embodiments have been described in connection with the figures, those of ordinary skill in the art will recognize and appreciate that embodiments encompassed by the disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications to the embodiments described herein may be made without departing from the scope of embodiments encompassed by the disclosure, such as those hereinafter claimed, including legal equivalents. In addition, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the disclosure as contemplated by the inventors.
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US15/653,181 US10453895B2 (en) | 2017-01-05 | 2017-07-18 | Magnetic memory device with a common source having an array of openings, system, and method of fabrication |
US15/982,251 US10727271B2 (en) | 2017-01-05 | 2018-05-17 | Memory device having source contacts located at intersections of linear portions of a common source, electronic systems, and associated methods |
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US15/982,251 Continuation-In-Part US10727271B2 (en) | 2017-01-05 | 2018-05-17 | Memory device having source contacts located at intersections of linear portions of a common source, electronic systems, and associated methods |
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Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4157571B2 (en) * | 2006-05-24 | 2008-10-01 | 株式会社東芝 | Spin injection magnetic random access memory |
JP2007317954A (en) | 2006-05-26 | 2007-12-06 | Nec Electronics Corp | Semiconductor device, and its manufacturing method |
JP2008091703A (en) * | 2006-10-03 | 2008-04-17 | Toshiba Corp | Semiconductor storage device |
JP5091495B2 (en) * | 2007-01-31 | 2012-12-05 | 株式会社東芝 | Magnetic random access memory |
JP2011023476A (en) * | 2009-07-14 | 2011-02-03 | Toshiba Corp | Magnetic memory device |
KR101886382B1 (en) * | 2011-12-14 | 2018-08-09 | 삼성전자주식회사 | Data storage devices and methods of manufacturing the same |
US9007818B2 (en) | 2012-03-22 | 2015-04-14 | Micron Technology, Inc. | Memory cells, semiconductor device structures, systems including such cells, and methods of fabrication |
US8923038B2 (en) | 2012-06-19 | 2014-12-30 | Micron Technology, Inc. | Memory cells, semiconductor device structures, memory systems, and methods of fabrication |
US9054030B2 (en) | 2012-06-19 | 2015-06-09 | Micron Technology, Inc. | Memory cells, semiconductor device structures, memory systems, and methods of fabrication |
US9373775B2 (en) | 2012-09-13 | 2016-06-21 | Micron Technology, Inc. | Methods of forming magnetic memory cells |
US9029822B2 (en) | 2012-11-17 | 2015-05-12 | Avalanche Technology, Inc. | High density resistive memory having a vertical dual channel transistor |
US9379315B2 (en) | 2013-03-12 | 2016-06-28 | Micron Technology, Inc. | Memory cells, methods of fabrication, semiconductor device structures, and memory systems |
US9368714B2 (en) | 2013-07-01 | 2016-06-14 | Micron Technology, Inc. | Memory cells, methods of operation and fabrication, semiconductor device structures, and memory systems |
US9466787B2 (en) | 2013-07-23 | 2016-10-11 | Micron Technology, Inc. | Memory cells, methods of fabrication, semiconductor device structures, memory systems, and electronic systems |
US9461242B2 (en) | 2013-09-13 | 2016-10-04 | Micron Technology, Inc. | Magnetic memory cells, methods of fabrication, semiconductor devices, memory systems, and electronic systems |
US9608197B2 (en) | 2013-09-18 | 2017-03-28 | Micron Technology, Inc. | Memory cells, methods of fabrication, and semiconductor devices |
US10454024B2 (en) | 2014-02-28 | 2019-10-22 | Micron Technology, Inc. | Memory cells, methods of fabrication, and memory devices |
US9281466B2 (en) | 2014-04-09 | 2016-03-08 | Micron Technology, Inc. | Memory cells, semiconductor structures, semiconductor devices, and methods of fabrication |
US9269888B2 (en) | 2014-04-18 | 2016-02-23 | Micron Technology, Inc. | Memory cells, methods of fabrication, and semiconductor devices |
US9349945B2 (en) | 2014-10-16 | 2016-05-24 | Micron Technology, Inc. | Memory cells, semiconductor devices, and methods of fabrication |
US9768377B2 (en) | 2014-12-02 | 2017-09-19 | Micron Technology, Inc. | Magnetic cell structures, and methods of fabrication |
US10439131B2 (en) | 2015-01-15 | 2019-10-08 | Micron Technology, Inc. | Methods of forming semiconductor devices including tunnel barrier materials |
-
2017
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