US20180182697A1 - Forming a stress compensation layer and structures formed thereby - Google Patents
Forming a stress compensation layer and structures formed thereby Download PDFInfo
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- US20180182697A1 US20180182697A1 US15/900,743 US201815900743A US2018182697A1 US 20180182697 A1 US20180182697 A1 US 20180182697A1 US 201815900743 A US201815900743 A US 201815900743A US 2018182697 A1 US2018182697 A1 US 2018182697A1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H05K3/3484—
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3485—Applying solder paste, slurry or powder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0568—Resist used for applying paste, ink or powder
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.
Description
- This patent application is a Divisional of U.S. patent application Ser. No. 10/990,228, filed Nov. 15, 2004, entitled “FORMING A STRESS COMPENSATION LAYER AND STRUCTURES FORMED THEREBY,” which designates the United States of America, the entire disclosure of which is hereby incorporated by reference in its entirety and for all purposes.
- As semiconductor technology advances for higher processor performance, package sizes may shrink and higher input/output (I/O) counts may be required to reduce manufacturing costs. Packaging technologies, especially in some chipset applications, may drive a finer pitch between interconnect structures, such as between solder balls in a ball grid array package. With the scaling of pitch, smaller ball size is expected which may pose a challenge to interconnect joint (i.e., the interface between an interconnect structure and another surface, such as a substrate or contact pad) performance.
- Interconnect joint failures have been observed in many types of packaging assemblies, such as in ball grid array assemblies. These failures may be due to various stresses, such as thermal or physical stresses that may be incurred after a reflow process has been performed on the interconnect structure, for example.
- While the specification concludes with claims particularly pointing out and distinctly claiming certain embodiments of the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
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FIGS. 1a-1i represent methods of forming structures according to an embodiment of the present invention. -
FIGS. 2a-2h represents methods of forming structures according to another embodiment of the present invention. -
FIGS. 3a-3b represents structures comprising a system according to an embodiment of the present invention. -
FIG. 4 represents a structure according the Prior Art. - In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
- Methods and associated structures of forming and utilizing a microelectronic structure, such as a joint structure, are described. Those methods may comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.
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FIGS. 1a-1h illustrate an embodiment of a method of forming a microelectronic structure, such as a joint structure, for example.FIG. 1a illustrates asubstrate 100. In one embodiment, thesubstrate 100 may comprise at least one of a package substrate, a motherboard, an interposer, a test coupon, and a land grid array. Astress compensation layer 102, such as, but not limited to, no-flow underfill type materials, as are known in the art, may be formed on the substrate 100 (FIG. 1b ). In one embodiment, thestress compensation layer 102 may comprise at least one of epoxy, a cyanate ester, a polyimide, a polybenzoxazole, a polybenzimidazole, and a polybenzothiazole, for example. - The
stress compensation layer 102 may be formed by such methods as dispensing and/or screen printing as are known in the art, for example. Thestress compensation layer 102 may comprise any such material that may relieve stresses that may exist between interconnect structures and/or between interconnect structures and a substrate that may be subsequently joined to the interconnect structures. In one embodiment, the stresses may exist, for example, between solder balls in a ball grid array structure and/or between solder balls and a package substrate joined to the solder balls. In another embodiment, the stresses may exist between wire bonds and/or between wire bonds and a package substrate joined to the wire bonds. - The
stress compensation layer 102 may undergo a heat treatment 104 (FIG. 1c ). Theheat treatment 104 may remove a portion of liquid and/or moisture from thestress compensation layer 102, such as solvents, for example, as is well known in the art. Theheat treatment 104 may also provide fluidity to thestress compensation layer 102 during a subsequent patterning process. The temperature of theheat treatment 104 may be less than the cure temperature of thestress compensation layer 102, so that the temperature of theheat treatment 104 may not substantially cure thestress compensation layer 102. In one embodiment, theheat treatment 104 may be from about 80 to about 120 degrees Celsius. - The
stress compensation layer 102 may be patterned using various methods as are well known in the art. In one embodiment, thestress compensation layer 102 may be patterned using amicrotool 106, as is well known in the art (FIG. 1d ). Themicrotool 106 may comprise a nickel electroplated microtool, for example, and may generally comprise a patterning tool that may replicate a pattern into a material, such as thestress compensation layer 102. Themicrotool 106 may indent, or imprint, a pattern, such as but not limited to an interconnect pattern, into and/or within thestress compensation layer 102. In one embodiment, at least one opening 108 (FIG. 1e ) may be formed within thestress compensation layer 102 by utilizing a patterning process, such as (but not limited to) by utilizing themicrotool 106. In one embodiment, the at least one opening 108 may comprise an interconnect pattern, such as by illustration and not limitation a ball grid array interconnect pattern, as is well known in the art. The at least one opening 108 may be formed at a temperature below the cure temperature of thestress compensation layer 102. In one embodiment, the temperature that may be applied during the formation of the at least one opening 108 may comprise from about 80 to about 120 degrees Celsius. The at least one opening 108 may comprise abottom surface 105 and at least onesidewall 107. - The
microtool 106 may be removed from thestress compensation layer 102 after the at least oneopening 108 is formed (FIG. 1e ). Themicrotool 106 may comprise a non-stick coating, as are well known in the art, that may prevent residual material, such asstress compensation layer 102 particles etc, from remaining within the at least one opening 108. In some embodiments however, acleaning process 110 may additionally be performed, such as an oxygen plasma cleaning process, as is well known in the art, that may remove any residual material that may be present from the at least one opening 108 (FIG. 1f ). - An
interconnect paste 112 may be formed within the at least one opening 108 (FIG. 1g ). Theinterconnect paste 112 may comprise any type of material or combination of materials that may be utilized to form interconnect structures, such as but not limited to ball grid array interconnect structures and/or wire bond interconnect structures, as are well known in the art. In one embodiment, theinterconnect paste 112 may be formed utilizing stencil printing, solder jet or solder mold transfer techniques, as are well known in the art. In another embodiment, theinterconnect paste 112 may comprise flux and/or solder balls that may be deposited within the at least oneopening 108 utilizing deposition methods known in the art, such as screen printing of flux followed by solder ball placement using standard solder ball pick and place equipment. In one embodiment theinterconnect paste 112 may comprise a solder paste, as is well known in the art. - The
interconnect paste 112 may comprise aheight 116. Aheight 114 of thestress compensation layer 102 may be less than theheight 116 of theinterconnect paste 112. In one embodiment, theheight 114 of thestress compensation layer 102 may comprise about 10 percent to about 60 percent of theheight 116 of theinterconnect paste 112. Theinterconnect paste 112 may be exposed to aheating process 117, as is known in the art, in which theinterconnect paste 112 may be heated to form at least one interconnect structure 120 (FIG. 1h ). A height after heating 115 of thestress compensation layer 102 may be less than theheight 116 of theinterconnect paste 112. In one embodiment, the heating process may comprise a reflow process and/or a die attach process, as are known in the art. In one embodiment, theheating process 117 may comprise a temperature from about 230 degrees to about 280 degrees Celsius. In one embodiment, the interconnect paste may comprise a near-eutectic Sn—Ag—Cu solder and/or paste. - The
stress compensation layer 102 may be substantially cured during theheating process 117. In one embodiment, the at least oneinterconnect structure 120 may comprise an array, or a plurality, of interconnect structures, such as but not limited to an array of solder balls, such as a ball grid array. Ajoint structure 122 may generally comprise the at least oneinterconnect structure 120 disposed on thesubstrate 100 with thestress compensation layer 102 disposed between at least two of the at least oneinterconnect structure 120. - The at least one
interconnect structure 120 may comprise aheight 118. Theheight 114 of thestress compensation layer 102 may be less than theheight 118 of the at least oneinterconnect structure 120. In one embodiment, theheight 114 of thestress compensation layer 102 may comprise about 10 percent to about 60 percent of theheight 116 of the at least oneinterconnect structure 120. Because theheight 114 of thestress compensation layer 102 may be less than theheight 118 of the at least one interconnect structure, thestress compensation layer 102 may be substantially prevented from contacting atop surface 121 of the at least oneinterconnect structure 120. -
FIG. 4 depicts atop surface 421 of aninterconnect structure 420 from the prior art. Thetop surface 421 of theinterconnect structure 420 may comprisesurface contamination 422 that may arise from residual stress compensation layer material, (that may be similar to thestress compensation layer 102 ofFIG. 1h , for example).FIG. 1i depicts a top view of thetop surface 121 of theinterconnect structure 120, wherein thetop surface 121 of theinterconnect structure 120 is substantially free of surface contamination. In one embodiment, thetop surface 121 of theinterconnect structure 120 may comprise less than about 5% surface contamination. By forming thestress compensation layer 102 prior to the formation of theinterconnect structure 120, wherein thestress compensation layer 102 is lower in height than theinterconnect structure 120, as in certain embodiments of the present invention, thestress compensation layer 102 is substantially prevented from contacting thetop surface 121 of theinterconnect structure 120. Therefore, thestress compensation layer 102 may be substantially prevented from contributing to the contamination of thetop surface 121 of theinterconnect structure 120 ofstress compensation layer 102 material. - In another embodiment, a
stress compensation layer 202, similar to thestress compensation layer 102, may be formed within at least oneopening 203 of a first substrate 206 (FIG. 2a-2b ). In one embodiment, thefirst substrate 206 may comprise an interconnect pattern tool. In another embodiment thefirst substrate 206 may comprise a microtool, for example. Thefirst substrate 206 may comprise a silicone mold in another embodiment. Thefirst substrate 206 may generally comprise a patterning tool that may form a pattern, such as a template for an interconnect pattern, utilizing a material, such as thestress compensation layer 202. - The
stress compensation layer 202 may be formed within the at least oneopening 203 of thefirst substrate 206 by any type of formation method, such as but not limited to screen printing, as is known in the art. Thestress compensation layer 202 may undergo aheat treatment 204, similar to theheat treatment 104. The temperature of theheat treatment 204 may be less than the cure temperature of thestress compensation layer 202. In one embodiment, theheat treatment 204 may be from about 80 to about 120 degrees Celsius. - A
second substrate 200 may be provided (FIG. 1c ). Thesecond substrate 200 may be placed in contact with thestress compensation layer 202 disposed within the at least oneopening 203 of the first substrate 206 (FIG. 1d ). In one embodiment, thefirst substrate 206 and thesecond substrate 200 may be exposed to aheat process 207. Theheat process 207 may comprise a temperature below the cure temperature of thestress compensation layer 202. In one embodiment, the temperature of theheat process 207 that may be applied during the contacting of thefirst substrate 200 and thesecond substrate 206 may be between about 80 and 120 degrees Celsius. Heating thefirst substrate 206 and thesecond substrate 200 may join and/or form abond 209 between thestress compensation layer 202 and thesecond substrate 200. - The
first substrate 206 may be removed from thesecond substrate 200, leaving thestress compensation layer 202 bonded and/or joined to the second substrate 200 (FIG. 2e ). Thestress compensation layer 202 may form, i.e. transfer, the pattern from thefirst substrate 206 to thesecond substrate 200. By forming the pattern from thefirst substrate 206 on thesecond substrate 200, at least oneopening 208 may be formed on thesecond substrate 200. In one embodiment, the at least oneopening 208 may comprise an interconnect pattern, such as by illustration and not limitation a ball grid array and/or a wire bond interconnect pattern, as are well known in the art. - The
second substrate 200 comprising thestress compensation layer 202 and the at least oneopening 208 may be exposed to a cleaning process 210 (FIG. 2f ). In some embodiments, thecleaning process 210 may comprise an oxygen plasma cleaning process, as is well known in the art, in order to remove any residual material that may be present from the at least one opening 208 (FIG. 1f ). - An
interconnect paste 212, similar to theinterconnect paste 112, may be formed within the at least one opening 208 (FIG. 2g ). In one embodiment, theinterconnect paste 212 may be formed utilizing stencil printing, solder jet or solder mold transfer techniques, as are well known in the art. In one embodiment the interconnect paste may comprise a solder paste, as is well known in the art. In another embodiment, theinterconnect paste 212 may comprise flux and/or solder balls that may be deposited within the at least oneopening 208 utilizing deposition methods known in the art, such as screen printing of flux followed by solder ball placement using standard solder ball pick and place equipment. Theinterconnect paste 212 may comprise aheight 216. Aheight 214 of thestress compensation layer 202 may be less than theheight 216 of theinterconnect paste 212. In one embodiment, theheight 214 of thestress compensation layer 202 may comprise about 10 percent to about 60 percent of theheight 216 of theinterconnect paste 212. - The
interconnect paste 212 may be exposed to aheating process 217, as is known in the art, in which theinterconnect paste 212 may be heated to form at least one interconnect structure 220 (FIG. 2g ). A height after heating 215 of thestress compensation layer 202 may be less than theheight 216 of theinterconnect paste 212. In one embodiment, theheating process 217 may comprise a reflow process and/or a die attach process, as is known in the art. In one embodiment, theheating process 217 may comprise a temperature from about 230 degrees to about 280 degrees Celsius. Ajoint structure 222 may generally comprise the at least oneinterconnect structure 220 disposed on thesecond substrate 200 with thestress compensation layer 202 disposed between at least two of the at least oneinterconnect structure 220. -
FIG. 3a depicts ajoint structure 342 that may be used in a system, such as in thesystem 300 depicted inFIG. 3b . Thejoint structure 342 may comprise afirst substrate 334. In one embodiment, thefirst substrate 334 may comprise a motherboard (such as a printed circuit board), a land grid array, an interposer and/or a test coupon, for example. At least oneinterconnect structure 340 may be attached to both thefirst substrate 334 and to asecond substrate 330. In one embodiment, thesecond substrate 330 may comprise a package substrate, for example. - A
stress compensation layer 332, (similar to thestress compensation layers 102 and 202), may be disposed between at least two of the at least oneinterconnect structure 340. Thestress compensation layer 332 may comprise aheight 334 that is less than aheight 336 of the at least oneinterconnect structure 340. Thestress compensation layer 332 may strengthen the interface between thesecond substrate 330 and the at least oneinterconnect structure 340 by providing stress relief and structural support at the interface. - Since the
stress compensation layer 332 may comprise aheight 334 that is less than theheight 336 of the at least oneinterconnect structure 340, a top surface (not shown, but similar to thetop surface 121 ofFIG. 1i ) may be substantially free of surface contamination. Thus, the methods of the present invention may serve to avoid and/or substantially reduce the surface contamination that may likely be present when thestress compensation layer 332 is formed after the interconnect structures are formed, such as may be the case in prior art structures, for example as depicted inFIG. 4 . Therefore, thestress compensation layer 332 may greatly increase the reliability and reduce interface related failures and/or joint failures of devices utilizing the methods and structures of certain embodiments of the present invention. -
FIG. 3b is a diagram illustrating an exemplary system capable of being operated with methods for fabricating a microelectronic structure, such as thejoint structure 342 ofFIG. 3a for example. It will be understood that the present embodiment is but one of many possible systems in which the joint structures of the present invention may be used. Thesystem 300 may be used, for example, to execute the processing by various processing tools, such as but not limited to die attach tools, as are well known in the art, for the methods described herein. - In the
system 300, ajoint structure 342 may be communicatively coupled to a printed circuit board (PCB) 301 by way of an I/O bus 308. The communicative coupling of thejoint structure 342 may be established by physical means, such as through the use of a package and/or a socket connection to mount thejoint structure 342 to the PCB 301 (for example by the use of a chip package and/or a land grid array socket). Thejoint structure 342 may also be communicatively coupled to thePCB 301 through various wireless means (for example, without the use of a physical connection to the PCB), as are well known in the art. - The
system 300 may include acomputing device 302, such as a processor, and acache memory 304 communicatively coupled to each other through aprocessor bus 305. Theprocessor bus 305 and the I/O bus 308 may be bridged by ahost bridge 306. Communicatively coupled to the I/O bus 308 and also to thejoint structure 342 may be amain memory 312. Examples of themain memory 312 may include, but are not limited to, static random access memory (SRAM) and/or dynamic random access memory (DRAM), and/or some other state preserving medium. Thesystem 300 may also include agraphics coprocessor 313, however incorporation of thegraphics coprocessor 313 into thesystem 300 is not necessary to the operation of thesystem 300. Coupled to the I/O bus 308 may also, for example, be adisplay device 314, amass storage device 320, and keyboard andpointing devices 322. - These elements perform their conventional functions well known in the art. In particular,
mass storage 320 may be used to provide long-term storage for the executable instructions for a method for forming joint structures in accordance with embodiments of the present invention, whereasmain memory 312 may be used to store on a shorter term basis the executable instructions of a method for forming joint structures in accordance with embodiments of the present invention during execution bycomputing device 302. In addition, the instructions may be stored, or otherwise associated with, machine accessible mediums communicatively coupled with the system, such as compact disk read only memories (CD-ROMs), digital versatile disks (DVDs), and floppy disks, carrier waves, and/or other propagated signals, for example. In one embodiment,main memory 312 may supply the computing device 302 (which may be a processor, for example) with the executable instructions for execution. - Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that various microelectronic structures, such as joint structures, are well known in the art. Therefore, the Figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein.
Claims (20)
1. A structure comprising:
a stress compensation layer disposed between a plurality of interconnect structures, wherein the plurality of interconnect structures are disposed on a substrate, and wherein a height of the stress compensation layer is less than a height of the plurality of interconnect structures.
2. The structure of claim 1 , wherein the stress compensation layer comprises at least one of epoxy, a cyanate ester, a polyimide, a polybenzoxazole, a polybenzimidazole, and a polybenzothiazole.
3. The structure of claim 1 , wherein the height of the stress compensation layer comprises about 10 percent to about 60 percent of the height of the interconnect structures.
4. The structure of claim 1 , wherein the percentage of a top surface of the interconnect structure comprises about 5% or less of surface contamination.
5. The structure of claim 1 , wherein the plurality of interconnect structures is a plurality of solder balls.
6. The structure of claim 1 , wherein the plurality of solder balls form a ball grid array.
7. The structure of claim 1 , wherein the stress compensation layer is a no-flow underfill material.
8. A structure comprising:
a package substrate having a surface;
a plurality of interconnect structures on the surface of the package substrate;
a stress compensation layer on the surface of the package substrate and between the plurality of interconnect structures;
a substrate coupled to the plurality of interconnect structures, the substrate on a side of the interconnect structures opposite the package substrate; and
a gap between the stress compensation layer and the substrate.
9. The structure of claim 8 , wherein the stress compensation layer is a no-flow underfill material.
10. The structure of claim 8 , wherein the substrate is selected from the group consisting of a motherboard, a land grid array, an interposer and a test coupon.
11. The structure of claim 8 , wherein the stress compensation layer comprises at least one of epoxy, a cyanate ester, a polyimide, a polybenzoxazole, a polybenzimidazole, and a polybenzothiazole.
12. The structure of claim 8 , wherein a height of the stress compensation layer comprises about 10 percent to about 60 percent of a height of the interconnect structures.
13. The structure of claim 8 , wherein the percentage of a surface of the interconnect structure coupled to the substrate comprises about 5% or less of surface contamination.
14. The structure of claim 8 , wherein the plurality of interconnect structures is a plurality of solder balls.
15. The structure of claim 8 , wherein the plurality of solder balls for a ball grid array.
16. A system comprising:
a joint structure comprising:
at least two interconnect structures disposed on a substrate;
a stress compensation layer disposed between the at least two interconnect structures, wherein a height of the stress compensation layer is less than a height of the at least two interconnect structures, and wherein a top surface of the at least two interconnect structures is substantially free of contamination;
a bus communicatively coupled to the at least two interconnect structures; and
a DRAM communicatively coupled to the bus.
17. The structure of claim 16 , wherein the stress compensation layer comprises at least one of epoxy, a cyanate ester, a polyimide, a polybenzoxazole, a polybenzimidazole, and a polybenzothiazole.
18. The structure of claim 16 , wherein the height of the stress compensation layer comprises about 10 percent to about 60 percent of the height of the at least two interconnect structures.
19. The structure of claim 16 , wherein the percentage of a top surface of the at least two interconnect structures comprises about 5% or less of surface contamination.
20. The structure of claim 16 , wherein the stress compensation layer is a no-flow underfill material.
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US20060105497A1 (en) | 2006-05-18 |
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