US20180175832A1 - Power switching circuitry including power-up control - Google Patents
Power switching circuitry including power-up control Download PDFInfo
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- US20180175832A1 US20180175832A1 US15/382,076 US201615382076A US2018175832A1 US 20180175832 A1 US20180175832 A1 US 20180175832A1 US 201615382076 A US201615382076 A US 201615382076A US 2018175832 A1 US2018175832 A1 US 2018175832A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
-
- H02M2001/0048—
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0036—Means reducing energy consumption
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- Embodiments described herein pertain to supply power in integrated circuits. Some embodiments relate to control of supply power in integrated circuits in different modes.
- Many electronic systems e.g., computers and cellular phones
- Such electronic systems also have reconnection operations to reconnect power supply to that particular part of the device in another mode (e.g., an active mode) of the device.
- designing components e.g., circuitry
- such reconnection operations with minimal side effects may pose a challenge.
- FIG. 1A shows an apparatus including an integrated circuit (IC) having power switching circuitry and functional units, according to some embodiments described herein.
- IC integrated circuit
- FIG. 1B is a timing diagram showing example waveforms of some of the voltages of the IC of FIG. 1A during different states of a functional unit of the IC, according to some embodiments described herein.
- FIG. 2A shows a schematic diagram of an IC including power switching circuitry that includes transistors coupled in parallel between power supply nodes, according to some embodiments described herein.
- FIG. 2B shows timing diagrams showing waveforms of some signals of the power switching circuitry of FIG. 2A , according to some embodiments described herein.
- FIG. 3 shows a schematic diagram of a portion of the power switching circuitry of FIG. 2A including a resistive network and a selector, according to some embodiments described herein.
- FIG. 4A shows a schematic diagram of the resistive network and the selector of FIG. 3 including transmission gates, according to some embodiments described herein.
- FIG. 4B is a chart showing relationships between the values of digital information provided to the selector of FIG. 4A and corresponding values of voltages provided to gates of the transistors of the power switching circuitry of FIG. 2A , according to some embodiments described herein.
- FIG. 5 shows an apparatus in the form of a system (e.g., electronic system), according to some embodiments described herein.
- a system e.g., electronic system
- FIG. 6 is a flowchart showing a method of operating an apparatus, according to some embodiments described herein.
- the techniques described herein include an IC having a functional unit and a power switching circuitry to control delivery of power to the functional unit in different operating states of the functional unit.
- the techniques described herein include many improvements over some conventional techniques that involve control of supply power in electronic devices and systems.
- some of the information (e.g., digital codes) used during part of the operations of the described power switching circuitry can be programmable (e.g., post-silicon programming). This avoids calibration (e.g., post-silicon trimming) of components associated with the power switching circuitry.
- the structures and operations of components (e.g., power switching circuitry) used in the described techniques can help reduce or avoid excessive heat that may occur at some part (e.g., transistors) of the components.
- the described techniques can help reduce voltage droops and noise in supply voltages, and reduce electro-migration in metal structures that are used to deliver current to some power supply nodes of the IC.
- the described techniques can make some relationships of the components (e.g., resistor ratios) of the described power switching circuitry insensitive to process-voltage-temperature (PVT) variations. This may improve current profiles in some operational modes of the described power switching circuitry. Other improvements are described below.
- FIG. 1A shows an apparatus 100 including an IC 102 having power switching circuitry 131 , 132 , and 133 , and functional units 111 , 112 , and 113 , according to some embodiments described herein.
- Apparatus 100 can include or be included in an electronic device or system. Examples of such devices or systems include computers (e.g., servers, desktops, laptops, and notebooks), tablets, cellular phones, wearable electronic things, and other electronic devices or systems.
- IC 102 can include an IC die (e.g., semiconductor (e.g., silicon) die (e.g., a chip)) where components of IC 102 are located.
- IC 102 include a general purpose processor (e.g., a microprocessor), a graphics processor, a microcontroller, an application-specific integrated circuit (ASIC), a system-on-chip (SoC), and other electronic devices or systems.
- IC 102 can include an IC die (e.g., semiconductor (e.g., silicon) die (e.g., a chip)) where components of IC 102 are located.
- Examples of IC 102 include a general purpose processor (e.g., a microprocessor), a graphics processor, a microcontroller, an application-specific integrated circuit (ASIC), a system-on-chip (SoC), and other electronic devices or systems.
- ASIC application-specific integrated circuit
- SoC system-on-chip
- Functional units 111 , 112 , and 113 can include or can be parts of a graphics processor (e.g., execution unit) or core (e.g., central processing unit (CPU)) of a processor, a memory cell array, and other types of functional units (e.g., functional units inside a processor).
- FIG. 1A shows IC 102 including three functional units 111 , 112 , and 113 as an example. However, the number of functional units in IC 102 can vary.
- apparatus 100 can include a power supply node 105 to receive a voltage VCC IN (e.g., un-gated power supply voltage) and power supply nodes 121 , 122 , and 123 to provide voltages (e.g., gated power supply voltages) VCC 1 , VCC 2 , and VCC 3 .
- Power supply node 105 can be part of a supply power rail (e.g., un-gated V CC power rail) of apparatus 100 that can receive supply power from a battery (not shown) through a power path coupled to the battery (not shown in FIG. 1A ).
- Such a power path may include a voltage regulator, which can receive power from the battery and generate a regulated voltage (e.g., voltage VCC IN ).
- voltage VCC IN can be a regulated supply voltage (e.g., provided at an output of a voltage regulator).
- the voltage regular (not shown in FIG. 1A ) can be an off-die (e.g., off-chip) voltage regulator located outside IC 102 or on-die (e.g., on-chip) voltage regulator located on IC 102 .
- power supply nodes 121 , 122 , and 123 can be parts of other supply power rails (e.g., gated VCC 1 , VCC 2 , and VCC 3 power rails) of IC 102 to provide respective voltages VCC 1 , VCC 2 , and VCC 3 to functional units 111 , 112 , and 113 , respectively.
- the value of voltages VCC 1 , VCC 2 , and VCC 3 is based on (e.g., equal to) the value of voltage VCC IN .
- the values of voltages VCC 1 , VCC 2 , and VCC 3 can be the same or different.
- Power switching circuitry 131 , 132 , and 133 can share voltage VCC IN but they can operate independently from each other to control (e.g., separately control) delivery of power from power supply node 105 to power supply nodes 121 , 122 , and 123 (where voltages VCC 1 , VCC 2 , and VCC 3 are respectively provided).
- Power switching circuitry 131 , 132 , and 133 can generate (e.g., provide) information (e.g., digital codes) CODE 1 , CODE 2 , and CODE 3 , respectively.
- information CODE 1 , CODE 2 , and CODE 3 can include digital information (e.g., a code including bits).
- Each of power switching circuitry 131 , 132 , and 133 can include transistors (not shown in FIG. 1A ) coupled between power supply nodes 105 and a respective power supply node among power supply nodes 121 , 122 , and 123 .
- Power switching circuitry 131 , 132 , and 133 can use respective information CODE 1 , CODE 2 , and CODE 3 to control delivery of power from power supply node 105 to nodes 121 , 122 , and 123 , respectively.
- Information CODE 1 , CODE 2 , and CODE 3 can be provided to IC 102 (e.g., by programming) during the manufacture of IC 102 before IC 102 is included in an IC package or in an electronic device or system (e.g., apparatus 100 ), or before IC 102 is shipped to a user (e.g., customer).
- information CODE can be provided to IC 102 after manufacturing (post-manufacturing) of IC 102 (e.g. after IC 102 is included in an IC package or in an electronic device or system (e.g., apparatus 100 ) or after IC 102 is shipped to a user (e.g., customer)).
- IC 102 can include lines (conductive lines) 104 , which can be conductive nodes within IC 102 or pins (or solder balls) on a package where IC 102 is located. Other devices external to IC 102 can communicate with IC 102 through lines 104 .
- Information CODE 1 , CODE 2 , and CODE 3 can be provided to IC 102 through lines 104 (e.g., by programming or by other techniques).
- IC 102 may store (e.g., store in internal memory of IC 102 ) the values of information CODE 1 , CODE 2 , and CODE 3 .
- power switching circuitry 131 , 132 , and 133 can generate (e.g., regenerate) information CODE 1 , CODE 2 , and CODE 3 having values based on (e.g., equal to) the stored values.
- Each of functional units 111 , 112 , and 113 can have different operational states (e.g., power states) that may include a higher power consumption state (e.g., active state) and a lower power consumption state (e.g., an inactive state).
- the functional unit e.g., 111 , 112 , or 113
- the functional unit may actively perform its operations (e.g., processing information, decoding instructions, storing information (e.g., data) in memory cells, retrieving information from memory cells, or other operations).
- the functional unit e.g., 111 , 112 , or 113
- the functional unit may be inactive or may be idling. Power consumed by the functional unit in a higher power consumption state is higher than power consumed by the functional unit in a lower power consumption state.
- Functional units 111 , 112 , and 113 may not be in the same state at a particular time interval during an operation of IC 102 .
- power supply node 105 can be disconnected from power supply node 121 , 122 , or 123 coupled to a particular functional unit (e.g., 111 , 112 , or 113 ) when that particular functional unit enters (or is in) the lower power consumption state.
- a particular functional unit e.g., 111 , 112 , or 113
- power switching circuitry 131 can disconnect power supply node 121 from power supply node 105 to avoid leakage of power.
- Power switching circuitry 131 can connect power supply node 121 to power supply node 105 (e.g., during a power-on mode) when functional unit 111 exits the lower power consumption state (e.g., changes from the lower power consumption state to the higher power consumption state). Power switching circuitry 131 can use information CODE 1 during part of its operation (e.g., during a power-on mode) when it connects power supply node 121 to power supply node 105 .
- FIG. 1B is a timing diagram showing example waveforms of voltages VCC IN and VCC 1 of FIG. 1A during different states of functional unit 111 of IC 102 , according to some embodiments described herein.
- FIG. 1B shows example waveform of voltage VCC 1 .
- waveforms of voltages VCC 2 and VCC 3 during lower and higher power consumption states of each of functional units 112 and 113 can be similar to the waveform of voltage VCC 1 of FIG. 1B .
- voltage VCC IN can have a value (e.g., value Vx) that is relatively unchanged (e.g., constant) between times T 0 and T 3 .
- Voltage VCC 1 can have different values (e.g., values V 0 (e.g., 0 volts) and Vx) depending on the states of functional unit 111 ( FIG. 1A ).
- the lower power consumption state of functional unit 111 can occur between times T 0 and T 1
- the higher power consumption state of functional unit 111 can occur between times T 1 and T 3 .
- the lower power consumption state can include a sleep mode.
- the sleep mode can be part of the lower power consumption state or can be the entire lower power consumption state.
- functional unit 111 can be inactive (e.g., consume relatively low power (e.g., approximately 0 watts or close to 0 watts)).
- the higher power consumption state can include power-on mode (e.g., wakeup mode) between times T 1 and T 2 , and an active mode between times T 2 and T 3 .
- voltage VCC 1 can have a value V 0 (e.g., 0 volts). This means that power supply node 121 may be disconnected from power supply node 105 by power switching circuitry 131 to avoid leakage of power.
- functional unit 111 exits the lower power consumption state (e.g., exit the sleep mode) and enters the higher power consumption state (e.g., enters a power-on (or wakeup) mode).
- power switching circuitry 131 can operate to connect power supply node 121 ( FIG. 1A ) to power supply node 105 . As shown in FIG.
- the value of voltage VCC 1 can gradually change (increase) from value V 0 and reach value Vx (e.g., the value of voltage VCC IN ) at time T 2 .
- power switching circuitry 131 can operate to keep the value of voltage VCC 1 equal to (e.g., substantially equal to) the value of voltage VCC IN .
- Functional unit 111 may actively perform a function (e.g., perform at least one of sending data, receiving data, storing data in memory cells, reading data from memory cells, performing math operations, or other functions) between times T 2 and T 3 .
- Each of power switching circuitry 131 , 132 , and 133 of FIG. 1A can include any of the power switching circuitry described below with reference to FIG. 2A through FIG. 6 .
- FIG. 2A shows a schematic diagram of an IC 202 including power switching circuitry 231 , which can include transistors coupled in parallel between power supply nodes 205 and 221 , according to some embodiments described herein.
- IC 202 can correspond to IC 102 of FIG. 1A .
- Power switching circuitry 231 of IC 202 can correspond to any of power switching circuitry 131 , 132 , and 132 of FIG. 1A .
- FIG. 2A omits other components of IC 202 in order to not obscure the embodiments described herein.
- IC 202 can include power supply nodes 205 and 221 .
- Node 205 can receive voltage VCC IN (e.g., a voltage from a voltage regulator (not shown in FIG. 2A )).
- Power supply node 221 can provide a voltage VCC 1 , which can be used as a power supply voltage for functional unit 211 of IC 202 .
- Power switching circuitry 231 can include transistors (e.g., first stage transistors) P 1 0 , and P 1 1 through P 1 N coupled in parallel between power supply nodes 205 and 221 , and transistors (e.g., second stage transistors) P 2 0 through P 2 M coupled in parallel between power supply nodes 205 and 221 .
- the number of transistors P 1 0 , and P 1 1 through P 1 N can be different from the number of transistors P 2 0 through P 2 M (e.g., the value of index N can be different from the value of index M).
- FIG. 2A shows an example where each of transistors P 1 0 , and P 1 1 through P 1 N and P 2 0 through P 2 M is a p-channel metal-oxide semiconductor (PMOS) transistor. Other types of transistors can be used.
- PMOS metal-oxide semiconductor
- Power switching circuitry 231 can include a controller 207 that can include nodes (e.g., output nodes) 241 and 242 to provide signals (e.g., control signals) CTL P1 and CTL P2 , respectively. Each of signals CTL P1 and CTL P2 can be provided with different voltages at different times.
- controller 207 can include nodes (e.g., output nodes) 241 and 242 to provide signals (e.g., control signals) CTL P1 and CTL P2 , respectively.
- signals CTL P1 and CTL P2 can be provided with different voltages at different times.
- controller 207 can use the voltages provided to signal CTL P1 to control the switching of (e.g., to turn on or turn off) transistors P 1 0 , and P 1 1 through P 1 N , and the voltages provided to signal CTL P2 to control the switching of (e.g., to turn on or turn off) P 2 0 through P 2 M .
- controller 207 can use signals CTL P1 to turn off transistors P 1 0 , and P 1 1 through P 1 N , and signal CTL P2 to turn off transistors and P 2 0 through P 2 M in order avoid leakage of power. Controller 207 can use signals CTL P1 to turn on transistors P 1 0 , and P 1 1 through PIN, and signal CTL P2 to turn on transistors and P 2 0 through P 2 M when functional unit 211 exits the lower power consumption state (e.g., exits the sleep mode) and enters a higher power consumption state.
- the lower power consumption state e.g., a sleep mode
- controller 207 can cause signal CTL P1 to have a ramped voltage during a power-on (e.g., wakeup) mode of the higher power consumption state in order to gradually turn on transistors P 1 0 , and P 1 1 through PIN. After transistors P 1 0 , and P 1 1 through P 1 N are turned on (e.g., fully turned on), controller 207 can activate (e.g., cause a change in the voltage of) signal CTL P2 to turn on transistors and P 2 0 through P 2 M .
- a power-on e.g., wakeup
- transistors P 1 0 , and P 1 1 through P 1 N can be controlled by the same signal (e.g., signal CTL P1 ) at node 241 .
- Controller 207 can use signal CTL P1 to concurrent (e.g., simultaneously) turn on transistors P 1 0 , and P 1 1 through P 1 N .
- Transistors P 2 0 through P 2 M can be controlled by the same signal (e.g., signal CTL P2 ) at node 242 .
- transistors P 2 0 through P 2 M can be grouped in parallel transistor groups 251 , 252 , 253 , and 254 , such that transistors P 2 0 through P 2 M between different transistor groups can be concurrently turned on, but transistors P 2 0 through P 2 M within the same transistor group can be turned on in a sequential fashion (e.g., delayed fashion).
- transistor groups 251 , 252 , 253 , and 254 are shown in FIG. 2A as an example. However, the number of transistor groups can vary.
- power switching circuitry 231 can include buffers (e.g., drivers) 261 coupled in series with node 242 , buffers (e.g., drivers) 262 coupled in series with node 242 , buffers (e.g., drivers) 263 coupled in series with node 242 , and buffers (e.g., drivers) 264 coupled in series with node 242 .
- Buffers 261 , 262 , 263 , and 264 can be coupled to node 242 in a parallel fashion as shown in FIG. 2A .
- Each of buffers 261 , 262 , 263 , and 264 can include an output node coupled to a gate of a transistor among transistors P 2 0 through P 2 M of a respective transistor group 251 , 252 , 253 , or 254 .
- each of buffers 261 can include an output node coupled to a gate of one of transistors P 2 0 through P 2 M of a respective transistor group 251 .
- each of buffers 262 can include an output node coupled to a gate of one of transistors P 2 0 through P 2 M of a respective transistor group 252 .
- Each of buffers 261 , 262 , 263 , and 264 can include a complementary metal-oxide semiconductor (CMOS) buffer (e.g., CMOS driver) that can propagate a signal.
- CMOS complementary metal-oxide semiconductor
- Buffers 261 , 262 , 263 , and 264 can form parallel circuit paths (e.g., separate circuit paths) from node 242 to transistor groups 251 , 252 , 253 , and 254 .
- the parallel circuit paths formed by buffers 261 , 262 , 263 , and 264 can propagate signal CTL P2 in a parallel fashion from node 242 to gates of transistors P 2 0 through P 2 M of transistor groups 251 , 252 , 253 , and 254 .
- buffers 261 can form a circuit path to propagate signal CTL P2 from the node 242 to the gates of transistors P 2 0 through P 2 M of transistor groups 251 .
- Buffers 262 can form a circuit path to propagate signal CTL P2 from the node 242 to the gates of transistors P 2 0 through P 2 M of transistor groups 252 .
- buffers 263 and 264 can form separate circuit paths to propagate signal CTL P2 from the node 242 to the gates of transistors P 2 0 through P 2 M of transistor groups 253 and 254 , respectively.
- the connection of buffers 261 , 262 , 263 , and 264 and transistor groups 251 , 252 , 253 , and 254 as shown in FIG. 2A can form parallel chains (e.g., parallel daisy chains).
- Controller 207 can include a generator 272 , a code generator 274 , a generator 276 , and a circuit 278 .
- Generator 272 can include a ramped voltage generator that can generate different voltages, such as voltages V 1 , V 2 , V 3 , and V 4 , having different values.
- Code generator 274 can generate information CODE (which is digital information).
- Generator 276 can generate signal CTL P2 and provide it to node 242 .
- Circuit 278 can operate to allow controller 207 to further control the value of signal CTL P1 at node 241 during different modes (e.g., sleep mode and active mode) of functional unit 211 .
- Controller 207 can include a node (e.g., a clock node) to receive a clock signal CLK (e.g., a periodical signal).
- CLK e.g., a periodical signal
- Code generator 274 can generate information CODE that can have different values (e.g., different bit values) based on timing (e.g., based on the number of periods) of signal CLK. Controller 207 can use information CODE to cause generator 272 to provide signal CTL P1 with voltages V 1 , V 2 , V 3 , and V 4 at different time intervals, such that the slope of signal CTL P1 is a ramped signal having decreasing voltage values. This allows controller 207 to gradually turn on transistors P 1 0 , and P 1 1 through P 1 N (which have their gates coupled to node 241 which carries signal CTL P1 ).
- Generator 276 can generate signal CTL P2 that can have different values (e.g., different voltages) based on timing (e.g., based on the number of periods) of signal CLK.
- FIG. 2B are timing diagrams showing waveforms of signals CTL P1 CTL P2 , and voltage VCC 1 of FIG. 2A , according to some embodiments described herein.
- a time interval between times T i and T j can occur during a lower power consumption state (e.g., during a sleep mode) of functional unit 211 (FIG. 2 A).
- a time interval between times T j and T n can occur during a higher power consumption state (e.g., during a power-on state) of functional unit 211 .
- Code_Value A , Code_Value B , Code_Value C , and Code_Value D are the values of information CODE (generated by code generator 274 of FIG. 2A ) at times T j , T k , T l , and T m , respectively.
- Code_Value C , and Code_Value D can have a value based on values of a number of bits.
- Values Code_Value A , Code_Value B , Code_Value C , and Code_Value D are different values (e.g., different digital values).
- signal CTL P1 is a continuous signal having voltage values in a decreasing direction.
- the waveform of signal CTL p e is based on values Code_Value A , Code_Value B , Code_Value C , and Code_Value D of information CODE.
- Generator 272 FIG. 2A
- Generator 272 can use values Code_Value A , Code_Value B , Code_Value C , and Code_Value D of information CODE to provide voltages V 4 , V 3 , V 2 , and V 1 , respectively, at different time intervals.
- signal CTL P2 can remain relatively unchanged at value Vx between times T i and T n .
- signal CTL P2 can be changed from one level (e.g., level at voltage Vx) to another level (e.g., level at voltage V 0 (e.g., zero volts)).
- the interval between times T i and T n can be measured based on the periods (cycles) of clock signal CLK.
- the time interval between times T j and T n can be measured by a number of periods (cycles) of clock signal CLK (e.g., P periods, where P is an integer).
- Controller 207 can cause signal CTL P2 to change from one level to another level after P periods of clock signal CLK have lapsed from a reference time (e.g., time T j ).
- the value of P can be based on a time interval from time T j to a time (e.g., time T n ) at which transistors P 1 0 , and P 1 1 through P 1 N are fully turned on, or alternatively a time at which voltage VCC 1 reaches a value close to the value of voltage VCC IN (e.g., approximately 95% of the value of VCC IN ).
- FIG. 2B shows an example where controller 207 can cause signal CTL P2 to change from one level to another level at time T n .
- controller 207 can cause signal CTL P2 to change from one level to another level at another time (e.g., a time between times T m and T n ) at which transistors P 1 0 , and P 1 1 through P 1 N are fully turned on (or alternatively, a time at which voltage VCC 1 reaches a value close to (e.g., 95% of) the value of voltage VCC IN ).
- voltage VCC 1 can gradually increase from value V 0 to value Vx (e.g., the value of voltage VCC IN ) while signal CTL P1 decreases from a level at voltage V 4 to voltage V 1 .
- the decreasing voltages provided to signal CTL P1 allows controller 207 to provide different voltages to gates of transistors P 1 0 , and P 1 1 through P 1 N to concurrently turn on transistors P 1 0 , and P 1 1 through P 1 N in a gradual fashion.
- FIG. 2A shows an example where transistors P 1 0 , and P 1 1 through P 1 N are located at the same location (e.g., located adjacent to each other) in power switching circuitry 231 .
- transistors P 1 0 , and P 1 1 through P 1 N can be distributed at different locations in power switching circuitry 231 .
- one group of transistors P 1 0 , and P 1 1 through P 1 N can be located at one location (e.g., a first location) in power switching circuitry 231
- another group of transistors P 1 0 , and P 1 1 through P 1 N can be located at another location (e.g., a location not adjacent to the first location).
- the distributed groups of transistors P 1 0 , and P 1 1 through P 1 N can be controlled by the same signal (e.g., signal CTL P1 ) generated by the same generator (e.g., generator 272 ).
- the distributed groups of transistors P 1 0 , and P 1 1 through P 1 N can be controlled by different signals (e.g., similar to signal CTL P1 ) generated by different generators (e.g., similar to generator 272 ).
- Distributing transistors P 1 0 , and P 1 1 through P 1 N in different groups at different locations (non-adjacent locations) may reduce electro-migration in metal structures that are used to deliver the current (e.g., rush current) to power supply node 221 during a power-on (e.g., wakeup mode).
- a power-on e.g., wakeup mode
- FIG. 2A shows an example where transistor groups 251 , 252 , 253 , and 254 can be controlled by signal CTL P2 , such that transistors P 2 0 through P 2 M among transistor groups 251 , 252 , 253 , and 254 , can be turned on at the same time (e.g., transistors P 2 0 through P 2 M of transistor group 251 are turned at the same time as transistors P 2 0 through P 2 M of each of the other transistor groups 252 , 253 , and 254 are turned on).
- transistors P 2 0 through P 2 M of fewer than all of transistor groups 251 , 252 , 253 , and 254 can be turned on when (e.g., after) transistors P 1 0 , and P 1 1 through P 1 N are fully turned on.
- transistors P 2 0 through P 2 M of transistor groups 251 and 252 can be turned on (while transistors P 2 0 through P 2 M of transistor groups 253 and 254 are not turned on) when transistors P 1 0 , and P 1 1 through P 1 N are fully turned on. Then, transistors P 2 0 through P 2 M of transistor groups 253 and 254 can be turned on after transistors P 2 0 through P 2 M of transistor groups 251 and 252 are turned on.
- the structure of power switching circuitry 231 (where transistors P 2 0 through P 2 M among transistor groups 251 , 252 , 253 , and 254 can be turned on at the same time) can provide a relatively shorter time for the value of voltage VCC 1 to reach the value of voltage VCC IN .
- supply voltage noise at power supply node 205 may occur.
- the described alternative structure of power switching circuitry 231 (where transistors P 2 0 through P 2 M in fewer than all of transistor groups 251 , 252 , 253 , and 254 can be turned on at the same time) can suppress supply voltage noise at power supply node 205 .
- this may result in a relatively longer time for the value of voltage VCC 1 to reach the value of voltage VCC IN .
- transistors P 2 0 through P 2 M of either fewer than all of transistor groups 251 , 252 , 253 , and 254 , or all of transistor groups 251 , 252 , 253 , and 254 , can be turned on after transistors P 1 0 , and P 1 1 through P 1 N are fully turned on.
- a tradeoff can be made between supply voltage noise and the amount of time at which the value of voltage VCC 1 can reach the value of voltage VCC IN .
- An example of such a tradeoff may involve selecting a number of transistor groups 251 , 252 , 253 , and 254 to be turned on (after transistors P 1 0 , and P 1 1 through P 1 N are fully turned on) such that supply voltage noise from such a selected number of transistor groups results in an equal supply voltage noise that may occur when transistors P 1 0 , and P 1 1 through P 1 N are turned on.
- operations of power switching circuitry 231 can include two phases: a gradual turning on of transistors P 1 0 , and P 1 1 through P 1 N and then a turning on of transistors P 2 0 through P 2 m .
- the number of transistors P 1 0 , and P 1 1 through P 1 N can be relatively small (e.g., N can be about at least ten times less than M).
- the amount of current to flow between power supply nodes 205 and 221 may not affect (e.g., cause excessive heat on) the structure (e.g., Fin Field Effect Transistor (FinFET) structure) of transistors P 1 0 , and P 1 1 through P 1 N , thereby preventing damage to transistors P 1 0 , and P 1 1 through P 1 N (e.g., damage caused by excessive heat).
- Fin Field Effect Transistor (FinFET) structure Fin Field Effect Transistor
- FIG. 3 shows a schematic diagram of a portion of power switching circuitry 231 of FIG. 2A including a resistive network 372 , and a selector 373 , according to some embodiments described herein.
- Resistive network 372 and selector 373 can be part of generator 272 of FIG. 2A .
- selector 373 can be part of another component of power switching circuitry 231 of FIG. 2A .
- resistive network 372 can include resistors R coupled in series between power supply node 205 and ground (e.g., a ground node).
- the value of resistors R can be the same.
- resistors R can have the same unit resistor value.
- Resistors R of resistive network 372 can form a resistor ladder (R-ladder) voltage divider that can generate voltages V 1 , V 2 , V 3 , and V 4 having different values between ground and the value of voltage VCC IN .
- the values of voltages V 4 , V 3 , V 2 , and V 1 can be decreased in a sequential order.
- the value of voltage V 4 is greater than the value of voltage V 3 ;
- the value of voltage V 3 is greater than the value of voltage V 2 ;
- the value of voltage V 2 is greater than the value of voltage V 1 .
- the value of voltage V 1 can be greater than zero.
- resistors R can have the same unit resistor value.
- global PVT variations affect the unit resistors in the R-ladder equally.
- the R-ladder voltage divider of resistive network 372 can be insensitive to global PVT. Therefore, a relatively constant ramped voltage at node 241 (which is based on voltages V 4 , V 3 , V 2 , and V 1 ) may be achieved.
- a constant ramped voltage helps improve the gradual turning on of transistors P 1 0 , and P 1 1 through P 1 N during a power-on (e.g., wakeup) mode. This can lead to robust, well controlled wake current profiles (e.g., power-on mode current profiles) across PVT corners.
- selector 373 can include input nodes (e.g., input nodes 1, 2, 3, and 4) coupled to respective nodes (e.g., voltage output nodes) of resistive network 372 that provide voltages V 1 , V 2 , V 3 , and V 4 , respectively.
- Selector 373 can include an output node coupled to node 241 , and nodes (e.g., control nodes) 373 c to receive information CODE.
- Nodes 373 c can include separate nodes (e.g., separate lines) to receive (e.g., receive in parallel) respective bits of information CODE.
- selector 373 can select voltages V 1 , V 2 , V 3 , and V 4 (generated by resistive network 372 ) and provide the selected voltage to node 241 .
- Selector 373 can select voltages V 1 , V 2 , V 3 , and V 4 in a decreasing order from high to low (e.g., voltages V 4 , V 3 , V 2 , and V 1 ), such that signal CTL P1 can provide voltages from a higher value to a lower value (e.g., based on the values of voltages V 4 , V 3 , V 2 , and V 1 ).
- resistive network 372 and selector 373 can form a digital-to-analog converter (DAC) to provide analog voltages (e.g., voltages V 1 , V 2 , V 3 , and V 4 ) to node 241 in the form of signal CTL P1 based on the value (digital value) of information CODE.
- DAC digital-to-analog converter
- selector 373 can select voltage V 4 and provide it to node 241 if the value of information CODE is value Code_Value A ( FIG. 2B ); selector 373 can select voltage V 3 and provide it to node 241 if the value of information CODE is value Code_Value B ; selector 373 can select voltage V 2 and provide it to node 241 if the value of information CODE is value Code_Value C ( FIG. 2B ); and selector 373 can select voltage V 1 and provide it to node 241 if the value of information CODE is value Code_Value D .
- the R-ladder-based voltage divider of resistive network 372 is used with selector 373 to form a resistive DAC (as shown in FIG. 3 ) as an example.
- Other DAC topology e.g., switched-capacitor DAC and current-based DAC can be used.
- power switching circuitry 231 may use signals SLEEP* and BYPASS to control transistors P 1 0 , and P 1 2 through P 1 N (in addition to signal CTL P1 ) depending on the states of functional unit 211 ( FIG. 2A ).
- signal BYPASS can have a level (e.g., “low” or zero volts) to turn off transistor N 3 . This can disconnect node 241 from ground.
- signal SLEEP* can have a level (e.g., “low” or zero volts) to turn on transistor P 3 . This can connect node 241 to power supply node 205 (through transistor P 3 ) to turn off transistors P 1 0 , and P 1 2 through P 1 N in order to avoid leakage of power.
- signal SLEEP* can have a level (e.g., “high” or 1V for example) to turn off transistor P 3 . This can disconnect node 241 from power supply node 205 ( FIG. 3 ).
- signal BYPASS can have a level (e.g., “low” or zero volts) to keep transistor N 3 turned off.
- node 241 is provided with voltages V 1 , V 2 , V 3 , and V 4 to gradually turn on transistors P 1 0 , and P 1 2 through PIN.
- signal CTL P1 can be deactivated, such that selector 373 may not provide voltages to signal CTL P1 .
- signal BYPASS can have a level (e.g., “high”) to turn on transistor N 3 . This can connect node 241 to ground in order to cause transistors P 1 0 , and P 1 2 through P 1 N to fully turn on.
- transistors P 1 0 , and P 1 2 through P 1 N can be concurrently (e.g., simultaneously) and gradually turned on using the DAC technique that applies a ramped voltage (e.g., voltages V 4 , V 3 , V 2 , and V 1 ) to the gates of transistors P 1 0 , and P 1 2 through P N based on digital values of information CODE.
- a ramped voltage e.g., voltages V 4 , V 3 , V 2 , and V 1
- concurrently and gradually turn on transistors P 1 0 , and P 1 2 through P 1 N can help avoid some drawbacks mentioned above, such as the relatively high rush current peaks, the voltage droops of the waveform of voltage VCC IN , and the supply voltage noise in neighboring components. Further, as described above, concurrently and gradually turning on transistors P 1 0 , and P 1 2 through P 1 N can also help avoid excessive heat on the structure (e.g., FinFET structure) of transistors P 1 0 , and P 1 2 through P 1 N , thereby preventing damage to transistors P 1 0 , and P 1 2 through P 1 N (e.g., damage caused by avoid excessive heat).
- structure e.g., FinFET structure
- information CODE can be programmable post-manufacturing (e.g., post-silicon). This may avoid calibration (e.g., post-silicon trimming) of components associated with power switching circuitry 231 of IC 202 .
- power switching circuitry 231 ( FIG. 2A through FIG. 3 ) can be individually structured and configured to operate in ways to fit operation of a particular functional unit during the power-on mode of that particular functional unit.
- different power switching circuitry can have different structures based on operations of respective functional units coupled to the different power switching circuitry.
- power switching circuitry 231 can be structured and configured to operate in ways based on different power domain sizes (e.g., different sizes of functional unit 211 in FIG. 2A or functional units 111 , 112 , 113 in FIG. 1A ).
- FIG. 4A shows a schematic diagram of resistive network 372 and selector 373 of FIG. 3A including transmission gates, according to some embodiments described herein.
- resistive network 372 can include transmission gates TG 0 through TG 4 coupled in series between power supply nodes 205 and ground.
- Each of transmission gates TG 0 through TG 4 can include two transistors (e.g., p-channel and n-channel transistors) coupled as shown in FIG. 4A .
- Voltages V 1 , V 2 , V 3 , and V 4 can be generated at respective nodes at transmission gates TG 0 through TG 4 .
- each of transmission gates TG 1 through TG 3 can be controlled by ground potential (e.g., zero volts) and a voltage V, such that transmission gates TG 1 through TG 3 can be normally turned on (e.g., turned on during operation of power switching circuitry 231 ( FIG. 2A )).
- Transmission gate TG 0 can be coupled to an inverter INV 0 and controlled by a signal SLEEP*. Transmission gate TG 0 can be turned on when signal SLEEP* has one level (e.g., “high”) and turned off on when signal SLEEP* has another level (e.g., “low”).
- Transmission gate TG 4 can be coupled to an inverter INV 4 and controlled by a signal BYPASS* (which can be a complement of signal BYPASS). Transmission gate TG 4 can be turned on when signal BYPASS* has one level (e.g., “high”) and turned off when signal BYPASS* has another level (e.g., “low”).
- BYPASS* which can be a complement of signal BYPASS.
- signal SLEEP* can have a level (e.g., “low”) to turn off transmission gate TG 0 . This can prevent static current from flowing (e.g., flowing between power supply nodes 205 and ground) in resistive network 372 .
- each of signals SLEEP* and BYPASS can have a level to turn on respective transmission gates TG 0 and TG 4 . This allows a current path to form between power supply nodes 205 and ground in order to generate voltages V 1 , V 2 , V 3 , and V 4 in resistive network 372 .
- Selector 373 can include transmission gates TG 11 through TG 14 and inverters INV 11 through INV 14 .
- the gates of transmission gates TG 11 through TG 14 can be respectively coupled to nodes 373 c , which receive information CODE. Based on the value of information CODE, selector 373 can turn on one of transmission gates TG 11 through TG 14 while the other transmission gates among transmission gates TG 11 through TG 14 are turned off.
- Selector 373 can select voltages V 1 , V 2 , V 3 , and V 4 (generated by resistive network 372 ) and provide the selected voltage to node 241 through one of transmission gates TG 11 through TG 14 that is turned on.
- information CODE can include bits B 1 , B 2 , B 3 , and B 4 that can be received in parallel at nodes 373 c .
- the value (binary value) of the combination of bits B 1 , B 2 , B 3 , and B 4 represents the value of one of values Code_Value A , Code_Value B , Code_Value C , and Code_Value D .
- Each value of the combination of bits B 1 , B 2 , B 3 , and B 4 can cause selector 373 to select a different voltage among voltages V 1 , V 2 , V 3 , and V 4 to be provided to node 241 .
- FIG. 4B is a chart showing the relationships among the values of information CODE and the voltages provided to node 241 in FIG. 4A , according to some embodiments described herein.
- values Code_Value A , Code_Value B , Code_Value C , and Code_Value D can be “0001”, “0010”, “0100”, and “1000”, respectively. These values can be used to select respective voltages V 4 , V 3 , V 2 , and V 1 (in a decreasing order), such that transistors P 1 0 , and P 1 2 through P 1 N can be gradually turned on.
- FIG. 4A shows resistive network 372 including transmission gates as an example.
- Other structures can be used.
- n-well resistors may be used as resistors in resistive network 372 .
- Using area-efficient transmission gates in resistive network 372 and selector 373 can save area in power switching circuitry 231 and can reduce costs associated with generating and providing voltages V 1 , V 2 , V 3 , and V 4 to node 241 .
- FIG. 5 shows an apparatus in the form of a system (e.g., electronic system) 500 , according to some embodiments described herein.
- System 500 can include or be included in a computer, a tablet, or other electronic systems.
- system 500 can include components such as a battery 503 , a processor 515 , a memory device 520 , a memory controller 530 , a graphics controller 540 , an input and output (I/O) controller 550 , a display 552 , a keyboard 554 , a pointing device 556 , at least one antenna 558 , a connector 559 , and a bus 560 .
- Bus 560 can include conductive lines (e.g., metal-based traces on a circuit board where the components of system 500 are located).
- system 500 does not have to include a display.
- display 552 can be omitted from system 500 .
- system 500 does not have to include any antenna.
- antenna 558 can be omitted from system 500 .
- Battery 503 can provide power to the components of system 500 , e.g., through a power delivery path 516 .
- Such components can include a processor 515 , a memory device 520 , a memory controller 530 , a graphics controller 540 , and input/output (I/O) controller 550 .
- Processor 515 can include a general-purpose processor or an application specific integrated circuit (ASIC). Processor 515 can include a CPU.
- ASIC application specific integrated circuit
- Memory device 520 can include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, a combination of these memory devices, or other types of memory.
- DRAM dynamic random access memory
- SRAM static random access memory
- FIG. 5 shows an example where memory device 520 is a stand-alone memory device separated from processor 515 .
- memory device 520 and processor 515 can be located on the same die.
- memory device 520 is an embedded memory in processor 515 , such as embedded DRAM (eDRAM), embedded SRAM (eSRAM), embedded flash memory, or another type of embedded memory.
- Display 552 can include a liquid crystal display (LCD), a touchscreen (e.g., capacitive or resistive touchscreen), or another type of display.
- Pointing device 556 can include a mouse, a stylus, or another type of pointing device.
- I/O controller 550 can include a communication module for wired or wireless communication (e.g., communication through one or more antennas 558 ). Such wireless communication may include communication in accordance with WiFi communication technique, Long Term Evolution Advanced (LTEA) communication technique, or other communication techniques.
- LTEA Long Term Evolution Advanced
- I/O controller 550 can also include a module to allow system 500 to communicate with other devices or systems in accordance with one or more standards or specifications (e.g., I/O standards or specifications), including Universal Serial Bus (USB), DisplayPort (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), Ethernet, and other specifications.
- I/O standards or specifications including Universal Serial Bus (USB), DisplayPort (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), Ethernet, and other specifications.
- USB Universal Serial Bus
- DP DisplayPort
- HDMI High-Definition Multimedia Interface
- Thunderbolt Thunderbolt
- PCIe Peripheral Component Interconnect Express
- Connector 559 can be structured (e.g., can include terminals, such as pins) to allow system 500 to be coupled to an external device (or system). This may allow system 500 to communicate (e.g., exchange information) with such a device (or system) through connector 559 .
- Connector 559 and at least a portion of bus 560 can include conductive lines that conform with at least one of USB, DP, HDMI, Thunderbolt, PCIe, Ethernet, and other specifications.
- each of processor 515 , memory device 520 , memory controller 530 , graphics controller 540 , and I/O controller 550 can include a functional unit 511 and power switching circuitry 531 .
- Functional unit 511 and power switching circuitry 531 can include any of the functional units and power switching circuitry described above with reference to FIG. 1A through FIG. 4B .
- system 500 can include voltage regulators 505 , each of which can include an input node coupled to power delivery path 516 to provide voltage VCC IN (e.g., un-gated VCC IN voltage) based on power from battery 503 .
- Some of the voltage regulators 505 can be on-die voltage regulator or off-die voltage regulators.
- processor 515 , graphics controller 540 , and I/O controller 550 can include an on-die voltage regulator 505 , and voltage regulators 505 providing voltages VCC IN to memory device 520 and memory controller 530 can be off-die voltage regulators 505 .
- FIG. 5 shows an example where each of processor 515 , graphics controller 540 , and I/O controller 550 includes an on-die voltage regulator 505 .
- processor 515 , graphics controller 540 , and I/O controller 550 may not include an on-die voltage regulator 505 .
- FIG. 5 shows the components of system 500 arranged separately from each other as an example.
- each of processor 515 , memory device 520 , memory controller 530 , graphics controller 540 , and I/O controller 550 can be located on a separate IC (e.g., semiconductor die or an IC chip).
- two or more components e.g., processor 515 , memory device 520 , graphics controller 540 , and I/O controller 550
- system 500 can be located on the same die (e.g., same IC chip) that forms a system-on-chip (SoC) or located on the same IC package that forms a system-on-package (SoP) or system-in-package (SiP).
- SoC system-on-chip
- SoP system-on-package
- SiP system-in-package
- FIG. 6 is a flowchart showing a method 600 of operating an apparatus, according to some embodiments described herein.
- the apparatus used in method 600 can include any of the apparatuses (e.g., apparatus 100 and system 500 including power switching circuitry 131 , 231 , and 531 ) described above with reference to FIG. 1A through FIG. 5 .
- Some of the activities in method 600 may be performed by hardware, software, firmware, or any combination of hardware, software, and firmware.
- activity 610 of method 600 can include providing first, second, and third digital information to a controller located on an IC die.
- the controller coupled to transistors can be located on the integrated circuit die.
- the transistors can be coupled in parallel between a first power supply node and a second power supply node.
- Activity 620 of method 600 can include applying a first voltage to gates of the transistors based on the first digital information.
- Activity 630 of method 600 can include applying a second voltage to gates of the transistors based on the second digital information.
- Activity 640 of method 600 can include applying a third voltage to gates of the transistors based on the third digital information.
- Method 600 can include fewer or more activities relative to activities 610 , 620 , 630 , and 640 shown in FIG. 6 .
- method 600 can include activities and operations of any of the apparatuses (e.g., apparatus 100 and system 500 including power switching circuitry 131 , 231 , and 531 ) described above with reference to FIG. 1A through FIG. 5 .
- apparatuses e.g., apparatus 100 and system 500 including power switching circuitry 131 , 231 , and 531
- methods e.g., method 600 and operations of apparatus 100 and system 500 including operations of power switching circuitry 131 , 231 , and 531
- apparatuses e.g., apparatus 100 and system 500 including power switching circuitry 131 , 231 , and 531
- methods e.g., method 600 and operations of apparatus 100 and system 500 including operations of power switching circuitry 131 , 231 , and 531
- the apparatuses and methods described above can include or be included in high-speed computers, communication and signal processing circuitry, single-processor modules or multi-processor modules, single embedded processors or multiple embedded processors, multi-core processors, message information switches, and application-specific modules including multilayer or multi-chip modules.
- Such apparatuses may further be included as sub-components within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, etc.), tablets (e.g., tablet computers), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set top boxes, and others.
- other apparatuses e.g., electronic systems
- televisions e.g., cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, etc.), tablets (e.g., tablet computers), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set top
- Example 1 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information, the first, second, and third voltages having different values based on values of the digital information.
- subject matter such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information, the first, second, and third voltages having different values based on values of the digital information.
- Example 2 the subject matter of Example 1 may optionally include, further comprising first additional transistors coupled in parallel between the first and second power supply nodes, and first buffers coupled in series with an output of the controller, each of the first buffers including an output node coupled to a gate of one of the first additional transistors.
- Example 3 the subject matter of Example 2 may optionally include, further comprising second additional transistors coupled in parallel between the first and second power supply nodes, and second buffers coupled in series with the output of the controller in parallel with the first buffers, each of the second buffers including an output node coupled to a gate of one of the second additional transistors.
- Example 4 the subject matter of any of Examples 1-3 may optionally include, wherein the controller includes a generator to generate the first, second, and third voltages, and a selector to receive the digital information and select the first, second, and third voltages provided to the gates of the transistors based on different values of the digital information.
- the controller includes a generator to generate the first, second, and third voltages, and a selector to receive the digital information and select the first, second, and third voltages provided to the gates of the transistors based on different values of the digital information.
- Example 5 the subject matter of any of Examples 1-3 may optionally include, wherein the controller includes a resistive network coupled to the first power supply node and a ground node, the resistive network including a first node to provide the first voltage, a second node to provide the second voltage, and a third node to provide the third voltage.
- the controller includes a resistive network coupled to the first power supply node and a ground node, the resistive network including a first node to provide the first voltage, a second node to provide the second voltage, and a third node to provide the third voltage.
- Example 6 the subject matter of Example 5 may optionally include, wherein the controller includes a selector including input nodes coupled to respective first, second, and third nodes of the resistive network, an output node coupled to the gates of the transistors, and nodes to receive bits of the digital information.
- the controller includes a selector including input nodes coupled to respective first, second, and third nodes of the resistive network, an output node coupled to the gates of the transistors, and nodes to receive bits of the digital information.
- Example 7 the subject matter of Example 6 may optionally include, wherein the selector includes first, second, and third transmission gates coupled to the first, second, and third nodes, respectively, of the resistive network.
- Example 8 the subject matter of Example 1 may optionally include, wherein the second power supply node is coupled to a functional unit, and the controller is to provide the first, second, and third voltages to the gates of the transistors when the functional unit changes from a first power consumption state to a second power consumption state.
- Example 9 the subject matter of Example 8 may optionally include, wherein the transistors are to turn off during the first power consumption state and to turn on in the second power consumption state.
- Example 10 the subject matter of Example 8 may optionally include, wherein the first power consumption state includes a sleep mode of the functional unit.
- Example 11 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including an integrated circuit die, a voltage regulator located on the integrated circuit die and coupled to a first power supply node, and power switching circuitry located on the integrated circuit die and coupled to the first power supply node and a second power supply node, the power switching circuitry including transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information, the first, second, and third voltages having different values based on values of the digital information.
- subject matter such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including an integrated circuit die, a voltage regulator located on the integrated circuit die and coupled to a first power supply node, and power switching circuitry located on the integrated circuit die and coupled to the first power supply node and a second power supply node, the
- Example 12 the subject matter of Example 11 may optionally include, further comprising first additional transistors coupled in parallel between the first and second power supply nodes, and a first circuit path coupled to a node of the controller to propagate a signal from the node of the controller to gates of the first additional transistors.
- Example 13 the subject matter of Example 12 may optionally include, further comprising second additional transistors coupled in parallel between the first and second power supply nodes, and a second circuit path different from the first circuit path, the second circuit path coupled to the node of the controller to propagate the signal from the node of the controller to gates of the second additional transistors.
- Example 14 the subject matter of Example 13 may optionally include, wherein each of the first and second circuit paths includes buffers coupled in series.
- Example 15 the subject matter of any of Examples 11-14 may optionally include, wherein the controller is to provide a first digital value of the digital information, a second digital value of the digital information, and third digital value of the digital information, and the values of the first, second, and third voltages are based on respective first, second, and third values of the digital information.
- Example 16 the subject matter of any of Examples 11-14 may optionally include, wherein the second power supply node is coupled to a functional unit, and the controller is to provide the first, second, and third voltages to the gates of the transistors when the functional unit changes from a lower power consumption state to a higher power consumption state.
- Example 17 the subject matter of any of Examples 11-14 may optionally include, further comprising a power delivery path to couple to a battery, wherein the voltage regulator includes an input node coupled to the power delivery path.
- Example 18 the subject matter of any of Examples 11-14 may optionally include, wherein the integrated circuit die includes a processor.
- Example 19 the subject matter of any of Examples 11-14 may optionally include, further comprising an antenna coupled to the integrated circuit die.
- Example 20 includes subject matter (such as a method of operating a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including providing first, second, and third digital information to a controller located on an integrated circuit die, the controller coupled to transistors located on the integrated circuit die, the transistors coupled in parallel between a first power supply node and a second power supply node, applying a first voltage to gates of the transistors based on the first digital information, applying a second voltage to the gates of the transistors based on the second digital information, and applying a third voltage to the gates of the transistors based on the third digital information.
- a controller located on an integrated circuit die
- the controller coupled to transistors located on the integrated circuit die, the transistors coupled in parallel between a first power supply node and a second power supply node, applying a first voltage to gates of the transistors based on the first digital information, applying a second voltage to the gates of the transistors based on the second digital information, and applying a third voltage to the gates of
- Example 21 the subject matter of Example 20 may optionally include, wherein the first voltage has a first value, the second voltage has a second value, the third voltage has a third value, the first value is greater than the second value, and the second value is greater than the third value.
- Example 22 the subject matter of Example 21 may optionally include, wherein the first voltage is applied to the gates of the transistors before the second voltage is applied to the gates of the transistors, and the second voltage is applied to the gates of the transistors before the third voltage is applied to the gates of the transistors.
- Example 23 the subject matter of Example 20 may optionally include, further comprising selecting the first voltage from a resistive ladder network based on the first digital information, selecting the second voltage from the resistive ladder network based on the second digital information, and selecting the third voltage from the resistive ladder network based on the third digital information.
- Example 24 the subject matter of Example 20 may optionally include, further comprising applying a fourth voltage to gates of additional transistors coupled in parallel between the first and second power supply nodes.
- Example 25 the subject matter of Example 20 may optionally include, wherein the second power supply node is coupled to a functional unit, and the first, second, and third voltages are applied to the gates of the transistors during a time interval when the functional unit changes from a lower power consumption state to a higher power consumption state.
- Example 26 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or machine) including means for performing any of the methods of claims 20 - 25 .
- Example 1 through Example 26 may be combined in any combination.
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Abstract
Description
- Embodiments described herein pertain to supply power in integrated circuits. Some embodiments relate to control of supply power in integrated circuits in different modes.
- Many electronic systems (e.g., computers and cellular phones) have operations that disconnect supply power from a particular part of a device in the system during some modes (e.g., an inactive mode) of the device to save power. Such electronic systems also have reconnection operations to reconnect power supply to that particular part of the device in another mode (e.g., an active mode) of the device. In some conventional systems, designing components (e.g., circuitry) to perform such reconnection operations with minimal side effects may pose a challenge.
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FIG. 1A shows an apparatus including an integrated circuit (IC) having power switching circuitry and functional units, according to some embodiments described herein. -
FIG. 1B is a timing diagram showing example waveforms of some of the voltages of the IC ofFIG. 1A during different states of a functional unit of the IC, according to some embodiments described herein. -
FIG. 2A shows a schematic diagram of an IC including power switching circuitry that includes transistors coupled in parallel between power supply nodes, according to some embodiments described herein. -
FIG. 2B shows timing diagrams showing waveforms of some signals of the power switching circuitry ofFIG. 2A , according to some embodiments described herein. -
FIG. 3 shows a schematic diagram of a portion of the power switching circuitry ofFIG. 2A including a resistive network and a selector, according to some embodiments described herein. -
FIG. 4A shows a schematic diagram of the resistive network and the selector ofFIG. 3 including transmission gates, according to some embodiments described herein. -
FIG. 4B is a chart showing relationships between the values of digital information provided to the selector ofFIG. 4A and corresponding values of voltages provided to gates of the transistors of the power switching circuitry ofFIG. 2A , according to some embodiments described herein. -
FIG. 5 shows an apparatus in the form of a system (e.g., electronic system), according to some embodiments described herein. -
FIG. 6 is a flowchart showing a method of operating an apparatus, according to some embodiments described herein. - The techniques described herein include an IC having a functional unit and a power switching circuitry to control delivery of power to the functional unit in different operating states of the functional unit. The techniques described herein include many improvements over some conventional techniques that involve control of supply power in electronic devices and systems. For example, some of the information (e.g., digital codes) used during part of the operations of the described power switching circuitry can be programmable (e.g., post-silicon programming). This avoids calibration (e.g., post-silicon trimming) of components associated with the power switching circuitry. The structures and operations of components (e.g., power switching circuitry) used in the described techniques can help reduce or avoid excessive heat that may occur at some part (e.g., transistors) of the components. The described techniques can help reduce voltage droops and noise in supply voltages, and reduce electro-migration in metal structures that are used to deliver current to some power supply nodes of the IC. The described techniques can make some relationships of the components (e.g., resistor ratios) of the described power switching circuitry insensitive to process-voltage-temperature (PVT) variations. This may improve current profiles in some operational modes of the described power switching circuitry. Other improvements are described below.
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FIG. 1A shows anapparatus 100 including anIC 102 havingpower switching circuitry functional units Apparatus 100 can include or be included in an electronic device or system. Examples of such devices or systems include computers (e.g., servers, desktops, laptops, and notebooks), tablets, cellular phones, wearable electronic things, and other electronic devices or systems. - IC 102 can include an IC die (e.g., semiconductor (e.g., silicon) die (e.g., a chip)) where components of IC 102 are located. Examples of IC 102 include a general purpose processor (e.g., a microprocessor), a graphics processor, a microcontroller, an application-specific integrated circuit (ASIC), a system-on-chip (SoC), and other electronic devices or systems.
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Functional units FIG. 1A shows IC 102 including threefunctional units - As shown in
FIG. 1A ,apparatus 100 can include apower supply node 105 to receive a voltage VCCIN (e.g., un-gated power supply voltage) andpower supply nodes Power supply node 105 can be part of a supply power rail (e.g., un-gated VCC power rail) ofapparatus 100 that can receive supply power from a battery (not shown) through a power path coupled to the battery (not shown inFIG. 1A ). Such a power path may include a voltage regulator, which can receive power from the battery and generate a regulated voltage (e.g., voltage VCCIN). Thus, inFIG. 1A , voltage VCCIN can be a regulated supply voltage (e.g., provided at an output of a voltage regulator). The voltage regular (not shown inFIG. 1A ) can be an off-die (e.g., off-chip) voltage regulator located outsideIC 102 or on-die (e.g., on-chip) voltage regulator located onIC 102. - In
FIG. 1A ,power supply nodes IC 102 to provide respective voltages VCC1, VCC2, and VCC3 tofunctional units -
Power switching circuitry power supply node 105 topower supply nodes Power switching circuitry power switching circuitry FIG. 1A ) coupled betweenpower supply nodes 105 and a respective power supply node amongpower supply nodes Power switching circuitry power supply node 105 tonodes - Information CODE1, CODE2, and CODE3 can be provided to IC 102 (e.g., by programming) during the manufacture of
IC 102 beforeIC 102 is included in an IC package or in an electronic device or system (e.g., apparatus 100), or beforeIC 102 is shipped to a user (e.g., customer). In another example, information CODE can be provided toIC 102 after manufacturing (post-manufacturing) of IC 102 (e.g. afterIC 102 is included in an IC package or in an electronic device or system (e.g., apparatus 100) or afterIC 102 is shipped to a user (e.g., customer)). - As shown in
FIG. 1A ,IC 102 can include lines (conductive lines) 104, which can be conductive nodes withinIC 102 or pins (or solder balls) on a package whereIC 102 is located. Other devices external toIC 102 can communicate withIC 102 throughlines 104. Information CODE1, CODE2, and CODE3 can be provided toIC 102 through lines 104 (e.g., by programming or by other techniques).IC 102 may store (e.g., store in internal memory of IC 102) the values of information CODE1, CODE2, and CODE3. During their operations,power switching circuitry - Each of
functional units -
Functional units IC 102. Thus, in order to avoid leakage of power,power supply node 105 can be disconnected frompower supply node functional unit 111 enters a lower power consumption state,power switching circuitry 131 can disconnectpower supply node 121 frompower supply node 105 to avoid leakage of power.Power switching circuitry 131 can connectpower supply node 121 to power supply node 105 (e.g., during a power-on mode) whenfunctional unit 111 exits the lower power consumption state (e.g., changes from the lower power consumption state to the higher power consumption state).Power switching circuitry 131 can use information CODE1 during part of its operation (e.g., during a power-on mode) when it connectspower supply node 121 topower supply node 105. -
FIG. 1B is a timing diagram showing example waveforms of voltages VCCIN and VCC1 ofFIG. 1A during different states offunctional unit 111 ofIC 102, according to some embodiments described herein.FIG. 1B shows example waveform of voltage VCC1. However, waveforms of voltages VCC2 and VCC3 during lower and higher power consumption states of each offunctional units FIG. 1B . - The following description refers to
FIG. 1A andFIG. 1B . As shown inFIG. 1B , voltage VCCIN can have a value (e.g., value Vx) that is relatively unchanged (e.g., constant) between times T0 and T3. Voltage VCC1 can have different values (e.g., values V0 (e.g., 0 volts) and Vx) depending on the states of functional unit 111 (FIG. 1A ). As shown inFIG. 1B , the lower power consumption state offunctional unit 111 can occur between times T0 and T1, and the higher power consumption state offunctional unit 111 can occur between times T1 and T3. The lower power consumption state can include a sleep mode. The sleep mode can be part of the lower power consumption state or can be the entire lower power consumption state. Between times T0 and T1,functional unit 111 can be inactive (e.g., consume relatively low power (e.g., approximately 0 watts or close to 0 watts)). The higher power consumption state can include power-on mode (e.g., wakeup mode) between times T1 and T2, and an active mode between times T2 and T3. - Between times T0 and T1 (e.g., sleep mode), voltage VCC1 can have a value V0 (e.g., 0 volts). This means that
power supply node 121 may be disconnected frompower supply node 105 bypower switching circuitry 131 to avoid leakage of power. At time T1,functional unit 111 exits the lower power consumption state (e.g., exit the sleep mode) and enters the higher power consumption state (e.g., enters a power-on (or wakeup) mode). In response tofunctional unit 111 entering the higher power consumption state at time T1,power switching circuitry 131 can operate to connect power supply node 121 (FIG. 1A ) topower supply node 105. As shown inFIG. 1B , as a result ofpower switching circuitry 131 connectingpower supply node 121 topower supply node 105, the value of voltage VCC1 can gradually change (increase) from value V0 and reach value Vx (e.g., the value of voltage VCCIN) at time T2. - Between times T2 and T3 (e.g., active mode),
power switching circuitry 131 can operate to keep the value of voltage VCC1 equal to (e.g., substantially equal to) the value of voltage VCCIN.Functional unit 111 may actively perform a function (e.g., perform at least one of sending data, receiving data, storing data in memory cells, reading data from memory cells, performing math operations, or other functions) between times T2 and T3. - Each of
power switching circuitry FIG. 1A can include any of the power switching circuitry described below with reference toFIG. 2A throughFIG. 6 . -
FIG. 2A shows a schematic diagram of anIC 202 includingpower switching circuitry 231, which can include transistors coupled in parallel betweenpower supply nodes IC 202 can correspond toIC 102 ofFIG. 1A .Power switching circuitry 231 ofIC 202 can correspond to any ofpower switching circuitry FIG. 1A .FIG. 2A omits other components ofIC 202 in order to not obscure the embodiments described herein. - As shown in
FIG. 2A ,IC 202 can includepower supply nodes Node 205 can receive voltage VCCIN (e.g., a voltage from a voltage regulator (not shown inFIG. 2A )).Power supply node 221 can provide a voltage VCC1, which can be used as a power supply voltage forfunctional unit 211 ofIC 202. -
Power switching circuitry 231 can include transistors (e.g., first stage transistors) P1 0, and P1 1 through P1 N coupled in parallel betweenpower supply nodes power supply nodes FIG. 2A shows an example where each of transistors P1 0, and P1 1 through P1 N and P2 0 through P2 M is a p-channel metal-oxide semiconductor (PMOS) transistor. Other types of transistors can be used. -
Power switching circuitry 231 can include acontroller 207 that can include nodes (e.g., output nodes) 241 and 242 to provide signals (e.g., control signals) CTLP1 and CTLP2, respectively. Each of signals CTLP1 and CTLP2 can be provided with different voltages at different times. Based on a state (e.g., lower or higher power consumption state) offunctional unit 211,controller 207 can use the voltages provided to signal CTLP1 to control the switching of (e.g., to turn on or turn off) transistors P1 0, and P1 1 through P1 N, and the voltages provided to signal CTLP2 to control the switching of (e.g., to turn on or turn off) P2 0 through P2 M. - During a lower power consumption state (e.g., a sleep mode) of
functional unit 211,controller 207 can use signals CTLP1 to turn off transistors P1 0, and P1 1 through P1 N, and signal CTLP2 to turn off transistors and P2 0 through P2 M in order avoid leakage of power.Controller 207 can use signals CTLP1 to turn on transistors P1 0, and P1 1 through PIN, and signal CTLP2 to turn on transistors and P2 0 through P2 M whenfunctional unit 211 exits the lower power consumption state (e.g., exits the sleep mode) and enters a higher power consumption state. As described in more detail below,controller 207 can cause signal CTLP1 to have a ramped voltage during a power-on (e.g., wakeup) mode of the higher power consumption state in order to gradually turn on transistors P1 0, and P1 1 through PIN. After transistors P1 0, and P1 1 through P1 N are turned on (e.g., fully turned on),controller 207 can activate (e.g., cause a change in the voltage of) signal CTLP2 to turn on transistors and P2 0 through P2 M. - As shown in
FIG. 2A , transistors P1 0, and P1 1 through P1 N can be controlled by the same signal (e.g., signal CTLP1) atnode 241.Controller 207 can use signal CTLP1 to concurrent (e.g., simultaneously) turn on transistors P1 0, and P1 1 through P1 N. Transistors P2 0 through P2 M can be controlled by the same signal (e.g., signal CTLP2) atnode 242. However, transistors P2 0 through P2 M can be grouped inparallel transistor groups transistor groups FIG. 2A as an example. However, the number of transistor groups can vary. - As shown in
FIG. 2A ,power switching circuitry 231 can include buffers (e.g., drivers) 261 coupled in series withnode 242, buffers (e.g., drivers) 262 coupled in series withnode 242, buffers (e.g., drivers) 263 coupled in series withnode 242, and buffers (e.g., drivers) 264 coupled in series withnode 242.Buffers node 242 in a parallel fashion as shown inFIG. 2A . Each ofbuffers respective transistor group buffers 261 can include an output node coupled to a gate of one of transistors P2 0 through P2 M of arespective transistor group 251. In another example, each ofbuffers 262 can include an output node coupled to a gate of one of transistors P2 0 through P2 M of arespective transistor group 252. - Each of
buffers Buffers node 242 totransistor groups buffers node 242 to gates of transistors P2 0 through P2 M oftransistor groups - As shown in
FIG. 2A , buffers 261 can form a circuit path to propagate signal CTLP2 from thenode 242 to the gates of transistors P2 0 through P2 M oftransistor groups 251.Buffers 262 can form a circuit path to propagate signal CTLP2 from thenode 242 to the gates of transistors P2 0 through P2 M oftransistor groups 252. Similarly buffers 263 and 264 can form separate circuit paths to propagate signal CTLP2 from thenode 242 to the gates of transistors P2 0 through P2 M oftransistor groups buffers transistor groups FIG. 2A can form parallel chains (e.g., parallel daisy chains). -
Controller 207 can include agenerator 272, acode generator 274, agenerator 276, and acircuit 278.Generator 272 can include a ramped voltage generator that can generate different voltages, such as voltages V1, V2, V3, and V4, having different values.Code generator 274 can generate information CODE (which is digital information).Generator 276 can generate signal CTLP2 and provide it tonode 242.Circuit 278 can operate to allowcontroller 207 to further control the value of signal CTLP1 atnode 241 during different modes (e.g., sleep mode and active mode) offunctional unit 211.Controller 207 can include a node (e.g., a clock node) to receive a clock signal CLK (e.g., a periodical signal). -
Code generator 274 can generate information CODE that can have different values (e.g., different bit values) based on timing (e.g., based on the number of periods) of signal CLK.Controller 207 can use information CODE to causegenerator 272 to provide signal CTLP1 with voltages V1, V2, V3, and V4 at different time intervals, such that the slope of signal CTLP1 is a ramped signal having decreasing voltage values. This allowscontroller 207 to gradually turn on transistors P1 0, and P1 1 through P1 N (which have their gates coupled tonode 241 which carries signal CTLP1).Generator 276 can generate signal CTLP2 that can have different values (e.g., different voltages) based on timing (e.g., based on the number of periods) of signal CLK. -
FIG. 2B are timing diagrams showing waveforms of signals CTLP1 CTLP2, and voltage VCC1 ofFIG. 2A , according to some embodiments described herein. InFIG. 2B , a time interval between times Ti and Tj can occur during a lower power consumption state (e.g., during a sleep mode) of functional unit 211 (FIG. 2A). A time interval between times Tj and Tn can occur during a higher power consumption state (e.g., during a power-on state) offunctional unit 211. - In
FIG. 2B , Code_ValueA, Code_ValueB, Code_ValueC, and Code_ValueD are the values of information CODE (generated bycode generator 274 ofFIG. 2A ) at times Tj, Tk, Tl, and Tm, respectively. Each of values Code_ValueA, Code_ValueB. Code_ValueC, and Code_ValueD can have a value based on values of a number of bits. Values Code_ValueA, Code_ValueB, Code_ValueC, and Code_ValueD are different values (e.g., different digital values). - A shown in
FIG. 2B , signal CTLP1 is a continuous signal having voltage values in a decreasing direction. The waveform of signal CTLpe is based on values Code_ValueA, Code_ValueB, Code_ValueC, and Code_ValueD of information CODE. Generator 272 (FIG. 2A ) can use values Code_ValueA, Code_ValueB, Code_ValueC, and Code_ValueD of information CODE to provide voltages V4, V3, V2, and V1, respectively, at different time intervals. - As shown in
FIG. 2B , signal CTLP2 can remain relatively unchanged at value Vx between times Ti and Tn. At time Tn signal CTLP2 can be changed from one level (e.g., level at voltage Vx) to another level (e.g., level at voltage V0 (e.g., zero volts)). The interval between times Ti and Tn can be measured based on the periods (cycles) of clock signal CLK. For example, as shown inFIG. 2B , the time interval between times Tj and Tn can be measured by a number of periods (cycles) of clock signal CLK (e.g., P periods, where P is an integer).Controller 207 can cause signal CTLP2 to change from one level to another level after P periods of clock signal CLK have lapsed from a reference time (e.g., time Tj). The value of P can be based on a time interval from time Tj to a time (e.g., time Tn) at which transistors P1 0, and P1 1 through P1 N are fully turned on, or alternatively a time at which voltage VCC1 reaches a value close to the value of voltage VCCIN (e.g., approximately 95% of the value of VCCIN).FIG. 2B shows an example wherecontroller 207 can cause signal CTLP2 to change from one level to another level at time Tn. However,controller 207 can cause signal CTLP2 to change from one level to another level at another time (e.g., a time between times Tm and Tn) at which transistors P1 0, and P1 1 through P1 N are fully turned on (or alternatively, a time at which voltage VCC1 reaches a value close to (e.g., 95% of) the value of voltage VCCIN). - As shown in
FIG. 2B , voltage VCC1 can gradually increase from value V0 to value Vx (e.g., the value of voltage VCCIN) while signal CTLP1 decreases from a level at voltage V4 to voltage V1. The decreasing voltages provided to signal CTLP1 allowscontroller 207 to provide different voltages to gates of transistors P1 0, and P1 1 through P1 N to concurrently turn on transistors P1 0, and P1 1 through P1 N in a gradual fashion. -
FIG. 2A shows an example where transistors P1 0, and P1 1 through P1 N are located at the same location (e.g., located adjacent to each other) inpower switching circuitry 231. However, transistors P1 0, and P1 1 through P1 N can be distributed at different locations inpower switching circuitry 231. For example, one group of transistors P1 0, and P1 1 through P1 N can be located at one location (e.g., a first location) inpower switching circuitry 231, and another group of transistors P1 0, and P1 1 through P1 N can be located at another location (e.g., a location not adjacent to the first location). The distributed groups of transistors P1 0, and P1 1 through P1 N can be controlled by the same signal (e.g., signal CTLP1) generated by the same generator (e.g., generator 272). Alternatively, the distributed groups of transistors P1 0, and P1 1 through P1 N can be controlled by different signals (e.g., similar to signal CTLP1) generated by different generators (e.g., similar to generator 272). Distributing transistors P1 0, and P1 1 through P1 N in different groups at different locations (non-adjacent locations) may reduce electro-migration in metal structures that are used to deliver the current (e.g., rush current) topower supply node 221 during a power-on (e.g., wakeup mode). -
FIG. 2A shows an example wheretransistor groups transistor groups transistor group 251 are turned at the same time as transistors P2 0 through P2 M of each of theother transistor groups power switching circuitry 231, transistors P2 0 through P2 M of fewer than all oftransistor groups transistor groups transistor groups transistor groups transistor groups transistor groups - The structure of power switching circuitry 231 (where transistors P2 0 through P2 M among
transistor groups power supply node 205 may occur. The described alternative structure of power switching circuitry 231 (where transistors P2 0 through P2 M in fewer than all oftransistor groups power supply node 205. However, this may result in a relatively longer time for the value of voltage VCC1 to reach the value of voltage VCCIN. Thus, transistors P2 0 through P2 M of either fewer than all oftransistor groups transistor groups transistor groups - Thus, as described above with reference to
FIG. 2A andFIG. 2B , operations ofpower switching circuitry 231 can include two phases: a gradual turning on of transistors P1 0, and P1 1 through P1 N and then a turning on of transistors P2 0 through P2 m. The number of transistors P1 0, and P1 1 through P1 N can be relatively small (e.g., N can be about at least ten times less than M). Since the number of transistors P1 0, and P1 1 through P1 N is relatively small and since transistors P1 0, and P1 1 through P1 N are gradually turned on, the amount of current to flow betweenpower supply nodes 205 and 221 (when transistors P1 0, and P1 1 through P1 N are turned on) may not affect (e.g., cause excessive heat on) the structure (e.g., Fin Field Effect Transistor (FinFET) structure) of transistors P1 0, and P1 1 through P1 N, thereby preventing damage to transistors P1 0, and P1 1 through P1 N(e.g., damage caused by excessive heat). -
FIG. 3 shows a schematic diagram of a portion ofpower switching circuitry 231 ofFIG. 2A including aresistive network 372, and aselector 373, according to some embodiments described herein.Resistive network 372 andselector 373 can be part ofgenerator 272 ofFIG. 2A . Alternatively,selector 373 can be part of another component ofpower switching circuitry 231 ofFIG. 2A . - As shown in
FIG. 3 ,resistive network 372 can include resistors R coupled in series betweenpower supply node 205 and ground (e.g., a ground node). The value of resistors R can be the same. For example, resistors R can have the same unit resistor value. Resistors R ofresistive network 372 can form a resistor ladder (R-ladder) voltage divider that can generate voltages V1, V2, V3, and V4 having different values between ground and the value of voltage VCCIN. - The values of voltages V4, V3, V2, and V1 can be decreased in a sequential order. For example, the value of voltage V4 is greater than the value of voltage V3; the value of voltage V3 is greater than the value of voltage V2; and the value of voltage V2 is greater than the value of voltage V1. The value of voltage V1 can be greater than zero.
- As described above, resistors R can have the same unit resistor value. Thus, global PVT variations affect the unit resistors in the R-ladder equally. This means that the R-ladder voltage divider of
resistive network 372 can be insensitive to global PVT. Therefore, a relatively constant ramped voltage at node 241 (which is based on voltages V4, V3, V2, and V1) may be achieved. A constant ramped voltage helps improve the gradual turning on of transistors P1 0, and P1 1 through P1 N during a power-on (e.g., wakeup) mode. This can lead to robust, well controlled wake current profiles (e.g., power-on mode current profiles) across PVT corners. - As shown in
FIG. 3 , selector (e.g., multiplexor) 373 can include input nodes (e.g.,input nodes 1, 2, 3, and 4) coupled to respective nodes (e.g., voltage output nodes) ofresistive network 372 that provide voltages V1, V2, V3, and V4, respectively.Selector 373 can include an output node coupled tonode 241, and nodes (e.g., control nodes) 373 c to receive information CODE.Nodes 373 c can include separate nodes (e.g., separate lines) to receive (e.g., receive in parallel) respective bits of information CODE. Based on the value of information CODE,selector 373 can select voltages V1, V2, V3, and V4 (generated by resistive network 372) and provide the selected voltage tonode 241.Selector 373 can select voltages V1, V2, V3, and V4 in a decreasing order from high to low (e.g., voltages V4, V3, V2, and V1), such that signal CTLP1 can provide voltages from a higher value to a lower value (e.g., based on the values of voltages V4, V3, V2, and V1). - Thus,
resistive network 372 andselector 373 can form a digital-to-analog converter (DAC) to provide analog voltages (e.g., voltages V1, V2, V3, and V4) tonode 241 in the form of signal CTLP1 based on the value (digital value) of information CODE. This means that the values of voltages (e.g., V1, V2, V3, and V4) provided to the gates of transistors P1 0, and P1 1 through P1 N (which are coupled to node 241) are based on the values of information CODE. As an example,selector 373 can select voltage V4 and provide it tonode 241 if the value of information CODE is value Code_ValueA(FIG. 2B );selector 373 can select voltage V3 and provide it tonode 241 if the value of information CODE is value Code_ValueB;selector 373 can select voltage V2 and provide it tonode 241 if the value of information CODE is value Code_ValueC (FIG. 2B ); andselector 373 can select voltage V1 and provide it tonode 241 if the value of information CODE is value Code_ValueD. The R-ladder-based voltage divider ofresistive network 372 is used withselector 373 to form a resistive DAC (as shown inFIG. 3 ) as an example. Other DAC topology (e.g., switched-capacitor DAC and current-based DAC) can be used. - As shown in
FIG. 3 ,power switching circuitry 231 may use signals SLEEP* and BYPASS to control transistors P1 0, and P1 2 through P1 N (in addition to signal CTLP1) depending on the states of functional unit 211 (FIG. 2A ). - During a time interval (e.g., between times Ti and Tj in
FIG. 2B ) in a lower power consumption state (e.g., sleep mode), signal BYPASS can have a level (e.g., “low” or zero volts) to turn off transistor N3. This can disconnectnode 241 from ground. During this time interval (e.g., between times Ti and Tj inFIG. 2B ), signal SLEEP* can have a level (e.g., “low” or zero volts) to turn on transistor P3. This can connectnode 241 to power supply node 205 (through transistor P3) to turn off transistors P1 0, and P1 2 through P1 N in order to avoid leakage of power. - During a time interval (e.g., between times Tj and Tn) of a higher consumption state (e.g., wakeup mode), signal SLEEP* can have a level (e.g., “high” or 1V for example) to turn off transistor P3. This can disconnect
node 241 from power supply node 205 (FIG. 3 ). During this time interval (e.g., between times Ti and Tn), signal BYPASS can have a level (e.g., “low” or zero volts) to keep transistor N3 turned off. During this time interval (e.g., between times Ti and Tn),node 241 is provided with voltages V1, V2, V3, and V4 to gradually turn on transistors P1 0, and P1 2 through PIN. After time Tn, signal CTLP1 can be deactivated, such thatselector 373 may not provide voltages to signal CTLP1. However, after time Tn, signal BYPASS can have a level (e.g., “high”) to turn on transistor N3. This can connectnode 241 to ground in order to cause transistors P1 0, and P1 2 through P1 N to fully turn on. - Thus, as described above, transistors P1 0, and P1 2 through P1 N can be concurrently (e.g., simultaneously) and gradually turned on using the DAC technique that applies a ramped voltage (e.g., voltages V4, V3, V2, and V1) to the gates of transistors P1 0, and P1 2 through P N based on digital values of information CODE. Not using this technique (e.g., by not gradually turning on transistors P1 0, and P1 2 through P1 N or by applying a digital signal to the gates of transistors P1 0, and P1 2 through P1 N) may result in relatively high rush current peaks (e.g., high di/dt at
power supply nodes 221 and 205), voltage droops of the waveform of voltage VCCIN, and supply voltage noise in neighboring components (e.g., functional units) that share voltage VCCIN withpower switching circuitry 231. - Using the described DAC technique to concurrently and gradually turn on transistors P1 0, and P1 2 through P1 N can help avoid some drawbacks mentioned above, such as the relatively high rush current peaks, the voltage droops of the waveform of voltage VCCIN, and the supply voltage noise in neighboring components. Further, as described above, concurrently and gradually turning on transistors P1 0, and P1 2 through P1 N can also help avoid excessive heat on the structure (e.g., FinFET structure) of transistors P1 0, and P1 2 through P1 N, thereby preventing damage to transistors P1 0, and P1 2 through P1 N (e.g., damage caused by avoid excessive heat).
- Moreover, as described above, information CODE can be programmable post-manufacturing (e.g., post-silicon). This may avoid calibration (e.g., post-silicon trimming) of components associated with
power switching circuitry 231 ofIC 202. - Moreover, the described techniques can be scalable to different design sizes. For example, different functional units (e.g.,
functional units FIG. 2A throughFIG. 3 ) can be individually structured and configured to operate in ways to fit operation of a particular functional unit during the power-on mode of that particular functional unit. Thus, in the same IC, different power switching circuitry can have different structures based on operations of respective functional units coupled to the different power switching circuitry. In another example,power switching circuitry 231 can be structured and configured to operate in ways based on different power domain sizes (e.g., different sizes offunctional unit 211 inFIG. 2A orfunctional units FIG. 1A ). -
FIG. 4A shows a schematic diagram ofresistive network 372 andselector 373 ofFIG. 3A including transmission gates, according to some embodiments described herein. As shown inFIG. 4A ,resistive network 372 can include transmission gates TG0 through TG4 coupled in series betweenpower supply nodes 205 and ground. Each of transmission gates TG0 through TG4 can include two transistors (e.g., p-channel and n-channel transistors) coupled as shown inFIG. 4A . Voltages V1, V2, V3, and V4 can be generated at respective nodes at transmission gates TG0 through TG4. The gates of each of transmission gates TG1 through TG3 can be controlled by ground potential (e.g., zero volts) and a voltage V, such that transmission gates TG1 through TG3 can be normally turned on (e.g., turned on during operation of power switching circuitry 231 (FIG. 2A )). - Transmission gate TG0 can be coupled to an inverter INV0 and controlled by a signal SLEEP*. Transmission gate TG0 can be turned on when signal SLEEP* has one level (e.g., “high”) and turned off on when signal SLEEP* has another level (e.g., “low”).
- Transmission gate TG4 can be coupled to an inverter INV4 and controlled by a signal BYPASS* (which can be a complement of signal BYPASS). Transmission gate TG4 can be turned on when signal BYPASS* has one level (e.g., “high”) and turned off when signal BYPASS* has another level (e.g., “low”).
- During a time interval (e.g., between times Ti and Tj in
FIG. 2B ) in a lower power consumption state (e.g., sleep mode), signal SLEEP* can have a level (e.g., “low”) to turn off transmission gate TG0. This can prevent static current from flowing (e.g., flowing betweenpower supply nodes 205 and ground) inresistive network 372. - During a time interval (e.g., between times Tj and Tn in
FIG. 2B ) in a higher power consumption state (e.g., wakeup mode) and before transistors P1 0, and P1 2 through P1 N are fully turned on (e.g., before signal CTLP1 is provided with voltage V1), each of signals SLEEP* and BYPASS can have a level to turn on respective transmission gates TG0 and TG4. This allows a current path to form betweenpower supply nodes 205 and ground in order to generate voltages V1, V2, V3, and V4 inresistive network 372. -
Selector 373 can include transmission gates TG11 through TG14 and inverters INV11 through INV14. The gates of transmission gates TG11 through TG14 can be respectively coupled tonodes 373 c, which receive information CODE. Based on the value of information CODE,selector 373 can turn on one of transmission gates TG11 through TG14 while the other transmission gates among transmission gates TG11 through TG14 are turned off.Selector 373 can select voltages V1, V2, V3, and V4 (generated by resistive network 372) and provide the selected voltage tonode 241 through one of transmission gates TG11 through TG14 that is turned on. - As shown in
FIG. 4A , information CODE can include bits B1, B2, B3, and B4 that can be received in parallel atnodes 373 c. The value (binary value) of the combination of bits B1, B2, B3, and B4 represents the value of one of values Code_ValueA, Code_ValueB, Code_ValueC, and Code_ValueD. Each value of the combination of bits B1, B2, B3, and B4 can causeselector 373 to select a different voltage among voltages V1, V2, V3, and V4 to be provided tonode 241. -
FIG. 4B is a chart showing the relationships among the values of information CODE and the voltages provided tonode 241 inFIG. 4A , according to some embodiments described herein. As shown inFIG. 4B , values Code_ValueA, Code_ValueB, Code_ValueC, and Code_ValueD can be “0001”, “0010”, “0100”, and “1000”, respectively. These values can be used to select respective voltages V4, V3, V2, and V1 (in a decreasing order), such that transistors P1 0, and P1 2 through P1 N can be gradually turned on. -
FIG. 4A showsresistive network 372 including transmission gates as an example. Other structures can be used. For example, n-well resistors may be used as resistors inresistive network 372. Using area-efficient transmission gates inresistive network 372 andselector 373 can save area inpower switching circuitry 231 and can reduce costs associated with generating and providing voltages V1, V2, V3, and V4 tonode 241. -
FIG. 5 shows an apparatus in the form of a system (e.g., electronic system) 500, according to some embodiments described herein.System 500 can include or be included in a computer, a tablet, or other electronic systems. As shown inFIG. 5 ,system 500 can include components such as abattery 503, a processor 515, amemory device 520, amemory controller 530, agraphics controller 540, an input and output (I/O)controller 550, adisplay 552, akeyboard 554, apointing device 556, at least oneantenna 558, aconnector 559, and abus 560.Bus 560 can include conductive lines (e.g., metal-based traces on a circuit board where the components ofsystem 500 are located). - In some arrangements,
system 500 does not have to include a display. Thus, display 552 can be omitted fromsystem 500. In some arrangements,system 500 does not have to include any antenna. Thus,antenna 558 can be omitted fromsystem 500. -
Battery 503 can provide power to the components ofsystem 500, e.g., through apower delivery path 516. Such components can include a processor 515, amemory device 520, amemory controller 530, agraphics controller 540, and input/output (I/O)controller 550. - Processor 515 can include a general-purpose processor or an application specific integrated circuit (ASIC). Processor 515 can include a CPU.
-
Memory device 520 can include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, a combination of these memory devices, or other types of memory.FIG. 5 shows an example wherememory device 520 is a stand-alone memory device separated from processor 515. In an alternative arrangement,memory device 520 and processor 515 can be located on the same die. In such an alternative arrangement,memory device 520 is an embedded memory in processor 515, such as embedded DRAM (eDRAM), embedded SRAM (eSRAM), embedded flash memory, or another type of embedded memory. -
Display 552 can include a liquid crystal display (LCD), a touchscreen (e.g., capacitive or resistive touchscreen), or another type of display.Pointing device 556 can include a mouse, a stylus, or another type of pointing device. - I/
O controller 550 can include a communication module for wired or wireless communication (e.g., communication through one or more antennas 558). Such wireless communication may include communication in accordance with WiFi communication technique, Long Term Evolution Advanced (LTEA) communication technique, or other communication techniques. - I/
O controller 550 can also include a module to allowsystem 500 to communicate with other devices or systems in accordance with one or more standards or specifications (e.g., I/O standards or specifications), including Universal Serial Bus (USB), DisplayPort (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), Ethernet, and other specifications. -
Connector 559 can be structured (e.g., can include terminals, such as pins) to allowsystem 500 to be coupled to an external device (or system). This may allowsystem 500 to communicate (e.g., exchange information) with such a device (or system) throughconnector 559. -
Connector 559 and at least a portion ofbus 560 can include conductive lines that conform with at least one of USB, DP, HDMI, Thunderbolt, PCIe, Ethernet, and other specifications. - As shown in
FIG. 5 , each of processor 515,memory device 520,memory controller 530,graphics controller 540, and I/O controller 550 can include afunctional unit 511 andpower switching circuitry 531.Functional unit 511 andpower switching circuitry 531 can include any of the functional units and power switching circuitry described above with reference toFIG. 1A throughFIG. 4B . - As shown in
FIG. 5 ,system 500 can includevoltage regulators 505, each of which can include an input node coupled topower delivery path 516 to provide voltage VCCIN (e.g., un-gated VCCIN voltage) based on power frombattery 503. Some of thevoltage regulators 505 can be on-die voltage regulator or off-die voltage regulators. For example, processor 515,graphics controller 540, and I/O controller 550 can include an on-die voltage regulator 505, andvoltage regulators 505 providing voltages VCCIN tomemory device 520 andmemory controller 530 can be off-die voltage regulators 505. -
FIG. 5 shows an example where each of processor 515,graphics controller 540, and I/O controller 550 includes an on-die voltage regulator 505. However, in some structures ofsystem 500, some (or all) of processor 515,graphics controller 540, and I/O controller 550 may not include an on-die voltage regulator 505. -
FIG. 5 shows the components ofsystem 500 arranged separately from each other as an example. For example, each of processor 515,memory device 520,memory controller 530,graphics controller 540, and I/O controller 550 can be located on a separate IC (e.g., semiconductor die or an IC chip). In some arrangements, two or more components (e.g., processor 515,memory device 520,graphics controller 540, and I/O controller 550) ofsystem 500 can be located on the same die (e.g., same IC chip) that forms a system-on-chip (SoC) or located on the same IC package that forms a system-on-package (SoP) or system-in-package (SiP). -
FIG. 6 is a flowchart showing amethod 600 of operating an apparatus, according to some embodiments described herein. The apparatus used inmethod 600 can include any of the apparatuses (e.g.,apparatus 100 andsystem 500 includingpower switching circuitry FIG. 1A throughFIG. 5 . Some of the activities inmethod 600 may be performed by hardware, software, firmware, or any combination of hardware, software, and firmware. - As shown in
FIG. 6 ,activity 610 ofmethod 600 can include providing first, second, and third digital information to a controller located on an IC die. The controller coupled to transistors can be located on the integrated circuit die. The transistors can be coupled in parallel between a first power supply node and a second power supply node.Activity 620 ofmethod 600 can include applying a first voltage to gates of the transistors based on the first digital information.Activity 630 ofmethod 600 can include applying a second voltage to gates of the transistors based on the second digital information.Activity 640 ofmethod 600 can include applying a third voltage to gates of the transistors based on the third digital information. -
Method 600 can include fewer or more activities relative toactivities FIG. 6 . For example,method 600 can include activities and operations of any of the apparatuses (e.g.,apparatus 100 andsystem 500 includingpower switching circuitry FIG. 1A throughFIG. 5 . - The illustrations of the apparatuses (e.g.,
apparatus 100 andsystem 500 includingpower switching circuitry method 600 and operations ofapparatus 100 andsystem 500 including operations ofpower switching circuitry - The apparatuses and methods described above can include or be included in high-speed computers, communication and signal processing circuitry, single-processor modules or multi-processor modules, single embedded processors or multiple embedded processors, multi-core processors, message information switches, and application-specific modules including multilayer or multi-chip modules. Such apparatuses may further be included as sub-components within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, etc.), tablets (e.g., tablet computers), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set top boxes, and others.
- Example 1 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information, the first, second, and third voltages having different values based on values of the digital information.
- In Example 2, the subject matter of Example 1 may optionally include, further comprising first additional transistors coupled in parallel between the first and second power supply nodes, and first buffers coupled in series with an output of the controller, each of the first buffers including an output node coupled to a gate of one of the first additional transistors.
- In Example 3, the subject matter of Example 2 may optionally include, further comprising second additional transistors coupled in parallel between the first and second power supply nodes, and second buffers coupled in series with the output of the controller in parallel with the first buffers, each of the second buffers including an output node coupled to a gate of one of the second additional transistors.
- In Example 4, the subject matter of any of Examples 1-3 may optionally include, wherein the controller includes a generator to generate the first, second, and third voltages, and a selector to receive the digital information and select the first, second, and third voltages provided to the gates of the transistors based on different values of the digital information.
- In Example 5, the subject matter of any of Examples 1-3 may optionally include, wherein the controller includes a resistive network coupled to the first power supply node and a ground node, the resistive network including a first node to provide the first voltage, a second node to provide the second voltage, and a third node to provide the third voltage.
- In Example 6, the subject matter of Example 5 may optionally include, wherein the controller includes a selector including input nodes coupled to respective first, second, and third nodes of the resistive network, an output node coupled to the gates of the transistors, and nodes to receive bits of the digital information.
- In Example 7, the subject matter of Example 6 may optionally include, wherein the selector includes first, second, and third transmission gates coupled to the first, second, and third nodes, respectively, of the resistive network.
- In Example 8, the subject matter of Example 1 may optionally include, wherein the second power supply node is coupled to a functional unit, and the controller is to provide the first, second, and third voltages to the gates of the transistors when the functional unit changes from a first power consumption state to a second power consumption state.
- In Example 9, the subject matter of Example 8 may optionally include, wherein the transistors are to turn off during the first power consumption state and to turn on in the second power consumption state.
- In Example 10, the subject matter of Example 8 may optionally include, wherein the first power consumption state includes a sleep mode of the functional unit.
- Example 11 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including an integrated circuit die, a voltage regulator located on the integrated circuit die and coupled to a first power supply node, and power switching circuitry located on the integrated circuit die and coupled to the first power supply node and a second power supply node, the power switching circuitry including transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information, the first, second, and third voltages having different values based on values of the digital information.
- In Example 12, the subject matter of Example 11 may optionally include, further comprising first additional transistors coupled in parallel between the first and second power supply nodes, and a first circuit path coupled to a node of the controller to propagate a signal from the node of the controller to gates of the first additional transistors.
- In Example 13, the subject matter of Example 12 may optionally include, further comprising second additional transistors coupled in parallel between the first and second power supply nodes, and a second circuit path different from the first circuit path, the second circuit path coupled to the node of the controller to propagate the signal from the node of the controller to gates of the second additional transistors.
- In Example 14, the subject matter of Example 13 may optionally include, wherein each of the first and second circuit paths includes buffers coupled in series.
- In Example 15, the subject matter of any of Examples 11-14 may optionally include, wherein the controller is to provide a first digital value of the digital information, a second digital value of the digital information, and third digital value of the digital information, and the values of the first, second, and third voltages are based on respective first, second, and third values of the digital information.
- In Example 16, the subject matter of any of Examples 11-14 may optionally include, wherein the second power supply node is coupled to a functional unit, and the controller is to provide the first, second, and third voltages to the gates of the transistors when the functional unit changes from a lower power consumption state to a higher power consumption state.
- In Example 17, the subject matter of any of Examples 11-14 may optionally include, further comprising a power delivery path to couple to a battery, wherein the voltage regulator includes an input node coupled to the power delivery path.
- In Example 18, the subject matter of any of Examples 11-14 may optionally include, wherein the integrated circuit die includes a processor.
- In Example 19, the subject matter of any of Examples 11-14 may optionally include, further comprising an antenna coupled to the integrated circuit die.
- Example 20 includes subject matter (such as a method of operating a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including providing first, second, and third digital information to a controller located on an integrated circuit die, the controller coupled to transistors located on the integrated circuit die, the transistors coupled in parallel between a first power supply node and a second power supply node, applying a first voltage to gates of the transistors based on the first digital information, applying a second voltage to the gates of the transistors based on the second digital information, and applying a third voltage to the gates of the transistors based on the third digital information.
- In Example 21, the subject matter of Example 20 may optionally include, wherein the first voltage has a first value, the second voltage has a second value, the third voltage has a third value, the first value is greater than the second value, and the second value is greater than the third value.
- In Example 22, the subject matter of Example 21 may optionally include, wherein the first voltage is applied to the gates of the transistors before the second voltage is applied to the gates of the transistors, and the second voltage is applied to the gates of the transistors before the third voltage is applied to the gates of the transistors.
- In Example 23, the subject matter of Example 20 may optionally include, further comprising selecting the first voltage from a resistive ladder network based on the first digital information, selecting the second voltage from the resistive ladder network based on the second digital information, and selecting the third voltage from the resistive ladder network based on the third digital information.
- In Example 24, the subject matter of Example 20 may optionally include, further comprising applying a fourth voltage to gates of additional transistors coupled in parallel between the first and second power supply nodes.
- In Example 25, the subject matter of Example 20 may optionally include, wherein the second power supply node is coupled to a functional unit, and the first, second, and third voltages are applied to the gates of the transistors during a time interval when the functional unit changes from a lower power consumption state to a higher power consumption state.
- Example 26 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or machine) including means for performing any of the methods of claims 20-25.
- The subject matter of Example 1 through Example 26 may be combined in any combination.
- The above description and the drawings illustrate some embodiments to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Therefore, the scope of various embodiments is determined by the appended claims, along with the full range of equivalents to which such claims are entitled.
- The Abstract is provided to comply with 37 C.F.R. Section 1.72(b) requiring an abstract that will allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to limit or interpret the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.
Claims (25)
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