US20180145054A1 - Semiconductor package - Google Patents

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Publication number
US20180145054A1
US20180145054A1 US15/815,042 US201715815042A US2018145054A1 US 20180145054 A1 US20180145054 A1 US 20180145054A1 US 201715815042 A US201715815042 A US 201715815042A US 2018145054 A1 US2018145054 A1 US 2018145054A1
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Prior art keywords
circuit board
printed circuit
transfer line
semiconductor chip
pad
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US15/815,042
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US10134713B2 (en
Inventor
Kwang-Seok Kim
Sun-Won Kang
Il-Joon KIM
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANG, SUN-WON, KIM, IL-JOON, KIM, KWANG-SEOK
Publication of US20180145054A1 publication Critical patent/US20180145054A1/en
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Definitions

  • One or more embodiments described herein relate to a semiconductor package.
  • Electronic devices are designed to be smaller and with greater functionality. As a result, there is a demand for large-capacity and multi-functional semiconductor chips. These chips may be incorporated within various semiconductor packages.
  • a semiconductor package includes a printed circuit board having a lower surface and an upper surface, the upper surface including a first pad and a second pad; an external connection terminal on the lower surface of the printed circuit board; a resistor circuit including a first connection terminal and a second connection terminal, the first connection terminal connected to the first pad and the second connection terminal is connected to the second pad; a first semiconductor chip mounted on the printed circuit board and connected to the first pad; and a second semiconductor chip stacked on the first semiconductor chip and connected to the second pad, wherein the printed circuit board includes: a signal transfer line that connects a branch in the printed circuit board to the external connection terminal; a first transfer line that connects the branch to the first pad; and a second transfer line that connects the branch to the second pad.
  • a semiconductor package includes a printed circuit board including a lower surface and an upper surface, the upper surface including a first pad and a second pad; an external connection terminal on the lower surface of the printed circuit board; a resistor circuit including a first connection terminal and a second connection terminal, the first connection terminal connected to the first pad and the second connection terminal connected to the second pad; a first semiconductor chip mounted on the printed circuit board and connected to the first pad; and a second semiconductor chip mounted on the printed circuit board and connected to the second pad, the first semiconductor chip and the second semiconductor chip mounted on a same plane of the printed circuit board, wherein the printed circuit board includes: a signal transfer line that connects a branch in the printed circuit board to the external connection terminal; a first transfer line that connects the branch to the first pad; and a second transfer line that connects the branch to the second pad.
  • a semiconductor package includes a printed circuit board; a first semiconductor chip and a second semiconductor chip mounted on the printed circuit board; and a power distribution device mounted on the printed circuit board and including: an input terminal to receive a signal; a first output terminal and a second output terminal to output a signal; a resistor circuit including a first connection terminal connected to the first output terminal and a second connection terminal connected to the second output terminal; a signal transfer line that connects a branch in the power distribution device to the input terminal; a first transfer line that connects the branch to the first connection terminal; and a second transfer line that connects the branch to the second connection terminal.
  • a semiconductor package includes a printed circuit board; a first semiconductor chip on the printed circuit board; a second semiconductor chip on the first semiconductor chip; and a resistor circuit including a first connection terminal connected to a first output terminal and a second connection terminal connected to a second output terminal, wherein the resistor circuit has a Wilkerson divider structure.
  • FIG. 1 illustrates an embodiment of a semiconductor package
  • FIG. 2A illustrates a view along section line A-A′ in FIG. 1
  • FIG. 2B illustrates an embodiment of a printed circuit board in the semiconductor package
  • FIG. 3 illustrates an embodiment for transferring signals in a semiconductor package
  • FIG. 4 illustrates another embodiment of a semiconductor package
  • FIG. 5 illustrates another embodiment of a semiconductor package
  • FIG. 6 illustrates another embodiment of a semiconductor package
  • FIG. 7 illustrates another embodiment for transferring signals in a semiconductor package
  • FIG. 8 illustrates another embodiment of a semiconductor package
  • FIG. 9 illustrates a view of the semiconductor package in FIG. 8 along section line B-B′;
  • FIG. 10 illustrates another embodiment of a semiconductor package
  • FIG. 11A illustrates another embodiment of a semiconductor package, and FIG. 11B illustrates an embodiment of a power distribution device
  • FIG. 12A illustrates another embodiment of a semiconductor package
  • FIG. 12B illustrates another embodiment of a power distribution device
  • FIG. 13 illustrates an embodiment of a semiconductor package.
  • FIG. 1 illustrates an embodiment of a semiconductor package 1000 which may include a printed circuit board 500 , a resistor unit 400 , a first semiconductor chip 100 , and a second semiconductor chip 200 .
  • the semiconductor package 1000 may further include external connection terminals 600 on a lower surface of the printed circuit board 500 .
  • a plurality of pads 516 , 526 , and 506 including a first pad 516 and a second pad 526 may be on an upper surface of the printed circuit board 500 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 are stacked on the printed circuit board 500 and may be sequentially mounted.
  • the first semiconductor chip 100 has an upper surface which may include a plurality of pads 116 and 106 .
  • the second semiconductor chip 200 has an upper surface which may include a plurality of pads 216 and 206 .
  • the pads 116 , 106 , 216 , and 206 may be on lower surfaces of the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500 , for example, by a wire bonding method. Therefore, the semiconductor package 1000 may include a first bonding wire 130 and a second bonding wire 230 .
  • the first bonding wire 130 may electrically connect the first pad 516 of the printed circuit board 500 to the first semiconductor chip 100 .
  • the second bonding wire 230 may electrically connect the second pad 526 of the printed circuit board 500 to the second semiconductor chip 200 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500 , for example, by a flip-chip bonding method.
  • the first semiconductor chip 100 and the second semiconductor chip 200 may include semiconductor devices, e.g., a plurality of individual devices of various kinds.
  • the individual devices may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor (CMOS) transistor, a system large scale integration (LSI), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, a passive device, etc.
  • MOSFET metal-oxide-semiconductor field effect transistor
  • CMOS complementary metal-insulator-semiconductor
  • LSI system large scale integration
  • an image sensor such as a CMOS imaging sensor (CIS)
  • MEMS micro-electro-mechanical system
  • the individual devices may be electrically connected to a conductive region of the semiconductor substrate, where the first semiconductor chip 100 and the second semiconductor chip 200 are
  • each of the first semiconductor chip 100 and the second semiconductor chip 200 may be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the resistor unit 400 may be mounted on the printed circuit board 500 and may include a plurality of connection terminals.
  • the connection terminals may include a first connection terminal and a second connection terminal.
  • the first connection terminal of the resistor unit 400 may be connected to the first pad 516 on the printed circuit board 500 .
  • the second connection terminal of the resistor unit 400 may be connected to the second pad 526 on the printed circuit board 500 .
  • the resistor unit 400 may be a resistor circuit, and the resistor circuit may include at least one resistor.
  • the resistor unit 400 may be implemented as at least one chip resistor, and may be mounted so that opposite ends of the resistor unit 400 contact the first pad 516 and the second pad 526 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 are mounted on a center portion of the printed circuit board 500 .
  • the resistor unit 400 may be mounted, for example, on a peripheral portion of the printed circuit board 500 which surrounds the center portion.
  • FIG. 2A illustrates a cross-sectional view of the semiconductor package 1000 taken along a line A-A′ of FIG. 1 .
  • FIG. 2B is a top view illustrating part of an upper surface of the printed circuit board 500 in the semiconductor package 1000 .
  • the semiconductor package 1000 may include the printed circuit board 500 , the resistor unit 400 , the first semiconductor chip 100 , the second semiconductor chip 200 , and the external connection terminals 600 formed on a lower surface of the printed circuit board 500 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be sequentially stacked on the printed circuit board 500 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be stacked and aligned with each other in a direction perpendicular to the upper surface of the printed circuit board 500 .
  • the resistor unit 400 may be mounted so that opposite ends of the resistor unit 400 contact the first pad 516 and the second pad 526 .
  • a first connection terminal 401 of the resistor unit 400 contact the first pad 516
  • a second connection terminal 402 of the resistor unit 400 contact the second pad 526 .
  • a bonding layer 120 may be between the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be bonded to each other via the bonding layer 120 .
  • Part of the first bonding wire 130 may be embedded by the bonding layer 120 .
  • a first rewiring layer and a second rewiring layer may be respectively formed on upper surfaces of the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the first bonding wire 130 connected to the first semiconductor chip 100 may be electrically connected to the first rewiring layer.
  • the second bonding wire 230 connected to the second semiconductor chip 200 may be electrically connected to the second rewiring layer. Therefore, the pads 116 , 106 , 216 , and 206 on the upper surfaces of the first semiconductor chip 100 and the second semiconductor chip 200 may be arranged in the first rewiring layer and the second rewiring layer.
  • the printed circuit board 500 may include a plurality of layers, in which a plurality of base layers 501 , 503 , and 505 are stacked.
  • each of the base layers 501 , 503 , and 505 may include at least one of a phenol resin, an epoxy resin, and polyimide.
  • each of the base layers 501 , 503 , and 505 may include at least one of frame retardant 4 (FR4), tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, polyimide, and liquid crystal polymer.
  • FIG. 2A shows three base layers 501 , 503 , and 505 , but a different number (e.g., two, four or more) base layers may be formed in another embodiment.
  • the first pad 516 and the second pad 526 are on an upper surface of the uppermost layer from among the base layers 501 , 503 , and 505 .
  • a lower pad 556 may be on a lower surface of the lowermost layer from among the base layers 501 , 503 , and 505 .
  • the lower pad 556 may contact the external connection terminal 600 to receive a signal from the external connection terminal 600 .
  • the lower pad 556 is shown to be formed at a center portion of the printed circuit board 500 , but may be at different location in another embodiment. According to formation of a first transfer line 510 a second transfer line 520 , and a signal transfer line 554 , the lower pad 556 may be on the peripheral region surrounding the center region of the printed circuit board 500 .
  • a metal layer may be further formed on each of the first pad 516 , the second pad 526 , and the lower pad 556 .
  • the metal layer may be formed to improve an adhesive force of each of the first pad 516 , the second pad 526 , and the lower pad 556 , and to reduce contact resistance.
  • the metal layer may be formed, for example, by a hot air solder leveling (H.A.S.L.) method, a Ni/Au plating method, or another method.
  • a branch 555 where the first transfer line 510 , the second transfer line 520 , and the signal transfer line 554 meet one another may be formed in the printed circuit board 500 .
  • the signal transfer line 554 electrically connects the branch 555 to the external connection terminal 600 , so that a signal transmitted from outside via the external connection terminal 600 may be transferred to the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the signal may be distributed to the first transfer line 510 and the second transfer line 520 based on the branch 555 and transferred to the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the signal transfer line 554 has a via structure and may include a conductive line at the same layer level.
  • the signal transfer line 554 may have a different structure in another embodiment.
  • the first transfer line 510 may electrically connect the branch 555 to the first pad 516 .
  • the first transfer line 510 may include a first via structure 514 penetrating through at least one layer of the printed circuit board 500 , and a first wiring pattern 512 formed at the same layer level as that of the printed circuit board 500 .
  • the second transfer line 520 may electrically connect the branch 555 to the second pad 526 .
  • the second transfer line 520 may include a second via structure 524 penetrating through at least one layer of the printed circuit board 500 , and a second wiring pattern 522 formed at the same layer level as that of the printed circuit board 500 .
  • the signal received by the lower pad 556 of the printed circuit board 500 is transferred inside the printed circuit board 500 along the signal transfer line 554 .
  • the signal is distributed to the first transfer line 510 and the second transfer line 520 based on the branch 555 and transferred to the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the first transfer line 510 and the second transfer line 520 may have substantially the same lengths as each other.
  • the lengths of the first transfer line 510 and the second transfer line 520 may be substantially equal to quarter of a wavelength of the signal transmitted from outside via the external connection terminal 600 .
  • the first transfer line 510 and the second transfer line 520 may have substantially the same impedance as each other.
  • Impedance of the resistor unit 400 may be related to the impedance of the first transfer line 510 and the second transfer line 520 . This is to implement a structure of Wilkinson divider on the printed circuit board 500 .
  • the first wiring pattern 512 and the second wiring pattern 522 may be on respective upper and lower surfaces of each of the base layers 501 , 503 , and 505 .
  • the first wiring pattern 512 and the second wiring pattern 522 may include, for example, electrolytically deposited (ED) copper foil, rolled-annealed (RA) copper foil, stainless steel foil, aluminum foil, ultra-thin copper foil, sputtered copper, copper alloys, etc.
  • the first wiring pattern 512 and the second wiring pattern 522 may be at different layer levels from each other.
  • the first wiring pattern 512 may be on an upper surface of the first base layer 501 and the second wiring pattern 522 may be on an upper surface of the second base layer 503 .
  • This arrangement may be different in another embodiment.
  • a space may be provided that is sufficient to allow both the first wiring pattern 512 and the second wiring pattern 522 to be formed at the same layer of the printed circuit board 500 .
  • the lengths of the first transfer line 512 and the second transfer line 520 may satisfy the quarter of the wavelength of the signal transmitted from outside.
  • the signal transfer line 554 , the first via structure 514 , and the second via structure 524 may include, for example, copper, nickel, stainless steel, or beryllium copper.
  • An upper solder resist layer 562 and a lower solder resist layer 564 may be formed respectively on an upper surface of the uppermost layer and a lower surface of the lowermost layer among the base layers 501 , 503 , and 505 .
  • Each of the upper solder resist layer 562 and the lower solder resist layer 564 may be formed, for example, by spraying a solder mask insulating ink onto the upper surface of the uppermost layer and the lower surface of the lowermost layer, among the base layers 501 , 503 , and 505 , by a screen printing method or an inkjet printing method and curing the sprayed solder mask insulating ink by ultraviolet (UV) or infrared (IR) light.
  • UV ultraviolet
  • IR infrared
  • each of the upper solder resist layer 562 and the lower solder resist layer 564 may be formed, on the upper surface of the uppermost layer and the lower surface of the lowermost layer among the plurality of base layers 501 , 503 , and 505 , by entirely spraying a photo-imageable solder resist by a screen printing method or a spray coating method, or by attaching a film-type solder resist material by a laminating method, removing unnecessary parts by an exposure and development process, and curing the solder resist by using heat, UV light, or IR light.
  • the first wiring pattern 512 and the second wiring pattern 522 may have a zig-zag shape.
  • the first wiring pattern 512 may be formed to have zig-zags. In one example embodiment, where there is sufficient length The first wiring pattern 512 may be formed to have a different shape (e.g., straight or a non-zig-zag shape) when there is sufficient length or space.
  • the second wiring pattern 522 is shown to be straight. In one example embodiment, the second wiring pattern 522 may be formed to have a zig-zag shape, in order to reach a length that is substantially equal to a quarter of the wavelength of the signal transmitted from outside via the external connection terminal 600 .
  • the first wiring pattern 512 and the second wiring pattern 522 may be formed to have different or other shapes in other embodiments.
  • FIG. 3 illustrates an embodiment for transferring signals in the semiconductor package 1000 .
  • the signal transfer line 554 , the branch 555 , the first transfer line 510 , the second transfer line 520 , and the resistor unit 400 of the semiconductor package 1000 may form a Wilkinson divider 10 .
  • the relationship of the signal transfer line 554 , branch 555 , first transfer line 510 , second transfer line 520 , and resistor unit 400 of the semiconductor package 1000 is described below.
  • the Wilkinson divider 10 may include a branch I, an input line 13 , a plurality of transfer lines 15 _ 1 and 15 _ 2 , and a resistor 17 .
  • the Wilkinson divider 10 may receive a signal from a driver 11 and divide the signal to a plurality of output lines using lines of T-junction structure.
  • each of the transfer lines branched from the branch I may have an impedance of ⁇ square root over (2) ⁇ Z0.
  • the length of each of the transfer lines 15 _ 1 and 15 _ 2 may be substantially equal to a quarter of a wavelength ( ⁇ ) of the signal transmitted from the driver 11 .
  • the branch I may correspond to the branch 555 of FIG. 2A .
  • the transfer lines 15 _ 1 and 15 _ 2 may correspond to the first transfer line 510 and the second transfer line 520 of FIG. 2A .
  • the input line 13 may correspond to the signal transfer line 554 . Therefore, the signal transfer line 554 may have an impedance of Z0.
  • the first and second wiring patterns 511 and 522 and the first and second via structures 514 and 524 may be formed so that each of the first and second transfer lines 510 and 520 has an impedance of ⁇ square root over (2) ⁇ Z0 and a length equal to a quarter of the wavelength ( ⁇ ) of the transmitted signal.
  • a plurality of output terminals OP 1 _ 1 and OP 1 _ 2 may be connected to the resistor 17 .
  • the magnitude of the resistor 17 may be 2Z0.
  • a plurality of semiconductor chips 19 _ 1 and 19 _ 2 may be connected to each of the output terminals OP 1 _ 1 and OP 1 _ 2 .
  • the output terminals OP 1 _ 1 and OP 1 _ 2 may respectively correspond to the first pad 516 and the second pad 526 of FIG. 2A .
  • the resistor 17 and the semiconductor chips 19 _ 1 and 19 _ 2 may respectively correspond to the resistor unit 400 , the first semiconductor chip 100 , and the second semiconductor chip 200 of FIG. 2A .
  • One type of structure includes an on-die termination (ODT) at a plurality of output terminals to prevent unnecessary interference between signals output from the plurality of output terminals.
  • ODT on-die termination
  • the Wilkinson divider 10 does not form a line in addition to the transfer lines 15 _ 1 and 15 _ 2 connected to the plurality of semiconductor chips 19 _ 1 and 19 _ 2 .
  • impedance matching is performed using the plurality of transfer lines 15 _ 1 and 15 2 and the resistor 17 .
  • isolation characteristics between the output terminals OP 1 _ 1 and OP 1 _ 2 may be improved. This may offset distortion of a signal reflected by a semiconductor chip that is not selected between the semiconductor chips 19 _ 1 and 19 _ 2 .
  • the Wilkinson divider 10 includes two output terminals OP 1 _ 1 and OP 1 _ 2 and two semiconductor chips that are connected. In one embodiment, a different number of semiconductor chips may be connected.
  • FIG. 4 illustrates another embodiment of a semiconductor package 1000 A which may include a printed circuit board 500 a, the resistor unit 400 , the external connection terminal 600 , the first semiconductor chip 100 , and the second semiconductor chip 200 .
  • the first transfer line 510 , a second transfer line 520 a, and the signal transfer line 554 meet one another at the branch 555 in the printed circuit board 500 a.
  • the signal transferred by the signal transfer line 554 is distributed to the first transfer line 510 and the second transfer line 520 a based on the branch 555 and transferred to the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the first transfer line 510 may include the first via structure 514 penetrating through at least one layer of the printed circuit board 500 a, and the first wiring pattern 512 formed at the same layer level as that of the printed circuit board 500 a.
  • the second transfer line 520 a may include a second via structure 524 a penetrating through at least one layer of the printed circuit board 500 a, and a second wiring pattern 522 a formed at the same layer level as that of the printed circuit board 500 a.
  • the second wiring pattern 522 a may include a plurality of wiring patterns at different layer levels from one another.
  • the second wiring pattern 522 a may be formed throughout an upper surface of the second base layer 503 and an upper surface of the third base layer 505 .
  • the second via structure 524 a may be formed as a via structure penetrating through the first base layer 501 and a via structure penetrating through the second base layer 503 .
  • the first wiring pattern 512 may also include a plurality of wiring patterns at different layer levels from one another.
  • the first via structure 514 , the first wiring pattern 512 , the second via structure 514 , and the second wiring pattern 522 a may be formed so that the lengths of the first transfer line 510 and the second transfer line 520 may satisfy a quarter of the wavelength of the signal transmitted from outside.
  • FIG. 5 illustrates another embodiment of a semiconductor package 1000 B which may include the printed circuit board 500 , the resistor unit 400 , the external connection terminal 600 , the first semiconductor chip 100 , and the second semiconductor chip 200 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be sequentially stacked on the printed circuit board 500 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be stacked as stairs.
  • the first bonding wire 130 may not be embedded by a bonding layer 120 b.
  • the stair shape may be formed so that the pad 116 on the first semiconductor chip 100 may be exposed to outside.
  • FIG. 6 illustrates another embodiment of a semiconductor package 1000 C which may include a printed circuit board 500 c, a resistor unit 400 c, the external connection terminal 600 , the first semiconductor chip 100 , the second semiconductor chip 200 , and a third semiconductor chip 300 .
  • the first pad 516 , the second pad 526 , a third pad 536 c, a fourth pad 516 _ 1 , a fifth pad 526 _ 1 , and a sixth pad 536 c _ 1 may be on an upper surface of the printed circuit board 500 c.
  • a first transfer line, a second transfer line, and a third transfer line may meet one another at a branch formed in the printed circuit board 500 c.
  • the signals transferred through the external connection terminal 600 and the signal transfer line are distributed to the first transfer line, the second transfer line, and the third transfer line based on the branch, and transferred to the first semiconductor chip 100 , the second semiconductor chip 200 , and the third semiconductor chip 300 .
  • first transfer line, the second transfer line, and the third transfer line on the printed circuit board 500 c may be similar to forming a third transfer line in addition to the structure of the first transfer line 510 and the second transfer line 520 of FIG. 2A , the first transfer line 510 and the second transfer line 520 a of FIG. 4 , and the first transfer line 510 and the second transfer line 520 of FIG. 5 .
  • the signal transfer line electrically connects the branch to the external connection terminal 600 and may transfer the signal transmitted from outside via the external connection terminal 600 to the first semiconductor chip 100 , the second semiconductor chip 200 , and the third semiconductor chip 300 .
  • the first transfer line may electrically connect the branch to the first pad 516 .
  • the second transfer line may electrically connect the branch to the second pad 526 .
  • the third transfer line may electrically connect the branch to the third pad 536 c.
  • the first transfer line, the second transfer line, and the third transfer line may have lengths that are substantially equal to a quarter of the wavelength of the signal transmitted from outside and may have substantially the same impedance as one another.
  • the impedance of the resistor unit 400 c may be related to the impedance of the first transfer line, the second transfer line, and the third transfer line. This is to implement a structure of Wilkinson divider on the printed circuit board 500 c.
  • the printed circuit board 500 c may include a plurality of layers.
  • Each of the first transfer line, the second transfer line, and the third transfer line may include a via structure penetrating through at least one layer of the printed circuit board 500 c, and a wiring pattern formed at the same layer level of the printed circuit board 500 c.
  • the first semiconductor chip 100 , the second semiconductor chip 200 , and the third semiconductor chip 300 may be sequentially stacked on the printed circuit board 500 c.
  • a second bonding layer 220 is between the second semiconductor chip 200 and third semiconductor chip 300 in order to bond the second semiconductor chip 200 and the third semiconductor chip 300 and insulate the second semiconductor chip 200 and third semiconductor chip 300 from each other.
  • the third semiconductor chip 300 may include a plurality of pads 316 and 306 on an upper surface thereof. In one embodiment, the pads 316 and 306 may be on a lower surface of the third semiconductor chip 300 .
  • the first semiconductor chip 100 , the second semiconductor chip 200 , and the third semiconductor chip 300 may be mounted on the printed circuit board 500 c, for example, by a wire bonding method.
  • a first bonding wire 130 may electrically connect the first pad 516 to the first semiconductor chip 100 .
  • a second bonding wire 230 may electrically connect the second pad 526 to the second semiconductor chip 200 .
  • a third bonding wire 330 may electrically connect the third pad 536 c to the third semiconductor chip 300 .
  • the first semiconductor chip 100 , the second semiconductor chip 200 , and the third semiconductor chip 300 may be mounted on the printed circuit board 500 c, for example, by a flip-chip bonding method.
  • the resistor unit 400 c may be mounted on the printed circuit board 500 c.
  • the resistor unit 400 c may include first to third chip resistors 400 c _ 1 , 400 c _ 2 , and 400 c _ 3 , and a plurality of connection terminals may be formed in the resistor unit 400 c.
  • a first connection terminal of the first chip resistor 400 c _ 1 may be connected to the first pad 516 on the printed circuit board 500 c, and a second connection terminal of the first chip resistor 400 c _ 1 may be connected to the fourth pad 516 _ 1 on the printed circuit board 500 c.
  • a first connection terminal of the second chip resistor 400 c _ 2 may be connected to the second pad 526 on the printed circuit board 500 c, and a second connection terminal of the second chip resistor 400 c _ 2 may be connected to the fifth pad 526 _ 1 on the printed circuit board 500 c.
  • a first connection terminal of the third chip resistor 400 c _ 3 may be connected to the third pad 536 c on the printed circuit board 500 c, and a second connection terminal of the third chip resistor 400 c _ 3 may be connected to the sixth pad 536 c _ 1 on the printed circuit board 500 c.
  • the second connection terminal of the first chip resistor 400 c _ 1 may be electrically connected to the second pad 526 through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 c and a wiring pattern formed at the same layer level of the printed circuit board 500 c.
  • the second connection terminal of the second chip resistor 400 c _ 2 may be electrically connected to the third pad 536 c through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 c and a wiring pattern formed at the same layer level of the printed circuit board 500 c.
  • the second connection terminal of the third chip resistor 400 c _ 3 may be electrically connected to the first pad 516 through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 c and a wiring pattern formed at the same layer level of the printed circuit board 500 c.
  • the first to third chip resistors 400 c _ 1 , 400 c _ 2 , and 400 c _ 3 may have substantially the same impedance values.
  • the resistance values may vary in a case where the same effect may be obtained from another equivalent circuit of different structure and a plurality of resistors included in the resistor unit 400 c may have different connecting structures.
  • FIG. 7 illustrates an embodiment for transferring signals in a semiconductor package 1000 C.
  • the signal transfer lines, the branch, the first transfer line, the second transfer line, the third transfer line, and the resistor unit 400 c of semiconductor package 1000 C may form a Wilkinson divider 20 .
  • the Wilkinson divider 20 may include a branch I, an input line 13 , a plurality of transfer lines 25 _ 1 , 25 _ 2 , and 25 _ 3 , and a plurality of resistors 27 _ 1 , 27 _ 2 , and 27 _ 3 .
  • each of the transfer lines 25 _ 1 , 25 _ 2 , and 25 _ 3 divided at the branch I may have substantially the same impedance, that is, ⁇ square root over (3) ⁇ Z0.
  • the length of each of the transfer lines 25 _ 1 , 25 _ 2 , and 25 _ 3 may be substantially equal to a quarter of the wavelength ( ⁇ ) of the signal transmitted from the driver 11 .
  • the branch I may correspond to the branch in the printed circuit board 500 c.
  • the transfer lines 25 _ 1 , 25 _ 2 , and 25 _ 3 may correspond to the first to third transfer lines in the printed circuit board 500 c.
  • the input lint 13 may correspond to the signal transfer line in the printed circuit board 500 c.
  • Output terminals OP 2 _ 1 , OP 2 _ 2 , and OP 2 _ 3 may be connected to the resistors 27 _ 1 , 27 _ 2 , and 27 _ 3 .
  • the first resistor 27 _ 1 may have opposite ends connected to the first output terminal OP 2 _ 1 and the second output terminal OP 2 _ 2 .
  • the second resistor 27 _ 2 may have opposite ends connected to the second output terminal OP 2 _ 2 and the third output terminal OP 2 _ 3 .
  • the third resistor 27 _ 3 may have opposite ends connected to the third output terminal OP 2 _ 3 and the first output terminal OP 2 _ 1 .
  • Each of the resistors 27 _ 1 , 27 _ 2 , and 27 _ 3 may have a resistance value of 3Z0.
  • the resistors 27 _ 1 , 27 _ 2 , and 27 _ 3 may configure another equivalent circuit to exhibit the same effects.
  • connecting structures between the resistors 27 _ 1 , 27 _ 2 , and 27 _ 3 and the output terminals OP 2 _ 1 , OP 2 _ 2 , and OP 2 _ 3 may vary, and impedance values of the resistors 27 _ 1 , 27 _ 2 , and 27 _ 3 may vary.
  • a plurality of semiconductor chips 29 _ 1 , 29 _ 2 , and 29 _ 3 may be connected respectively to the output terminals OP 2 _ 1 , OP 2 _ 2 , and OP 2 _ 3 .
  • the output terminals OP 2 _ 1 , OP 2 _ 2 , and OP 2 _ 3 may correspond to the first to third pads 516 , 526 , and 536 c of FIG. 6 .
  • the resistors 27 _ 1 , 27 _ 2 , and 27 _ 3 and the semiconductor chips 29 _ 1 , 29 _ 2 , and 29 _ 3 may respectively correspond to the resistor unit 400 c and the first to third semiconductor chips 100 , 200 , and 300 of FIG. 6 .
  • the Wilkinson divider 20 does not necessarily form additional lines besides the transfer lines 25 _ 1 , 25 _ 2 , and 25 _ 3 connected to the semiconductor chips 29 _ 1 , 29 _ 2 , and 29 _ 3 . Thus, unnecessary power consumption may be reduced.
  • impedance matching may be performed using the transfer lines 25 _ 1 , 25 _ 2 , and 25 _ 3 and the resistors 27 _ 1 , 27 _ 2 , and 27 _ 3 , and distortion of the signal reflected by a semiconductor chip that is not selected from among the semiconductor chips 29 _ 1 , 29 _ 2 , and 29 _ 3 may be offset.
  • FIG. 8 illustrates another embodiment of a semiconductor package 1000 D
  • FIG. 9 illustrates view taken along section line B-B′ in FIG. 8
  • the semiconductor package 1000 D may include a printed circuit board 500 d, a resistor unit 400 d, the external connection terminal 600 , the first semiconductor chip 100 , and the second semiconductor chip 200 .
  • a plurality of pads 516 d, 526 d, and 506 d including a first pad 516 d and a second pad 526 d may be formed on an upper surface of the printed circuit board 500 d.
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the same plane of the printed circuit board 500 d.
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500 d, for example, by a wire bonding method. Therefore, the semiconductor package 1000 D may include a first bonding wire 130 electrically connecting the first pad 516 d of the printed circuit board 500 d to the first semiconductor chip 100 , and a second bonding wire 230 connecting the second pad 526 d of the printed circuit board 500 d to the second semiconductor chip 200 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500 d, for example, by a flip-chip bonding method.
  • the resistor unit 400 d may be mounted on the printed circuit board 500 d.
  • the resistor unit 400 d may include a plurality of connection terminals including a first connection terminal 401 d and a second connection terminal 402 d.
  • the first connection terminal 401 d of the resistor unit 400 d is connected to the first pad 516 d on the printed circuit board 500 d.
  • the second connection terminal 402 d of the resistor unit 400 d may be connected to the second pad 526 d on the printed circuit board 500 d.
  • the resistor unit 400 d may be implemented as at least one chip resistor and may be mounted so that opposite ends of the resistor unit 400 d may contact the first pad 516 d and the second pad 526 d.
  • the resistor unit 400 d may be on a region between the first semiconductor chip 100 and the second semiconductor chip 200 on the printed circuit board 500 d.
  • the printed circuit board 500 d may include a plurality of base layers 501 , 503 , and 505 stacked with one another.
  • the first pad 516 d and the second pad 526 d are on an upper surface of the uppermost layer from among the base layers 501 , 503 , and 505 .
  • /A lower pad 556 d may be on a lower surface of the lowermost layer from among the base layers 501 , 503 , and 505 .
  • the lower pad 556 d may be formed, for example, on a peripheral region surrounding a center region of the printed circuit board 500 d. According to formation of a first transfer line 510 d, a second transfer line 520 d, and a signal transfer line 554 d, the lower pad 556 d may be formed on the center region of the printed circuit board 500 d.
  • the first transfer line 510 d, the second transfer line 520 d, and the signal transfer line 554 d meet one another at a branch 555 d formed in the printed circuit board 500 d.
  • the signal transfer line 554 d electrically connects the branch 555 d to the external connection terminal 600 , so that a signal transmitted from outside via the external connection terminal 600 may be transferred to the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the first transfer line 510 d and the second transfer line 520 d may be electrically isolated from each other at the branch 555 d.
  • the first transfer line 510 d may electrically connect the branch 555 d to the first pad 516 d.
  • the first transfer line 510 d may include a first via structure 514 d penetrating through at least one layer of the printed circuit board 500 d, and a first wiring pattern 512 d formed at the same layer level as that of the printed circuit board 500 d.
  • the second transfer line 520 d may electrically connect the branch 555 d to the second pad 526 d.
  • the second transfer line 520 d may include a second via structure 524 d penetrating through at least one layer of the printed circuit board 500 d, and a second wiring pattern 522 d at the same layer level as that of the printed circuit board 500 d.
  • the first transfer line 510 d and the second transfer line 520 d may have substantially the same lengths as each other.
  • the lengths of the first transfer line 510 d and the second transfer line 520 d may be substantially equal to a quarter of the wavelength of the signal transmitted from outside via the external connection terminal 600 .
  • the first transfer line 510 d and the second transfer line 520 d may have substantially the same impedance as each other.
  • the first wiring pattern 512 d and the second wiring pattern 522 d may be at different layer levels from each other. In a case where there is a space sufficient to form both the first wiring pattern 512 d and the second wiring pattern 522 d at the same layer of the printed circuit board 500 d, the lengths of the first transfer line 510 d and the second transfer line 520 d may satisfy a quarter of the wavelength of the signal transmitted from outside and the first wiring pattern 512 d and the second wiring pattern 522 d may be formed at the same layer.
  • the first wiring pattern 512 d and the second wiring pattern 522 d may include a plurality of wiring patterns at different layers from each other.
  • the second wiring pattern 522 d may be formed throughout an upper surface of the second base layer 503 and an upper surface of the third base layer 505 .
  • the second via structure 524 d may be formed as a via structure penetrating through the first base layer 501 and a via structure penetrating through the second base layer 503 .
  • At least one of the first wiring pattern 512 d and the second wiring pattern 522 d may have zig-zags similar to the first wiring pattern 512 in FIG. 2B .
  • the first wiring pattern 512 d may have zig-zags so that the first transfer line 510 d has a length substantially equal to a quarter the wavelength of the received signal.
  • the first wiring pattern 512 d may be formed straight or may have a non-zig-zag shape.
  • the lower pad 556 d may be, for example, on the peripheral region surrounding the center region of the printed circuit board 500 d. According to formation of the first transfer line 510 d, the second transfer line 520 d, and the signal transfer line 554 d, the lower pad 556 d may be on the center region of the printed circuit board 500 d.
  • FIG. 10 illustrates another embodiment of a semiconductor package 1000 E which may include a printed circuit board 500 e, a resistor unit 400 e, the external connection terminal 600 , the first semiconductor chip 100 , the second semiconductor chip 200 , and the third semiconductor chip 300 .
  • the first pad 516 d, the second pad 526 d, a third pad 536 e, a fourth pad 516 d _ 1 , a fifth pad 526 d _ 1 and a sixth pad 536 e _ 1 may be on an upper surface of the printed circuit board 500 e.
  • a first transfer line, a second transfer line, and a third transfer line may meet one another at a branch formed in the printed circuit board 500 e.
  • the first transfer line, the second transfer line, and the third transfer line may be electrically isolated from one another at the branch.
  • first transfer line, the second transfer line, and the third transfer line on the printed circuit board 500 e may be similar to forming the third transfer line in addition to the structure including the first transfer line 510 d and the second transfer line 520 d of FIG. 9 .
  • the signal transfer line electrically connects the branch to the external connection terminal 600 and may transfer the signal transmitted from outside via the external connection terminal 600 to the first semiconductor chip 100 , the second semiconductor chip 200 , and the third semiconductor chip 300 .
  • the first transfer line may electrically connect the branch to the first pad 516 d.
  • the second transfer line may electrically connect the branch to the second pad 526 d.
  • the third transfer line may electrically connect the branch to the third pad 536 e.
  • the first transfer line, the second transfer line, and the third transfer line may have lengths substantially equal to a quarter of the wavelength of the signal transmitted from outside and may have substantially the same impedance as one another. As described above with reference to FIG. 7 , when an input line connected to the branch in the printed circuit board 500 e has a resistance value of Z0, each of the first, second, and third transfer lines may have a resistance value of ⁇ square root over (3) ⁇ Z0.
  • the printed circuit board 500 e may include a plurality of layers.
  • the third transfer line may include a via structure penetrating at least one layer of the printed circuit board 500 e and a wiring pattern at the same layer as the via structure in the printed circuit board 500 e.
  • the third semiconductor chip 300 may be stacked on the second semiconductor chip 200 .
  • the second semiconductor chip 200 and the third semiconductor chip 300 may be stacked as stairs or may be stacked to be aligned with each other in a direction perpendicular to an upper surface of the printed circuit board 500 e.
  • the third semiconductor chip 300 may be mounted on the same plane as those of the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the third semiconductor chip 300 may be mounted on the printed circuit board 500 e, for example, by a wire bonding method.
  • a first bonding wire 130 may electrically connect the first pad 516 d to the first semiconductor chip 100 .
  • a second bonding wire 230 may electrically connect the second pad 526 d to the second semiconductor chip 200 .
  • the third bonding wire 330 may electrically connect the third pad 536 e to the third semiconductor chip 300 .
  • the first semiconductor chip 100 , the second semiconductor chip 200 , and the third semiconductor chip 300 may be mounted on the printed circuit board 500 e, for example, by a flip-chip bonding method.
  • the resistor unit 400 e may be mounted on the printed circuit board 500 e.
  • the resistor unit 400 e may include first to third chip resistors 400 e _ 1 , 400 e _ 2 , and 400 e _ 3 , and may include a plurality of connection terminals.
  • a first connection terminal of the first chip resistor 400 e _ 1 may be connected to the first pad 516 d on the printed circuit board 500 e, and a second connection terminal of the first chip resistor 400 e _ 1 may be connected to the fourth pad 516 d _ 1 on the printed circuit board 500 e.
  • a first connection terminal of the second chip resistor 400 e _ 2 may be connected to the second pad 526 d on the printed circuit board 500 e, and a second connection terminal of the second chip resistor 400 e _ 2 may be connected to the fifth pad 526 d _ 1 on the printed circuit board 500 e.
  • a first connection terminal of the third chip resistor 400 e _ 3 may be connected to the third pad 536 e on the printed circuit board 500 e, and a second connection terminal of the third chip resistor 400 e _ 3 may be connected to the sixth pad 536 e _ 1 on the printed circuit board 500 e.
  • the second connection terminal of the first chip resistor 400 e _ 1 may be electrically connected to the second pad 526 d through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 e and a wiring pattern formed at the same layer level of the printed circuit board 500 e.
  • the second connection terminal of the second chip resistor 400 e _ 2 may be electrically connected to the third pad 536 e through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 e and a wiring pattern formed at the same layer level of the printed circuit board 500 e.
  • the second connection terminal of the third chip resistor 400 e _ 3 may be electrically connected to the first pad 516 d through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 e and a wiring pattern formed at the same layer level of the printed circuit board 500 e.
  • the first to third chip resistors 400 e _ 1 , 400 e _ 2 , and 400 e _ 3 may have substantially the same impedance values. As described above with reference to FIG. 7 . each of the first to third chip resistors 400 e _ 1 , 400 e _ 2 , and 400 e _ 3 may have a resistance value of 3Z0. In one or more embodiments, the resistance values may vary in a case where the same effect may be obtained from another equivalent circuit of different structure and a plurality of resistors included in the resistor unit 400 e may have different connecting structures.
  • FIG. 11A illustrates another embodiment of a semiconductor package 1000 F
  • FIG. 11B illustrates an embodiment of a power distribution device 700 in a semiconductor package.
  • the semiconductor package 1000 F may include a printed circuit board 500 f, the first semiconductor chip 100 , the second semiconductor chip 200 , and the power distribution device 700 .
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be sequentially stacked on the printed circuit board 500 f.
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be stacked as stairs or may be stacked to be aligned with each other in a direction perpendicular to an upper surface of the printed circuit board 500 f.
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the same plane of the printed circuit board 500 f.
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500 f, for example, by a wire bonding method.
  • one or more semiconductor chips may be mounted on the printed circuit board 500 f.
  • the mounted semiconductor chips may be respectively connected to power distribution device 700 .
  • a first rewiring layer and a second rewiring layer may be respectively formed on upper surfaces of the first semiconductor chip 100 and the second semiconductor chip 200 .
  • a first bonding wire 130 f connecting the first semiconductor chip 100 to the power distribution device 700 may be electrically connected to the first rewiring layer.
  • a second bonding wire 230 f connecting the second semiconductor chip 200 to the power distribution device 700 may be electrically connected to the second rewiring layer.
  • a plurality of wiring patterns 532 may be on an upper surface and a lower surface of each of the base layers 501 , 503 , and 505 .
  • the wiring patterns 532 may include, for example, ED copper foil, RA copper foil, stainless steel foil, aluminum foil, ultra-thin copper foil, sputtered copper, copper alloys, etc.
  • the printed circuit board 500 f may include a plurality of via structures penetrating through at least one of the plurality of base layers 501 , 503 , and 505 .
  • the via structures 534 may include copper, nickel, stainless steel, or beryllium copper.
  • the power distribution device 700 may be mounted on the printed circuit board 500 f, for example, by a wire bonding method.
  • the power distribution device 700 may receive a signal from the printed circuit board 500 f via a bonding wire 730 connected to upper pad 538 .
  • the power distribution device 700 may transfer the signal respectively to the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the power distribution device 700 may block a distortion signal reflected by the second semiconductor chip 200 .
  • the power distribution device 700 may prevent signal interference between the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the power distribution device 700 may have a Wilkinson divider structure. Therefore, interference between the semiconductor chips 100 and 200 on the semiconductor package 1000 F may be prevented, and reliability of the signals transferred to the semiconductor chips 100 and 200 may be ensured. Also, since the ODT is not used, unnecessary power consumption may be reduced.
  • the power distribution device 700 may be implemented as a semiconductor package.
  • the power distribution device 700 may include a plurality of insulating layers 702 and 704 , an input terminal 756 , a first output terminal 716 , a second output terminal 726 , a resistor unit 740 , a signal transfer line 750 , a first transfer line 710 , and a second transfer line 720 .
  • Each of the insulating layers 702 and 704 may include the same material as the base layers 501 , 503 , and 505 .
  • Two insulating layers 702 and 704 are formed in the present embodiment, but one insulating layer or three or more insulating layers may be formed in other embodiments.
  • a solder resist layer 762 may be at the uppermost layer between the insulating layers 702 and 704 .
  • the solder resist layer 762 may be formed in a similar way to forming of an upper solder resist layer 562 and a lower solder resist layer 564 .
  • the input terminal 756 , the first output terminal 716 , and the second output terminal 726 may be on an upper surface of the uppermost layer between the insulating layers 702 and 704 . In one embodiment, the input terminal 756 , the first output terminal 716 , and the second output terminal 726 may be on a lower surface of the lowermost layer between the insulating layers 702 and 704 .
  • the input terminal 756 may receive a signal from the printed circuit board 500 f.
  • the first output terminal 716 may transmit the signal to the first semiconductor chip 100 via a first bonding wire 130 f.
  • the second output terminal 726 may transmit the signal to the second semiconductor chip 200 via a second bonding wire 230 f.
  • the input terminal 756 , the first output terminal 716 , and the second output terminal 726 may be implemented as pads exposed from the solder resist layer 762 .
  • the power distribution device 700 may include one or more output terminals.
  • the one or more output terminals and the one or more semiconductor chips may be connected in one-to-one correspondence.
  • a metal layer may be further formed on each of the input terminal 756 , the first output terminal 716 , and the second output terminal 726 .
  • the metal layer may be formed by a hot air solder leveling (H.A.S.L.), a Ni/Au plating method, etc.
  • the first transfer line 710 , the second transfer line 720 , and the signal transfer line 750 meet one another at a branch 755 . Therefore, the first transfer line 710 and the second transfer line 720 may be electrically isolated from each other at the branch 755 .
  • the signal transfer line 750 electrically connects the branch 755 to the input terminal 756 , to transfer the signal from the printed circuit board 500 f to the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the signal received by the input terminal 756 may be transferred to the power distribution device 700 along the signal transfer line 750 .
  • the signal is distributed to the first transfer line 710 and second transfer line 720 based on the branch 755 and transferred to the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the signal transfer line 750 may include a vertical structure 754 penetrating through at least one of the insulating layers 702 and 704 and a horizontal structure 752 at the same layer level as that of the insulating layers 702 and 704 .
  • the first transfer line 710 may electrically connect the branch 755 to the first output terminal 716 .
  • the first transfer line 710 may include a first via structure 714 penetrating through at least one of the insulating layers 702 and 704 , and a first wiring pattern 712 formed at the same layer level as that of the insulating layers 702 and 704 .
  • the second transfer line 720 may electrically connect the branch 755 to the second output terminal 726 .
  • the second transfer line 720 may include a second via structure 724 penetrating through at least one of the insulating layers 702 and 704 , and a second wiring pattern 722 formed at the same insulating layer between the insulating layers 702 and 704 .
  • the first transfer line 710 and second transfer line 720 may have substantially the same lengths as each other.
  • the lengths of the first transfer line 710 and the second transfer line 720 may be substantially equal to a quarter of the wavelength of the signal received by the input terminal 756 .
  • the first transfer line 710 and the second transfer line 720 may have substantially the same impedance as each other.
  • the lengths and the impedance of the first transfer line 710 and the second transfer line 720 may be adjusted to satisfy conditions of the Wilkinson divider.
  • At least one of the first wiring pattern 712 or the second wiring pattern 722 may have zig-zags similar to the first wiring pattern 512 in FIG. 2B .
  • the first wiring pattern 712 may have zig-zags. In a case where there is sufficient length or space, the first wiring pattern 712 may be straight or may have a non-zig-zag shape.
  • the resistor unit 740 may include a plurality of connection terminals, e.g., a first connection terminal 741 and a second connection terminal 742 .
  • the first connection terminal 741 of the resistor unit 740 may be connected to the first output terminal 716 .
  • the second connection terminal 742 of the resistor unit 740 may be connected to the second output terminal 726 .
  • the resistor unit 740 may be implemented as at least one chip resistor and may be mounted so that opposite ends of the resistor unit 740 contact the first output terminal 716 and the second output terminal 726 .
  • the resistor unit 740 may include a plurality of chip resistors that have impedance values substantially equal to one another. The impedance of the resistor unit 740 may be adjusted, for example, to satisfy the conditions of the Wilkinson divider.
  • FIG. 12A illustrates another embodiment of a semiconductor package 1000 G
  • FIG. 12B illustrates an embodiment of of a power distribution device 700 g in the semiconductor package 1000 G.
  • the semiconductor package 1000 G may include the printed circuit board 500 f, the first semiconductor chip 100 , the second semiconductor chip 200 , and the power distribution device 700 g.
  • the first semiconductor chip 100 may be mounted on the printed circuit board 500 f via a first bump 140 .
  • the second semiconductor chip 200 may be mounted on the first semiconductor chip 100 via a second bump 240 , for example, by a flip-chip bonding method.
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be stacked as stairs or may be stacked and aligned with each other in a direction perpendicular to an upper surface of the printed circuit board 500 f.
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the same plane of the printed circuit board 500 f, for example, by the flip-chip bonding method.
  • One or more semiconductor chips, in addition to the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500 f and respectively connected to the power distribution device 700 g.
  • the power distribution device 700 g may be mounted on the printed circuit board 500 f, for example, by a flip-chip bonding method.
  • the power distribution device 700 g may receive a signal from the printed circuit board 500 f via a bump 760 contacting the upper pad 538 .
  • the power distribution device 700 g may transfer the signal from the printed circuit board 500 f to the first semiconductor chip 100 and the second semiconductor chip 200 .
  • the power distribution device 700 g may have, for example, a Wilkinson divider structure.
  • the power distribution device 700 g may include a plurality of insulating layers 702 and 704 , an input terminal 756 , a first output terminal 716 , a second output terminal 726 , a resistor unit 740 , a signal transfer line 750 , a first transfer line 710 , a second transfer line 720 , and a bump 760 .
  • Solder resist layers 762 and 764 may be respectively formed on an upper surface of the uppermost layer and a lower surface of the lowermost layer between the insulating layers 702 and 704 .
  • the input terminal 756 receives the signal transmitted from the printed circuit board 500 f via the bump 760 and transfers the signal to the signal transfer line 750 .
  • the signal may be divided at the branch 755 and transferred to the first semiconductor chip 100 and the second semiconductor chip 200 .
  • FIG. 13 illustrates an embodiment of a system 1200 including a semiconductor package.
  • the system 1200 includes a controller 1210 , an input/output device 1220 , a memory 1230 , and an interface 1240 .
  • the system 1200 may be a mobile system or a system transmitting/receiving information.
  • the mobile system may include a personal digital assistant (PDA), a portable computer, a Web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card.
  • PDA personal digital assistant
  • the controller 1210 controls execution programs in the system 1200 and may include a microprocessor, a digital signal processor, a microcontroller, or a similar device.
  • the input/output device 1220 may be used to input/output data into/from the system 1200 .
  • the system 1200 may be connected to an external device, e.g., a personal computer or network, via the input/output device 1220 , and may exchange data with the external device.
  • the input/output device 1220 may be, for example, a keypad, a keyboard, or a display.
  • the memory 1230 may store codes and/or data for operating the controller 1210 , or data processed by the controller 1210 .
  • the memory 1230 may include a semiconductor package according to an embodiment.
  • the memory 1230 may include the semiconductor package 1000 , 1000 A, 1000 B, 1000 C, 1000 D, 1000 E, 1000 F, or 1000 G exemplarily shown in FIGS. 1 to 12A .
  • the interface 1240 may be a data transmission path between the system 1200 and an external device.
  • the controller 1210 , the input/output device 1220 , the memory 1230 , and the interface 1240 may communicate with one another via a bus 1250 .
  • the system 1200 may be used, for example, in a mobile phone, an MP3 player, a navigation system, a portable multimedia player (PMP), a solid state disk (SSD), or household appliances.
  • the methods, processes, and/or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device.
  • the computer, processor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.
  • the processors, controllers, and other signal generating and signal processing features of the embodiments disclosed herein may be implemented in logic which, for example, may include hardware, software, or both.
  • the processors, controllers, and other signal generating and signal processing features may be, for example, any one of a variety of integrated circuits including but not limited to an application-specific integrated circuit, a field-programmable gate array, a combination of logic gates, a system-on-chip, a microprocessor, or another type of processing or control circuit.
  • the processors, controllers, and other signal generating and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device.
  • the computer, processor, microprocessor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.

Abstract

A semiconductor package includes a printed circuit board, a resistor circuit, and first and second semiconductor chips. First and second pads are on a first surface of the printed circuit board, and external connection terminal is on a second surface of the printed circuit board. The resistor circuit has a first connection terminal connected to the first pad and a second connection terminal connected to the second pad. The first semiconductor chip is connected to the first pad and the second semiconductor chip is stacked on the first semiconductor chip and connected to the second pad. The printed circuit board includes a signal transfer line connecting a branch in the printed circuit board to the external connection terminal. A first transfer line connects the branch to the first pad. A second transfer line connects the branch to the second pad.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • Korean Patent Application No. 10-2016-0154452, filed on Nov. 18, 2016, and entitled: “Semiconductor Package,” is incorporated by reference herein in its entirety.
    • BACKGROUND 1. Field
  • One or more embodiments described herein relate to a semiconductor package.
    • 2. Description of the Related Art
  • Electronic devices are designed to be smaller and with greater functionality. As a result, there is a demand for large-capacity and multi-functional semiconductor chips. These chips may be incorporated within various semiconductor packages.
    • SUMMARY
  • In accordance with one or more embodiments, a semiconductor package includes a printed circuit board having a lower surface and an upper surface, the upper surface including a first pad and a second pad; an external connection terminal on the lower surface of the printed circuit board; a resistor circuit including a first connection terminal and a second connection terminal, the first connection terminal connected to the first pad and the second connection terminal is connected to the second pad; a first semiconductor chip mounted on the printed circuit board and connected to the first pad; and a second semiconductor chip stacked on the first semiconductor chip and connected to the second pad, wherein the printed circuit board includes: a signal transfer line that connects a branch in the printed circuit board to the external connection terminal; a first transfer line that connects the branch to the first pad; and a second transfer line that connects the branch to the second pad.
  • In accordance with one or more other embodiments, a semiconductor package includes a printed circuit board including a lower surface and an upper surface, the upper surface including a first pad and a second pad; an external connection terminal on the lower surface of the printed circuit board; a resistor circuit including a first connection terminal and a second connection terminal, the first connection terminal connected to the first pad and the second connection terminal connected to the second pad; a first semiconductor chip mounted on the printed circuit board and connected to the first pad; and a second semiconductor chip mounted on the printed circuit board and connected to the second pad, the first semiconductor chip and the second semiconductor chip mounted on a same plane of the printed circuit board, wherein the printed circuit board includes: a signal transfer line that connects a branch in the printed circuit board to the external connection terminal; a first transfer line that connects the branch to the first pad; and a second transfer line that connects the branch to the second pad.
  • In accordance with one or more other embodiments, a semiconductor package includes a printed circuit board; a first semiconductor chip and a second semiconductor chip mounted on the printed circuit board; and a power distribution device mounted on the printed circuit board and including: an input terminal to receive a signal; a first output terminal and a second output terminal to output a signal; a resistor circuit including a first connection terminal connected to the first output terminal and a second connection terminal connected to the second output terminal; a signal transfer line that connects a branch in the power distribution device to the input terminal; a first transfer line that connects the branch to the first connection terminal; and a second transfer line that connects the branch to the second connection terminal.
  • In accordance with one or more other embodiments, a semiconductor package includes a printed circuit board; a first semiconductor chip on the printed circuit board; a second semiconductor chip on the first semiconductor chip; and a resistor circuit including a first connection terminal connected to a first output terminal and a second connection terminal connected to a second output terminal, wherein the resistor circuit has a Wilkerson divider structure.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:
  • FIG. 1 illustrates an embodiment of a semiconductor package;
  • FIG. 2A illustrates a view along section line A-A′ in FIG. 1, and FIG. 2B illustrates an embodiment of a printed circuit board in the semiconductor package;
  • FIG. 3 illustrates an embodiment for transferring signals in a semiconductor package;
  • FIG. 4 illustrates another embodiment of a semiconductor package;
  • FIG. 5 illustrates another embodiment of a semiconductor package;
  • FIG. 6 illustrates another embodiment of a semiconductor package;
  • FIG. 7 illustrates another embodiment for transferring signals in a semiconductor package;
  • FIG. 8 illustrates another embodiment of a semiconductor package;
  • FIG. 9 illustrates a view of the semiconductor package in FIG. 8 along section line B-B′;
  • FIG. 10 illustrates another embodiment of a semiconductor package;
  • FIG. 11A illustrates another embodiment of a semiconductor package, and FIG. 11B illustrates an embodiment of a power distribution device;
  • FIG. 12A illustrates another embodiment of a semiconductor package, and FIG. 12B illustrates another embodiment of a power distribution device; and
  • FIG. 13 illustrates an embodiment of a semiconductor package.
    •  DETAILED DESCRIPTION
  • FIG. 1 illustrates an embodiment of a semiconductor package 1000 which may include a printed circuit board 500, a resistor unit 400, a first semiconductor chip 100, and a second semiconductor chip 200. The semiconductor package 1000 may further include external connection terminals 600 on a lower surface of the printed circuit board 500. A plurality of pads 516, 526, and 506 including a first pad 516 and a second pad 526 may be on an upper surface of the printed circuit board 500.
  • The first semiconductor chip 100 and the second semiconductor chip 200 are stacked on the printed circuit board 500 and may be sequentially mounted. The first semiconductor chip 100 has an upper surface which may include a plurality of pads 116 and 106. The second semiconductor chip 200 has an upper surface which may include a plurality of pads 216 and 206. In one example embodiment, the pads 116, 106, 216, and 206 may be on lower surfaces of the first semiconductor chip 100 and the second semiconductor chip 200.
  • The first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500, for example, by a wire bonding method. Therefore, the semiconductor package 1000 may include a first bonding wire 130 and a second bonding wire 230. The first bonding wire 130 may electrically connect the first pad 516 of the printed circuit board 500 to the first semiconductor chip 100. The second bonding wire 230 may electrically connect the second pad 526 of the printed circuit board 500 to the second semiconductor chip 200. In one example embodiment, the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500, for example, by a flip-chip bonding method.
  • The first semiconductor chip 100 and the second semiconductor chip 200 may include semiconductor devices, e.g., a plurality of individual devices of various kinds. The individual devices may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor (CMOS) transistor, a system large scale integration (LSI), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, a passive device, etc. The individual devices may be electrically connected to a conductive region of the semiconductor substrate, where the first semiconductor chip 100 and the second semiconductor chip 200 are mounted. Active surfaces of the first and second semiconductor chips 100 and 200, where the individual devices are on the active surfaces, may face opposite the printed circuit board 500.
  • In some embodiments, each of the first semiconductor chip 100 and the second semiconductor chip 200 may be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM).
  • The resistor unit 400 may be mounted on the printed circuit board 500 and may include a plurality of connection terminals. The connection terminals may include a first connection terminal and a second connection terminal. The first connection terminal of the resistor unit 400 may be connected to the first pad 516 on the printed circuit board 500. The second connection terminal of the resistor unit 400 may be connected to the second pad 526 on the printed circuit board 500. For example, the resistor unit 400 may be a resistor circuit, and the resistor circuit may include at least one resistor. For example, the resistor unit 400 may be implemented as at least one chip resistor, and may be mounted so that opposite ends of the resistor unit 400 contact the first pad 516 and the second pad 526. The first semiconductor chip 100 and the second semiconductor chip 200 are mounted on a center portion of the printed circuit board 500. The resistor unit 400 may be mounted, for example, on a peripheral portion of the printed circuit board 500 which surrounds the center portion.
  • FIG. 2A illustrates a cross-sectional view of the semiconductor package 1000 taken along a line A-A′ of FIG. 1. FIG. 2B is a top view illustrating part of an upper surface of the printed circuit board 500 in the semiconductor package 1000.
  • Referring to FIG. 2A, the semiconductor package 1000 may include the printed circuit board 500, the resistor unit 400, the first semiconductor chip 100, the second semiconductor chip 200, and the external connection terminals 600 formed on a lower surface of the printed circuit board 500. The first semiconductor chip 100 and the second semiconductor chip 200 may be sequentially stacked on the printed circuit board 500. The first semiconductor chip 100 and the second semiconductor chip 200 may be stacked and aligned with each other in a direction perpendicular to the upper surface of the printed circuit board 500. The resistor unit 400 may be mounted so that opposite ends of the resistor unit 400 contact the first pad 516 and the second pad 526. A first connection terminal 401 of the resistor unit 400 contact the first pad 516, and a second connection terminal 402 of the resistor unit 400 contact the second pad 526.
  • A bonding layer 120 may be between the first semiconductor chip 100 and the second semiconductor chip 200. The first semiconductor chip 100 and the second semiconductor chip 200 may be bonded to each other via the bonding layer 120. Part of the first bonding wire 130 may be embedded by the bonding layer 120.
  • A first rewiring layer and a second rewiring layer may be respectively formed on upper surfaces of the first semiconductor chip 100 and the second semiconductor chip 200. The first bonding wire 130 connected to the first semiconductor chip 100 may be electrically connected to the first rewiring layer. The second bonding wire 230 connected to the second semiconductor chip 200 may be electrically connected to the second rewiring layer. Therefore, the pads 116, 106, 216, and 206 on the upper surfaces of the first semiconductor chip 100 and the second semiconductor chip 200 may be arranged in the first rewiring layer and the second rewiring layer.
  • The printed circuit board 500 may include a plurality of layers, in which a plurality of base layers 501, 503, and 505 are stacked. In some embodiments, each of the base layers 501, 503, and 505 may include at least one of a phenol resin, an epoxy resin, and polyimide. For example, each of the base layers 501, 503, and 505 may include at least one of frame retardant 4 (FR4), tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, polyimide, and liquid crystal polymer. FIG. 2A shows three base layers 501, 503, and 505, but a different number (e.g., two, four or more) base layers may be formed in another embodiment.
  • The first pad 516 and the second pad 526 are on an upper surface of the uppermost layer from among the base layers 501, 503, and 505. A lower pad 556 may be on a lower surface of the lowermost layer from among the base layers 501, 503, and 505. The lower pad 556 may contact the external connection terminal 600 to receive a signal from the external connection terminal 600. The lower pad 556 is shown to be formed at a center portion of the printed circuit board 500, but may be at different location in another embodiment. According to formation of a first transfer line 510 a second transfer line 520, and a signal transfer line 554, the lower pad 556 may be on the peripheral region surrounding the center region of the printed circuit board 500.
  • A metal layer may be further formed on each of the first pad 516, the second pad 526, and the lower pad 556. The metal layer may be formed to improve an adhesive force of each of the first pad 516, the second pad 526, and the lower pad 556, and to reduce contact resistance. The metal layer may be formed, for example, by a hot air solder leveling (H.A.S.L.) method, a Ni/Au plating method, or another method.
  • A branch 555 where the first transfer line 510, the second transfer line 520, and the signal transfer line 554 meet one another may be formed in the printed circuit board 500. The signal transfer line 554 electrically connects the branch 555 to the external connection terminal 600, so that a signal transmitted from outside via the external connection terminal 600 may be transferred to the first semiconductor chip 100 and the second semiconductor chip 200. The signal may be distributed to the first transfer line 510 and the second transfer line 520 based on the branch 555 and transferred to the first semiconductor chip 100 and the second semiconductor chip 200. In FIG. 2A, the signal transfer line 554 has a via structure and may include a conductive line at the same layer level. The signal transfer line 554 may have a different structure in another embodiment.
  • The first transfer line 510 may electrically connect the branch 555 to the first pad 516. The first transfer line 510 may include a first via structure 514 penetrating through at least one layer of the printed circuit board 500, and a first wiring pattern 512 formed at the same layer level as that of the printed circuit board 500. The second transfer line 520 may electrically connect the branch 555 to the second pad 526. The second transfer line 520 may include a second via structure 524 penetrating through at least one layer of the printed circuit board 500, and a second wiring pattern 522 formed at the same layer level as that of the printed circuit board 500.
  • The signal received by the lower pad 556 of the printed circuit board 500 is transferred inside the printed circuit board 500 along the signal transfer line 554. The signal is distributed to the first transfer line 510 and the second transfer line 520 based on the branch 555 and transferred to the first semiconductor chip 100 and the second semiconductor chip 200.
  • The first transfer line 510 and the second transfer line 520 may have substantially the same lengths as each other. For example, the lengths of the first transfer line 510 and the second transfer line 520 may be substantially equal to quarter of a wavelength of the signal transmitted from outside via the external connection terminal 600. The first transfer line 510 and the second transfer line 520 may have substantially the same impedance as each other. Impedance of the resistor unit 400 may be related to the impedance of the first transfer line 510 and the second transfer line 520. This is to implement a structure of Wilkinson divider on the printed circuit board 500.
  • The first wiring pattern 512 and the second wiring pattern 522 may be on respective upper and lower surfaces of each of the base layers 501, 503, and 505. The first wiring pattern 512 and the second wiring pattern 522 may include, for example, electrolytically deposited (ED) copper foil, rolled-annealed (RA) copper foil, stainless steel foil, aluminum foil, ultra-thin copper foil, sputtered copper, copper alloys, etc.
  • The first wiring pattern 512 and the second wiring pattern 522 may be at different layer levels from each other. For example, the first wiring pattern 512 may be on an upper surface of the first base layer 501 and the second wiring pattern 522 may be on an upper surface of the second base layer 503. This arrangement may be different in another embodiment. For example, a space may be provided that is sufficient to allow both the first wiring pattern 512 and the second wiring pattern 522 to be formed at the same layer of the printed circuit board 500. In this case (e.g., when the first wiring pattern 512 and the second wiring pattern 522 are at the same layer), the lengths of the first transfer line 512 and the second transfer line 520 may satisfy the quarter of the wavelength of the signal transmitted from outside.
  • The signal transfer line 554, the first via structure 514, and the second via structure 524 may include, for example, copper, nickel, stainless steel, or beryllium copper.
  • An upper solder resist layer 562 and a lower solder resist layer 564 may be formed respectively on an upper surface of the uppermost layer and a lower surface of the lowermost layer among the base layers 501, 503, and 505. Each of the upper solder resist layer 562 and the lower solder resist layer 564 may be formed, for example, by spraying a solder mask insulating ink onto the upper surface of the uppermost layer and the lower surface of the lowermost layer, among the base layers 501, 503, and 505, by a screen printing method or an inkjet printing method and curing the sprayed solder mask insulating ink by ultraviolet (UV) or infrared (IR) light.
  • In some embodiments, each of the upper solder resist layer 562 and the lower solder resist layer 564 may be formed, on the upper surface of the uppermost layer and the lower surface of the lowermost layer among the plurality of base layers 501, 503, and 505, by entirely spraying a photo-imageable solder resist by a screen printing method or a spray coating method, or by attaching a film-type solder resist material by a laminating method, removing unnecessary parts by an exposure and development process, and curing the solder resist by using heat, UV light, or IR light.
  • Referring to FIGS. 2A and 2B, at least one of the first wiring pattern 512 and the second wiring pattern 522 may have a zig-zag shape. In order to make the length of the first transfer line 510 substantially equal to a quarter of the wavelength of the signal transmitted from outside via the external connection terminal 600, the first wiring pattern 512 may be formed to have zig-zags. In one example embodiment, where there is sufficient length The first wiring pattern 512 may be formed to have a different shape (e.g., straight or a non-zig-zag shape) when there is sufficient length or space.
  • The second wiring pattern 522 is shown to be straight. In one example embodiment, the second wiring pattern 522 may be formed to have a zig-zag shape, in order to reach a length that is substantially equal to a quarter of the wavelength of the signal transmitted from outside via the external connection terminal 600. The first wiring pattern 512 and the second wiring pattern 522 may be formed to have different or other shapes in other embodiments.
  • FIG. 3 illustrates an embodiment for transferring signals in the semiconductor package 1000. Referring to FIGS. 2A and 3, the signal transfer line 554, the branch 555, the first transfer line 510, the second transfer line 520, and the resistor unit 400 of the semiconductor package 1000 may form a Wilkinson divider 10. The relationship of the signal transfer line 554, branch 555, first transfer line 510, second transfer line 520, and resistor unit 400 of the semiconductor package 1000 is described below.
  • The Wilkinson divider 10 may include a branch I, an input line 13, a plurality of transfer lines 15_1 and 15_2, and a resistor 17. The Wilkinson divider 10 may receive a signal from a driver 11 and divide the signal to a plurality of output lines using lines of T-junction structure. When the input line 13 has an impedance of Z0, each of the transfer lines branched from the branch I may have an impedance of √{square root over (2)}Z0. The length of each of the transfer lines 15_1 and 15_2 may be substantially equal to a quarter of a wavelength (λ) of the signal transmitted from the driver 11.
  • The branch I may correspond to the branch 555 of FIG. 2A. The transfer lines 15_1 and 15_2 may correspond to the first transfer line 510 and the second transfer line 520 of FIG. 2A. The input line 13 may correspond to the signal transfer line 554. Therefore, the signal transfer line 554 may have an impedance of Z0. Also, the first and second wiring patterns 511 and 522 and the first and second via structures 514 and 524 may be formed so that each of the first and second transfer lines 510 and 520 has an impedance of √{square root over (2)}Z0 and a length equal to a quarter of the wavelength (λ) of the transmitted signal.
  • A plurality of output terminals OP1_1 and OP1_2 may be connected to the resistor 17. The magnitude of the resistor 17 may be 2Z0. A plurality of semiconductor chips 19_1 and 19_2 may be connected to each of the output terminals OP1_1 and OP1_2. The output terminals OP1_1 and OP1_2 may respectively correspond to the first pad 516 and the second pad 526 of FIG. 2A. The resistor 17 and the semiconductor chips 19_1 and 19_2 may respectively correspond to the resistor unit 400, the first semiconductor chip 100, and the second semiconductor chip 200 of FIG. 2A.
  • One type of structure includes an on-die termination (ODT) at a plurality of output terminals to prevent unnecessary interference between signals output from the plurality of output terminals. In such a structure, electric current may flow to the ODT and cause unnecessary power consumption. On the other hand, the Wilkinson divider 10 does not form a line in addition to the transfer lines 15_1 and 15_2 connected to the plurality of semiconductor chips 19_1 and 19_2. Thus, power consumption may be reduced. In addition, impedance matching is performed using the plurality of transfer lines 15_1 and 15 2 and the resistor 17. Also, isolation characteristics between the output terminals OP1_1 and OP1_2 may be improved. This may offset distortion of a signal reflected by a semiconductor chip that is not selected between the semiconductor chips 19_1 and 19_2.
  • The Wilkinson divider 10 includes two output terminals OP1_1 and OP1_2 and two semiconductor chips that are connected. In one embodiment, a different number of semiconductor chips may be connected.
  • FIG. 4 illustrates another embodiment of a semiconductor package 1000A which may include a printed circuit board 500 a, the resistor unit 400, the external connection terminal 600, the first semiconductor chip 100, and the second semiconductor chip 200.
  • The first transfer line 510, a second transfer line 520 a, and the signal transfer line 554 meet one another at the branch 555 in the printed circuit board 500 a. The signal transferred by the signal transfer line 554 is distributed to the first transfer line 510 and the second transfer line 520 a based on the branch 555 and transferred to the first semiconductor chip 100 and the second semiconductor chip 200.
  • The first transfer line 510 may include the first via structure 514 penetrating through at least one layer of the printed circuit board 500 a, and the first wiring pattern 512 formed at the same layer level as that of the printed circuit board 500 a. The second transfer line 520 a may include a second via structure 524 a penetrating through at least one layer of the printed circuit board 500 a, and a second wiring pattern 522 a formed at the same layer level as that of the printed circuit board 500 a.
  • The second wiring pattern 522 a may include a plurality of wiring patterns at different layer levels from one another. For example, the second wiring pattern 522 a may be formed throughout an upper surface of the second base layer 503 and an upper surface of the third base layer 505. Accordingly, the second via structure 524 a may be formed as a via structure penetrating through the first base layer 501 and a via structure penetrating through the second base layer 503. In one embodiment, the first wiring pattern 512 may also include a plurality of wiring patterns at different layer levels from one another. The first via structure 514, the first wiring pattern 512, the second via structure 514, and the second wiring pattern 522 a may be formed so that the lengths of the first transfer line 510 and the second transfer line 520 may satisfy a quarter of the wavelength of the signal transmitted from outside.
  • FIG. 5 illustrates another embodiment of a semiconductor package 1000B which may include the printed circuit board 500, the resistor unit 400, the external connection terminal 600, the first semiconductor chip 100, and the second semiconductor chip 200.
  • The first semiconductor chip 100 and the second semiconductor chip 200 may be sequentially stacked on the printed circuit board 500. In one embodiment, the first semiconductor chip 100 and the second semiconductor chip 200 may be stacked as stairs. Accordingly, the first bonding wire 130 may not be embedded by a bonding layer 120 b. The stair shape may be formed so that the pad 116 on the first semiconductor chip 100 may be exposed to outside.
  • FIG. 6 illustrates another embodiment of a semiconductor package 1000C which may include a printed circuit board 500 c, a resistor unit 400 c, the external connection terminal 600, the first semiconductor chip 100, the second semiconductor chip 200, and a third semiconductor chip 300.
  • The first pad 516, the second pad 526, a third pad 536 c, a fourth pad 516_1, a fifth pad 526_1, and a sixth pad 536 c_1 may be on an upper surface of the printed circuit board 500 c. A first transfer line, a second transfer line, and a third transfer line may meet one another at a branch formed in the printed circuit board 500 c. The signals transferred through the external connection terminal 600 and the signal transfer line are distributed to the first transfer line, the second transfer line, and the third transfer line based on the branch, and transferred to the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300. For example, the first transfer line, the second transfer line, and the third transfer line on the printed circuit board 500 c may be similar to forming a third transfer line in addition to the structure of the first transfer line 510 and the second transfer line 520 of FIG. 2A, the first transfer line 510 and the second transfer line 520 a of FIG. 4, and the first transfer line 510 and the second transfer line 520 of FIG. 5.
  • The signal transfer line electrically connects the branch to the external connection terminal 600 and may transfer the signal transmitted from outside via the external connection terminal 600 to the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300. The first transfer line may electrically connect the branch to the first pad 516. The second transfer line may electrically connect the branch to the second pad 526. The third transfer line may electrically connect the branch to the third pad 536 c.
  • The first transfer line, the second transfer line, and the third transfer line may have lengths that are substantially equal to a quarter of the wavelength of the signal transmitted from outside and may have substantially the same impedance as one another. The impedance of the resistor unit 400 c may be related to the impedance of the first transfer line, the second transfer line, and the third transfer line. This is to implement a structure of Wilkinson divider on the printed circuit board 500 c.
  • The printed circuit board 500 c may include a plurality of layers. Each of the first transfer line, the second transfer line, and the third transfer line may include a via structure penetrating through at least one layer of the printed circuit board 500 c, and a wiring pattern formed at the same layer level of the printed circuit board 500 c.
  • The first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 may be sequentially stacked on the printed circuit board 500 c. A second bonding layer 220 is between the second semiconductor chip 200 and third semiconductor chip 300 in order to bond the second semiconductor chip 200 and the third semiconductor chip 300 and insulate the second semiconductor chip 200 and third semiconductor chip 300 from each other. The third semiconductor chip 300 may include a plurality of pads 316 and 306 on an upper surface thereof. In one embodiment, the pads 316 and 306 may be on a lower surface of the third semiconductor chip 300.
  • The first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 may be mounted on the printed circuit board 500 c, for example, by a wire bonding method. A first bonding wire 130 may electrically connect the first pad 516 to the first semiconductor chip 100. A second bonding wire 230 may electrically connect the second pad 526 to the second semiconductor chip 200. A third bonding wire 330 may electrically connect the third pad 536 c to the third semiconductor chip 300. In one embodiment, the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 may be mounted on the printed circuit board 500 c, for example, by a flip-chip bonding method.
  • The resistor unit 400 c may be mounted on the printed circuit board 500 c. The resistor unit 400 c may include first to third chip resistors 400 c_1, 400 c_2, and 400 c_3, and a plurality of connection terminals may be formed in the resistor unit 400 c. A first connection terminal of the first chip resistor 400 c_1 may be connected to the first pad 516 on the printed circuit board 500 c, and a second connection terminal of the first chip resistor 400 c_1 may be connected to the fourth pad 516_1 on the printed circuit board 500 c. A first connection terminal of the second chip resistor 400 c_2 may be connected to the second pad 526 on the printed circuit board 500 c, and a second connection terminal of the second chip resistor 400 c_2 may be connected to the fifth pad 526_1 on the printed circuit board 500 c. A first connection terminal of the third chip resistor 400 c_3 may be connected to the third pad 536 c on the printed circuit board 500 c, and a second connection terminal of the third chip resistor 400 c_3 may be connected to the sixth pad 536 c_1 on the printed circuit board 500 c.
  • The second connection terminal of the first chip resistor 400 c_1 may be electrically connected to the second pad 526 through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 c and a wiring pattern formed at the same layer level of the printed circuit board 500 c. The second connection terminal of the second chip resistor 400 c_2 may be electrically connected to the third pad 536 c through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 c and a wiring pattern formed at the same layer level of the printed circuit board 500 c. The second connection terminal of the third chip resistor 400 c_3 may be electrically connected to the first pad 516 through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 c and a wiring pattern formed at the same layer level of the printed circuit board 500 c.
  • The first to third chip resistors 400 c_1, 400 c_2, and 400 c_3 may have substantially the same impedance values. In one embodiment, the resistance values may vary in a case where the same effect may be obtained from another equivalent circuit of different structure and a plurality of resistors included in the resistor unit 400 c may have different connecting structures.
  • FIG. 7 illustrates an embodiment for transferring signals in a semiconductor package 1000C. Referring to FIGS. 6 and 7, the signal transfer lines, the branch, the first transfer line, the second transfer line, the third transfer line, and the resistor unit 400 c of semiconductor package 1000C may form a Wilkinson divider 20.
  • The Wilkinson divider 20 may include a branch I, an input line 13, a plurality of transfer lines 25_1, 25_2, and 25_3, and a plurality of resistors 27_1, 27_2, and 27_3. When the input line 13 has an impedance of Z0, each of the transfer lines 25_1, 25_2, and 25_3 divided at the branch I may have substantially the same impedance, that is, √{square root over (3)}Z0. The length of each of the transfer lines 25_1, 25_2, and 25_3 may be substantially equal to a quarter of the wavelength (λ) of the signal transmitted from the driver 11.
  • The branch I may correspond to the branch in the printed circuit board 500 c. The transfer lines 25_1, 25_2, and 25_3 may correspond to the first to third transfer lines in the printed circuit board 500 c. The input lint 13 may correspond to the signal transfer line in the printed circuit board 500 c.
  • Output terminals OP2_1, OP2_2, and OP2_3 may be connected to the resistors 27_1, 27_2, and 27_3. For example, the first resistor 27_1 may have opposite ends connected to the first output terminal OP2_1 and the second output terminal OP2_2. The second resistor 27_2 may have opposite ends connected to the second output terminal OP2_2 and the third output terminal OP2_3. The third resistor 27_3 may have opposite ends connected to the third output terminal OP2_3 and the first output terminal OP2_1. Each of the resistors 27_1, 27_2, and 27_3 may have a resistance value of 3Z0.
  • In one embodiment, the resistors 27_1, 27_2, and 27_3 may configure another equivalent circuit to exhibit the same effects. When an equivalent circuit having a different structure from that of FIG. 7 is configured, connecting structures between the resistors 27_1, 27_2, and 27_3 and the output terminals OP2_1, OP2_2, and OP2_3 may vary, and impedance values of the resistors 27_1, 27_2, and 27_3 may vary.
  • A plurality of semiconductor chips 29_1, 29_2, and 29_3 may be connected respectively to the output terminals OP2_1, OP2_2, and OP2_3. The output terminals OP2_1, OP2_2, and OP2_3 may correspond to the first to third pads 516, 526, and 536 c of FIG. 6. The resistors 27_1, 27_2, and 27_3 and the semiconductor chips 29_1, 29_2, and 29_3 may respectively correspond to the resistor unit 400 c and the first to third semiconductor chips 100, 200, and 300 of FIG. 6.
  • The Wilkinson divider 20 does not necessarily form additional lines besides the transfer lines 25_1, 25_2, and 25_3 connected to the semiconductor chips 29_1, 29_2, and 29_3. Thus, unnecessary power consumption may be reduced. In addition, impedance matching may be performed using the transfer lines 25_1, 25_2, and 25_3 and the resistors 27_1, 27_2, and 27_3, and distortion of the signal reflected by a semiconductor chip that is not selected from among the semiconductor chips 29_1, 29_2, and 29_3 may be offset.
  • FIG. 8 illustrates another embodiment of a semiconductor package 1000D, and FIG. 9 illustrates view taken along section line B-B′ in FIG. 8. Referring to FIG. 8, the semiconductor package 1000D may include a printed circuit board 500 d, a resistor unit 400 d, the external connection terminal 600, the first semiconductor chip 100, and the second semiconductor chip 200. A plurality of pads 516 d, 526 d, and 506 d including a first pad 516 d and a second pad 526 d may be formed on an upper surface of the printed circuit board 500 d.
  • The first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the same plane of the printed circuit board 500 d. The first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500 d, for example, by a wire bonding method. Therefore, the semiconductor package 1000D may include a first bonding wire 130 electrically connecting the first pad 516 d of the printed circuit board 500 d to the first semiconductor chip 100, and a second bonding wire 230 connecting the second pad 526 d of the printed circuit board 500 d to the second semiconductor chip 200. In one embodiment, the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500 d, for example, by a flip-chip bonding method.
  • Referring to FIG. 8 and FIG. 9, the resistor unit 400 d may be mounted on the printed circuit board 500 d. The resistor unit 400 d may include a plurality of connection terminals including a first connection terminal 401 d and a second connection terminal 402 d. The first connection terminal 401 d of the resistor unit 400 d is connected to the first pad 516 d on the printed circuit board 500 d. The second connection terminal 402 d of the resistor unit 400 d may be connected to the second pad 526 d on the printed circuit board 500 d. For example, the resistor unit 400 d may be implemented as at least one chip resistor and may be mounted so that opposite ends of the resistor unit 400 d may contact the first pad 516 d and the second pad 526 d. The resistor unit 400 d may be on a region between the first semiconductor chip 100 and the second semiconductor chip 200 on the printed circuit board 500 d.
  • Referring to FIG. 9, the printed circuit board 500 d may include a plurality of base layers 501, 503, and 505 stacked with one another. The first pad 516 d and the second pad 526 d are on an upper surface of the uppermost layer from among the base layers 501, 503, and 505./A lower pad 556 d may be on a lower surface of the lowermost layer from among the base layers 501, 503, and 505.
  • The lower pad 556 d may be formed, for example, on a peripheral region surrounding a center region of the printed circuit board 500 d. According to formation of a first transfer line 510 d, a second transfer line 520 d, and a signal transfer line 554 d, the lower pad 556 d may be formed on the center region of the printed circuit board 500 d.
  • The first transfer line 510 d, the second transfer line 520 d, and the signal transfer line 554 d meet one another at a branch 555 d formed in the printed circuit board 500 d. The signal transfer line 554 d electrically connects the branch 555 d to the external connection terminal 600, so that a signal transmitted from outside via the external connection terminal 600 may be transferred to the first semiconductor chip 100 and the second semiconductor chip 200. The first transfer line 510 d and the second transfer line 520 d may be electrically isolated from each other at the branch 555 d.
  • The first transfer line 510 d may electrically connect the branch 555 d to the first pad 516 d. The first transfer line 510 d may include a first via structure 514 d penetrating through at least one layer of the printed circuit board 500 d, and a first wiring pattern 512 d formed at the same layer level as that of the printed circuit board 500 d. The second transfer line 520 d may electrically connect the branch 555 d to the second pad 526 d. The second transfer line 520 d may include a second via structure 524 d penetrating through at least one layer of the printed circuit board 500 d, and a second wiring pattern 522 d at the same layer level as that of the printed circuit board 500 d.
  • The first transfer line 510 d and the second transfer line 520 d may have substantially the same lengths as each other. The lengths of the first transfer line 510 d and the second transfer line 520 d may be substantially equal to a quarter of the wavelength of the signal transmitted from outside via the external connection terminal 600. The first transfer line 510 d and the second transfer line 520 d may have substantially the same impedance as each other.
  • The first wiring pattern 512 d and the second wiring pattern 522 d may be at different layer levels from each other. In a case where there is a space sufficient to form both the first wiring pattern 512 d and the second wiring pattern 522 d at the same layer of the printed circuit board 500 d, the lengths of the first transfer line 510 d and the second transfer line 520 d may satisfy a quarter of the wavelength of the signal transmitted from outside and the first wiring pattern 512 d and the second wiring pattern 522 d may be formed at the same layer.
  • The first wiring pattern 512 d and the second wiring pattern 522 d may include a plurality of wiring patterns at different layers from each other. For example, the second wiring pattern 522 d may be formed throughout an upper surface of the second base layer 503 and an upper surface of the third base layer 505. Accordingly, the second via structure 524 d may be formed as a via structure penetrating through the first base layer 501 and a via structure penetrating through the second base layer 503.
  • At least one of the first wiring pattern 512 d and the second wiring pattern 522 d may have zig-zags similar to the first wiring pattern 512 in FIG. 2B. For example, the first wiring pattern 512 d may have zig-zags so that the first transfer line 510 d has a length substantially equal to a quarter the wavelength of the received signal. In a case where there is sufficient length, the first wiring pattern 512 d may be formed straight or may have a non-zig-zag shape.
  • The lower pad 556 d may be, for example, on the peripheral region surrounding the center region of the printed circuit board 500 d. According to formation of the first transfer line 510 d, the second transfer line 520 d, and the signal transfer line 554 d, the lower pad 556 d may be on the center region of the printed circuit board 500 d.
  • FIG. 10 illustrates another embodiment of a semiconductor package 1000E which may include a printed circuit board 500 e, a resistor unit 400 e, the external connection terminal 600, the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300.
  • The first pad 516 d, the second pad 526 d, a third pad 536 e, a fourth pad 516 d_1, a fifth pad 526 d_1 and a sixth pad 536 e_1 may be on an upper surface of the printed circuit board 500 e. A first transfer line, a second transfer line, and a third transfer line may meet one another at a branch formed in the printed circuit board 500 e. The first transfer line, the second transfer line, and the third transfer line may be electrically isolated from one another at the branch. For example, the first transfer line, the second transfer line, and the third transfer line on the printed circuit board 500 e may be similar to forming the third transfer line in addition to the structure including the first transfer line 510 d and the second transfer line 520 d of FIG. 9.
  • The signal transfer line electrically connects the branch to the external connection terminal 600 and may transfer the signal transmitted from outside via the external connection terminal 600 to the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300.
  • The first transfer line may electrically connect the branch to the first pad 516 d. The second transfer line may electrically connect the branch to the second pad 526 d. The third transfer line may electrically connect the branch to the third pad 536 e. The first transfer line, the second transfer line, and the third transfer line may have lengths substantially equal to a quarter of the wavelength of the signal transmitted from outside and may have substantially the same impedance as one another. As described above with reference to FIG. 7, when an input line connected to the branch in the printed circuit board 500 e has a resistance value of Z0, each of the first, second, and third transfer lines may have a resistance value of √{square root over (3)}Z0.
  • The printed circuit board 500 e may include a plurality of layers. The third transfer line may include a via structure penetrating at least one layer of the printed circuit board 500 e and a wiring pattern at the same layer as the via structure in the printed circuit board 500 e.
  • The third semiconductor chip 300 may be stacked on the second semiconductor chip 200. The second semiconductor chip 200 and the third semiconductor chip 300 may be stacked as stairs or may be stacked to be aligned with each other in a direction perpendicular to an upper surface of the printed circuit board 500 e. In one embodiment, the third semiconductor chip 300 may be mounted on the same plane as those of the first semiconductor chip 100 and the second semiconductor chip 200.
  • The third semiconductor chip 300 may be mounted on the printed circuit board 500 e, for example, by a wire bonding method. A first bonding wire 130 may electrically connect the first pad 516 d to the first semiconductor chip 100. A second bonding wire 230 may electrically connect the second pad 526 d to the second semiconductor chip 200. The third bonding wire 330 may electrically connect the third pad 536 e to the third semiconductor chip 300. In one embodiment, the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 may be mounted on the printed circuit board 500 e, for example, by a flip-chip bonding method.
  • The resistor unit 400 e may be mounted on the printed circuit board 500 e. The resistor unit 400 e may include first to third chip resistors 400 e_1, 400 e_2, and 400 e_3, and may include a plurality of connection terminals. A first connection terminal of the first chip resistor 400 e_1 may be connected to the first pad 516 d on the printed circuit board 500 e, and a second connection terminal of the first chip resistor 400 e_1 may be connected to the fourth pad 516 d_1 on the printed circuit board 500 e. A first connection terminal of the second chip resistor 400 e_2 may be connected to the second pad 526 d on the printed circuit board 500 e, and a second connection terminal of the second chip resistor 400 e_2 may be connected to the fifth pad 526 d_1 on the printed circuit board 500 e. A first connection terminal of the third chip resistor 400 e_3 may be connected to the third pad 536 e on the printed circuit board 500 e, and a second connection terminal of the third chip resistor 400 e_3 may be connected to the sixth pad 536 e_1 on the printed circuit board 500 e.
  • The second connection terminal of the first chip resistor 400 e_1 may be electrically connected to the second pad 526 d through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 e and a wiring pattern formed at the same layer level of the printed circuit board 500 e. The second connection terminal of the second chip resistor 400 e_2 may be electrically connected to the third pad 536 e through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 e and a wiring pattern formed at the same layer level of the printed circuit board 500 e. The second connection terminal of the third chip resistor 400 e_3 may be electrically connected to the first pad 516 d through a conduction line which includes a via structure penetrating through at least one layer of the printed circuit board 500 e and a wiring pattern formed at the same layer level of the printed circuit board 500 e.
  • The first to third chip resistors 400 e_1, 400 e_2, and 400 e_3 may have substantially the same impedance values. As described above with reference to FIG. 7. each of the first to third chip resistors 400 e_1, 400 e_2, and 400 e_3 may have a resistance value of 3Z0. In one or more embodiments, the resistance values may vary in a case where the same effect may be obtained from another equivalent circuit of different structure and a plurality of resistors included in the resistor unit 400 e may have different connecting structures.
  • FIG. 11A illustrates another embodiment of a semiconductor package 1000F, and FIG. 11B illustrates an embodiment of a power distribution device 700 in a semiconductor package.
  • Referring to FIG. 11A, the semiconductor package 1000F may include a printed circuit board 500 f, the first semiconductor chip 100, the second semiconductor chip 200, and the power distribution device 700. The first semiconductor chip 100 and the second semiconductor chip 200 may be sequentially stacked on the printed circuit board 500 f. The first semiconductor chip 100 and the second semiconductor chip 200 may be stacked as stairs or may be stacked to be aligned with each other in a direction perpendicular to an upper surface of the printed circuit board 500 f.
  • In one embodiment, the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the same plane of the printed circuit board 500 f. The first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the printed circuit board 500 f, for example, by a wire bonding method. In addition to the first semiconductor chip 100 and the second semiconductor chip 200, one or more semiconductor chips may be mounted on the printed circuit board 500 f. The mounted semiconductor chips may be respectively connected to power distribution device 700.
  • A first rewiring layer and a second rewiring layer may be respectively formed on upper surfaces of the first semiconductor chip 100 and the second semiconductor chip 200. A first bonding wire 130 f connecting the first semiconductor chip 100 to the power distribution device 700 may be electrically connected to the first rewiring layer. In addition, a second bonding wire 230 f connecting the second semiconductor chip 200 to the power distribution device 700 may be electrically connected to the second rewiring layer.
  • A plurality of wiring patterns 532 may be on an upper surface and a lower surface of each of the base layers 501, 503, and 505. The wiring patterns 532 may include, for example, ED copper foil, RA copper foil, stainless steel foil, aluminum foil, ultra-thin copper foil, sputtered copper, copper alloys, etc. The printed circuit board 500 f may include a plurality of via structures penetrating through at least one of the plurality of base layers 501, 503, and 505. For example, the via structures 534 may include copper, nickel, stainless steel, or beryllium copper.
  • The power distribution device 700 may be mounted on the printed circuit board 500 f, for example, by a wire bonding method. The power distribution device 700 may receive a signal from the printed circuit board 500 f via a bonding wire 730 connected to upper pad 538. The power distribution device 700 may transfer the signal respectively to the first semiconductor chip 100 and the second semiconductor chip 200. In order to transfer the signal to the first semiconductor chip 100, the power distribution device 700 may block a distortion signal reflected by the second semiconductor chip 200.
  • For example, the power distribution device 700 may prevent signal interference between the first semiconductor chip 100 and the second semiconductor chip 200. The power distribution device 700 may have a Wilkinson divider structure. Therefore, interference between the semiconductor chips 100 and 200 on the semiconductor package 1000F may be prevented, and reliability of the signals transferred to the semiconductor chips 100 and 200 may be ensured. Also, since the ODT is not used, unnecessary power consumption may be reduced. For example, the power distribution device 700 may be implemented as a semiconductor package.
  • Referring to FIGS. 11A and 11B, the power distribution device 700 may include a plurality of insulating layers 702 and 704, an input terminal 756, a first output terminal 716, a second output terminal 726, a resistor unit 740, a signal transfer line 750, a first transfer line 710, and a second transfer line 720. Each of the insulating layers 702 and 704 may include the same material as the base layers 501, 503, and 505. Two insulating layers 702 and 704 are formed in the present embodiment, but one insulating layer or three or more insulating layers may be formed in other embodiments.
  • A solder resist layer 762 may be at the uppermost layer between the insulating layers 702 and 704. The solder resist layer 762 may be formed in a similar way to forming of an upper solder resist layer 562 and a lower solder resist layer 564.
  • The input terminal 756, the first output terminal 716, and the second output terminal 726 may be on an upper surface of the uppermost layer between the insulating layers 702 and 704. In one embodiment, the input terminal 756, the first output terminal 716, and the second output terminal 726 may be on a lower surface of the lowermost layer between the insulating layers 702 and 704.
  • The input terminal 756 may receive a signal from the printed circuit board 500 f. The first output terminal 716 may transmit the signal to the first semiconductor chip 100 via a first bonding wire 130 f. The second output terminal 726 may transmit the signal to the second semiconductor chip 200 via a second bonding wire 230 f. The input terminal 756, the first output terminal 716, and the second output terminal 726 may be implemented as pads exposed from the solder resist layer 762.
  • When one or more semiconductor chips are additionally mounted on the printed circuit board 500 f, the power distribution device 700 may include one or more output terminals. The one or more output terminals and the one or more semiconductor chips may be connected in one-to-one correspondence.
  • A metal layer may be further formed on each of the input terminal 756, the first output terminal 716, and the second output terminal 726. For example, the metal layer may be formed by a hot air solder leveling (H.A.S.L.), a Ni/Au plating method, etc.
  • In the power distribution device 700, the first transfer line 710, the second transfer line 720, and the signal transfer line 750 meet one another at a branch 755. Therefore, the first transfer line 710 and the second transfer line 720 may be electrically isolated from each other at the branch 755.
  • The signal transfer line 750 electrically connects the branch 755 to the input terminal 756, to transfer the signal from the printed circuit board 500 f to the first semiconductor chip 100 and the second semiconductor chip 200. For example, the signal received by the input terminal 756 may be transferred to the power distribution device 700 along the signal transfer line 750. The signal is distributed to the first transfer line 710 and second transfer line 720 based on the branch 755 and transferred to the first semiconductor chip 100 and the second semiconductor chip 200. The signal transfer line 750 may include a vertical structure 754 penetrating through at least one of the insulating layers 702 and 704 and a horizontal structure 752 at the same layer level as that of the insulating layers 702 and 704.
  • The first transfer line 710 may electrically connect the branch 755 to the first output terminal 716. The first transfer line 710 may include a first via structure 714 penetrating through at least one of the insulating layers 702 and 704, and a first wiring pattern 712 formed at the same layer level as that of the insulating layers 702 and 704. The second transfer line 720 may electrically connect the branch 755 to the second output terminal 726. The second transfer line 720 may include a second via structure 724 penetrating through at least one of the insulating layers 702 and 704, and a second wiring pattern 722 formed at the same insulating layer between the insulating layers 702 and 704.
  • The first transfer line 710 and second transfer line 720 may have substantially the same lengths as each other. The lengths of the first transfer line 710 and the second transfer line 720 may be substantially equal to a quarter of the wavelength of the signal received by the input terminal 756. The first transfer line 710 and the second transfer line 720 may have substantially the same impedance as each other. The lengths and the impedance of the first transfer line 710 and the second transfer line 720 may be adjusted to satisfy conditions of the Wilkinson divider.
  • At least one of the first wiring pattern 712 or the second wiring pattern 722 may have zig-zags similar to the first wiring pattern 512 in FIG. 2B. In order to make the length of the first transfer line 710 substantially equal to a quarter of the wavelength of the signal transmitted from outside via the external connection terminal 600, the first wiring pattern 712 may have zig-zags. In a case where there is sufficient length or space, the first wiring pattern 712 may be straight or may have a non-zig-zag shape.
  • The resistor unit 740 may include a plurality of connection terminals, e.g., a first connection terminal 741 and a second connection terminal 742. The first connection terminal 741 of the resistor unit 740 may be connected to the first output terminal 716. The second connection terminal 742 of the resistor unit 740 may be connected to the second output terminal 726. For example, the resistor unit 740 may be implemented as at least one chip resistor and may be mounted so that opposite ends of the resistor unit 740 contact the first output terminal 716 and the second output terminal 726. In a case where one or more semiconductor chips are additionally mounted on the printed circuit board 500 f, the resistor unit 740 may include a plurality of chip resistors that have impedance values substantially equal to one another. The impedance of the resistor unit 740 may be adjusted, for example, to satisfy the conditions of the Wilkinson divider.
  • FIG. 12A illustrates another embodiment of a semiconductor package 1000G, and FIG. 12B illustrates an embodiment of of a power distribution device 700 g in the semiconductor package 1000G.
  • Referring to FIG. 12A, the semiconductor package 1000G may include the printed circuit board 500 f, the first semiconductor chip 100, the second semiconductor chip 200, and the power distribution device 700 g.
  • The first semiconductor chip 100 may be mounted on the printed circuit board 500 f via a first bump 140. The second semiconductor chip 200 may be mounted on the first semiconductor chip 100 via a second bump 240, for example, by a flip-chip bonding method. The first semiconductor chip 100 and the second semiconductor chip 200 may be stacked as stairs or may be stacked and aligned with each other in a direction perpendicular to an upper surface of the printed circuit board 500 f. In one embodiment, the first semiconductor chip 100 and the second semiconductor chip 200 may be mounted on the same plane of the printed circuit board 500 f, for example, by the flip-chip bonding method. One or more semiconductor chips, in addition to the first semiconductor chip 100 and the second semiconductor chip 200, may be mounted on the printed circuit board 500 f and respectively connected to the power distribution device 700 g.
  • The power distribution device 700 g may be mounted on the printed circuit board 500 f, for example, by a flip-chip bonding method. The power distribution device 700 g may receive a signal from the printed circuit board 500 f via a bump 760 contacting the upper pad 538. The power distribution device 700 g may transfer the signal from the printed circuit board 500 f to the first semiconductor chip 100 and the second semiconductor chip 200. The power distribution device 700 g may have, for example, a Wilkinson divider structure.
  • Referring to FIGS. 12A and 12B, the power distribution device 700 g may include a plurality of insulating layers 702 and 704, an input terminal 756, a first output terminal 716, a second output terminal 726, a resistor unit 740, a signal transfer line 750, a first transfer line 710, a second transfer line 720, and a bump 760. Solder resist layers 762 and 764 may be respectively formed on an upper surface of the uppermost layer and a lower surface of the lowermost layer between the insulating layers 702 and 704.
  • The input terminal 756 receives the signal transmitted from the printed circuit board 500 f via the bump 760 and transfers the signal to the signal transfer line 750. The signal may be divided at the branch 755 and transferred to the first semiconductor chip 100 and the second semiconductor chip 200.
  • FIG. 13 illustrates an embodiment of a system 1200 including a semiconductor package. Referring to FIG. 13, the system 1200 includes a controller 1210, an input/output device 1220, a memory 1230, and an interface 1240. The system 1200 may be a mobile system or a system transmitting/receiving information. In some embodiments, the mobile system may include a personal digital assistant (PDA), a portable computer, a Web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card.
  • The controller 1210 controls execution programs in the system 1200 and may include a microprocessor, a digital signal processor, a microcontroller, or a similar device. The input/output device 1220 may be used to input/output data into/from the system 1200. The system 1200 may be connected to an external device, e.g., a personal computer or network, via the input/output device 1220, and may exchange data with the external device. The input/output device 1220 may be, for example, a keypad, a keyboard, or a display.
  • The memory 1230 may store codes and/or data for operating the controller 1210, or data processed by the controller 1210. The memory 1230 may include a semiconductor package according to an embodiment. For example, the memory 1230 may include the semiconductor package 1000, 1000A, 1000B, 1000C, 1000D, 1000E, 1000F, or 1000G exemplarily shown in FIGS. 1 to 12A.
  • The interface 1240 may be a data transmission path between the system 1200 and an external device. The controller 1210, the input/output device 1220, the memory 1230, and the interface 1240 may communicate with one another via a bus 1250. The system 1200 may be used, for example, in a mobile phone, an MP3 player, a navigation system, a portable multimedia player (PMP), a solid state disk (SSD), or household appliances.
  • The methods, processes, and/or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.
  • The processors, controllers, and other signal generating and signal processing features of the embodiments disclosed herein may be implemented in logic which, for example, may include hardware, software, or both. When implemented at least partially in hardware, the processors, controllers, and other signal generating and signal processing features may be, for example, any one of a variety of integrated circuits including but not limited to an application-specific integrated circuit, a field-programmable gate array, a combination of logic gates, a system-on-chip, a microprocessor, or another type of processing or control circuit.
  • When implemented in at least partially in software, the processors, controllers, and other signal generating and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.
  • Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise indicated. Accordingly, various changes in form and details may be made without departing from the spirit and scope of the embodiments set forth in the claims.

Claims (20)

What is claimed is:
1. A semiconductor package, comprising:
a printed circuit board having a lower surface and an upper surface, the upper surface including a first pad and a second pad;
an external connection terminal on the lower surface of the printed circuit board;
a resistor circuit including a first connection terminal and a second connection terminal, the first connection terminal connected to the first pad and the second connection terminal is connected to the second pad;
a first semiconductor chip mounted on the printed circuit board and connected to the first pad; and
a second semiconductor chip stacked on the first semiconductor chip and connected to the second pad, wherein the printed circuit board includes:
a signal transfer line that connects a branch in the printed circuit board to the external connection terminal;
a first transfer line that connects the branch to the first pad; and
a second transfer line that connects the branch to the second pad.
2. The semiconductor package as claimed in claim 1, wherein:
the printed circuit board includes a plurality of layers,
the first transfer line includes:
a first via structure penetrating through at least one of the layers, and
a first wiring pattern at a same layer level of the printed circuit board, and
the second transfer line includes:
a second via structure penetrating through at least one of the layers, and
a second wiring pattern at a same layer level of the printed circuit board.
3. The semiconductor package as claimed in claim 2, wherein the first wiring pattern and the second wiring pattern are at different layers from each other.
4. The semiconductor package as claimed in claim 1, further comprising:
a third semiconductor chip mounted on the printed circuit board,
wherein the printed circuit board includes a third pad on the upper surface, wherein the resistor circuit includes a third connection terminal, and wherein the third semiconductor chip and the third connection terminal are connected to the third pad.
5. The semiconductor package as claimed in claim 1, wherein the resistor circuit includes a plurality of chip resistors having equal impedances.
6. The semiconductor package as claimed in claim 5, wherein the first semiconductor chip and the second semiconductor chip are stacked and aligned with each other in a direction perpendicular to the upper surface of the printed circuit board.
7. The semiconductor package as claimed in claim 1, wherein each of the first transfer line and the second transfer line has a length equal to a quarter of a wavelength of a signal transmitted from the external connection terminal.
8. The semiconductor package as claimed in claim 1, wherein the first transfer line and the second transfer line have equal impedances.
9. The semiconductor package as claimed in claim 1, wherein at least one of the first transfer line or the second transfer line has a zig-zag pattern.
10. A semiconductor package, comprising:
a printed circuit board including a lower surface and an upper surface, the upper surface including a first pad and a second pad;
an external connection terminal on the lower surface of the printed circuit board;
a resistor circuit including a first connection terminal and a second connection terminal, the first connection terminal connected to the first pad and the second connection terminal connected to the second pad;
a first semiconductor chip mounted on the printed circuit board and connected to the first pad; and
a second semiconductor chip mounted on the printed circuit board and connected to the second pad, the first semiconductor chip and the second semiconductor chip mounted on a same plane of the printed circuit board, wherein the printed circuit board includes:
a signal transfer line that connects a branch in the printed circuit board to the external connection terminal;
a first transfer line that connects the branch to the first pad; and
a second transfer line that connects the branch to the second pad.
11. The semiconductor package as claimed in claim 10, wherein:
the printed circuit board includes a plurality of layers,
the first transfer line includes:
a first via structure penetrating through at least one of the layers, and
a first wiring pattern formed at a same layer level of the printed circuit board, and
the second transfer line includes:
a second via structure penetrating through at least one of the plurality of layers, and
a second wiring pattern formed at a same layer level of the printed circuit board.
12. The semiconductor package as claimed in claim 10, further comprising:
a third semiconductor chip mounted on the printed circuit board,
wherein the upper surface of the printed circuit board includes a third pad and wherein a third transfer line connects the branch to the third pad.
13. The semiconductor package as claimed in claim 12, wherein the third semiconductor chip is stacked on the second semiconductor chip.
14. The semiconductor package as claimed in claim 10, wherein the first transfer line and the second transfer line have equal impedance values.
15. The semiconductor package as claimed in claim 10, wherein each of the first transfer line and the second transfer line has a length equal to a quarter of a wavelength of a signal transmitted from the external connection terminal.
16. A semiconductor package, comprising:
a printed circuit board;
a first semiconductor chip and a second semiconductor chip mounted on the printed circuit board; and
a power distribution device mounted on the printed circuit board and including:
an input terminal to receive a signal;
a first output terminal and a second output terminal to output a signal;
a resistor circuit including a first connection terminal connected to the first output terminal and a second connection terminal connected to the second output terminal;
a signal transfer line that connects a branch in the power distribution device to the input terminal;
a first transfer line that connects the branch to the first connection terminal; and
a second transfer line that connects the branch to the second connection terminal.
17. The semiconductor package as claimed in claim 16, wherein the first semiconductor chip and the second semiconductor chip are mounted on the printed circuit board in a stacked pattern.
18. The semiconductor package as claimed in claim 16, wherein the first semiconductor chip and the second semiconductor chip are mounted on the printed circuit board based on a flip-chip bond.
19. The semiconductor package as claimed in claim 16, wherein at least one of the first transfer line or the second transfer line has a zig-zag pattern.
20. The semiconductor package as claimed in claim 16, wherein:
the power distribution device includes a plurality of layers, and
each of the first and second transfer lines includes a via structure penetrating through at least one of the layers.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10643676B2 (en) 2018-09-28 2020-05-05 Western Digital Technologies, Inc. Series resistance in transmission lines for die-to-die communication
WO2020188146A1 (en) * 2019-03-18 2020-09-24 Teknologian Tutkimuskeskus Vtt Oy Wilkinson divider
US20210407915A1 (en) * 2020-06-30 2021-12-30 Western Digital Technologies, Inc. Printed circuit board compensation structure for high bandwidth and high die-count memory stacks

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200025543A (en) * 2018-08-30 2020-03-10 삼성전자주식회사 electronic device including semiconductor package having package ball
CN110299332A (en) * 2019-07-19 2019-10-01 安徽安努奇科技有限公司 Chip-packaging structure
KR20210128681A (en) * 2020-04-17 2021-10-27 에스케이하이닉스 주식회사 Semiconductor device having resistor
CN113067155B (en) * 2021-02-26 2022-12-13 成都天马微电子有限公司 Transmission line structure, manufacturing method thereof and liquid crystal antenna

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6861923B2 (en) * 2002-03-19 2005-03-01 Nokia Corporation Power divider/combiner with a multilayer structure
US20060006516A1 (en) * 2004-07-09 2006-01-12 Elpida Memory, Inc Stacked semiconductor device and semiconductor memory module
US20130168842A1 (en) * 2011-12-30 2013-07-04 Chul Park Integrated circuit packages having redistribution structures
US9349713B2 (en) * 2014-07-24 2016-05-24 Samsung Electronics Co., Ltd. Semiconductor package stack structure having interposer substrate

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574415A (en) 1992-06-11 1996-11-12 Peterson; Robert K. Method of fabricating microwave interconnects and packaging and the interconnects and packaging
US6125419A (en) 1996-06-13 2000-09-26 Hitachi, Ltd. Bus system, printed circuit board, signal transmission line, series circuit and memory module
JP3344685B2 (en) 1996-06-13 2002-11-11 株式会社日立製作所 Bus system and circuit board
US6518856B1 (en) * 1999-10-13 2003-02-11 Signal Technology Corporation RF power divider/combiner circuit
US6300789B1 (en) 1999-12-22 2001-10-09 Intel Corporation Dynamic termination for non-symmetric transmission line network topologies
EP3907820A1 (en) * 2005-11-30 2021-11-10 Leonardo UK Ltd Microwave power splitter/combiner
KR100689967B1 (en) 2006-02-03 2007-03-08 삼성전자주식회사 Memory system with improved multi-module memory bus using wilkinson power divider
KR101481571B1 (en) 2007-08-21 2015-01-14 삼성전자주식회사 Semiconductor Package apparatus and its manufacturing method
JP4516101B2 (en) 2007-09-21 2010-08-04 三菱電機株式会社 Transmission line substrate and semiconductor package
US8081045B1 (en) * 2008-08-08 2011-12-20 Lockheed Martin Corporation Beamformer power divider/combiner with transmission lines distributed between MMIC and associated PC board
US8216912B2 (en) 2009-08-26 2012-07-10 International Business Machines Corporation Method, structure, and design structure for a through-silicon-via Wilkinson power divider
KR101831692B1 (en) * 2011-08-17 2018-02-26 삼성전자주식회사 Semiconductor Devices, Package Substrates, Semiconductor Packages, Package Stack Structures, and Electronic Systems having Functionally Asymmetric Conductive elements
JP6320167B2 (en) 2014-05-21 2018-05-09 三菱電機株式会社 Wilkinson distributor and high frequency circuit
KR20160090705A (en) * 2015-01-22 2016-08-01 에스케이하이닉스 주식회사 Package substrate, and semiconductor package using the package substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6861923B2 (en) * 2002-03-19 2005-03-01 Nokia Corporation Power divider/combiner with a multilayer structure
US20060006516A1 (en) * 2004-07-09 2006-01-12 Elpida Memory, Inc Stacked semiconductor device and semiconductor memory module
US20130168842A1 (en) * 2011-12-30 2013-07-04 Chul Park Integrated circuit packages having redistribution structures
US9349713B2 (en) * 2014-07-24 2016-05-24 Samsung Electronics Co., Ltd. Semiconductor package stack structure having interposer substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10643676B2 (en) 2018-09-28 2020-05-05 Western Digital Technologies, Inc. Series resistance in transmission lines for die-to-die communication
WO2020188146A1 (en) * 2019-03-18 2020-09-24 Teknologian Tutkimuskeskus Vtt Oy Wilkinson divider
US20210407915A1 (en) * 2020-06-30 2021-12-30 Western Digital Technologies, Inc. Printed circuit board compensation structure for high bandwidth and high die-count memory stacks
US11302645B2 (en) * 2020-06-30 2022-04-12 Western Digital Technologies, Inc. Printed circuit board compensation structure for high bandwidth and high die-count memory stacks

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KR102554415B1 (en) 2023-07-11
US10134713B2 (en) 2018-11-20

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