US20180115286A1

US20180115286A1 - Pvt invariant peaking stage for continuous time linear equalizer

Info

Publication number: US20180115286A1
Application number: US15/332,830
Authority: US
Inventors: Yonggang Chen; Sagar Kumar
Original assignee: Wells Fargo Bank NA
Current assignee: Wells Fargo Bank NA
Priority date: 2016-10-24
Filing date: 2016-10-24
Publication date: 2018-04-26
Anticipated expiration: 2036-10-24
Also published as: US9954495B1

Abstract

Frequency characteristics of a peaking stage can vary depending on variations in the process used to fabricate the peaking stage. For example, depending on the batch of wafers and where on a wafer the peaking stage is formed, the capacitors and resistors may have different values, thereby changing the frequency characteristics of the peaking stage. The embodiments herein describe a peaking stage that is invariant of the process variation. That is, one or more of the frequency characteristics of the peaking stages do not vary as the values of a capacitor or resistor change. As such, peaking stages formed in different process corners on the wafer have the same frequency characteristics, and thus, function in a similar manner.

Description

FIELD OF THE INVENTION

This invention generally relates to electronic devices and equalizing power distribution using a peaking stage in an amplifier.

BACKGROUND OF THE INVENTION

Peaking amplifiers are used in electronic systems where a peaking characteristic in a frequency transfer function is needed (e.g., higher gain at high frequencies than at low frequencies). One important application for peaking amplifiers is signal equalization. For instance, when high-speed (e.g., multi-Gb/s) digital data streams are transferred over electrical serial links, the transmitted pulses are distorted by high-frequency losses in the channel media. To improve the maximum data rates of such links, it is preferred to equalize the frequency response of the channel so that the pulse distortion is reduced. For this reason, the receivers of modern high-speed data communication links commonly employ peaking amplifiers, which boost the high-frequency components of the received signal that were attenuated by the channel response.

BRIEF SUMMARY OF THE INVENTION

One embodiment described herein is a peaking stage that includes a first variable resistance comprising a first end coupled to a voltage rail, a second variable resistance comprising a first end coupled to the voltage rail, and a resistance control circuit comprising a first comparator and a first analog to digital converter (ADC) configured to generate a first digital signal for setting a first resistance value of the first variable resistance and a second resistance value of the second variable resistance. The peaking stage also includes a first transistor coupled to a second end of the first variable resistance and a second transistor coupled to a second end of the second variable resistance, where the first and second transistors are configured to generate equalized output signals based on respective input signals.
Another embodiment described herein is an amplifier that includes a peaking stage. The peaking stage includes a first variable resistance comprising a first end coupled to a voltage rail, a second variable resistance comprising a first end coupled to the voltage rail, and a first resistance control circuit comprising a first comparator configured to generate a first signal for setting a first resistance value of the first variable resistance and a second resistance value of the second variable resistance. The peaking stage also includes a first transistor coupled to a second end of the first variable resistance and a second transistor coupled to a second end of the second variable resistance, where the first and second transistors are configured to generate equalized output signals based on respective input signals received by the amplifier.
Another embodiment described herein is an integrated circuit that includes a peaking stage. The peaking stage includes a first variable resistance comprising a first end coupled to a voltage rail, a second variable resistance comprising a first end coupled to the voltage rail, and a resistance control circuit comprising a comparator configured to generate a first signal for setting a first resistance value of the first variable resistance and a second resistance value of the second variable resistance. The peaking stage includes a first transistor coupled to a second end of the first variable resistance and a second transistor coupled to a second end of the second variable resistance, wherein the first and second transistors are configured to generate equalized output signals based on respective input signals received by the amplifier.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a system that includes peaking amplifiers, in accordance with an embodiment described herein;

FIG. 2A illustrates a peaking stage in an amplifier in accordance with an embodiment described herein;

FIG. 2B illustrates a transfer function for the peaking stage in FIG. 2A in accordance with an embodiment described herein;

FIG. 3 illustrates a reference current generator for a peaking stage in accordance with an embodiment described herein;

FIG. 4 illustrates a load impedance control generator for a peaking stage in accordance with an embodiment described herein;

FIG. 5 illustrates a variable resistor for the load impedance control generator in accordance with an embodiment described herein; and

FIG. 6 illustrates a degeneration resistance control generator in accordance with an embodiment described herein.

FIG. 7 illustrates a variable resistor for the degeneration resistance control generator in accordance with an embodiment described herein.

FIG. 8 illustrates a peaking stage for an amplifier in accordance with an embodiment described herein.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. The drawings referred to here should not be understood as being drawn to scale unless specifically noted. Also, the drawings are often simplified and details or components omitted for clarity of presentation and explanation. The drawings and discussion serve to explain principles discussed below, where like designations denote like elements.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and is not intended to limit the disclosure or its application and uses. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
Various embodiments of the present invention provide input devices and methods that facilitate improved usability. Some signals in the input device may have power distributed across multiple frequencies or bands. However, the power may not be distributed equally across the frequencies—e.g., a lower frequency may have more power than a higher frequency. To equalize the power distribution, an amplifier may include a peaking stage which has a gain that varies across a frequency band. Thus, the peaking stage can adjust the signals so that the power distribution between frequencies is similar.
Frequency characteristics of the peaking stage, however, can vary depending on variations in the process used to fabricate the peaking stage. For example, the peaking stage may be formed in an integrated circuit and include different capacitive elements and poly resistors which affect the frequency characteristics of the peaking stage. Depending on where on a wafer the peaking stage is formed, the capacitive elements and resistors may have different values, thereby changing the frequency characteristics of the peaking stage. Thus, the gain of the peaking stages formed on the wafer may vary depending on where the peaking stages were formed.
The embodiments herein describe a peaking stage that is invariant of the process variation. That is, one or more of the frequency characteristics of the peaking stages do not vary as the values of a capacitive element or resistor change. As such, peaking stages formed in different process corners on the wafer have the same frequency characteristics, and thus, function in a similar manner. In one embodiment, the peaking stage includes a variable resistance that is controlled by resistance control circuit that includes a comparator and an analog-to-digital converter (ADC) which generate a digital control signal that adjusts the resistance value of the variable resistance. As a result, even as the values of the physical capacitive elements and resistors change relative to other peaking circuits formed on the same wafer, each peaking stage can compensate for this process variation by adjusting the resistance value of the variable resistance thereby maintaining the desired frequency characteristics.
FIG. 1 illustrates a system 100 that includes peaking amplifiers 115, in accordance with an embodiment described herein. Specifically, the system 100 includes cameras 110 coupled to the peaking amplifiers 115 which in turn provide equalized signals to a gesture recognition module 120. In one embodiment, the peaking amplifiers 115 and the gesture recognition module 120 are disposed on an integrated circuit—e.g., a system on chip (SOC). The SOC can be coupled to the high-speed video cameras 110 via connection cables. In operation, the cameras 110 capture high-definition images of gestures or motion made by a hand 105 of a user which typical requires a high bandwidth. For example, the data speed at which the data captured by the cameras 110 is transmitted to the gesture recognition module 120 may be between 1-10 GHz.
The channel insertion loss of the high speed data signals transmitted by the cameras 110 means that the signals received by the gesture recognition module 120 are difficult to recover. For example, the channel insertion loss may result in poor power distribution among the frequencies in the high speed data signals—i.e., the signals are not equalized. Instead, the high speed signals are transmitted to respective peaking amplifiers 115 which equalize the power distribution of the signals which make the signals easier to recover at the gesture recognition module 120.
After receiving the signals, the gesture recognition module 120 processes the data to identify different gestures of the hand 105. Because two cameras 110 are used, the module 120 can identify gestures in 3-D motion capture rather than just 2-D. In one embodiment, the system 100 is used in an augmented reality or virtual reality application. However, the peaking amplifiers 115 described herein are not limited to a system that performs gesture recognition, and instead, may be used in any system where data signals have poor power distribution.
FIG. 2A illustrates a peaking stage 200 in an amplifier in accordance with an embodiment described herein. In one embodiment, the circuitry in the peaking stage 200 may be disposed in an integrated circuit that was formed on a wafer. When processing the wafer, hundreds or thousands of the peaking stages 200 may be formed in parallel on the wafer. Once formed, the wafer is cleaved into separate integrated circuits which may include one or more amplifiers that each includes the peaking stage 200. As discussed above, the values of the capacitors and/or resistors in the peaking stage 200 can affect the frequency characteristics of the stage 200 which dictate the gain of the peaking stage 200 across a band of frequencies. However, the peaking stage 200 includes variable resistors 205 and 210 which compensate for fluctuations in the values of the capacitors and/or resistors as a result of process variations when forming the peaking stage 200.
Positive and negative input signals (IP and IN) are received at the gates of a first transistor 215 and a second transistor 220 (e.g., an induction channel MOSFETs). As described above, the peaking stage 200 equalizes these signals—i.e., adjusts the distribution of power across the frequencies in the signals for a more even power distribution. Thus, the positive and negative outputs (OP and ON) of the peaking stage 200 have a more even or equal distribution of power across the frequencies relative to the input signals.
The peaking stage 200 also includes variable resistances 225 and 230 that are disposed in series between the first transistor 215 and the second transistor 220. Like the variable resistances 205 and 210, the variable resistances 225 and 230 can be controlled to compensate for capacitance and resistance values that vary depending on process variation. However, in other embodiments, the variable resistances 225 and 230 may be replaced by one or more static (i.e., unchanging) resistors. The peaking stage 200 also includes a variable capacitance 235 and two static resistors R1 and R2 which are in parallel with the variable resistors 225 and 230. The peaking stage 200 can be disabled by disconnecting the variable capacitor 235 from the circuit.
Moreover, the peaking stage 200 includes a third transistor 240 and a fourth transistor 245 whose gates are coupled to a biasing voltage (V_BIAS) for biasing the peaking stage 200. Moreover, the third transistor 240 and fourth transistor 245 are coupled to a reference voltage—e.g., ground.
Equation 1 defines the gain (A₀) of the peaking stage 200, where R_Lis the resistance value of one of the variable resistances 205 or 210 and R_Sis the resistance value of one of the variable resistances 225 or 230.
$\begin{matrix} A_{0} = \frac{g_{m} R_{L}}{1 + g_{m} R_{S}} & (1) \end{matrix}$
Equation 2 defines the peaking frequency (ω_Z) of the peaking stage 200.
$\begin{matrix} ω_{z} = \frac{1}{R_{S} C_{S}} & (2) \end{matrix}$
Equation 3 defines a first pole frequency (ω_p1) of the peaking stage 200.
$\begin{matrix} ω_{p 1} = \frac{1 + g_{m} R_{S}}{R_{S} C_{S}} & (3) \end{matrix}$
Equation 4 defines a second pole frequency (ω_p2) of the peaking stage 200.
$\begin{matrix} ω_{p 2} = \frac{1}{R_{L} C_{L}} & (4) \end{matrix}$
The values of the gain (A₀) peaking frequency (ω_Z), the first pole frequency (ω_p1), and the second pole frequency (ω_p2) are the frequency characteristics of the peaking stage 200. As shown by Equations 2, 3, and 4, the values of these frequencies depend on the values of R_S, R_L, C_s, and C_L. However, because the resistances R_S, R_L(i.e., variable resistances 205, 210, 225, and 230) are variable rather than static, the peaking stage 200 can adjust these resistances to compensate for process variations. Put differently, if the variable resistances 205, 210, 225, and 230 where fixed resistances, the values of the frequency characteristics of the peaking stage 200 would vary depending on process variations. However, as described below, the variable resistances 205, 210, 225, and 230 can be adjusted such that the frequency characteristics are invariant to process variations. A process invariant peaking stage is useful for many different applications such as a high-speed SERDES, high-speed display applications for the input device 100, and the like.
FIG. 2B is a chart 250 which illustrates a transfer function for the peaking stage in FIG. 2A in accordance with an embodiment described herein. The Y axis of the chart 250 illustrates the gain of the peaking stage while the X axis illustrates the frequency of the signal inputted to the peaking stage. As shown, for frequencies below the peaking frequency (ω_Z), the peaking stage operates in a low frequency gain region where the gain is relatively flat (i.e., A₀). However, at the peaking frequency, the gain increases until the first pole frequency (ω_p1) is reached (also referred to as the saturation frequency). Between the first pole frequency and the second pole frequency (ω_p2), the gain of the peaking stage is again relatively flat. The gain of the peaking stage between the first and second pole frequencies can be expressed as:
$\begin{matrix} A = A_{0} \frac{w_{p 1}}{w_{z}} & (5) \end{matrix}$
After the second pole frequency, the gain of the peaking stage begins to decrease. Using the variable gain shown in chart 250, the peaking stage can equalize power distribution between the frequencies in a signal. For example, if the higher frequencies in a signal (e.g., frequencies between the first and second pole frequencies) have less power than the frequencies below the peaking frequency, inputting this signal into the peaking stage increases the power of the higher frequencies relative to the lower frequencies. As used herein, the terms “equalizer,” “equalization,” “equalize,” or “equalizing” does not mean the peaking stage ensures the power across all frequencies is precisely equal, but rather outputs a signal with improved distribution of the power across its frequencies relative to an input signal.
FIG. 3 illustrates a reference current generator 300 for a peaking stage in accordance with an embodiment described herein. In one embodiment, the reference current generator 300 outputs one or more reference currents which are used in other circuits in the peaking stage as described below. The reference current generator 300 includes a first current mirror formed by transistor 305 and 310 and a second current mirror formed by transistors 315 and 322. The drain of transistor 345 generates a positive reference current (I_REFP) while the drain of transistor 340 generates a negative reference current (I_REFN). The reference current generator 300 is also coupled to a startup circuit 335 which is used to start the generator 300 when the peaking stage is turned on or initialized to ensure the circuit does not stay in the zero current state, and the startup circuit 335 will shut off itself when the generator 300 is in a normal working state.
The reference current I_REFis proportional to the square of the frequency (f) of the clock and the value of capacitor C₁as shown in the following equation:
I _REF∝(f*C ₁)² (6)
Thus, as the value of the capacitor C₁changes due to a process variation, the reference current also changes.
The source of transistor 322 is coupled to a switched capacitor network that forms an equivalent resistance 320 (R_EQ). The switched capacitor network includes a switch 325 (S₂) and a switch 330 (S₁) which are activated based on the clocking values ϕ and ϕ, where f=frequency(ϕ). In one embodiment, the switches 325 and 330 are activated using a non-overlapped signal where the switches 325 and 330 are never on at the same time. However, the switches 325 and 330 may both be off at the same time.
When the switch 325 is off (deactivated) and the switch 330 is on (activated) as shown in FIG. 3, the capacitor C₁is discharged. Conversely, when the switch 325 is on and the switch 330 is off, the capacitor C₁is charged in parallel with the capacitor C₂. By controlling the switches, the value of the equivalent resistance 320 is proportional to (f*C₁) and the value of the reference current is as follows:
$\begin{matrix} I_{REF} = \frac{{({fC}_{1})}^{2}}{\frac{1}{2} μ C_{ox}^{'} (\frac{W}{L})} {(1 - \frac{1}{\sqrt{m}})}^{2} & (7) \end{matrix}$
Equation 7 can be simplified using a ratio of constants B₀as:
I _REF =B ₀(fC ₁)²∝(fC ₁)² (8)
Moreover, the gain of the reference current generator 300 is also proportional to the clock frequency and the capacitor C₁. As such, these values are dependent on the clock frequency (which is based on a reference clock such as a crystal oscillator) and the value of the capacitor C₁which can vary depending on process variations.
FIG. 4 illustrates a load impedance control generator 400 (e.g., a resistance control circuit) for a peaking stage in accordance with an embodiment described herein. As shown, the load impedance control generator 400 uses the positive reference current (i.e., I_REFP) generated by the reference current generator 300 in FIG. 3 to control the variable resistance 401 (R_EQP) in the peaking stage. That is, the load impedance control generator 400 generates a digital control signal 430 which adjusts the value of the variable resistance 401. However, as will be described in FIG. 8, the digital control signal 430 can also control the variable resistances 205 and 210 (i.e., R_EQP1and R_EQP2) in the peaking stage shown in FIG. 2.
The load impedance control generator 400 includes a switched capacitor network that forms an equivalent resistance 405 which operates in a similar manner as the switched capacitor network shown in FIG. 3. In one embodiment, the capacitance value of C₀is greater than the value of C₃to keep the voltage ripple at node V1 small. The equivalent resistance 405 includes a first switch 415 and a second switch 410 which, in one embodiment, are driven by non-overlapping signals.
The switched capacitor network outputs a current I₁while the variable resistor 401 outputs the current I₂. Both of the currents I₁and I₂are fed into a current mirror formed by transistors 440 and 445. To make these currents equal, the load impedance control generator 400 feeds voltages V₁and V₂into respective inputs of a comparator 420.
The output of the comparator 420 varies according to the difference between the currents I₁and I₂. The output of the comparator 420 is coupled to an analog to digital converter (ADC) 425 which generates the digital control signal 430 which varies according to the difference between the currents I₁and I₂. Stated generally, the digital control signal 430 adjusts the value of the variable resistance 401 until the currents I₁and I₂are equal. As a result, the resistance values of the variable resistance 401 and the equivalent resistance 405 are equal. Thus, the resistance value of variable resistance 401 can be expressed as:
$\begin{matrix} R_{EQP} = \frac{1}{{fC}_{3}} & (9) \end{matrix}$
As shown by Equation 9, the value of the variable resistance 401 varies according to the value of the capacitor C₃which can vary in response to process variations and the frequency (f) of the clock.
FIG. 5 illustrates the variable resistance 401 for the peaking stage 200 in accordance with an embodiment described herein. In one embodiment, the variable resistance 401 receives the digital control signal 430 which activates or deactivates a plurality of transistors 505. Each of the transistors 505 is coupled to a respective fixed, or static, resistor 510. The value of the digital control signal 430 determines the number of the transistors 505 that are activated which combines the resistors 510 in parallel. In this manner, the load impedance control generator can alter the variable resistance 401 in the peaking stage 200 shown in FIG. 2.
In one embodiment, the resistors 510 are poly resistors, and as such, the value of the resistors 510 may change because of process variations. However, because of the feedback loop shown in FIG. 4 where the current (or voltage) of the variable resistance 401 is compared to the current (or voltage) outputted by the equivalent resistance 405, the load impedance control generator 400 can adjust the number of resistors 510 coupled in parallel, thereby changing the total resistance value of the variable resistance 401. Thus, even as the underlying value of the static resistors 510 changes, the load impedance control generator 400 can compensate for these changes using the digital control signals 430.
In one embodiment, the circuit schematic for the variable resistance 401 in the load impedance control generator 400 is also used for the variable resistance 205 and 210 in the peaking stage 200. In one example, the same digital control signal 430 sets the resistance values of the variable resistances 401, 205, and 210 to the same value.
FIG. 6 illustrates a degeneration resistance control generator 600 in accordance with an embodiment described herein. The degeneration resistance control generator 600 is similar to the load impedance control generator 400 shown in FIG. 4. However, the peaking stage uses the degeneration resistance control generator 600 to control the variable resistance 225 and 230 (i.e., R_EQN1and R_EQN2) shown in FIG. 2. To do so, the degeneration resistance control generator 600 uses the negative reference current (I_REFN), a switched capacitor network (i.e., equivalent resistance 620), a first comparator 605, a second comparator 625, and a ADC 610 to output a digital control signal 615 that varies the resistance of a variable resistance 601. As described below, in one embodiment, the digital control signal 615 also controls the variable resistances 225 and 230 in the peaking stage.
FIG. 7 illustrates the variable resistance 601 for the degeneration resistance control generator 600 in accordance with an embodiment described herein. In one embodiment, the variable resistance 601 receives the digital control signal 615 which activates or deactivates a plurality of transistors 710. Each of the transistors 710 is coupled to a respective fixed or static resistor 705 (e.g., poly resistors). The value of the digital control signal 615 determines the number of the transistors 710 that are activated which combines the resistors 705 in parallel. In this manner, the degeneration resistance control generator can alter the variable resistance 601 in the peaking stage 200 shown in FIG. 2.
In one embodiment, the value of the resistors 705 changes because of process variations used to form the peaking stage. However, because of the feedback loop shown in FIG. 6 where the current (or voltage) of the variable resistance 601 is compared to the current (or voltage) outputted by the equivalent resistance 620, the degeneration resistance control generator 600 can adjust the number of resistors 705 coupled in parallel, thereby changing the total resistance value of the variable resistance 601. Thus, even as the underlying value of the static resistors 705 changes, the degeneration resistance control generator 600 can compensate for these changes using the digital control signals 615.
In one embodiment, the circuit schematic for the variable resistance 601 is also used for the variable resistances 225 and 230 in the peaking stage 200. In one example, the same digital control signal 615 sets the resistance values of the variable resistances 601, 225, and 230 to the same value.
FIG. 8 illustrates a peaking stage 800 for an amplifier in accordance with an embodiment described herein. The peaking stage 800 is the same as the peaking stage 200 shown in FIG. 2 except that the peaking stage 800 illustrates the digital control signal 430 outputted by the load impedance control generator and the digital control signal 615 outputted by the degeneration resistance control generator. In one embodiment, the digital control signals 430 adjust the values of the variable resistances 205 and 210 to the same resistance value while the digital control signal 615 adjusts the values of the variable resistances 225 and 230 to the same resistance value. Although respective digital control signals are shown for variable resistance 205 and 210 and for variable resistances 225 and 230, the peaking stage 800 may generate a digital control signal for each of the variable resistances 205, 210, 225, and 230 individually.
The gain of the peaking stage 800 can be expressed as:
$\begin{matrix} A_{0} = \frac{g_{m} R_{L}}{1 + g_{m} R_{S}} = \frac{B_{1} B_{2} ({fC}_{1}) {({fC}_{3})}^{- 1}}{1 + B_{1} B_{2} ({fC}_{1}) {B_{3} ({fC}_{1})}^{- 1}} & (11) \end{matrix}$
In Equation 11, the values B₁, B₂, and B₃represent constant ratios that do not change in response to process variations. Equation 11 can be further reduced as follows:
$\begin{matrix} A_{0} = \frac{B_{1} B_{2} B_{5}}{1 + B_{1} B_{2} B_{3}} & (12) \end{matrix}$
As illustrated by Equation 12, the gain of the peaking stage 800 does not depend on the value of the capacitors or resistors in the underlying circuitry. Instead, the gain depends on the value of the constants which do not change depending on process variation. Thus, the peaking stage 800 has a gain which is invariant to process variations.
The peaking frequency of the peaking stage 800 can be expressed as:
$\begin{matrix} ω_{z} = \frac{1}{R_{S} C_{S}} = \frac{1}{{B_{3} ({fC}_{1})}^{- 1} B_{4} C_{1}} = \frac{1}{{fB}_{3} B_{4}} & (13) \end{matrix}$
Like the gain, Equation 13 illustrates that the peaking frequency of the peaking stage 800 is invariant to process variations. Here, the peaking frequency depends on the clock frequency (which depends on a crystal oscillator that generates the clock) and the constant ratios B₃and B₄. Thus, as the values of the underlying static resistors and capacitive elements changes, the peaking frequency is unaffected.
The first pole frequency of the peaking stage 800 can be expressed as:
$\begin{matrix} ω_{p 1} = \frac{1 + g_{m} R_{S}}{R_{S} C_{S}} = \frac{1 + B_{1} B_{2} B_{3}}{{fB}_{3} B_{4}} & (14) \end{matrix}$
Like the peaking frequency, first pole frequency depends on the clock frequency and the constant B ratios. As such, the first pole frequency is invariant to process variation and is unaffected as the values of the underlying static resistors and capacitive elements changes.
The second pole frequency of the peaking stage 800 can be expressed as:
$\begin{matrix} ω_{p 2} = \frac{1}{R_{L} C_{L}} = \frac{1}{{({fC}_{3})}^{- 1} C_{L}} & (15) \end{matrix}$
As shown by Equation 15, the second pole frequency depends on the capacitance C₃and C_Lthus may vary depending on process variation. However, the second pole frequency is not as important as the gain, peaking frequency, and the first pole frequency of the peaking stage 800 which are invariant to the processing corner in which the peaking stage 800 was fabricated.
Thus, the embodiments and examples set forth herein were presented in order to best explain the embodiments in accordance with the present technology and its particular application and to thereby enable those skilled in the art to make and use the present technology. However, those skilled in the art will recognize that the foregoing description and examples have been presented for the purposes of illustration and example only. The description as set forth is not intended to be exhaustive or to limit the disclosure to the precise form disclosed.
In view of the foregoing, the scope of the present disclosure is determined by the claims that follow.

Claims

1. A peaking stage, comprising:

a first variable resistance comprising a first end coupled to a voltage rail;

a second variable resistance comprising a first end coupled to the voltage rail;

a resistance control circuit comprising a first comparator and a first analog to digital converter (ADC) configured to generate a first digital signal for setting a first resistance value of the first variable resistance and a second resistance value of the second variable resistance;

a first transistor coupled to a second end of the first variable resistance;

a second transistor coupled to a second end of the second variable resistance, wherein the first and second transistors are configured to generate equalized output signals based on respective input signals; and

a capacitive switching network comprising a plurality of capacitors and a plurality of switches, wherein the plurality of switches are selectively activated based on a clock signal, wherein an output of the capacitive switching network is coupled to a first input of the first comparator, and

wherein the second end of the first variable resistance is coupled to a second input of the first comparator.

2. The peaking stage of claim 1, wherein the first variable resistance comprises:

a plurality of transistors comprising respective gates coupled to the first digital signal; and

a plurality of resistors respectively coupled to a first end of one of the plurality of transistors, wherein the first digital signal selectively activates the plurality of transistors to change the first resistance value of the first variable resistance.

3. (canceled)

4. The peaking stage of claim 1, wherein the resistance control circuit comprises:

a current mirror, wherein the output of the capacitive switching network couples to a third transistor in the current mirror and the second end of the first variable resistance couples to a fourth transistor in the current mirror,

wherein the first digital signal adjusts the first resistance value of the first variable resistance such that a first current flowing through the third transistor substantially matches a second current flowing through the fourth transistor.

5. The peaking stage of claim 1, further comprising:

a reference current generator comprising:

a current mirror, wherein a third transistor in the current mirror is coupled to the capacitive switching network and a fourth transistor in the current mirror is coupled to a reference voltage;

a fifth transistor coupled to the current mirror, wherein the fifth transistor generates a reference current used by the resistance control circuit to generate the first digital signal.

6. The peaking stage of claim 1, further comprising:

a third variable resistance coupled to the first transistor; and

a fourth variable resistance coupled to the second transistor, wherein the third and fourth variable resistances are in series.

7. The peaking stage of claim 6, further comprising:

a second resistance control circuit comprising a second comparator and a second ADC configured to generate a second digital signal for setting a third resistance value of the third variable resistance and a fourth resistance value of the fourth variable resistance.

8. The peaking stage of claim 6, further comprising:

a variable capacitor coupled between the first and second transistors, wherein the variable capacitor is coupled in parallel with the third and fourth variable resistances.

9. The peaking stage of claim 6, further comprising:

a third transistor coupled a reference voltage, wherein the third transistor is directly coupled to the first transistor and the third variable resistance; and

a fourth transistor coupled to the reference voltage, wherein the fourth transistor is directly coupled to the second transistor and the fourth variable resistance.

10. An amplifier comprising:

a peaking stage comprising:

a first variable resistance comprising a first end coupled to a voltage rail;

a third variable resistance coupled to the first transistor;

a fourth variable resistance coupled to the second transistor, wherein the third and fourth variable resistances are in series;

a first resistance control circuit comprising a first comparator configured to generate a first signal for setting a first resistance value of the first variable resistance and a second resistance value of the second variable resistance;

a first transistor coupled to a second end of the first variable resistance; and

a second transistor coupled to a second end of the second variable resistance, wherein the first and second transistors are configured to generate equalized output signals based on respective input signals received by the amplifier.

11. The amplifier of claim 10, wherein the first variable resistance comprises:

a plurality of transistors comprising respective gates coupled to the first signal; and

a plurality of resistors respectively coupled to a first end of one of the plurality of transistors, wherein the first signal selectively activates the plurality of transistors to change the first resistance value of the first variable resistance.

12. The amplifier of claim 10, wherein the first resistance control circuit comprises:

a capacitive switching network comprising a plurality of capacitors and a plurality of switches, wherein the plurality of switches are selectively activated based on a clock signal, and wherein an output of the capacitive switching network is coupled to a first input of the first comparator,

13. The amplifier of claim 12, wherein the first resistance control circuit comprises:

wherein the first signal adjusts the first resistance value of the first variable resistance such that a first current flowing through the third transistor substantially matches a second current flowing through the fourth transistor.

14. (canceled)

15. The amplifier of claim 10, wherein the peaking stage comprises:

a second resistance control circuit comprising a second comparator configured to generate a second signal for setting a third resistance value of the third variable resistance and a fourth resistance value of the fourth variable resistance.

16. The amplifier of claim 10, wherein the peaking stage comprises:

17. The amplifier of claim 10, wherein the peaking stage comprises:

a third transistor coupled to a reference voltage, wherein the third transistor is directly coupled to the first transistor and the third variable resistance; and

18. An integrated circuit, comprising:

a peaking stage comprising:

a first variable resistance comprising; a first end coupled to a voltage rail, a plurality of transistors, and a plurality of resistors respectively coupled to a first end of one of the plurality of transistors;

a resistance control circuit comprising a comparator configured to generate a first signal for setting a first resistance value of the first variable resistance and a second resistance value of the second variable resistance, wherein the first signal is coupled to respective gates of the plurality of transistors, and selectively activates the plurality of transistors to change the first resistance value of the first variable resistance;

a second transistor coupled to a second end of the second variable resistance, wherein the first and second transistors are configured to generate equalized output signals based on respective input signals.

19. (canceled)

20. The integrated circuit of claim 18, wherein the resistance control circuit comprises:

a capacitive switching network comprising a plurality of capacitors and a plurality of switches, wherein the plurality of switches are selectively activated based on a clock signal, and wherein an output of the capacitive switching network is coupled to a first input of the comparator,

wherein the second end of the first variable resistance is coupled to a second input of the comparator.

21. A method for generating equalized output signals, the method comprising:

generating a first signal for setting a first resistance value of a first variable resistance having a first end coupled to a voltage rail and a second resistance value of a second variable resistance having a first end coupled to the voltage rail;

selectively activating a plurality of switches of a capacitive switching network having a plurality of capacitors based on a clock signal, wherein an output of the capacitive switching network is coupled to a first input of a first comparator and a second input of the first comparator is coupled to a second end of the first variable resistance; and

generating the equalized output signals from a first transistor coupled to a second end of the first variable resistance and a second transistor coupled to a second end of the second variable resistance based on respective input signals.

22. The method of claim 21 further comprising:

adjusting the first resistance value of the first variable resistance with the first signal such that a first current flowing through a third transistor of a current mirror substantially matches a second current flowing through a fourth transistor of the current mirror.

23. The method of claim 21 further comprising:

generate a second signal for setting a third resistance value of a third variable resistance and a fourth resistance value of a fourth variable resistance.