US20180063362A1 - Serial data transfer using transfer type information to select a storage unit - Google Patents
Serial data transfer using transfer type information to select a storage unit Download PDFInfo
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- US20180063362A1 US20180063362A1 US15/804,628 US201715804628A US2018063362A1 US 20180063362 A1 US20180063362 A1 US 20180063362A1 US 201715804628 A US201715804628 A US 201715804628A US 2018063362 A1 US2018063362 A1 US 2018063362A1
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- transfer type
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/21—Intermediate information storage
- H04N1/2104—Intermediate information storage for one or a few pictures
- H04N1/2158—Intermediate information storage for one or a few pictures using a detachable storage unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/14—Conversion to or from non-weighted codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N2201/00—Indexing scheme relating to scanning, transmission or reproduction of documents or the like, and to details thereof
- H04N2201/0077—Types of the still picture apparatus
- H04N2201/0094—Multifunctional device, i.e. a device capable of all of reading, reproducing, copying, facsimile transception, file transception
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Information Transfer Systems (AREA)
Abstract
A serial data transfer apparatus includes a decoder, a counter, and a calculation circuit. The decoder is configured to decode serial data to obtain written data, a base address, and transfer type information for specifying a storage unit for storing the written data. The counter is configured to count a frame synchronization pulse. The calculation circuit is configured to generate a chip select signal based on the transfer type information and the base address, as decoded by the decoder, and a count value of the frame synchronization pulse output by the counter.
Description
- This application is a continuation of U.S. patent application Ser. No. 14/796,672, filed on Jul. 10, 2015, the entire contents of each of which are incorporated herein by reference.
- Embodiments described herein relate generally to a serial data transfer apparatus, a serial data transfer method, an image formation apparatus, and a recording medium.
- Serial communication is used for communication between a master device and a plurality of slave devices. For writing data in registers in the slave devices by the master device, the master device sends a pair of address data and serial data to the slave devices. For writing the data in the plurality of slave devices, it is necessary for the master device to designate an address for each of the registers in the slave devices and write the data. Therefore, as the number of registers in the slave devices increases, it takes longer to write all the data in the registers.
-
FIG. 1 is a diagram illustrating a configuration example of an image formation apparatus according to an embodiment. -
FIG. 2 is a diagram illustrating a configuration example of an image processing unit according to the embodiment. -
FIG. 3 is a diagram illustrating a timing of data as a target of serial communication according to the embodiment. -
FIG. 4 is a diagram illustrating an example of transfer type information according to the embodiment. -
FIG. 5 is a diagram illustrating an order of burst access when a second bit of the transfer type information is 1 and a third bit thereof is 0 according to the embodiment. -
FIG. 6 is a diagram illustrating an order of the burst access when the second bit of the transfer type information is 1 and the third bit thereof is 1 according to the embodiment. -
FIG. 7 is a diagram illustrating an order of the burst access when the second bit of the transfer type information is 0 and the third bit thereof is 1 according to the embodiment. -
FIG. 8 is a diagram illustrating an order of the burst access when the second bit of the transfer type information is 0 and the third bit thereof is 0 according to the embodiment. -
FIG. 9 is a diagram illustrating a timing of data as a target of serial communication in a case of burst access and direct access to storage units according to the embodiment. - In general, according to one embodiment, a serial data transfer apparatus includes a decoder, a counter, and a calculation circuit. The decoder is configured to decode serial data to obtain written data, abase address, and transfer type information for specifying a storage unit for storing the written data. The counter is configured to count a frame synchronization pulse. The calculation circuit is configured to generate a chip select signal based on the transfer type information and the base address, as decoded by the decoder, and a count value of the frame synchronization pulse output by the counter.
- Hereinafter, a description will be given of the serial data transfer apparatus according to the embodiment with reference to drawings.
FIG. 1 is a diagram illustrating a configuration example of a serialdata transfer apparatus 1 according to the embodiment. For example, the serialdata transfer apparatus 1 is a quadruple tandem-type image formation apparatus. In the embodiment, a description will be given of a case where the serialdata transfer apparatus 1 is an image formation apparatus. - An
image formation apparatus 1 includes a central processing unit (CPU) 10, anengine 20, an image processing unit 30_1, and an image processing unit 30_2. - The
CPU 10 performs serial communication with the image processing unit 30_1 and the image processing unit 30_2. TheCPU 10 is connected to the image processing unit 30_1 and the image processing unit 30_2 via a plurality of different communication lines. TheCPU 10 is a master device. Although a configuration in which the number of image processing units for the serial communication is two will be described, the number is not limited thereto. - The communication lines include a first communication line, a second communication line, and a third communication line. The first communication line transmits a frame synchronization pulse (FSS) to the image processing unit 30_1 and the image processing unit 30_2. The second communication line is a line for transmitting a serial clock (SCLK) to the image processing unit 30_1 and the image processing unit 30_2. The third communication line transmits serial data (SDL) to the image processing unit 30_1 and the image processing unit 30_2.
- The
engine 20 has a print function, a facsimile function, a scanner function, and a copy function. For example, theengine 20 is a print engine and a scanner engine. Theengine 20 reads an original document. Theengine 20 sends image data read from the original document to the image processing unit 30_1. - The image processing unit 30_1 acquires the image data from the
engine 20. The image processing unit 30_1 separates colors of the acquired image data into Y, M, C, and K. The image processing unit 30_1 outputs the image data after the color separation to theengine 20. In addition, the image processing unit 30_1 performs serial communication with theCPU 10. For example, the image processing unit 30_1 is a hardware device. For example, the hardware device is an application specific integrated circuit (ASIC). The image processing unit 30_1 is a slave device. Since the image processing unit 30_2 has the same configuration as that of the image processing unit 30_1, the description thereof will be omitted. -
FIG. 2 is a block diagram illustrating a configuration example of the image processing unit 30_1. The image processing unit 30_1 includes adecoder 31, a transfer typeinformation storage unit 32, a baseaddress storage unit 33, acounter 34, acontroller 35, acalculation circuit 36, adata holding unit 37, andstorage units 301 to 304. - The
decoder 31 acquires the frame synchronization pulse, the serial clock, and the serial data from theCPU 10 via the communication lines. Thedecoder 31 decodes the serial data.FIG. 3 is a timing chart of data as a target of serial communication between the image processing unit 30_1 and theCPU 10. According to the embodiment, a size of serial data of one frame in the serial communication between the image processing unit 30_1 and theCPU 10 is 16 bits. The first frame in the serial data during burst access includes transfer type information. For example, the transfer type information determines which of burst access or direct access is to be selected. The burst access is an access method where an address is not designated for each data item. The direct access is an access method of designating an address for each data item. Direct access is a well-known technology and the description thereof will be omitted for clarity. The next frame includes a base address. The base address is an address that is a reference for writing data in thestorage units 301 to 304 during the burst access. The serial data after the base address is data to be written in thestorage units 301 to 304.FIG. 4 is a diagram illustrating an example of the transfer type information. In addition, the transfer type information illustrated inFIG. 4 is an example, and the exemplary embodiments are not limited thereto. - The first bit (D0) represents access information. If D0 is logic “1”, the access information represents the burst access. If D0 is logic “0”, the access information represents the direct access. The second bit (D1) and the third bit (D2) represent information necessary for specifying modules to be accessed. For example, the modules are the
storage units 301 to 304. A case where the second bit (D1) is logic “1” and the third bit (D2) is logic “0” represents that one of the plurality of modules (storage units 301 to 304) is to be accessed. A case where the second bit (D1) is logic “1” and the third bit (D2) is logic “1” represents that theCPU 10 is to access the modules in order with reference to the base address. A case where the second bit (D1) is logic “0” and the third bit (D2) is logic “1” represents that a module of every two modules is to be accessed with reference to the base address. A case where the second bit (D1) is logic “0” and the third bit (D2) is logic “0” represents that theCPU 10 is to access a base address of the adjacent image processing unit 30_2 with reference to the base address of the image processing unit 30_1. The fourth bit (D3) is used when the image processing unit is cascade-connected. If the fourth bit (D3) is logic “1”, continuous burst access between the image processing unit 30_1 and the image processing unit 30_2 is allowed. - The fifth bit (D4) to the eighth bit (D7) represent the image processing unit as a target of the burst access among the cascade-connected image processing units.
- The ninth bit (D8) to the sixteenth bit (D15) represent a burst size. For example, the burst size is a total number of times of the burst access (hereinafter, referred to as a “burst access threshold value”). In addition, the transfer type information from the second bit (D1) to the sixteenth bit (D15) is information during the burst access.
- The
decoder 31 reads the transfer type information from the received serial data. Thedecoder 31 interprets the transfer type information of the received serial data. Thedecoder 31 writes the read transfer type information in the transfer typeinformation storage unit 32. If the read transfer type information is burst access information, for example, thedecoder 31 stores logic “1” on the transfer typeinformation storage unit 32. That is, thedecoder 31 sets a flag bit to the transfer typeinformation storage unit 32. A case where logic “1” is stored on the transfer typeinformation storage unit 32 represents that the burst access to thestorage units 301 to 304 are currently performed. - The
decoder 31 reads the base address from the received serial data. Thedecoder 31 writes the base address read from the received serial data in the baseaddress storage unit 33. - The counter 34 counts the number of frames in the data sent during the burst access. For example, the
counter 34 counts the frame synchronization pulse during the burst access. - The
controller 35 reads the count value of thecounter 34 at a constant cycle. Thecontroller 35 resets the transfer typeinformation storage unit 32 based on the count value or the number of times of the burst access. If the number of times of the burst access is equal to or greater than the burst access threshold value, for example, thecontroller 35 resets the transfer typeinformation storage unit 32. - The
calculation circuit 36 reads the base address from the baseaddress storage unit 33. Thecalculation circuit 36 reads the count value from thecounter 34. Thecalculation circuit 36 selects a storage unit as a target of the burst access among thestorage units 301 to 304 based on the transfer type information, the base address, and the count value. Thecalculation circuit 36 outputs a chip select signal to the selected storage unit. In addition, the transfer type information is information that determines a module to be accessed, for example. - The
data holding unit 37 holds data (hereinafter, referred to as “written data”) to be written in thestorage units 301 to 304 from the serial data. Thedata holding unit 37 outputs the written data to thestorage units 301 to 304. - The
storage units 301 to 304 acquire the chip select signal and store the written data acquired from thedata holding unit 37. For example, thestorage units 301 to 304 are registers corresponding to Y, M, C, and K, respectively. Thestorage units 301 to 304 have the same configuration. - Next, a description will be given of a method of the burst access to the
storage units 301 to 304. In addition, the order described below is an example, and the embodiments are not limited thereto. In addition, a description will be given of a case where thestorage units 301 to 304 are registers corresponding to Y, M, C, and K, respectively. - In the example shown below, the base address is 0000h.
-
FIG. 5 is a diagram illustrating a method of burst access when the second bit (D1) of the transfer type information is logic “1” and the third bit (D2) is logic “0”. - For example, the
storage unit 301 includes registers REG0_0 to REG0_5 corresponding toaddresses 0000h to 0005h, respectively. Thestorage unit 302 includes registers REG1_0 to REG1_5 corresponding toaddresses 1000h to 1005h, respectively. Thestorage unit 303 includes registers REG2_0 to REG2_5 corresponding toaddresses 2000h to 2005h, respectively. Thestorage unit 304 includes registers REG3_0 to REG3_5 corresponding toaddresses 3000h to 3005h, respectively. - As illustrated in
FIG. 5 , theCPU 10 accesses the register REG0_0 designated by thebase address 0000h first. Then, thestorage unit 301 writes written data corresponding to one frame in the register REG0_0. Then, thestorage unit 301 writes written data corresponding to the next frame in the register REG0_1 following the register REG0_0. If the written data is written to the register REG0_5, theCPU 10 performs burst access to a register designated by a lower address in the next module. In addition, the next module may be set in advance. According to the embodiment, the burst access is performed in order of thestorage unit 301, thestorage unit 302, thestorage unit 303, and thestorage unit 304. Therefore, thestorage unit 302 writes the written data corresponding to one frame in the register REG1_0. As described above, the burst access is sequentially performed to the continuing registers from the register designated by the base address, and the written data is written therein. That is, after the written data is written in a register, the module accesses an address obtained by incrementing an address of the register. -
FIG. 6 is a diagram illustrating a method of the burst access when the second bit (D1) of the transfer type information is logic “1” and the third bit (D2) is logic “1”. Thestorage unit 301 accesses the register REG0_0 designated by thebase address 0000h. Then, thestorage unit 301 writes the written data corresponding to one frame in the register REG0_0. After the written data is written in the register REG0_1, the written data corresponding to the next frame is written in the register in thestorage unit 302. The register in thestorage unit 302, in which the written data is to be written, is the register REG1_1 corresponding to the register REG0_1. That is, the written data is written in a register in a module following a module including the register in which the written data is previously written. Therefore, theCPU 10 accesses theaddresses storage unit 301 is accessed. At this time, the address of thestorage unit 301 to be accessed is an address obtained by incrementing an address which is previously written in thestorage unit 301. Therefore, thestorage unit 301 accesses the address 0001h and writes the data to be written in the REG0_1. Then, the access is performed to an address obtained by incrementing an address which is previously written in the storage unit itself in order of thestorage unit 302, thestorage unit 303, and thestorage unit 304. Then, the written data is written in the register corresponding to the address. -
FIG. 7 is a diagram illustrating a method of the burst access when the second bit (D1) of the transfer type information is logic “0” and the third bit (D2) is logic “1”. - As illustrated in
FIG. 7 , thestorage unit 301 accesses the register REG0_0 designated by thebase address 0000h. Then, thestorage unit 301 writes the written data corresponding to one frame in the register REG0_0. If the written data corresponding to one frame is written, an address of thestorage unit 303 as a module after skipping one module is accessed. The address to be accessed is theaddress 2000h corresponding to thebase address 0000h. Then, the written data corresponding to the next frame is written in the register REG2_0 corresponding to theaddress 2000h. If the written data is written in the register REG2_0, an address of thestorage unit 301 as a module after skipping one module is accessed. At this time, the address of thestorage unit 301 to be accessed is an address obtained by incrementing an address that is previously written in thestorage unit 301. Therefore, thestorage unit 301 accesses the address 0001h and writes the data to be written in the REG0_1. As described above, the addresses are accessed in order of theaddress 0000h, theaddress 2000h, the address 0001h, theaddress 2001h, and so on. That is, the written data is sequentially written in the registers in the two modules (thestorage unit 301 and the storage unit 303). -
FIG. 8 is a diagram illustrating a method of the burst access when the second bit (D1) of the transfer type information is logic “0” and the third bit (D2) is logic “0”. As illustrated inFIG. 8 , thestorage unit 301 accesses the register REG0_0 designated by thebase address 0000h. Then, thestorage unit 301 writes the written data corresponding to one frame in the register REG0_0. If the written data corresponding to one frame is written, thestorage unit 301 in the image processing unit 30_2 is accessed. That is, a register in another slave device is accessed. Another slave device may be set in advance. The module to be accessed is thestorage unit 301 in the image processing unit 30_2 corresponding to thestorage unit 301 in the image processing unit 30_1. In addition, the register to be accessed has the same address as the address accessed in thestorage unit 301 in the image processing unit 30_1. That is, thestorage unit 301 in the image processing unit 30_2 accesses thebase address 0000h. Then, thestorage unit 301 in the image processing unit 30_2 writes the written data corresponding to the next frame in the register REG0_0. If the written data corresponding to one frame is written as described above, a module of the next slave device is sequentially accessed. If the base addresses 0000h of all the slave devices are sequentially accessed, a slave device as a target of the access is regarded as a initial slave device. That is, the image processing unit 30_1 accesses an address obtained by incrementing an address which is previously written in the image processing unit 30_1. Then, the written data is written in the register corresponding to the address. As described above, the written data is sequentially written in the same storage units in adjacent slave devices for each frame. - According to at least one of the embodiments described above, the serial
data transfer apparatus 1 according to the embodiment includes thedecoder 31, thecounter 34, and thecalculation circuit 36. Thedecoder 31 decodes the written data and the serial data including the base address and the transfer type information for specifying thestorage units 301 to 304 for storing the written data. The counter 34 counts the frame synchronization pulse. Thecalculation circuit 36 generates the chip select signal based on the transfer type information and the base address, which are decoded by thedecoder 31, and the count value of the frame synchronization pulse. Due to such a configuration, it is not necessary for theCPU 10 to designate an address for each of the storage units in the serialdata transfer apparatus 1 and write the data. Therefore, it is possible to shorten the time until all the data items are written in the storage units. - According to the aforementioned embodiments, direct access to the
storage units FIG. 9 is a timing chart of data as a target of serial communication during the burst access and the direct access to thestorage units decoder 31 determines which of the burst access and the direct access to be selected based on the access information. - The image processing unit according to the aforementioned embodiments may be a software function unit or a hardware function unit, such as a large-scale integration (LSI) integrated circuit (IC).
- For an entirety or a part of the functions of the aforementioned image processing unit, a program for achieving the functions is recorded in a computer readable recording medium. Then, the program recorded in the recording medium may be achieved by the
CPU 10 executing the program. - In addition, the “computer readable recording medium” includes a portable medium and a storage unit. Examples of the portable medium include a flexible disk, a magnet-optical disk, a ROM, and a CD-ROM. Examples of the storage unit include a built-in hard disk in a computer system. Furthermore, the “computer readable recording medium” includes a network, a recording medium which dynamically holds the program for a short time, and a recording medium which holds the program for a predetermined time. Examples of the network include the Internet. Examples of the recording medium that dynamically holds the program include a communication line in a case of sending the program via a communication link. Examples of the recording medium which holds the program for a predetermined time include a volatile memory in a computer system which serves as a server or a client. In addition, the program may achieve a part of the aforementioned functions. Furthermore, the program may achieve the aforementioned functions in combination with a program which is recorded in advance in the computer system.
- While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Claims (19)
1. A serial data transfer apparatus, comprising:
a determination circuit configured to determine transfer type information according to information in serial data;
a writing circuit configured to write a base address read from the serial data in response to the transfer type being burst access;
a counting circuit configured to count a frame synchronization pulse during the burst access;
a reading circuit configured to read a count value from the counting circuit;
a selecting circuit configured to select a storage unit of a plurality of storage units based on the transfer type;
an output circuit configured to output a chip select signal to the selected storage unit; and
a holding circuit configured to hold data to be written to the selected storage unit.
2. The apparatus according to claim 1 ,
wherein the transfer type information indicates an order of the plurality of storage units in which to store the written data.
3. The apparatus according to claim 2 ,
wherein the output circuit is configured to sequentially output the chip select signal to adjacent storage units of the plurality of storage units based on the transfer type information.
4. The apparatus according to claim 2 ,
wherein the output circuit is configured to output the chip select signal to a storage unit of every two adjacent storage units of the plurality of storage units based on the transfer type information.
5. The apparatus according to claim 1 ,
wherein the transfer type information further includes access information for determining whether to perform burst access or direct access.
6. The apparatus according to claim 5 ,
wherein the writing circuit is configured to set a flag bit to a storage unit in response to the access information representing the burst access.
7. The apparatus according to claim 6 ,
wherein the serial data includes a burst access threshold value representing a total number of accesses to the storage unit, and
wherein the apparatus further comprises a controller configured to reset the flag bit in response to the number of accesses to the storage unit exceeding the burst access threshold value.
8. A serial data transfer method, comprising:
determining transfer type information according to information in serial data;
writing a base address read from the serial data in response to the transfer type being burst access;
counting a frame synchronization pulse during the burst access;
reading a count value from the counting circuit;
selecting a storage unit of a plurality of storage units based on the transfer type;
outputting a chip select signal to the selected storage unit; and
holding data to be written to the selected storage unit.
9. The method according to claim 8 ,
wherein the transfer type information indicates an order of the plurality of storage units in which to store the written data.
10. The method according to claim 9 ,
further comprising sequentially outputting the chip select signal to adjacent storage units of the plurality of storage units based on the transfer type information.
11. The method according to claim 9 ,
further comprising outputting the chip select signal to a storage unit of every two adjacent storage units of the plurality of storage units based on the transfer type information.
12. The method according to claim 8 ,
wherein the transfer type information further includes access information for determining whether to perform burst access or direct access.
13. An image formation apparatus, comprising:
an engine configured to read image data of an original document; and
a serial data transfer apparatus configured to write the image data in a storage unit,
wherein the serial data transfer apparatus includes:
a determination circuit configured to determine transfer type information according to information in serial data;
a writing circuit configured to write a base address read from the serial data in response to the transfer type being burst access;
a counting circuit configured to count a frame synchronization pulse during the burst access;
a reading circuit configured to read a count value from the counting circuit;
a selecting circuit configured to select the storage unit of a plurality of storage units based on the transfer type;
an output circuit configured to output a chip select signal to the selected storage unit; and
a holding circuit configured to hold data to be written to the selected storage unit.
14. The image formation apparatus according to claim 13 ,
wherein the transfer type information indicates an order of the plurality of storage units in which to store the written data.
15. The image formation apparatus according to claim 14 ,
wherein the output circuit is configured to sequentially output the chip select signal to adjacent storage units of the plurality of storage units based on the transfer type information.
16. The apparatus according to claim 14 ,
wherein the output circuit is configured to output the chip select signal to a storage unit of every two adjacent storage units of the plurality of storage units based on the transfer type information.
17. The apparatus according to claim 13 ,
wherein the transfer type information further includes access information for determining whether to perform burst access or direct access.
18. The apparatus according to claim 17 ,
wherein the writing circuit is configured to set a flag bit to a storage unit in response to the access information representing the burst access.
19. The apparatus according to claim 18 ,
wherein the serial data includes a burst access threshold value representing a total number of accesses to the storage unit, and
wherein the apparatus further comprises a controller configured to reset the flag bit in response to the number of accesses to the storage unit exceeding the burst access threshold value.
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US15/804,628 US20180063362A1 (en) | 2015-07-10 | 2017-11-06 | Serial data transfer using transfer type information to select a storage unit |
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US14/796,672 US9838561B2 (en) | 2015-07-10 | 2015-07-10 | Serial data transfer using transfer type information to select a storage unit |
US15/804,628 US20180063362A1 (en) | 2015-07-10 | 2017-11-06 | Serial data transfer using transfer type information to select a storage unit |
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US10503686B2 (en) * | 2015-12-09 | 2019-12-10 | Microchip Technology Incorporated | SPI interface with automatic slave select generation |
US10083754B1 (en) * | 2017-06-05 | 2018-09-25 | Western Digital Technologies, Inc. | Dynamic selection of soft decoding information |
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US6275890B1 (en) * | 1998-08-19 | 2001-08-14 | International Business Machines Corporation | Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration |
US20110246687A1 (en) * | 2010-03-31 | 2011-10-06 | Fujitsu Limited | Storage control apparatus, storage system and method |
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FR2705520B1 (en) * | 1993-05-19 | 1995-08-04 | Sgs Thomson Microelectronics | Device for adjusting the black level of a video signal. |
JP2012064021A (en) | 2010-09-16 | 2012-03-29 | Ricoh Co Ltd | Communication system, master device and slave device, and communication method |
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US6275890B1 (en) * | 1998-08-19 | 2001-08-14 | International Business Machines Corporation | Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration |
US20110246687A1 (en) * | 2010-03-31 | 2011-10-06 | Fujitsu Limited | Storage control apparatus, storage system and method |
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