US20180041232A1

US20180041232A1 - Impedance and swing control for voltage-mode driver

Info

Publication number: US20180041232A1
Application number: US15/227,853
Authority: US
Inventors: Siok Wei Lim; Kok Lim Chan; Kee Hian Tan; Hongyuan Zhao; Chin Yang Koay; Yohan Frans; Kun-Yung Chang
Original assignee: Xilinx Inc
Current assignee: Xilinx Inc
Priority date: 2016-08-03
Filing date: 2016-08-03
Publication date: 2018-02-08
Anticipated expiration: 2036-08-03
Also published as: US10033412B2; US20180102797A1; US9887710B1

Abstract

A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

Description

TECHNICAL FIELD

Examples of the present disclosure generally relate to electronic circuits and, in particular, to impedance and swing control for a voltage-mode driver.

BACKGROUND

In serial communication systems, a large percentage of the total power is consumed in the transmitter, which must provide for adequate signal swing on a low-impedance channel while maintaining an appropriate source termination. In addition, the transmitter often includes equalization to compensate for frequency-dependent loss in the channel. The driver circuit in the transmitter often consumes the majority of the power of the transmitter. Driver circuits can be implemented as current-mode drivers or voltage-mode drivers. Voltage-mode drivers are known to consume far less power in comparison to current-mode drivers. For example, a voltage-mode driver can consume four times less DC power than a current-mode driver to provide the same output swing.
A voltage-mode driver for a transmitter requires swing and impedance control such that the swing and common-mode/differential-mode return loss are within specifications. One technique for output signal swing control in a driver circuit is to use a single voltage regulator to generate a reference voltage that sets the voltage swing. However, with a single regulator, the common-mode will shift as the output swing of the driver circuit changes. Such a shift in the common-mode can cause the return loss to exceed specifications.

SUMMARY

Techniques for impedance and swing control for a voltage-mode driver are described. In an example, a driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.
In another example, a driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of enable circuits, a pair of inverters, and a pair of resistors, coupled between the differential input and the differential output; a first transistor coupled between the first common node and first source terminals of the pair of inverters; and a second transistor coupled between the second common node and second source terminals of the pair of inverters. The driver circuit further includes first and second replica output circuits coupled in series between the first and second common nodes; and a control circuit coupled to each of: respective gates of the first and second transistors in each of the plurality of output circuits; and the first and second replica output circuits.
In another example, a method of controlling a driver circuit in a transmitter includes receiving a plurality of outputs of an equalizer in the transmitter; coupling each of the plurality of outputs of the equalizer to at least one of a plurality of output circuits of the driver circuit; enabling first and second voltage regulators coupled to the plurality of output circuits; and enabling at least one of a plurality of current compensation circuits coupled between the first and second voltage regulators.
These and other aspects may be understood with reference to the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.

FIG. 1 is a block diagram depicting an example of a serial communication system.

FIG. 2 is a schematic diagram depicting an output driver according to an example.

FIGS. 3A-3B depict a schematic diagram of an output driver according to another example.

FIG. 4 is a flow diagram depicting a method of controlling a driver circuit in a transmitter according to an example.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples.

DETAILED DESCRIPTION

Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated or if not so explicitly described.
Techniques for impedance and swing control for a voltage-mode driver are described. In an example, a driver circuit includes output circuits between a differential input and a differential output. The output circuits are coupled between first and second common nodes. Each output circuit includes a pair of inverters and a pair of resistors coupled between the differential input and output. First source terminals of the pair of inverters are coupled to the first common node and second source terminals of the pair of inverters are coupled to the second common node. First and second voltage regulators are coupled to the first and second common nodes. A current compensation circuit is coupled between outputs of the first and second voltage regulators. Zero or more of the current compensation circuits can be selectively enabled to draw dummy current from the voltage regulators to improve return loss, as discussed further below. Further, use of dual regulators allows for a fixed common mode in both low- and high-swing modes. These and further aspects are discussed below with respect to the drawings.
FIG. 1 is a block diagram depicting an example of a serial communication system 100. The serial communication system 100 comprises a transmitter 112 coupled to a receiver 126 over transmission medium 160. The transmitter 112 can be part of a serializer-deserializer (SERDES) 116. The receiver 126 can be part of a SERDES 122. The transmission medium 160 comprises an electrical path between the transmitter 112 and the receiver 126 and can include printed circuit board (PCB) traces, vias, cables, connectors, decoupling capacitors, and the like. In examples, the transmission medium 160 includes a matched pair of transmission lines each having a characteristic impedance (Z₀). The receiver of the SERDES 116, and the transmitter of the SERDES 122, are omitted for clarity. In some examples, the SERDES 116 can be disposed in an integrated circuit (IC) 110, and the SERDES 122 can be disposed in an IC 120.
In general, the transmitter 112 generates a serial data signal from a parallel data path (serialization). The serial data signal has a particular data rate (symbol rate). In some examples, data bytes from the parallel data path can be encoded prior to serialization using, for example, and 813/10B encoder or the like. The transmitter 112 drives the serial data signal onto the transmission medium 160 using a digital modulation technique, such as binary non-return-to-zero (NRZ) pulse amplitude modulation (PAM). The transmission medium 160 propagates electrical signal(s) representing symbols of the serial data signal (e.g., logic “1” and logic “0”) towards the receiver 126.
In the example shown, the transmission medium 160 is a differential channel. Data on the differential channel is represented using two electrical signals (“true” and “complement” signals). A logic “0” is represented by driving the true signal to its lower voltage limit and driving the complement signal to its upper voltage limit. A logic “1” is represented by driving the true signal to its upper voltage limit and driving the complement signal to its lower voltage limit. Thus, the logic value of each transmitted symbol is based on the difference between the true and complement signals, and not based on the level of either signal individually. The peak-to-peak difference between the true signal and the complement signal is the voltage swing (also referred to as signal swing or swing).
The transmitter 112 includes a finite impulse response (FIR) filter 114, a pre-driver 115, an output driver 118, and control logic 150. The transmitter 112 is configured to equalize the serial data signal prior to transmission over the transmission medium 160. The FIR 114 can be used to mitigate inter-symbol interference (ISI) caused by the transmission medium 160. The transmission medium 160 degrades the signal quality of the transmitted signal. Channel insertion loss is the frequency-dependent degradation in signal power of the transmitted signal. When signals travel through a transmission line, the high frequency components of the transmitted signal are attenuated more than the low frequency components. In general, channel insertion loss increases as frequency increases. Signal pulse energy in the transmitted signal can be spread from one symbol period to another during propagation on the transmission medium 160. The resulting distortion is known as ISI. In general, ISI becomes worse as the speed of the communication system increases.
The output of the FIR filter 114 is coupled to an input of the pre-driver 115. The output of the FIR filter 114 can include a plurality of signals, including a main-cursor signal, and one or more pre-cursor signals, one or more post-cursor signals, or a plurality of post-cursor and pre-cursor signals. For purposes of clarity by example, the present description assumes the FIR filter 114 outputs one main-cursor signal, one pre-cursor signal, and one post-cursor signal. The pre-driver 115 is configured to couple the output of the FIR filter 114 to the output driver 118. As discussed below, the output driver 118 is segmented and includes a plurality of output circuits coupled in parallel to the transmission medium 160. The pre-driver 115 couples each of the main-cursor, the pre-cursor, and the post-cursor signals to a selected percentage of the output circuits of the output driver 118. The percentages of output circuits driven by the main-cursor, pre-cursor, and post-cursor signals as selected by the pre-driver 115 is controlled by the control logic 150. The control logic 150 also controls aspects of the output driver 118, as discussed further below.
While the SERDES 116 and the SERDES 122 are shown, in other examples, each of the transmitter 112 and/or the receiver 126 can be a stand-alone circuit not being part of a larger transceiver circuit. In some examples, the transmitter 112 and the receiver 126 can be part of one or more integrated circuits (ICs), such as application specific integrated circuits (ASICs) or programmable ICs, such as field programmable gate arrays (FPGAs).
FIG. 2 is a schematic diagram depicting the output driver 118 according to an example. The output driver 118 includes output circuits 208 ₁through 208 _N(where N is an integer greater than one), voltage regulators 210 ₁and 210 ₂, and current compensation circuits 206 ₁through 206 _M(where M is an integer greater than one). The output circuits 208 ₁through 208 _Nare collectively referred to as output circuits 208; the voltage regulators 210 ₁and 210 ₂are collectively referred to as voltage regulators 210; and the current compensation circuits 206 ₁through 206 _Mare collectively referred to as current compensation circuits 206.
The output circuits 208 are coupled in parallel between a differential input 202 and a differential output (Txp, Txn). The differential input 202 includes N differential signals output by the pre-driver 115. Each differential signal includes a true signal, Inp, and a complement signal, Inn. Thus, the differential input 202 includes signals Inp₁through Inp_Nand signals Inn₁through Inn_N.
The output circuits 208 are coupled to common nodes V_refpand V_refn. Each of the output circuits 208 includes transistors M_p1, M_p2, M_n1, and M_n2. Each of the output circuits 208 also includes resistors R_pand R_n. The transistors M_p1and M_n1comprise p-channel field effect transistors (FETs), such as P-type metal-oxide semiconductor FETs (MOSFETs) (also referred to as PMOS transistors). The transistors M_p2and M_n2comprise n-channel FETs, such as N-type MOSFETs (also referred to as NMOS transistors). For purposes of clarity, only the output circuit 208 ₁is shown in detail. However, each of the output circuits 208 ₂through 208 _Nare configured identically with the output circuit 208 ₁.
Sources of the transistors M_p1and M_n1are coupled to the common node V_refp. Drains of the transistors M_p1and M_n1are coupled to drains of the transistors M_p2and M_n2, respectively. Sources of the transistors M_p2and M_n2are coupled to the common node V_refn. Gates of the transistors M_p1and M_p2are coupled together and are coupled to receive a signal Inp of one of the input differential signals. Gates of the transistors M_n1and M_n2are coupled together and are coupled to receive a signal Inn of one of the input differential signals. A first terminal of the resistor R_pis coupled to the drains of the transistors M_p1and M_p2, and a second terminal of the resistor R_pis coupled to the node Txp of the differential output. A first terminal of the resistor R_nis coupled to the drains of the transistors M_n1and M_n2, and a second terminal of the resistor R_nis coupled to the node Txn of the differential output. The transistors M_p1and M_p2form a first inverter (M_p), and the transistors M_n1and M_n2form a second inverter (M_n). A series combination of the pair of inverters (M_p, M_n) and the pair of resistors R_pand R_nis coupled between the differential input 202 and the differential output (Txp, Txn). The source terminals of the inverters are coupled between the nodes V_refpand V_refn.
The voltage regulator 210 ₁includes an operational amplifier A_vrefpand a transistor M_vrefp. The transistor M_vrefpis an n-channel FET, such as an N-type MOSFET. A non-inverting input terminal of the operational amplifier A_vrefpis coupled to a first reference voltage source (V_ref1). An inverting input of the operational amplifier A_vrefpis coupled to the node V_refp. A drain of the transistor M_vrefpis coupled to a supply voltage source (V_sup). A source of the transistor M_vrefpis coupled to the node V_refp. A gate of the transistor M_vrefpis coupled to an output of the operational amplifier A_vrefp.
The voltage regulator 210 ₂includes an operational amplifier A_vrefnand a transistor M_vrefn. The transistor M_vrefnis an n-channel FET, such as an N-type MOSFET. A non-inverting input terminal of the operational amplifier A_vrefnis coupled to a second reference voltage source (V_ref2). An inverting input of the operational amplifier A_vrefnis coupled to the node V_refn. A source of the transistor M_vrefnis coupled to a ground voltage source. A drain of the transistor M_vrefnis coupled to the node V_refn. A gate of the transistor M_vrefnis coupled to an output of the operational amplifier A_vrefn.
The current compensation circuits 206 are coupled in parallel between the nodes V_refpand V_refn. Each of the current compensation circuits 206 includes transistors M₁, M₂, and M₃. The transistor M₁is a p-channel FET, such as a P-type MOSFET. The transistors M₂and M₃are n-channel FETs, such as an N-type MOSFET. For purposes of clarity, only the current compensation circuit 206 ₁is shown in detail. However, each of the current compensation circuits 206 ₂through 206 _Mare configured identically with the current compensation circuit 206 ₁.
A source of the transistor M₁is coupled to the node V_refp. A drain of the transistor M₁is coupled to a drain of the transistor M₂. A source of the transistor M₂is coupled to a drain of the transistor M₃. A source of the transistor M₃is coupled to the node V_refn. A gate of the transistor M₂in each of the current compensation circuits 206 is coupled to a bias voltage source V₁. A gate of the transistor M₃in each of the current compensation circuits 206 is coupled to a bias voltage source V₂. A gate of the transistor M₁is coupled to receive an enable signal of an enable input 204. The enable input 204 includes M enable signals EN₁through EN_Mcoupled to the M current compensation circuits 206, respectively.
The output driver 118 further includes capacitors C_vrefpand C_vrefn. The capacitor C_vrefpis coupled between the node V_refpand electrical ground. The capacitor C_vrefnis coupled between the node V_refnand electrical ground.
The differential output (Txp, Txn) is coupled to a pair of transmission lines 212 _Pand 212 _n(collectively transmission lines 212). The transmission lines 212 drive a load resistance R_L. The transmission lines 212 and the load resistance R_Lare not part of the output driver 118. Rather, the transmission lines 212 are part of the transmission medium 160 and the load resistance R_Lis part of the receiver 126.
In operation, each output circuit 208 includes a pair of inverters driven by complementary input (a differential signal of the differential input 202). Each differential signal of the differential input 202 can be one of a main-cursor signal, a post-cursor signal, or a pre-cursor signal. As discussed above, the pre-driver 115 controls the number of output circuits 208 receiving each of the main-cursor, post-cursor, and pre-cursor signals. For example, the output circuits can receive all main-cursor signals, some main-cursor signals and some pre-cursor signals, some main-cursor signals and some post-cursor signals, or some main-cursor signals, some post-cursor signals, and some pre-cursor signals. Mixing post/pre-cursor signals with the main-cursor signals is used to implement emphasis and de-emphasis equalization in the transmitter 112.
The voltage regulators 210 set the swing of the output driver 118. The differential peak-to-peak swing is V_refp−V_refn. In an example, the voltage regulator 210 ₂can include a switch 214 configured to short the drain of the transistor M_vrefnto electrical ground. This allows the voltage regulator 210 ₂to be disabled in one mode (high-swing mode) and enabled in another mode (low swing mode). Zero or more of the current compensation circuits 206 are selectively enabled using the enable input 204 to draw dummy current from the voltage regulator 210 to improve return loss, as discussed further below. A control signal for the switch 214, and the enable input to the current compensation circuits 206, can be generated by the control logic 150.
With the dual regulators 210 ₁and 210 ₂in the output driver 118, the swing and common-mode can be set independently. For example, the common-mode can be fixed at 0.45 V. Table 1 below illustrates characteristics of the high-swing mode and the low-swing mode for both dual regulators and a single regulator.

TABLE 1

Regulator Mode	Swing	V_refp	V_refn	Common-mode

Dual	0.6 V	0.75 V	0.15 V	0.45 V
Dual	0.9 V	0.9 V	0 V	0.45 V
Single	0.6 V	0.6 V	0 V	0.3 V
Single	0.9 V	0.9 V	0 V	0.45 V

As shown in Table 1, when both regulators 210 ₁and 210 ₂are enabled, the common-mode is the target 0.45 V for the low-swing mode (e.g., 0.6 V). If only the regulator 210 ₁is enabled, the common mode is lower than the target 0.45 V (e.g., 0.3 V) for the low-swing mode. Use of dual regulators allows for a fixed common mode in both low- and high-swing modes. The values in Table 1 are exemplary and the output driver 118 can be configured with other common-mode voltages, other high-swing voltages, and other-low-swing voltages.

In the output driver 118, equalization can be implemented by driving a different number of the output circuits 208 with different main/pre/post cursor signals. With the dual-regulator approach, the swing is changed by adjusting the regulator voltage. Thus, equalization control is independent of the swing control. This allows for high FIR resolution even in low-swing mode.
For a voltage-mode driver, the current drawn by the output circuits 208 can be calculated using the following relationship: Id=(differential swing)/(external differential resistance+internal differential resistance). In an example, each transmission line 212 _pand 212 _nhas a characteristic impedance Z₀of 50 ohms (external differential resistance=100 ohms). Ideally, the output driver 118 provides a matching impedance of 50 ohms for each transmission line 212 (e.g., internal differential resistance=100 ohms). If the desired swing is 0.9 V, then the current drawn by the output circuits 208 is approximately 4.5 mA. The actual current consumption may be higher to account for transient switching crowbar current.
For the above equation, it is noted that the current drawn by the output circuits 208 changes with the output swing. For lower swing, less current is drawn by the output circuits 208 from the voltage regulator 210 ₁. The output impedance of the voltage regulator 210 ₁increases as less current is drawn from the voltage regulator 210 ₁. Notably, the output impedance of the voltage regulator 210 ₁is the output resistance of the transistor M_vrefp(gm) divided by (1+loop gain). When the voltage regulator 210 ₁supplies low current, the operational amplifier A_vrefpprovides less loop gain, thereby increasing the output impedance of the voltage regulator 210 ₁. The output circuits 208 see an effective impedance of the capacitor C_vrefpin parallel with the output impedance of the voltage regulator 210 ₁. For mid- to low-frequencies (e.g., 100 MHz), the impedance of the capacitor C_vrefpis high and thus the output impedance of the voltage regulator 210 ₁is not negligible. Thus, the decreased output impedance of the voltage regulator 210 ₁due to low current draw by the output circuits 208 degrades the return loss of the output driver 118.
The current compensation circuits 206 are selectively enabled to mitigate the increase in return loss by drawing a constant dummy current in parallel with the output circuits 208. Thus, at higher swing settings, less or none of the current compensation circuits 206 can be enabled, as sufficient current is drawn from the voltage regulator 210 ₁. At lower swing settings, more of the current compensation circuits 206 can be enabled, which ensures that sufficient current is drawn from the voltage regulator 210 ₁to maintain loop gain and low output impedance.
FIGS. 3A-3B depict a schematic diagram of the output driver 118 according to another example. FIG. 3A shows a portion 118A of the output driver 118, and FIG. 3B shows a portion 118B of the output driver 118. Elements in FIGS. 3A and 3B that are the same or similar to those of FIG. 2 are designated with identical reference numerals and are described above. The output driver 118 includes output circuits 308 ₁through 308 _N(where N is an integer greater than one), the voltage regulators 210 ₁and 210 ₂, replica circuits 320 ₁and 320 ₂, and a control circuit 350 comprising operational amplifiers A_repl1, A_repl2, and resistors R_ref1through R_ref11. The output circuits 308 ₁through 308 _Nare collectively referred to as output circuits 308, and the replica circuits 320 ₁and 320 ₂are collectively referred to as replica circuits 320. In some examples, the output driver shown in FIGS. 3A and 3B can also include the current compensation circuits 206 described above. For purposes of clarity, the current compensation circuits 206 are omitted from FIGS. 3A and 3B.
As shown in the portion 118A of the output driver 118 in FIG. 3A, the output circuits 308 are coupled in parallel between the differential input 202 and the differential output (Txp, Txn). The output circuits 308 are coupled to the common nodes V_refpand V_refn. Each of the output circuits 308 includes transistors M_pdrv1, M_pdrv2, M_ndrv1, M_ndrv2, M_res1, and M_res2. Each of the output circuits 208 also includes resistors R_pdrvand R_ndrv, and enable circuit U_pformed by NAND gate U_p1and U_p2, and an enable circuit Un formed by U_n1and U_n2. The transistors M_pdrv1and M_ndrv1comprise p-channel FETs, such as P-type MOSFETs. The transistors M_pdrv2and M_ndrv2comprise n-channel FETs, such as N-type MOSFETs. Sources of the transistors M_pdrv1and M_ndrv1are coupled to a drain of the transistor M_res1. Drains of the transistors M_pdrv1and M_ndrv1are coupled to drains of the transistors M_pdrv2and M_ndrv2, respectively. Sources of the transistors M_pdrv2and M_ndrv2are coupled to a drain of the transistor M_res2.
Gates of the transistors M_pdrv1and M_pdrv2are coupled to outputs of the NAND gate U_p1and the NOR gate U_p2, respectively. In another example, the NAND gate U_p1and the NOR gate U_p2are replaced by a single inverter having an output coupled to the gates of the transistors M_pdrv1and M_pdrv2. First input terminals of the NAND gate U_p1and the NOR gate U_p2are coupled together, and are coupled to receive one end of a differential input signal (Inp). Second inputs of the NAND gate U_p1and the NOR gate U_p2are coupled to a true enable signal en and a complement enable signal enb. Gates of the transistors M_ndrv1and M_ndrv2are coupled to outputs of the NAND gate U_n1and the NOR gate U_n2, respectively. First input terminals of the NAND gate U_n1and the NOR gate U_n2are coupled together, and are coupled to receive the other end of the differential input signal (Inn). Second inputs of the NAND gate U_n1and the NOR gate U_n2are coupled to the true enable signal en and the complement enable signal enb. The true enable signal en and the complement enable signal enb are signals of a true enable input and a complement enable input, respectively. The true enable input includes N true enable signals en through en_Nrespectively coupled to the N output circuits 308, and the complement enable input includes N complement enable signals enb₁through enb_Nrespectively coupled to the N output circuits 308.
A source of the transistor M_res1is coupled to the common node V_refp. A source of the transistor M_res2is coupled to the common node V_refn. A gate of the transistor M_res1is coupled to an output of the operational amplifier A_repl1(designated node V_g1). A gate of the transistor M_res2is coupled to an output of the operational amplifier A_repl2(designated node V_g2).
One terminal of the resistor R_pdrvis coupled to the drains of the transistors M_pdrv1and M_pdrv2, and another terminal of the resistor R_pdrvis coupled to the node Txp of the differential output. One terminal of the resistor R_ndrvis coupled to the drains of the transistors M_ndrv1and M_ndrv2, and another terminal of the resistor R_ndrvis coupled to the node Txn of the differential output. The transistors M_pdrv1and M_pdrv2form a first inverter (M_pdrv), and the transistors M_ndrv1and M_ndrv2form a second inverter (M_ndrv). A series combination of the enable circuits (U_p, U_n), the pair of inverters (M_pdrv, M_ndrv) and the pair of resistors R_pdrvand R_ndrvis coupled between the differential input 202 and the differential output (Txp, Txn). The source terminals of the inverters (M_pdrv, M_ndrv) are coupled between the nodes V_refpand V_refn.
As shown in the portion 118B of the output driver 118, the replica output circuit 320 ₁includes transistors M_resrepl1and M_repl1and a resistor R_repl1. The transistors M_resrepl1and M_repl1are each a p-channel FET, such as a P-type MOSFET. A source of the transistor M_resrepl1is coupled to the common node V_refp. A drain of the transistor M_resrepl1is coupled to a source of the transistor M_repl1. A drain of the transistor M_repl1is coupled to one terminal of the resistor R_repl1. Another terminal of the resistor R_repl1is coupled to one terminal of a resistor R_repl _{_} _loadat a node V_p. A gate of the transistor M_resrepl1is coupled to the output of the operational amplifier A_repl1. A gate of the transistor M_rep1is coupled to a ground source.
The replica output circuit 320 ₂includes transistors M_resrepl2and M_repl2and a resistor R_repl2. The transistors M_resrepl2and M_repl2are each an n-channel FET, such as a N-type MOSFET. A source of the transistor M_resrepl2is coupled to the common node V_refn. A drain of the transistor M_resrepl2is coupled to a source of the transistor M_repl2. A drain of the transistor M_repl2is coupled to one terminal of the resistor R_repl2. Another terminal of the resistor R_repl2is coupled to a second terminal of a resistor R_repl _{_} _loadat a node V_n. A gate of the transistor M_resrepl2is coupled to the output of the operational amplifier A_repl2. A gate of the transistor M_rep2is coupled to a supply source (Vsup). The replica output circuit 320 ₂also includes a startup circuit S1. The startup circuit S1 comprises a switch coupled between the output of the operational amplifier A_repl2and the supply source Vsup.
An inverting input of the operational amplifier A_repl1is coupled between the resistor R_repl1and the resistor R_repl _{_} _load. A non-inverting input of the operational amplifier A_repl1is coupled to a switched resistor network 322 ₁. The switched resistor network 322 ₁comprises the resistors R_ref1through R_ref5and a switch Sw1. The resistors R_ref1through R_ref5are coupled in series between the node V_refpand the resistor R_ref6. The switched resistor network 322 ₁includes a plurality of taps (e.g., 5 taps in the example). The switch Sw1 is controllable to couple the non-inverting input of the operational amplifier A_repl1to one of the taps.
An inverting input of the operational amplifier A_repl2is coupled between the resistor R_repl2and the resistor R_repl _{_} _load. A non-inverting input of the operational amplifier A_repl2is coupled to a switched resistor network 322 ₂. The switched resistor network 322 ₂comprises the resistors R_ref7through R_ref11and a switch Sw2. The resistors R_ref7through R_ref11are coupled in series between the node V_refnand the resistor R_ref6. The switched resistor network 322 ₂includes a plurality of taps (e.g., 5 taps in the example). The switch Sw2 is controllable to couple the non-inverting input of the operational amplifier A_repl2to one of the taps.
One example technique for impedance control is to provide a pair of programmable resistors stacked in series with all output slices of the driver array. The intent is to adjust the programmable resistors to compensate for variations in the output slices. However, as the programmable resistors are shared by all of the output slices, the differential impedance will deviate from the desired 100 ohms when some output slices are driven in the opposite direction. Another example technique for impedance control is to configure the output slices of the driver array to be selectively enabled/disabled. However, such a technique alone does not compensate for the difference in process variations of PMOS and NMOS transistors, e.g., when PMOS is at fast corner while NMOS is at slow corner and vice versa.
In an example, the output driver 118 provides for impedance control that addresses these problems. Turning on/off output circuits 308 is used to only compensate for on-chip resistor variations. To compensate for NMOS/PMOS variations, each output circuit 308 includes a pair of stacked programmable resistors (described below). The impedance of the stacked programmable resistors is controlled by two impedance control loops.
In operation, the output circuits 308 can be selectively enabled on or off through the enable input. The enable input can be provided by the control logic 150. If enabled, an output circuit 308 contributes to the differential output (Txp, Txn). If disabled, the output circuit 308 does not contribute to the differential output (Txp, Txn) (high impedance state). Turning output circuits 308 on/off provides for coarse impedance control to compensate for variation in the on-chip resistors R_pdrvand R_ndrv. The transistors M_res1and M_res2are driven to operate in the triode region to provide programmable resistors controllable through V_g1and V_g2, respectively. The transistors M_res1and M_res2are controlled to compensate for variation in the transistors M_pdrv1, M_pdrv2, M_ndrv1, and M_ndrv2. The resistance provided by the transistors M_res1and M_res2is controlled by adjusting their respective gate-to-source voltages using feedback control loops. A feedback control loop that controls the transistor M_res1comprises the replica 320 ₁and the operational amplifier A_repl1. A feedback control loop that controls the transistor M_res2comprises the replica 320 ₂and the operational amplifier A_repl2.
The operational amplifier A_repl1adjusts the gate-to-source voltage of the transistor M_resrepl1such that its impedance is set to a desired value. Notably, the transistor M_resrepl1is fabricated to be a replica of the transistor M_res1. The transistor M_repl1is fabricated to be a replica of a p-channel FET in the output circuits 308 (e.g., the characteristics for each of M_pdrv1, M_pdrv2, and M_repl1are the same or substantially similar). The resistor R_repl1is fabricated to be a replica of an on-chip resistor in the output circuits 308 (e.g., the characteristics for each of R_pdrv, R_ndrv, and R_repl1are the same or substantially similar). Each output circuit 308 (if enabled) includes an internal impedance in series with one of the transmission lines 212 formed by a series combination of M_res1, one p-channel FET (i.e., M_pdrv1or M_ndrv1), and one resistor (R_pdrvor R_ndrv). The replica 320 ₁replicates this internal impedance. The desired voltage at node V_pis selected at the non-inverting input of the operational amplifier A_repl1and the operational amplifier A_repl1drives the node V_pto that voltage by controlling the impedance of the transistor M_resrepl1. The operational amplifier A_repl1provides the same control voltage to the gate of the transistor M_res1in each output circuit 308.
The operational amplifier A_repl2adjusts the gate-to-source voltage of the transistor M_resrepl2such that its impedance is set to a desired value. The transistor M_resrepl2is fabricated to be a replica of the transistor M_res2. The transistor M_repl2is fabricated to be a replica of a n-channel FET in the output circuits 308 (e.g., the characteristics for each of M_ndrv1, M_ndrv2, and M_repl2are the same or substantially similar). The resistor R_repl2is fabricated to be a replica of an on-chip resistor in the output circuits 308 (e.g., the characteristics for each of R_pdrv, R_ndrv, and R_repl2are the same or substantially similar). Each output circuit 308 (if enabled) includes an internal impedance in series with one of the transmission lines 212 formed by a series combination of M_res2, one n-channel FET (i.e., M_pdrv1or M_ndrv1), and one resistor (R_pdrvor R_ndrv). The replica 320 ₂replicates this internal impedance. The desired voltage at node V_nis selected at the non-inverting input of the operational amplifier A_repl2and the operational amplifier A_repl2drives the node V_nto that voltage by controlling the impedance of the transistor M_resrepl2. The operational amplifier A_repl2provides the same control voltage to the gate of the transistor M_res2in each output circuit 308.
By including transistors M_res1and M_res2in each output circuit 308, the differential output impedance of the output driver 118 can be maintained to match the transmission medium 160 even when the main and pre/post cursor signals switch in the opposite direction. Further, by provide two feedback control loops for separately controlling the resistance provided by the transistors M_res1and M_res2, the output driver 118 can compensate for different NMOS and PMOS process variations.
As shown in FIG. 3B, the two feedback control loops are coupled together through the resistor R_repl _{_} _loadso that the current through the two loops can be re-used. To ensure both loops start up properly, the startup circuit S1 can be incorporated into the replica circuit 320 ₂. The startup circuit S1 can disable one loop initially so that the other loop starts up properly. Alternatively, rather than the startup circuit S1, a common-mode buffer can be used to decouple the two feedback control loops by driving the midpoint of the replica load to a common-mode voltage.
To illustrate the impedance control in more detail, consider an example where the output driver 118 includes N=75 to 85 output circuits 308. Typically, an on-chip resistor can change by ±10% due to process variations. As discussed above, variation in the on-chip resistors R_pdrvand R_ndrvis compensated for by adjusting the number of enabled output circuits 308 (e.g., between 75 and 85 as shown in the example of Table 2).

TABLE 2

		Each slice with	+10% resistor	Each slice with	−10% resistor
80 Slices	Each Slice	resistor + 10%	with 85 slices	resistor − 10%	with 75 slices

Transistor	20 ohms	1600 ohms	1600 ohms	18.8 ohms	1600 ohms	21.3 ohms
resistance
On-chip	30 ohms	2400 ohms	2640 ohms	31.1 ohms	2160 ohms	28.8 ohms
resistance
Total	50 ohms	4000 ohms	4240 ohms	49.9 ohms	3760 ohms	50.2 ohms
resistance

As shown in Table 2, the total output impedance can be maintained at approximately 50 ohms for a given differential output (assuming a 50-ohm characteristic impedance of the transmission line) despite a ±10% variation in on-chip resistance by enabling more or less of the output circuits 308. To calibrate the number of output circuits 308 to be turned on/off, the resistance of the on-chip resistors R_pdrvand R_ndrvcan be sensed with a constant current source (not shown). The control logic 150 can read the output of the sensing operation and then enable/disable the output circuits 308 based on values in a lookup table.
One difference between the replica output circuits 320 and the output circuits 308 is that the load of the replica circuits 320, R_repl _{_} _load, is implemented with an on-chip resistor, while the actual load for the transmitter, R_load, is a constant termination at the receiver. To avoid using an external resistor or trimming the on-chip resistor R_repl _{_} _load, the reference voltages used in the feedback control loops can be adjusted to compensate for variation in the on-chip replica resistor R_repl _{_} _load. This is achieved by selecting a desired voltage at the non-inverting inputs to the operational amplifiers A_repl1and A_repl2. Note that although each switched resistor network 322 is shown has having five taps for providing five reference voltages, the switched resistor networks 322 can have more or less than five taps.
FIG. 4 is a flow diagram depicting a method 400 of controlling a driver circuit in a transmitter according to an example. The method 400 can be performed to control the output driver 118 of the transmitter 112. The method 400 begins at step 402, where the pre-driver 115 receives the outputs of an equalizer in the transmitter 112 (e.g., FIR filter 114). At step 404, the pre-driver 115 couples each equalizer output to at least one of a plurality of output circuits in the output driver 118 (e.g., output circuits 208 or 308). Step 404 implements equalizer control independently from swing control and impedance control. The main-, pre-, and post-cursor signals can be coupled to any number of output circuits in the output driver 118 to achieve the desired emphasis or de-emphasis.
At step 406, the control logic 150 enables first and second voltage regulators 210 coupled to the output circuits in the output driver 118 to establish a desired swing. The voltage output from the dual voltage regulators 210 can be set to generate a desired peak-to-peak voltage swing at the output of the output driver 118. In some cases, at step 410, the control logic 150 can optionally enable one or more current compensation circuits 206 to equalize current drawn from the current-supplying voltage regular (e.g., the voltage regulator 210 ₁). Step 406 implements output swing control independent of equalizer control and impedance control.
At step 408, the impedance of the output driver is controlled. For example, at step 412, the control logic 150 disables one or more of the output circuits in the output driver 118 to compensate for on-chip resistor variation. This provides for a coarse impedance control. At step 414, feedback control loops in the output driver adjust the gate-to-source voltage of stacked transistors M_res1and M_res2in each output circuit based on feedback from replica circuits 320 to adjust for NMOS/PMOS transistor variation and provide for fine impedance control. As discussed above, the feedback control loops can independently adjust the impedance of the stacked transistors M_res1and M_res2to independently compensate for NMOS and PMOS variations.
While the foregoing is directed to specific examples, other and further examples may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A driver circuit, comprising:

a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node, each of the plurality of output circuits comprising:

a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output;

first source terminals of the pair of inverters coupled to the first common node; and

second source terminals of the pair of inverters coupled to the second common node;

a first voltage regulator having an output coupled to the first common node of the plurality of output circuits;

a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and

a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

2. The driver circuit of claim 1, wherein the current compensation circuit comprises:

a plurality of circuits having an enable input, a first bias input, and a second bias input, each of the plurality of circuits having a first transistor, a second transistor, and a third transistor serially connected to provide a current path between the outputs of the first and second voltage regulators.

3. The driver circuit of claim 2, wherein, for each of the plurality of circuits of the current compensation circuit, a gate of the first transistor is coupled to receive a signal of the enable input, a gate of the second transistor is coupled to receive a signal of the first bias input, and a gate of the third transistor is coupled to receive a signal of the second bias input.

4. The driver circuit of claim 1, wherein the first voltage regulator comprises:

a first transistor coupled between a supply voltage source and the first common node of the plurality of outputs circuits; and

a first operational amplifier having a first input coupled to a first reference voltage source, a second input coupled to the first common node of the plurality of output circuits, and an output coupled to a gate of the first transistor.

5. The driver circuit of claim 4, wherein the second voltage regulator comprises:

a second transistor coupled between a ground source and the second common node of the plurality of outputs circuits; and

a second operational amplifier having a first input coupled to a second reference voltage source, a second input coupled to the second common node of the plurality of output circuits, and an output coupled to a gate of the second transistor.

6. The driver circuit of claim 1, further comprising:

a first capacitor coupled between the first common node of the plurality of output circuits and a ground source; and

a second capacitor coupled between the second common node of the plurality of output circuits and the ground source.

7. The driver circuit of claim 1, wherein the differential output of the plurality of output circuits is coupled to a pair of transmission lines.

8. A driver circuit, comprising:

a series combination of a pair of enable circuits, a pair of inverters, and a pair of resistors, coupled between the differential input and the differential output;

a first transistor coupled between the first common node and first source terminals of the pair of inverters; and

a second transistor coupled between the second common node and second source terminals of the pair of inverters;

first and second replica output circuits coupled in series between the first and second common nodes; and

a control circuit coupled to each of: respective gates of the first and second transistors in each of the plurality of output circuits; and the first and second replica output circuits.

9. The driver circuit of claim 8, further comprising:

a replica load resistor coupled in series between the first and second replica output circuits.

10. The driver circuit of claim 9, wherein:

the first replica output circuit comprises a first replica transistor, a second replica transistor, and a first replica resistor serially connected to provide a current path between the first common node and the replica load resistor; and

the second replica output circuit comprises a third replica transistor, a fourth replica transistor, and a second replica resistor serially connected to provide a current path between the replica load resistor and the second common node.

11. The driver circuit of claim 10, wherein the control circuit comprises:

a first operational amplifier having a first terminal coupled to a first switched resistor network, a second terminal coupled to a node between the first replica resistor and the replica load resistor, and an output terminal coupled to each of: a gate of the first replica transistor; and gate of the first transistor in each of the plurality of output circuits; and

a second operational amplifier having a first terminal coupled to a second switched resistor network, a second terminal coupled to a node between the second replica resistor and the replica load resistor, and an output terminal coupled to each of: a gate of the fourth replica transistor; and gate of the second transistor in each of the plurality of output circuits.

12. The driver circuit of claim 11, wherein the first switched resistor network is coupled between the first common node and a reference resistor, and wherein the second switched resistor network is coupled between the reference resistor and the second common node.

13. The driver circuit of claim 12, wherein the first switched resistor network comprises a first plurality of taps and a first switch coupled between the first plurality of taps and the first terminal of the first operational amplifier, and wherein the second switched resistor network comprises a second plurality of taps and a second switch coupled between the second plurality of taps and the first terminal of the second operational amplifier.

14. The driver circuit of claim 11, wherein the second replica output circuit further comprises:

a startup circuit coupled to the output terminal of the second operational amplifier.

15. The driver circuit of claim 8, wherein the pair of enable circuits in each of the plurality of output circuits each comprises a NAND gate and a NOR gate.

16. The driver circuit of claim 8, further comprising:

a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; and

a second voltage regulator having an output coupled to the second common node of the plurality of circuits.

17. The driver circuit of claim 16, further comprising:

18. The driver circuit of claim 8, wherein the differential output of the plurality of output circuits is coupled to a pair of transmission lines.

19. A method of controlling a driver circuit in a transmitter, comprising:

receiving a plurality of outputs of an equalizer in the transmitter;

coupling each of the plurality of outputs of the equalizer to at least one of a plurality of output circuits of the driver circuit;

enabling first and second voltage regulators coupled to the plurality of output circuits; and

enabling at least one of a plurality of current compensation circuits coupled between the first and second voltage regulators.

20. The method of claim 19, wherein the plurality of output circuits is coupled in parallel between a differential input and a differential output and includes a first common node and a second common node, wherein each of the plurality of output circuits comprises a series combination of a pair of enable circuits, a pair of inverters, and a pair of resistors, coupled between the differential input and the differential output; a first transistor coupled between the first common node and first source terminals of the pair of inverters; and a second transistor coupled between the second common node and second source terminals of the pair of inverters, and wherein the method further comprises:

disabling at least one of the plurality of output circuits; and

adjusting a gate-to-source voltage of each of the first transistor and the second transistor in each of the plurality of circuits based on feedback from first and second replica output circuits.