US20180040819A1 - Subtractive patterning of back end of line compatible mixed ionic electronic conductor materials - Google Patents
Subtractive patterning of back end of line compatible mixed ionic electronic conductor materials Download PDFInfo
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- 239000000463 material Substances 0.000 title claims abstract description 134
- 238000000059 patterning Methods 0.000 title claims description 25
- 239000011533 mixed conductor Substances 0.000 title description 85
- 229910052751 metal Inorganic materials 0.000 claims abstract description 87
- 239000002184 metal Substances 0.000 claims abstract description 86
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 239000003989 dielectric material Substances 0.000 claims description 55
- 239000004065 semiconductor Substances 0.000 claims description 30
- 230000003667 anti-reflective effect Effects 0.000 claims description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 229910052799 carbon Inorganic materials 0.000 claims description 10
- 229910052709 silver Inorganic materials 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 229910052718 tin Inorganic materials 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052741 iridium Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 229910004166 TaN Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 229910052744 lithium Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 229910052711 selenium Inorganic materials 0.000 claims description 3
- 229910052717 sulfur Inorganic materials 0.000 claims description 3
- 229910052714 tellurium Inorganic materials 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims 2
- 230000015654 memory Effects 0.000 abstract description 25
- 238000000151 deposition Methods 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 description 21
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000004528 spin coating Methods 0.000 description 6
- -1 for example Substances 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910000681 Silicon-tin Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052800 carbon group element Inorganic materials 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 229910052798 chalcogen Inorganic materials 0.000 description 1
- 150000001787 chalcogens Chemical class 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000001995 intermetallic alloy Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002734 metacrylic acid derivatives Chemical class 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000412 polyarylene Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
-
- H01L45/1675—
-
- H01L27/2463—
-
- H01L45/1266—
-
- H01L45/141—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8416—Electrodes adapted for supplying ionic species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8822—Sulfides, e.g. CuS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8825—Selenides, e.g. GeSe
Definitions
- the present application relates to integrated circuit fabrication, and more particularly, to the fabrication of mixed ionic electronic conductor-based memory cell access devices using a subtractive etch process.
- MIEC Mixed ionic electronic conductors
- the MIEC-based memory cell access devices are typically formed using an additive damascene process in which a dielectric material layer is patterned to include vias therein.
- the MIEC material is subsequently deposited within the vias and thereafter any MIEC material that is located outside the vias is removed utilizing a planarization process, e.g., chemical mechanical planarization (CMP).
- CMP chemical mechanical planarization
- FIG. 1 shows a MIEC-based memory cell access device 100 formed by the additive damascene process.
- the MIEC-based memory cell access device 100 includes a MIEC material portion 120 sandwiched between a bottom electrode 110 and a top electrode 130 .
- the MIEC material portion 120 is formed by filling a via formed in a dielectric material layer 140 .
- the via etching process typically forms a via having a tapered profile; the MIEC material portion 120 formed within the via is also tapered to have a smaller cross-section area at the bottom of the MIEC material portion 120 than at the top of the MIEC material portion 120 .
- the contact area between the MIEC material portion 120 and the bottom electrode 110 is smaller than that between the MIEC material portion 120 and the top electrode 130 .
- the different contact areas lead to asymmetric current vs. voltage (I-V) characteristics during bi-directional electrical operation of the access device. This device asymmetry also results in an increase in the low leakage current of the access device.
- I-V current vs. voltage
- the CMP process that is employed to remove the excess MIEC material from the top of the dielectric material layer 140 forms surface defects on the MIEC material portion 120 , which adversely affect the device performance. Therefore a need exists to overcome the problems with the prior art as discussed above.
- the present application provides methods of forming MIEC-based memory cell access devices using a subtractive etch process.
- the method includes first forming a MIEC material layer on a bottom electrode and a dielectric material layer laterally surrounding the bottom electrode. A metal layer is subsequently formed on the MIEC material layer. After forming a metallic hard mask portion on the metal layer, portions of the metal layer and portions of the MIEC material layer that are not covered by the metallic hard mask portion are removed.
- the method includes first forming alternating MIEC material layers and metal layers on a bottom electrode and a dielectric material layer laterally surrounding the bottom electrode.
- a metallic hard mask portion is subsequently formed on a topmost metal layer in the alternating MIEC material layers and metal layers. Portions of the alternating MIEC material layers and metal layers that are not covered by the metallic hard mask portion are then removed.
- FIG. 1 is a cross-sectional view of a MIEC-based access device formed using a prior art additive damascene process.
- FIG. 2 is a cross-section view of a first exemplary semiconductor structure according to a first embodiment of the present application after forming a first material stack over a substrate; the first material stack includes, from bottom to top, a first dielectric material layer, a second dielectric material layer having a bottom electrode embedded there in, a MIEC material layer, a metal layer, a metallic hard mask layer, a dielectric hard mask layer, an organic planarization layer (OPL), an antireflective hard mask layer and a photoresist portion.
- a first dielectric material layer includes, from bottom to top, a first dielectric material layer, a second dielectric material layer having a bottom electrode embedded there in, a MIEC material layer, a metal layer, a metallic hard mask layer, a dielectric hard mask layer, an organic planarization layer (OPL), an antireflective hard mask layer and a photoresist portion.
- OPL organic planarization layer
- FIG. 3 is a cross-sectional view of the first exemplary semiconductor structure of FIG. 2 after forming an antireflective hard mask portion and an OPL portion by patterning the antireflective hard mask layer and the OPL using the photoresist portion as an etch mask.
- FIG. 4 is a cross-sectional view of the first exemplary semiconductor structure of FIG. 3 after forming a dielectric hard mask portion and a metallic hard mask portion by patterning the dielectric hard mask layer and the metallic hard mask layer using the OPL portion as an etch mask.
- FIG. 5 is a cross-sectional view of the first exemplary semiconductor structure of FIG. 4 after removing the dielectric hard mask portion.
- FIG. 6 is a cross-sectional view of the first exemplary semiconductor structure of FIG. 5 after forming a metal portion and a MIEC material portion by simultaneously patterning the metal layer and the MIEC material layer using the metallic hard mask portion as an etch mask.
- FIG. 7 is a cross-sectional view of the first exemplary semiconductor structure of FIG. 6 after forming an interlevel dielectric (ILD) layer to laterally surround the MIEC material portion, the metal portion and the metallic hard mask portion according to one embodiment of the present application.
- ILD interlevel dielectric
- FIG. 8 is a cross-sectional view of the first exemplary semiconductor structure of FIG. 6 after forming an ILD layer to laterally surround the MIEC material portion and the metal portion according to another embodiment of the present application.
- FIG. 9 is a cross-section view of a second exemplary semiconductor structure according to a second embodiment of the present application after forming a second material stack over a substrate; the second material stack includes, from bottom to top, a first dielectric material layer, a second dielectric material layer having a bottom electrode embedded there in, a stack of alternating MIEC material layers and metal layers, a metallic hard mask layer, a dielectric hard mask layer, an OPL, an antireflective hard mask layer, and a photoresist portion.
- FIG. 10 is a cross-sectional view of the second exemplary semiconductor structure of FIG. 9 after forming a metallic hard mask portion by sequentially patterning the ARC layer, the OPL, the dielectric hard mask layer and the metallic hard mask layer and removing remaining portions of the antireflective hard mask layer, the OPL and the dielectric hard mask layer.
- FIG. 11 is a cross-sectional view of the second exemplary semiconductor structure of FIG. 10 after simultaneously patterning the stack of alternating MIEC material layers and metal layers and forming the ILD layer.
- a first exemplary semiconductor structure includes a first material stack formed over a substrate 10 .
- the first material stack includes, from bottom to top, a first dielectric material layer 20 , a second dielectric material layer 30 having a bottom electrode 40 embedded therein, a MIEC material layer 50 , a metal layer 60 , a metallic hard mask layer 70 , a dielectric hard mask layer 80 , an organic planarization layer (OPL) 92 , an antireflective hard mask layer 94 and a photoresist portion 96 P.
- OPL organic planarization layer
- the substrate 10 may be composed of a semiconductor material.
- Exemplary semiconductor materials that may be used as substrate 10 include, but are not limited to, Si, SiGe, SiGeC, SiC, Ge alloys GaAs, InAs, InP, carbon-containing materials such as, for example, carbon nanotubes and graphene, and other III/V or II/VI compound semiconductors.
- the semiconductor material which can be employed as substrate 10 may be present in a bulk semiconductor substrate.
- the semiconductor material which can be employed as substrate 10 may be a topmost layer of a multilayered semiconductor material stack.
- the semiconductor material that can be employed as substrate 10 can be a topmost layer of a semiconductor-on-insulator substrate.
- the semiconductor material that can be employed as substrate 10 can be single crystalline (i.e., a material in which the crystal lattice of the entire sample is continuous and unbroken to the edges of the sample, with no grain boundaries).
- the semiconductor material that can be employed as substrate 10 can be polycrystalline (i.e., a material that is composed of many crystallites of varying size and orientation; the variation in direction can be random (called random texture) or directed, possibly due to growth and processing conditions).
- the semiconductor material that can be employed as substrate 10 can be amorphous (i.e., a non-crystalline material that lacks the long-range order characteristic of a crystal).
- the semiconductor material that can be employed as substrate 10 is a single crystalline semiconductor material, such as, for example, single crystalline silicon.
- the substrate 10 may be doped, undoped or contain doped and undoped regions therein. For clarity, the doped regions are not specifically shown in substrate 10 . Each doped region within the substrate 10 may have the same, or they may have different conductivities and/or doping concentrations.
- the substrate 10 can be processed utilizing techniques known in the art to include one or more semiconductor devices such as, for example, transistors, capacitors, diodes, resistors, or other components that are part of integrated circuits. For clarity, the semiconductor devices are not shown in the drawings of the present application.
- the first dielectric material layer 20 is formed on the substrate 10 .
- the first dielectric material layer 20 may include a dielectric material such as, for example, silicon dioxide, silicon nitride, or silicon oxyntride.
- the first dielectric material layer 20 may also include a low-k dielectric material having a dielectric constant that is about 4.0 or less.
- Exemplary low-k dielectric materials include, but are not limited to, organosilicates, silsequioxanes, undoped silicate glass (USG), fluorosilicate glass (FSG), tetraethylorthosilicate (TEOS), SiCOH or borophosphosilicate glass (BPSG).
- the first dielectric material layer 20 may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or spin coating.
- the thickness of the first dielectric material layer 20 may be from 100 nm to 1,000 nm, although lesser and greater thicknesses can also be employed.
- the first dielectric material layer 20 may include interconnect structures (not shown) to provide electric connections among electric components formed in the substrate 10 .
- the first dielectric material layer 20 may also include memory cells (not shown) embedded therein. For clarity, the interconnect structures and memory cells are not shown in the drawings of the present application.
- the second dielectric material layer 30 is formed on the first dielectric material layer 20 .
- the second dielectric material layer 30 may include a dielectric material that is the same as, or different from, the dielectric material of the first dielectric material layer 20 .
- the second dielectric material layer 30 is composed of a dielectric material that can be selectively etched with respect to the first dielectric material layer 20 .
- the first dielectric material layer 20 is composed of a dielectric oxide
- the second dielectric material layer 30 may be composed of silicon nitride.
- the second dielectric material layer 30 may be formed by CVD, PECVD or spin coating.
- the thickness of the second dielectric material layer 30 may be from 10 nm to 1 , 000 nm, although lesser and greater thicknesses can also be employed.
- the bottom electrode 40 is formed within the second dielectric material layer 30 .
- the bottom electrode 40 is laterally surrounded by the second dielectric material layer 30 .
- the bottom electrode 40 can be a top electrode of a memory cell.
- the bottom electrode 40 may include any suitable conductive material such as, for example, TiN, TaN, W, Al, Cu, Ag, Ir, Pt, Au, Co or Ni.
- the bottom electrode 40 can be formed by first patterning the second dielectric material layer 30 , utilizing lithography and etching processes known in the art, to provide an opening (not shown) that extends through the second dielectric material layer 30 .
- the lithographic step may include applying a photoresist layer (not shown) to the second dielectric material layer 30 , exposing the photoresist layer to a pattern of radiation and developing the pattern into the exposed photoresist layer unitizing a resist developer.
- the etching step performed to transfer the pattern from the patterned photoresist layer into the second dielectric material layer 30 can include an anisotropic etch which can be a dry etch such as, for example, reactive ion etch (RIE) or a wet etch.
- RIE reactive ion etch
- the patterned photoresist layer can be removed from the structure utilizing a resist stripping process such as, for example, ashing.
- the opening is then filled with the conductive material by a conventional deposition method such as, for example, CVD, physical vapor deposition (PVD) or plating.
- a conventional deposition method such as, for example, CVD, physical vapor deposition (PVD) or plating.
- the excess conductive material is subsequently removed from the top surface of the second dielectric material layer 30 , for example, by CMP.
- the bottom electrode 40 thus formed has a top surface coplanar with the top surface of the second dielectric material layer 30 .
- the MIEC material layer 50 is formed on the second dielectric material layer 30 and the bottom electrode 40 as a blanket layer (i.e., as an unpatterned contiguous layer).
- the MIEC material layer 50 may include a material that is capable of conducting both ions and electronic charge carriers (electrons and/or holes).
- the MIEC material layer 50 may be composed of a material represented by a formula of M a X b Y c , wherein M is a metallic element including but not limited to Cu, Ag, Li, or Zn, X is a Group XIV element including, but not limited to, Ge, Si, Sn or C or a Group VIB transition metal including but not limited to Cr, Mo or W, and Y is a Group XVI or chalcogen element including but not limited to S, Se, Te or O, and wherein a is from 20 to 70 atomic %, b is from 4 to 30 atomic %, and c is from 30 to 60 atomic %.
- M is a metallic element including but not limited to Cu, Ag, Li, or Zn
- X is a Group XIV element including, but not limited to, Ge, Si, Sn or C or a Group VIB transition metal including but not limited to Cr, Mo or W
- Y is a Group XVI or chalcogen element including but
- the MIEC material layer 50 includes Cu 8 GeS 6 or Cu 8 GeSe 6 . In some embodiments, combinations of the various elements mentioned above, such as Ag 4.7 Cu 3.3 GeS 6 , could also be used as the MIEC layer 50 .
- the MIEC material layer 50 can be deposited, for example, by PVD, CVD or atomic layer deposition (ALD).
- the deposition temperature of the MIEC material is typically below 400° C., thus is compatible with low-temperature back-end-of-line (BEOL) semiconductor processing conditions.
- the thickness of the MIEC material layer 50 that is formed can be from 10 nm to 200 nm, although lesser and greater thicknesses can also be employed.
- the metal layer 60 is formed on the MIEC material layer 50 as a blanket layer.
- the metal layer 60 may include a conductive material that can withstand the etch chemistry employed to etch the overlying metallic hard mask layer 70 , thus acting as a barrier to prevent damage to the MIEC material layer 50 during the etching of the metallic hard mask layer 70 subsequently performed.
- the metal layer 60 may include Ru, Cu, Ag, Au, Ni, Fe, Pt, Pd, W, Ir or Co.
- the metal layer 60 may be formed utilizing a conventional deposition method such as, for example, CVD, PECVD or ALD.
- the metallic hard mask layer 70 is formed on the metal layer 60 as a blanket layer.
- the metallic hard mask layer 70 may include a metal nitride, a metal carbide, an elemental metal, an intermetallic alloy, or a combination or a stack thereof.
- the metallic hard mask layer 70 includes a metal nitride such as TiN, TaN, WN or an alloy thereof.
- the metallic hard mask layer 70 may be deposited, for example, by CVD or PVD.
- the thickness of the metallic hard mask layer 70 can be from 10 to 200 nm, although lesser and greater thickness can also be employed.
- the dielectric hard mask layer 80 is formed on the metallic hard mask layer 70 as a blanket layer.
- the dielectric hard mask layer 80 may include a dielectric oxide or dielectric nitride.
- the dielectric hard mask layer 80 is composed of silicon dioxide.
- the dielectric hard mask layer 80 may be formed, for example, by CVD, PECVD or ALD.
- the thickness of the dielectric hard mask layer 80 can be from 10 nm to 50 nm, although lesser and greater thicknesses can also be employed.
- the OPL 92 is formed on the dielectric hard mask layer 80 as a blanket layer.
- the OPL 92 may include an organic planarization material, which is a self-planarizing organic material that includes carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon.
- the self-planarizing organic material can be a polymer with sufficiently low viscosity so that the top surface of the OPL 92 forms a planar horizontal surface.
- Exemplary organic planarization materials include, but are not limited to, near-frictionless carbon (NFC) material, diamond-like carbon, polyarylene ether, and polyimide.
- the OPL 92 can be deposited, for example, by spin coating. The thickness of the OPL 92 can be from 100 nm to 500 nm, although lesser and greater thicknesses can also be employed.
- the antireflective hard mask layer 94 is formed on the OPL 92 as a blanket layer.
- the antireflective hard mask layer 94 may include an antireflective coating material as known in the art.
- the antireflective hard mask layer 94 is employed in the lithographic process to improve the photoresist profile and to reduce the line width variation caused by scattering and reflecting light.
- the antireflective hard mask layer 94 may include a silicon-containing antireflective coating (SiARC) material, a titanium-containing antireflective coating material (TiARC), silicon nitride, silicon oxide or TiN.
- the antireflective hard mask layer 94 is composed of a SiARC material.
- the antireflective hard mask layer 94 can be applied, for example, by spin coating or CVD.
- the thickness of the antireflective hard mask layer 94 can be from 10 nm to 150 nm, although lesser and greater thicknesses can also be employed.
- a photoresist layer (not shown) is deposited as a blanket layer atop the antireflective hard mask layer 94 , for example, by spin coating.
- the photoresist layer may include any conventional organic photoresist material such as, for example, methacrylates or polyesters.
- the photoresist layer may have a thickness from 30 nm to 500 nm, although lesser and greater thicknesses can also be employed.
- the photoresist layer is then lithographically patterned into a predetermined shape forming the photoresist portion 96 P atop the antireflective hard mask layer 94 .
- the antireflective hard mask layer 94 and the OPL 92 are patterned using the photoresist portion 96 P as an etch mask.
- the patterning of the antireflective hard mask layer 94 and the OPL layer 92 can include a dry etch such as, for example, RIE, plasma etch, or ion beam etch that removes materials that provide the antireflective hard mask layer 94 and the OPL 92 selective to the dielectric material that provides the dielectric hard mask layer 80 .
- a RIE process employing at least one hydrofluorocarbon gas and/or at least one hydrochlorocarbon gas as an etchant may be performed to removing portions of the antireflective hard mask layer 94 and the OPL 92 that are not covered by the photoresist portion 96 P.
- the remaining portion of the antireflective hard mask layer 94 is herein referred to as an antireflective hard mask portion 94 P.
- the remaining portion of the OPL 92 is herein referred to as an OPL portion 92 P.
- sidewalls of the antireflective hard mask portion 94 P and the OPL portion 92 P are vertically aligned to sidewalls of the photoresist portion 96 P.
- the photoresist portion 96 P can be removed during the patterning of the antireflective hard mask layer 94 and the OPL 92 .
- the dielectric hard mask layer 80 is patterned using the OPL portion 92 P as an etch mask.
- the patterning of the dielectric hard mask layer 80 can include a dry etch such as, for example, RIE, plasma etch, or ion beam etch that removes the dielectric material that provides the dielectric hard mask layer 80 selective to the metal that provides the metallic hard mask layer 70 .
- RIE reactive ion etch
- ion beam etch ion beam etch
- the metallic hard mask layer 70 is patterned using the OPL portion 92 P as an etch mask.
- the patterning of the metallic hard mask layer 70 can include a dry etch such as, for example, RIE, plasma etch, or ion beam etch that removes the metal that provides the metallic hard mask layer 70 selective to the metal that provides the metal layer 60 .
- the metallic hard mask layer 70 can be etched with a RIE process employing chlorine (Cl 2 ) gas or chlorine-containing gases as an etchant. After the etch, the remaining portion of the metallic hard mask layer 70 is herein referred to as a metallic hard mask portion 70 P.
- a metallic hard mask portion 70 P In one embodiment and as shown in FIG. 4 , after patterning sidewalls of the dielectric hard mask portion 80 P and the metallic hard mask portion 70 P are vertically aligned to the sidewalls of the OPL portion 92 P.
- the antireflective hard mask portion 94 P is removed by the etch chemistries employed to etch the dielectric hard mask layer 80 and the metallic hard mask layer 70 . Any OPL portion 92 P remained after the dry etches can be subsequently, removed, for example, by plasma ashing.
- the dielectric hard mask portion 80 P is removed from the structure, leaving the metallic hard mask portion 70 P atop the metal layer 60 .
- the dielectric hard mask portion 80 P can be removed employing a planarization process such as, for example, CMP and/or grinding.
- a wet etch can be used to remove dielectric hard mask portion 80 P from the structure.
- the dielectric hard mask portion 80 P can be removed utilizing a diluted HF solution.
- the metal layer 60 and the MIEC material layer 50 are simultaneously patterned using the metallic hard mask portion 70 P as an etch mask.
- the patterning of the metal layer 60 and the MIEC material layer 50 can include a dry etch such as, for example, RIE, plasma etch, or ion beam etch that removes the metal that provides the metal layer 60 and the material that provides the MIEC material layer 50 selective to the metal that provides the bottom electrode 40 and the dielectric material that provides the second dielectric material layer 30 .
- the top electrode layer 60 and the MIEC material layer 50 can be simultaneously etched with a RIE process employing one or more gases comprised of C, H, and O such as CH 3 OH, C 2 H 5 OH or a gas mixture containing NH 3 and CO, NH 3 and CH 4 or CH 3 and C 2 H 4 as an etchant. Peripheral portions of the bottom electrode 40 are exposed after the etch.
- gases comprised of C, H, and O such as CH 3 OH, C 2 H 5 OH or a gas mixture containing NH 3 and CO, NH 3 and CH 4 or CH 3 and C 2 H 4 as an etchant.
- the remaining portion of the metal layer 60 is herein referred to as a metal portion 60 P
- the remaining portion of the MIEC material layer 50 is herein referred to as a MIEC material portion 50 P.
- sidewalls of the metal portion 60 P and the MIEC material portion 50 P are vertically aligned to the sidewalls of the metallic hard mask portion 70 P.
- an interlevel dielectric (ILD) layer 90 is formed on the bottom electrode 40 and the second dielectric material layer 30 .
- the ILD layer 90 may include a dielectric material that can be easily planarized.
- the ILD layer 90 can be a doped silicate glass, an undoped silicate glass (silicon oxide), an organosilicate glass (OSG), silicon nitride, silicon oxynitride, or a porous dielectric material.
- the ILD layer 90 can be formed by CVD, PVD or spin coating. The thickness of the ILD layer 90 can be selected so that an entirety of the top surface of the ILD layer 90 is initially formed above the top surface of the metallic hard mask portion 70 P.
- the ILD layer 90 can be subsequently planarized, for example, by CMP.
- the planarization of the ILD 90 is performed using the metallic hard mask portion 70 P as a planarization stop layer.
- the ILD layer 90 has a top surface coplanar with the top surface of the metallic hard mask portion 70 P.
- the metallic hard mask portion 70 P and the metal portion 60 P together constitute a top electrode for a MIEC-based memory cell access device.
- the planarization of the ILD 90 also removes the metallic hard mask portion 70 P completely from the structure.
- the ILD layer 90 has a top surface coplanar with the top surface of the metal portion 60 P.
- the metal portion 60 P acts as a top electrode for a MIEC-based memory cell access device.
- a MIEC-based memory cell access device for a memory cell is thus formed using a subtractive etch process.
- the MIEC-based memory cell access device includes a MIEC material portion 50 P sandwiched between a bottom electrode 40 and a top electrode ( 60 P or the combination of 60 P and 70 P).
- the contact area between the top electrode ( 60 P or the combination of 60 P and 70 P) and the MIEC material portion 50 P is substantially the same as the contact area between the bottom electrode 40 and the MIEC material portion 50 P.
- the contact area between the top electrode ( 60 P or the combination of 60 P and 70 P) and the MIEC material portion 50 P is no more than 20% greater than the contact area between the bottom electrode 40 and the MIEC material portion 50 P. Due to the better symmetry with respect to the electrode contact areas, the resulting MIEC-based memory cell access device exhibits improved I-V characteristics and reduced low voltage leakage currents.
- CMP process for the MIEC material is not needed in the subtractive etch process, surface defects caused by the CMP process can be eliminated.
- the critical dimension (i.e., smallest allowable with) of the MIEC-based memory cell is defined by the lithograph tool. The subtractive etch process employed in the present application thus allows fabricating large numbers of devices for a given area.
- a second exemplary semiconductor structure according to a second embodiment of the present application includes a second material stack formed over the substrate 10 .
- the second material stack employed in the second embodiment of the present application has a similar structure to the first material stack in the first embodiment except that in the second embodiment a stack of alternating MIEC material layers 50 and metal layers 60 is formed between the bottom electrode 40 and the metallic hard mask layer 70 .
- the second material stack includes, from bottom to top, a first dielectric material layer 20 , a second dielectric material layer 30 having a bottom electrode 40 embedded there in, a stack of alternating MIEC material layers 50 and metal layers 60 , a metallic hard mask layer 70 , a dielectric hard mask layer 80 , an organic planarization layer (OPL) 92 , an antireflective hard mask layer 94 , and a photoresist portion 96 P.
- the stack of alternating MIEC material layers 50 and metal layers 60 includes two pairs of MIEC material layer 50 and metal layers 60 .
- Each component layer of the second material stack can have the same composition and range of thickness and can be fabricated using the same deposition process as described above in conjunction with the first material stack described above in FIG. 1 , thus will not be described in detail herein.
- processing steps described above in FIGS. 1-5 can be performed to provide a metallic hard mask portion 70 P atop the topmost metal layer 60 in the stack of alternating MIEC material layers 50 and metal layers 60 .
- the stack of alternating MIEC material layers 50 and metal layers 60 can be patterned simultaneously by performing the processing steps of FIG. 6 to provide a stack of alternating MIEC material portions 50 P and metal portions 60 P.
- the processing steps described above in FIG. 7 are performed to form an ILD layer 90 laterally surrounding the alternating MIEC material portions 50 P and metal portions 60 P and the metallic hard mask portion 70 P, if present.
- the metallic hard mask portion 70 P and the topmost metal portion 60 P together constitute a top electrode for a MIEC-based memory cell access device. If not present, the topmost metal portion 60 P acts as a top electrode for a MIEC-based memory cell access device.
- a MIEC-based memory cell access device is thus formed.
- the MIEC-based memory cell access device includes vertically stacked MIEC material portions 50 P sandwiched between a bottom electrode 40 and a top electrode.
- the vertically stacked MIED material portions 50 P are separated from one another by metal portions 60 P.
- the access device with vertically stacked MIEC material portions 50 P exhibits a higher MIEC voltage margin than the access device with a single MIEC material portion 60 P, which enables driving larger sizes of memory arrays.
- the stack of alternating MIEC material layers 50 and metal layers 60 can be etched in a single etch step, no additional processing step is needed in the second embodiment compared to the first embodiment.
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Abstract
A method of forming a mixed ionic electron conductor (MIEC)-based memory cell access device using a subtractive etch process is provided. After blanket depositing a MIEC material layer on a bottom electrode and a dielectric layer laterally surrounding the bottom electrode and blanket depositing a metal layer on the MIEC material layer, the metal layer and the MIEC material layer are patterned simultaneously.
Description
- The present application relates to integrated circuit fabrication, and more particularly, to the fabrication of mixed ionic electronic conductor-based memory cell access devices using a subtractive etch process.
- Mixed ionic electronic conductors (MIEC) are being explored as access devices for non-volatile memories such as, for example, phase-change memory, resistive random access memory, and spin-torque transfer random access memory. MIEC-based access devices having high voltage margins for use in large memory arrays are desirable. Study shows that MIEC voltage margins increase as the confined volume of MIEC material decreases.
- The MIEC-based memory cell access devices are typically formed using an additive damascene process in which a dielectric material layer is patterned to include vias therein. The MIEC material is subsequently deposited within the vias and thereafter any MIEC material that is located outside the vias is removed utilizing a planarization process, e.g., chemical mechanical planarization (CMP).
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FIG. 1 shows a MIEC-based memorycell access device 100 formed by the additive damascene process. The MIEC-based memorycell access device 100 includes aMIEC material portion 120 sandwiched between abottom electrode 110 and atop electrode 130. TheMIEC material portion 120 is formed by filling a via formed in adielectric material layer 140. Several issues are associated with this conventional damascene process in forming the MIEC-based memorycell access device 100. First, the via etching process typically forms a via having a tapered profile; theMIEC material portion 120 formed within the via is also tapered to have a smaller cross-section area at the bottom of theMIEC material portion 120 than at the top of theMIEC material portion 120. Thus, the contact area between theMIEC material portion 120 and thebottom electrode 110 is smaller than that between theMIEC material portion 120 and thetop electrode 130. The different contact areas lead to asymmetric current vs. voltage (I-V) characteristics during bi-directional electrical operation of the access device. This device asymmetry also results in an increase in the low leakage current of the access device. Moreover, it is known that the CMP process that is employed to remove the excess MIEC material from the top of thedielectric material layer 140 forms surface defects on theMIEC material portion 120, which adversely affect the device performance. Therefore a need exists to overcome the problems with the prior art as discussed above. - The present application provides methods of forming MIEC-based memory cell access devices using a subtractive etch process.
- In one embodiment, the method includes first forming a MIEC material layer on a bottom electrode and a dielectric material layer laterally surrounding the bottom electrode. A metal layer is subsequently formed on the MIEC material layer. After forming a metallic hard mask portion on the metal layer, portions of the metal layer and portions of the MIEC material layer that are not covered by the metallic hard mask portion are removed.
- In another embodiment, the method includes first forming alternating MIEC material layers and metal layers on a bottom electrode and a dielectric material layer laterally surrounding the bottom electrode. A metallic hard mask portion is subsequently formed on a topmost metal layer in the alternating MIEC material layers and metal layers. Portions of the alternating MIEC material layers and metal layers that are not covered by the metallic hard mask portion are then removed.
-
FIG. 1 is a cross-sectional view of a MIEC-based access device formed using a prior art additive damascene process. -
FIG. 2 is a cross-section view of a first exemplary semiconductor structure according to a first embodiment of the present application after forming a first material stack over a substrate; the first material stack includes, from bottom to top, a first dielectric material layer, a second dielectric material layer having a bottom electrode embedded there in, a MIEC material layer, a metal layer, a metallic hard mask layer, a dielectric hard mask layer, an organic planarization layer (OPL), an antireflective hard mask layer and a photoresist portion. -
FIG. 3 is a cross-sectional view of the first exemplary semiconductor structure ofFIG. 2 after forming an antireflective hard mask portion and an OPL portion by patterning the antireflective hard mask layer and the OPL using the photoresist portion as an etch mask. -
FIG. 4 is a cross-sectional view of the first exemplary semiconductor structure ofFIG. 3 after forming a dielectric hard mask portion and a metallic hard mask portion by patterning the dielectric hard mask layer and the metallic hard mask layer using the OPL portion as an etch mask. -
FIG. 5 is a cross-sectional view of the first exemplary semiconductor structure ofFIG. 4 after removing the dielectric hard mask portion. -
FIG. 6 is a cross-sectional view of the first exemplary semiconductor structure ofFIG. 5 after forming a metal portion and a MIEC material portion by simultaneously patterning the metal layer and the MIEC material layer using the metallic hard mask portion as an etch mask. -
FIG. 7 is a cross-sectional view of the first exemplary semiconductor structure ofFIG. 6 after forming an interlevel dielectric (ILD) layer to laterally surround the MIEC material portion, the metal portion and the metallic hard mask portion according to one embodiment of the present application. -
FIG. 8 is a cross-sectional view of the first exemplary semiconductor structure ofFIG. 6 after forming an ILD layer to laterally surround the MIEC material portion and the metal portion according to another embodiment of the present application. -
FIG. 9 is a cross-section view of a second exemplary semiconductor structure according to a second embodiment of the present application after forming a second material stack over a substrate; the second material stack includes, from bottom to top, a first dielectric material layer, a second dielectric material layer having a bottom electrode embedded there in, a stack of alternating MIEC material layers and metal layers, a metallic hard mask layer, a dielectric hard mask layer, an OPL, an antireflective hard mask layer, and a photoresist portion. -
FIG. 10 is a cross-sectional view of the second exemplary semiconductor structure ofFIG. 9 after forming a metallic hard mask portion by sequentially patterning the ARC layer, the OPL, the dielectric hard mask layer and the metallic hard mask layer and removing remaining portions of the antireflective hard mask layer, the OPL and the dielectric hard mask layer. -
FIG. 11 is a cross-sectional view of the second exemplary semiconductor structure ofFIG. 10 after simultaneously patterning the stack of alternating MIEC material layers and metal layers and forming the ILD layer. - The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.
- In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.
- Referring to
FIG. 2 , a first exemplary semiconductor structure according to a first embodiment of the present application includes a first material stack formed over asubstrate 10. The first material stack includes, from bottom to top, a firstdielectric material layer 20, a seconddielectric material layer 30 having abottom electrode 40 embedded therein, aMIEC material layer 50, ametal layer 60, a metallichard mask layer 70, a dielectrichard mask layer 80, an organic planarization layer (OPL) 92, an antireflective hard mask layer 94 and aphotoresist portion 96P. - The
substrate 10 may be composed of a semiconductor material. Exemplary semiconductor materials that may be used assubstrate 10 include, but are not limited to, Si, SiGe, SiGeC, SiC, Ge alloys GaAs, InAs, InP, carbon-containing materials such as, for example, carbon nanotubes and graphene, and other III/V or II/VI compound semiconductors. In one embodiment, the semiconductor material which can be employed assubstrate 10 may be present in a bulk semiconductor substrate. In another embodiment, the semiconductor material which can be employed assubstrate 10 may be a topmost layer of a multilayered semiconductor material stack. In yet another embodiment, the semiconductor material that can be employed assubstrate 10 can be a topmost layer of a semiconductor-on-insulator substrate. - In some embodiments, the semiconductor material that can be employed as
substrate 10 can be single crystalline (i.e., a material in which the crystal lattice of the entire sample is continuous and unbroken to the edges of the sample, with no grain boundaries). In another embodiment, the semiconductor material that can be employed assubstrate 10 can be polycrystalline (i.e., a material that is composed of many crystallites of varying size and orientation; the variation in direction can be random (called random texture) or directed, possibly due to growth and processing conditions). In yet another embodiment of the present application, the semiconductor material that can be employed assubstrate 10 can be amorphous (i.e., a non-crystalline material that lacks the long-range order characteristic of a crystal). Typically, the semiconductor material that can be employed assubstrate 10 is a single crystalline semiconductor material, such as, for example, single crystalline silicon. - The
substrate 10 may be doped, undoped or contain doped and undoped regions therein. For clarity, the doped regions are not specifically shown insubstrate 10. Each doped region within thesubstrate 10 may have the same, or they may have different conductivities and/or doping concentrations. - The
substrate 10 can be processed utilizing techniques known in the art to include one or more semiconductor devices such as, for example, transistors, capacitors, diodes, resistors, or other components that are part of integrated circuits. For clarity, the semiconductor devices are not shown in the drawings of the present application. - The first
dielectric material layer 20 is formed on thesubstrate 10. The firstdielectric material layer 20 may include a dielectric material such as, for example, silicon dioxide, silicon nitride, or silicon oxyntride. In some embodiments of the present application, the firstdielectric material layer 20 may also include a low-k dielectric material having a dielectric constant that is about 4.0 or less. Exemplary low-k dielectric materials include, but are not limited to, organosilicates, silsequioxanes, undoped silicate glass (USG), fluorosilicate glass (FSG), tetraethylorthosilicate (TEOS), SiCOH or borophosphosilicate glass (BPSG). The firstdielectric material layer 20 may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or spin coating. The thickness of the firstdielectric material layer 20 may be from 100 nm to 1,000 nm, although lesser and greater thicknesses can also be employed. - The first
dielectric material layer 20 may include interconnect structures (not shown) to provide electric connections among electric components formed in thesubstrate 10. The firstdielectric material layer 20 may also include memory cells (not shown) embedded therein. For clarity, the interconnect structures and memory cells are not shown in the drawings of the present application. - The second
dielectric material layer 30 is formed on the firstdielectric material layer 20. The seconddielectric material layer 30 may include a dielectric material that is the same as, or different from, the dielectric material of the firstdielectric material layer 20. In one embodiment, the seconddielectric material layer 30 is composed of a dielectric material that can be selectively etched with respect to the firstdielectric material layer 20. For example and when the firstdielectric material layer 20 is composed of a dielectric oxide, the seconddielectric material layer 30 may be composed of silicon nitride. The seconddielectric material layer 30 may be formed by CVD, PECVD or spin coating. The thickness of the seconddielectric material layer 30 may be from 10 nm to 1,000 nm, although lesser and greater thicknesses can also be employed. - Following the deposition of the second
dielectric material layer 30, thebottom electrode 40 is formed within the seconddielectric material layer 30. Thebottom electrode 40 is laterally surrounded by the seconddielectric material layer 30. In some embodiments of the present application, thebottom electrode 40 can be a top electrode of a memory cell. Thebottom electrode 40 may include any suitable conductive material such as, for example, TiN, TaN, W, Al, Cu, Ag, Ir, Pt, Au, Co or Ni. In one embodiment, thebottom electrode 40 can be formed by first patterning the seconddielectric material layer 30, utilizing lithography and etching processes known in the art, to provide an opening (not shown) that extends through the seconddielectric material layer 30. The lithographic step may include applying a photoresist layer (not shown) to the seconddielectric material layer 30, exposing the photoresist layer to a pattern of radiation and developing the pattern into the exposed photoresist layer unitizing a resist developer. The etching step performed to transfer the pattern from the patterned photoresist layer into the seconddielectric material layer 30 can include an anisotropic etch which can be a dry etch such as, for example, reactive ion etch (RIE) or a wet etch. After the etch, the patterned photoresist layer can be removed from the structure utilizing a resist stripping process such as, for example, ashing. The opening is then filled with the conductive material by a conventional deposition method such as, for example, CVD, physical vapor deposition (PVD) or plating. The excess conductive material is subsequently removed from the top surface of the seconddielectric material layer 30, for example, by CMP. Thebottom electrode 40 thus formed has a top surface coplanar with the top surface of the seconddielectric material layer 30. - The
MIEC material layer 50 is formed on the seconddielectric material layer 30 and thebottom electrode 40 as a blanket layer (i.e., as an unpatterned contiguous layer). TheMIEC material layer 50 may include a material that is capable of conducting both ions and electronic charge carriers (electrons and/or holes). For example, theMIEC material layer 50 may be composed of a material represented by a formula of MaXbYc, wherein M is a metallic element including but not limited to Cu, Ag, Li, or Zn, X is a Group XIV element including, but not limited to, Ge, Si, Sn or C or a Group VIB transition metal including but not limited to Cr, Mo or W, and Y is a Group XVI or chalcogen element including but not limited to S, Se, Te or O, and wherein a is from 20 to 70 atomic %, b is from 4 to 30 atomic %, and c is from 30 to 60 atomic %. In one embodiment, theMIEC material layer 50 includes Cu8GeS6 or Cu8GeSe6. In some embodiments, combinations of the various elements mentioned above, such as Ag4.7Cu3.3GeS6, could also be used as theMIEC layer 50. TheMIEC material layer 50 can be deposited, for example, by PVD, CVD or atomic layer deposition (ALD). The deposition temperature of the MIEC material is typically below 400° C., thus is compatible with low-temperature back-end-of-line (BEOL) semiconductor processing conditions. The thickness of theMIEC material layer 50 that is formed can be from 10 nm to 200 nm, although lesser and greater thicknesses can also be employed. - The
metal layer 60 is formed on theMIEC material layer 50 as a blanket layer. Themetal layer 60 may include a conductive material that can withstand the etch chemistry employed to etch the overlying metallichard mask layer 70, thus acting as a barrier to prevent damage to theMIEC material layer 50 during the etching of the metallichard mask layer 70 subsequently performed. In one embodiment, themetal layer 60 may include Ru, Cu, Ag, Au, Ni, Fe, Pt, Pd, W, Ir or Co. Themetal layer 60 may be formed utilizing a conventional deposition method such as, for example, CVD, PECVD or ALD. - The metallic
hard mask layer 70 is formed on themetal layer 60 as a blanket layer. The metallichard mask layer 70 may include a metal nitride, a metal carbide, an elemental metal, an intermetallic alloy, or a combination or a stack thereof. In one embodiment, the metallichard mask layer 70 includes a metal nitride such as TiN, TaN, WN or an alloy thereof. The metallichard mask layer 70 may be deposited, for example, by CVD or PVD. The thickness of the metallichard mask layer 70 can be from 10 to 200 nm, although lesser and greater thickness can also be employed. - The dielectric
hard mask layer 80 is formed on the metallichard mask layer 70 as a blanket layer. The dielectrichard mask layer 80 may include a dielectric oxide or dielectric nitride. In one embodiment, the dielectrichard mask layer 80 is composed of silicon dioxide. The dielectrichard mask layer 80 may be formed, for example, by CVD, PECVD or ALD. The thickness of the dielectrichard mask layer 80 can be from 10 nm to 50 nm, although lesser and greater thicknesses can also be employed. - The
OPL 92 is formed on the dielectrichard mask layer 80 as a blanket layer. TheOPL 92 may include an organic planarization material, which is a self-planarizing organic material that includes carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. In one embodiment, the self-planarizing organic material can be a polymer with sufficiently low viscosity so that the top surface of theOPL 92 forms a planar horizontal surface. Exemplary organic planarization materials include, but are not limited to, near-frictionless carbon (NFC) material, diamond-like carbon, polyarylene ether, and polyimide. TheOPL 92 can be deposited, for example, by spin coating. The thickness of theOPL 92 can be from 100 nm to 500 nm, although lesser and greater thicknesses can also be employed. - The antireflective hard mask layer 94 is formed on the
OPL 92 as a blanket layer. The antireflective hard mask layer 94 may include an antireflective coating material as known in the art. The antireflective hard mask layer 94 is employed in the lithographic process to improve the photoresist profile and to reduce the line width variation caused by scattering and reflecting light. The antireflective hard mask layer 94 may include a silicon-containing antireflective coating (SiARC) material, a titanium-containing antireflective coating material (TiARC), silicon nitride, silicon oxide or TiN. In one embodiment, the antireflective hard mask layer 94 is composed of a SiARC material. The antireflective hard mask layer 94 can be applied, for example, by spin coating or CVD. The thickness of the antireflective hard mask layer 94 can be from 10 nm to 150 nm, although lesser and greater thicknesses can also be employed. - A photoresist layer (not shown) is deposited as a blanket layer atop the antireflective hard mask layer 94, for example, by spin coating. The photoresist layer may include any conventional organic photoresist material such as, for example, methacrylates or polyesters. The photoresist layer may have a thickness from 30 nm to 500 nm, although lesser and greater thicknesses can also be employed. The photoresist layer is then lithographically patterned into a predetermined shape forming the
photoresist portion 96P atop the antireflective hard mask layer 94. - Referring to
FIG. 3 , the antireflective hard mask layer 94 and theOPL 92 are patterned using thephotoresist portion 96P as an etch mask. The patterning of the antireflective hard mask layer 94 and theOPL layer 92 can include a dry etch such as, for example, RIE, plasma etch, or ion beam etch that removes materials that provide the antireflective hard mask layer 94 and theOPL 92 selective to the dielectric material that provides the dielectrichard mask layer 80. In one embodiment, a RIE process employing at least one hydrofluorocarbon gas and/or at least one hydrochlorocarbon gas as an etchant may be performed to removing portions of the antireflective hard mask layer 94 and theOPL 92 that are not covered by thephotoresist portion 96P. The remaining portion of the antireflective hard mask layer 94 is herein referred to as an antireflectivehard mask portion 94P. The remaining portion of theOPL 92 is herein referred to as anOPL portion 92P. In one embodiment and as shown inFIG. 3 , sidewalls of the antireflectivehard mask portion 94P and theOPL portion 92P are vertically aligned to sidewalls of thephotoresist portion 96P. Thephotoresist portion 96P can be removed during the patterning of the antireflective hard mask layer 94 and theOPL 92. - Referring to
FIG. 4 , the dielectrichard mask layer 80 is patterned using theOPL portion 92P as an etch mask. The patterning of the dielectrichard mask layer 80 can include a dry etch such as, for example, RIE, plasma etch, or ion beam etch that removes the dielectric material that provides the dielectrichard mask layer 80 selective to the metal that provides the metallichard mask layer 70. After the etch, the remaining portion of the dielectrichard mask layer 80 is herein referred to as a dielectrichard mask portion 80P. - Subsequently, the metallic
hard mask layer 70 is patterned using theOPL portion 92P as an etch mask. The patterning of the metallichard mask layer 70 can include a dry etch such as, for example, RIE, plasma etch, or ion beam etch that removes the metal that provides the metallichard mask layer 70 selective to the metal that provides themetal layer 60. In one embodiment, the metallichard mask layer 70 can be etched with a RIE process employing chlorine (Cl2) gas or chlorine-containing gases as an etchant. After the etch, the remaining portion of the metallichard mask layer 70 is herein referred to as a metallichard mask portion 70P. In one embodiment and as shown inFIG. 4 , after patterning sidewalls of the dielectrichard mask portion 80P and the metallichard mask portion 70P are vertically aligned to the sidewalls of theOPL portion 92P. - The antireflective
hard mask portion 94P is removed by the etch chemistries employed to etch the dielectrichard mask layer 80 and the metallichard mask layer 70. AnyOPL portion 92P remained after the dry etches can be subsequently, removed, for example, by plasma ashing. - Referring to
FIG. 5 , the dielectrichard mask portion 80P is removed from the structure, leaving the metallichard mask portion 70P atop themetal layer 60. In one embodiment, the dielectrichard mask portion 80P can be removed employing a planarization process such as, for example, CMP and/or grinding. In another embodiment, a wet etch can be used to remove dielectrichard mask portion 80P from the structure. For example, the dielectrichard mask portion 80P can be removed utilizing a diluted HF solution. - Referring to
FIG. 6 , themetal layer 60 and theMIEC material layer 50 are simultaneously patterned using the metallichard mask portion 70P as an etch mask. The patterning of themetal layer 60 and theMIEC material layer 50 can include a dry etch such as, for example, RIE, plasma etch, or ion beam etch that removes the metal that provides themetal layer 60 and the material that provides theMIEC material layer 50 selective to the metal that provides thebottom electrode 40 and the dielectric material that provides the seconddielectric material layer 30. In one embodiment, thetop electrode layer 60 and theMIEC material layer 50 can be simultaneously etched with a RIE process employing one or more gases comprised of C, H, and O such as CH3OH, C2H5OH or a gas mixture containing NH3 and CO, NH3 and CH4 or CH3 and C2H4 as an etchant. Peripheral portions of thebottom electrode 40 are exposed after the etch. - After the etch, the remaining portion of the
metal layer 60 is herein referred to as ametal portion 60P, and the remaining portion of theMIEC material layer 50 is herein referred to as aMIEC material portion 50P. In one embodiment and as shown inFIG. 6 , sidewalls of themetal portion 60P and theMIEC material portion 50P are vertically aligned to the sidewalls of the metallichard mask portion 70P. - Referring to
FIG. 7 , an interlevel dielectric (ILD)layer 90 is formed on thebottom electrode 40 and the seconddielectric material layer 30. TheILD layer 90 may include a dielectric material that can be easily planarized. For example, theILD layer 90 can be a doped silicate glass, an undoped silicate glass (silicon oxide), an organosilicate glass (OSG), silicon nitride, silicon oxynitride, or a porous dielectric material. TheILD layer 90 can be formed by CVD, PVD or spin coating. The thickness of theILD layer 90 can be selected so that an entirety of the top surface of theILD layer 90 is initially formed above the top surface of the metallichard mask portion 70P. TheILD layer 90 can be subsequently planarized, for example, by CMP. In one embodiment and as shown inFIG. 7 , the planarization of theILD 90 is performed using the metallichard mask portion 70P as a planarization stop layer. Thus, after the planarization, theILD layer 90 has a top surface coplanar with the top surface of the metallichard mask portion 70P. The metallichard mask portion 70P and themetal portion 60P together constitute a top electrode for a MIEC-based memory cell access device. In another embodiment, the planarization of theILD 90 also removes the metallichard mask portion 70P completely from the structure. Thus, as shown inFIG. 8 , after the planarization, theILD layer 90 has a top surface coplanar with the top surface of themetal portion 60P. In this case, themetal portion 60P acts as a top electrode for a MIEC-based memory cell access device. - A MIEC-based memory cell access device for a memory cell is thus formed using a subtractive etch process. The MIEC-based memory cell access device includes a
MIEC material portion 50P sandwiched between abottom electrode 40 and a top electrode (60P or the combination of 60P and 70P). In the present application, since theMIEC material portion 50P is formed by a subtractive etch process, the contact area between the top electrode (60P or the combination of 60P and 70P) and theMIEC material portion 50P is substantially the same as the contact area between thebottom electrode 40 and theMIEC material portion 50P. That is, the contact area between the top electrode (60P or the combination of 60P and 70P) and theMIEC material portion 50P is no more than 20% greater than the contact area between thebottom electrode 40 and theMIEC material portion 50P. Due to the better symmetry with respect to the electrode contact areas, the resulting MIEC-based memory cell access device exhibits improved I-V characteristics and reduced low voltage leakage currents. In addition, since CMP process for the MIEC material is not needed in the subtractive etch process, surface defects caused by the CMP process can be eliminated. In the present application, the critical dimension (i.e., smallest allowable with) of the MIEC-based memory cell is defined by the lithograph tool. The subtractive etch process employed in the present application thus allows fabricating large numbers of devices for a given area. - Referring to
FIG. 9 , a second exemplary semiconductor structure according to a second embodiment of the present application includes a second material stack formed over thesubstrate 10. The second material stack employed in the second embodiment of the present application has a similar structure to the first material stack in the first embodiment except that in the second embodiment a stack of alternating MIEC material layers 50 andmetal layers 60 is formed between thebottom electrode 40 and the metallichard mask layer 70. Specifically, the second material stack includes, from bottom to top, a firstdielectric material layer 20, a seconddielectric material layer 30 having abottom electrode 40 embedded there in, a stack of alternating MIEC material layers 50 andmetal layers 60, a metallichard mask layer 70, a dielectrichard mask layer 80, an organic planarization layer (OPL) 92, an antireflective hard mask layer 94, and aphotoresist portion 96P. In one embodiment and as shown inFIG. 9 , the stack of alternating MIEC material layers 50 andmetal layers 60 includes two pairs ofMIEC material layer 50 and metal layers 60. Each component layer of the second material stack can have the same composition and range of thickness and can be fabricated using the same deposition process as described above in conjunction with the first material stack described above inFIG. 1 , thus will not be described in detail herein. - Referring to
FIG. 10 , processing steps described above inFIGS. 1-5 can be performed to provide a metallichard mask portion 70P atop thetopmost metal layer 60 in the stack of alternating MIEC material layers 50 and metal layers 60. - Referring
FIG. 11 , the stack of alternating MIEC material layers 50 andmetal layers 60 can be patterned simultaneously by performing the processing steps ofFIG. 6 to provide a stack of alternatingMIEC material portions 50P andmetal portions 60P. - Next, the processing steps described above in
FIG. 7 are performed to form anILD layer 90 laterally surrounding the alternatingMIEC material portions 50P andmetal portions 60P and the metallichard mask portion 70P, if present. When present, the metallichard mask portion 70P and thetopmost metal portion 60P together constitute a top electrode for a MIEC-based memory cell access device. If not present, thetopmost metal portion 60P acts as a top electrode for a MIEC-based memory cell access device. - A MIEC-based memory cell access device is thus formed. The MIEC-based memory cell access device includes vertically stacked
MIEC material portions 50P sandwiched between abottom electrode 40 and a top electrode. The vertically stackedMIED material portions 50P are separated from one another bymetal portions 60P. In the second embodiment, the access device with vertically stackedMIEC material portions 50P exhibits a higher MIEC voltage margin than the access device with a singleMIEC material portion 60P, which enables driving larger sizes of memory arrays. In addition, since the stack of alternating MIEC material layers 50 andmetal layers 60 can be etched in a single etch step, no additional processing step is needed in the second embodiment compared to the first embodiment. - While the present application has been particularly shown and described with respect to various embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Claims (20)
1. A method of forming a semiconductor structure comprising:
forming a mixed ionic electric conductor (MIEC) material layer as a blanket layer on a bottom electrode and a dielectric material layer laterally surrounding the bottom electrode;
forming a metal layer as a blanket layer on the MIEC material layer;
forming a metallic hard mask portion consisting of a metal nitride directly on the metal layer; and
patterning the metal layer and the MIEC material layer to remove portions of the metal layer and portions of the MIEC material layer that are not covered by the metallic hard mask portion, wherein peripheral portions of the bottom electrode are exposed after the patterning.
2. The method of claim 1 , wherein the patterning the metal layer and the MIEC material layer to remove the portions of the metal layer and the portions of the MIEC material layer that are not covered by the metallic hard mask portion are performed simultaneously utilizing an anisotropic etch.
3. The method of claim 2 , wherein the anisotropic etch comprises etching the metal layer and the MIEC material layer with at least one etching gas comprising C, H and O or a gas mixture of NH3 and CO, a gas mixture of NH3 and CH4 or a gas mixture of NH3 and C2H4.
4. The method of claim 1 , wherein the MIEC material layer comprises a material represented by a formula of MaXbYc, wherein:
M is selected from the group consisting of Cu, Ag, Li and Zn,
X is selected from the group consisting of Ge, Si, Sn, C, Cr, Mo and W, and
Y is selected from the group consisting of S, Se, Te or O, and
wherein a is from 20 to 70 atomic %, b is from 4 to 30 atomic %, and c is from 30 to 60 atomic %.
5. The method of claim 1 , wherein the bottom electrode comprises TiN, TaN, W, Al, Cu, Ag, Ir, Pt, Au, Co or Ni.
6. The method of claim 1 , wherein the metal layer comprises Ru, Cu, Ag, Au, Ni, Fe, Pt, Pd, W, Ir or Co.
7. The method of claim 1 , further comprising:
forming a metallic hard mask layer directly on the metal layer;
forming a dielectric hard mask layer on the metallic hard mask layer;
forming an organic planarization layer (OPL) on the dielectric hard mask layer;
forming an antireflective hard mask layer on the OPL; and
forming a photoresist portion on the OPL.
8. The method of claim 7 , further comprising:
patterning the antireflective hard mask layer and the OPL using the photoresist portion as an etch mask;
patterning the dielectric hard mask layer and the metallic hard mask layer using a remaining portion of the OPL as an etch mask; and
removing a remaining portion of the dielectric hard mask layer, wherein a remaining portion of the metallic hard mask layer provides the metallic hard mask portion.
9. The method of claim 1 , further comprising removing the metallic hard mask portion after patterning the metal layer and the MIEC material layer to remove the metal layer and the portions of the MIEC material layer that are not covered by the metallic hard mask portion.
10. The method of claim 1 , further comprising forming an interlevel dielectric layer laterally surrounding a remaining portion of the MIEC material layer and a remaining portion of the metal layer after the removing the portions of the metal layer and the portions of the MIEC material layer that are not covered by the metallic hard mask portion.
11. A method of forming a semiconductor structure comprising:
forming alternating mixed ionic electric conductor (MIEC) material layers and metal layers with a bottommost layer being a MIEC material layer on a bottom electrode and a dielectric material layer laterally surrounding the bottom electrode, wherein adjacent MIEC material layers are separated from each other by one of the metal layers;
forming a metallic hard mask portion consisting of a metal nitride directly on a topmost metal layer in the alternating MIEC material layers and metal layers; and
patterning the alternating MIEC material layers and metal layers to remove portions of the alternating MIEC material layers and metal layers that are not covered by the metallic hard mask portion, wherein peripheral portions of the bottom electrode are exposed after the patterning.
12. The method of claim 11 , wherein the patterning the metal layer and the MIEC material layer to remove the portions of the alternating MIEC material layers and metal layers that are not covered by the metallic hard mask portion are performed simultaneously utilizing an anisotropic etch.
13. The method of claim 12 , wherein the anisotropic etch comprises etching alternating MIEC material layers and metal layers with at least one etching gas comprising C, H and O or a gas mixture of NH3 and CO, a gas mixture of NH3 and CH4 or a gas mixture of NH3 and C2H4.
14. The method of claim 11 , wherein each of the MIEC material layers comprises a material represented by a formula of MaXbYc, wherein:
M is selected from the group consisting of Cu, Ag, Li and Zn,
X is selected from the group consisting of Ge, Si, Sn, C, Cr, Mo and W, and
Y is selected from the group consisting of S, Se, Te or O, and
wherein a is from 20 to 70 atomic %, b is from 4 to 30 atomic %, and c is from 30 to 60 atomic %.
15. The method of claim 11 , wherein the bottom electrode comprises TiN, TaN, W, Al, Cu, Ag, Ir, Pt, Au, Co or Ni.
16. The method of claim 11 , wherein each of the metal layers comprises Ru, Cu, Ag, Au, Ni, Fe, Pt, Pd, W, Ir or Co.
17. The method of claim 11 , further comprising:
forming a metallic hard mask layer directly on the topmost metal layer in the alternating MIEC material layers and metal layers;
forming a dielectric hard mask layer on the metallic hard mask layer;
forming an organic planarization layer (OPL) on the dielectric hard mask layer;
forming an antireflective hard mask layer on the OPL; and
forming a photoresist portion on the OPL.
18. The method of claim 17 , further comprising:
patterning the antireflective hard mask layer and the OPL using the photoresist portion as an etch mask;
patterning the dielectric hard mask layer and the metallic hard mask layer using a remaining portion of the OPL as an etch mask; and
removing a remaining portion of the dielectric hard mask layer, wherein a remaining portion of the metallic hard mask layer provides the metallic hard mask portion.
19. The method of claim 11 , further comprising removing the metallic hard mask portion after the patterning the metal layer and the MIEC material layer to remove the portions of the alternating MIEC material layers and metal layers that are not covered by the metallic hard mask portion.
20. The method of claim 11 , further comprising forming an interlevel dielectric layer laterally surrounding remaining portions of the alternating MIEC material layers and metal layers after the removing the portions of the alternating MIEC material layers and metal layers that are not covered by the metallic hard mask portion.
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