US20170358527A1 - Interposer, semiconductor package structure, and semiconductor process - Google Patents
Interposer, semiconductor package structure, and semiconductor process Download PDFInfo
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- US20170358527A1 US20170358527A1 US15/178,066 US201615178066A US2017358527A1 US 20170358527 A1 US20170358527 A1 US 20170358527A1 US 201615178066 A US201615178066 A US 201615178066A US 2017358527 A1 US2017358527 A1 US 2017358527A1
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract
An interposer includes an interconnection structure and a redistribution layer. The interconnection structure includes a metal layer, at least one metal via and an isolation material. The metal layer defines at least one through hole having a side wall. The at least one metal via is disposed in the through hole. A space is defined between the at least one metal via and the side wall of the through hole, and the isolation material fills the space. The redistribution layer is disposed on a surface of the interconnection structure and is electrically connected to the metal via.
Description
- The present disclosure relates to an interposer, a semiconductor package structure, and a semiconductor process, and more particularly to an interposer with a metal layer, a semiconductor package structure including the same, and a semiconductor process for manufacturing the same.
- A conventional semiconductor package structure includes an interposer with conductive through vias to electrically connect a high density redistribution layer (RDL) and a low density RDL. A material of the conventional interposer may be silicon or an organic material. A conventional silicon interposer has disadvantages that include high cost and complicated manufacturing. A conventional organic interposer has disadvantages that include a coefficient of thermal expansion (CTE) different from CTEs of conductive through vias and a circuit layer, thus, undesired warpage of the conventional organic interposer can occur. In addition, the distribution density of the conductive through vias of the conventional interposer is limited.
- In an aspect, an interposer includes an interconnection structure and a redistribution layer. The interconnection structure includes a metal layer, at least one metal via and an isolation material. The metal layer defines at least one through hole having a side wall. The at least one metal via is disposed in the through hole. A space is defined between the at least one metal via and the side wall of the through hole, and the isolation material fills the space. The redistribution layer is disposed on a surface of the interconnection structure and is electrically connected to the metal via.
- In an aspect, a semiconductor package structure includes an interposer and a semiconductor die disposed on and electrically connected to the interposer. The interposer includes an interconnection structure, and the interconnection structure includes a metal layer, a metal via and an isolation material. The metal layer defines a through hole having a side wall. The metal via is disposed in the through hole. The isolation material fills a space between the metal via and the side wall of the through hole.
- In an aspect, a semiconductor process includes (a) attaching a metal layer on a carrier; (b) removing a portion of the metal layer to form a through hole and at least one metal via; and (c) forming a redistribution layer on the metal layer, wherein the redistribution layer is electrically connected to the at least one metal via. The at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space.
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FIG. 1 illustrates a cross-sectional view of an interposer according to an embodiment of the present disclosure. -
FIG. 2 illustrates a top view of an interconnection structure ofFIG. 1 according to an embodiment of the present disclosure. -
FIG. 3 illustrates a top view of an interconnection structure according to an embodiment of the present disclosure. -
FIG. 4 illustrates an enlarged view of an area ‘A’ ofFIG. 1 according to an embodiment of the present disclosure. -
FIG. 5 illustrates an enlarged view of metal vias according to an embodiment of the present disclosure. -
FIG. 6 illustrates a cross-sectional view of an interposer according to an embodiment of the present disclosure. -
FIG. 7 illustrates a cross-sectional view of an interposer according to an embodiment of the present disclosure. -
FIG. 8 illustrates a cross-sectional view of an interposer according to an embodiment of the present disclosure. -
FIG. 9 illustrates a top view of an interconnection structure ofFIG. 8 according to an embodiment of the present disclosure. -
FIG. 10 illustrates a cross-sectional view of a semiconductor package structure according to an embodiment of the present disclosure. -
FIG. 11 illustrates a cross-sectional view of a semiconductor package structure according to an embodiment of the present disclosure. -
FIG. 12 illustrates a cross-sectional view of a semiconductor package structure according to an embodiment of the present disclosure. -
FIG. 13 illustrates a cross-sectional view of a semiconductor package structure according to an embodiment of the present disclosure. -
FIG. 14 ,FIG. 15 ,FIG. 16 ,FIG. 17 ,FIG. 18 andFIG. 19 illustrate a semiconductor process according to an embodiment of the present disclosure. -
FIG. 20 ,FIG. 21 ,FIG. 22 ,FIG. 23 ,FIG. 24 ,FIG. 25 andFIG. 26 illustrate a semiconductor process according to an embodiment of the present disclosure. - As noted, one kind of a conventional interposer is an organic interposer with conductive through vias and at least one circuit layer. The materials of the conductive through via and the circuit layer are metal. A mismatch of a CTE of the organic interposer body and CTEs of the conductive through via and the circuit layer may distort (warp) the organic interposer, which can affect the integrity of the organic interposer, and make handling and assembly more difficult. In addition, a structural strength of the organic interposer is relatively low, and a thickness of the organic interposer is correspondingly relatively large (e.g., greater than about 25 micrometers (μm)).
- In a conventional manufacturing process for making an organic interposer, a seed layer is formed on a base material (carrier) and an organic insulation material is formed on the seed layer. Openings are formed in the organic insulation material to expose portions of the seed layer. The openings are plated and filled with metal to form conductive through vias, and an RDL is formed on the surface of the organic insulation material. Then, the seed layer and the base material are removed. Disadvantages of such a manufacturing process include the following. First, a surface condition of a surface of the base material (carrier) will influence a surface condition of a surface of the conductive through vias and a surface of the RDL, and will further influence the formation of RDL structure and electrical connection quality. Therefore, manufacturing tolerances related to the base material (carrier) are stringent (e.g., a total thickness variation (TTV) less than 5 μm, and uniformity less than 3%), especially when manufacturing a fine pitch circuit (e.g., a line width/line space (L/S) less than 7/7 μm). Second, the use of the seed layer complicates the conventional manufacturing process and increases the manufacturing cost.
- In a conventional manufacturing process for making a conventional silicon (Si) interposer, openings are formed in the Si interposer (e.g., by laser drilling or etching) and an isolation layer is formed in each opening such that a central cavity is defined in each opening. The central cavity is plated by a conductive material to form a conductive through via. Then, an RDL is formed on the Si interposer. Disadvantages of such a manufacturing process include that it is a complicated process and the manufacturing cost is high. In addition, for fine L/S circuitry, a cost of forming the openings in the Si interposer (e.g., by laser drilling) increases.
- In the above two conventional processes for making an interposer, dimpling can occur at the end of the conductive through via during the plating stage, especially for high aspect ratio through vias (e.g., greater than 10:1), which can result in an open circuit between the through via and a connection point of a device to which the interposer is later connected. To address the dimpling, the interposer may be thinned to remove a top portion and/or a bottom portion of the interposer including the dimple. However, such thinning will increase the manufacturing cost.
- To address the above concerns, the present disclosure provides an improved interposer structure, and improved techniques for manufacturing the interposer structure, in which a main body of the interposer is metal, which reduces warpage, such as warpage that could occur during thermal treatment for forming an RDL structure. The benefits of the techniques of the present disclosure are especially pronounced for via structures having an L/S less than about 7/7 μm. Further, because the main body of the interposer is metal, which has a relatively high structural strength as compared to silicon or organic interposers, the interposer can be relatively thin as compared to silicon or organic interposers. In addition, conductive through vias are formed by etching the main body rather than by plating, thus, manufacturing is simplified and manufacturing cost is relatively low. The use of etching also provides for improved manufacturing tolerances related to the main body (e.g., TTV and uniformity) as compared to the use of plating, further reducing manufacturing complexity and cost.
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FIG. 1 illustrates a cross-sectional view of aninterposer 1 according to an embodiment of the present disclosure. Theinterposer 1 has afirst surface 11 and asecond surface 12 opposite thefirst surface 11. Theinterposer 1 includes aninterconnection structure 2, at least one redistribution layer (RDL) (e.g., afirst RDL 3 and a second RDL 4) and at least oneexternal connection element 14. - The
interconnection structure 2 has afirst surface 201 and asecond surface 202 opposite thefirst surface 201. Theinterconnection structure 2 includes a metal layer 20 (the interposer body), at least one metal via 22 (e.g., a first metal via 221 and a second metal via 222) and anisolation material 24. A first surface of themetal layer 20 is along (is a portion of) thefirst surface 201 of theinterconnection structure 2, and a second surface of themetal layer 20 is along (is a portion of) thesecond surface 202 of theinterconnection structure 2. Themetal layer 20 defines at least one through hole 21 (e.g., a first throughhole 21 a and a second throughhole 21 b). The material of themetal layer 20 is copper, another metal or metal alloy, or other conductive material. The first throughhole 21 a has aside wall 211 a, and the second throughhole 21 b has aside wall 211 b. The through holes 21 (e.g., the first throughhole 21 a and the second throughhole 21 b) extend through themetal layer 20, that is, extend from thefirst surface 201 to thesecond surface 202. - The metal vias 22 are disposed in respective through
holes 21. A space 23 (e.g., afirst space 23 a and asecond space 23 b) is present between each metal via 22 and acorresponding side wall hole 21. That is, the first metal via 221 is disposed in the first throughhole 21 a, and thefirst space 23 a is between the first metal via 221 and theside wall 211 a of the first throughhole 21 a. Similarly, the second metal via 222 is disposed in the second throughhole 21 b, and thesecond space 23 b is between the second metal via 222 and theside wall 211 b of the second throughhole 21 b. - As noted, the first surface of the
metal layer 20 is along (is a portion of) thefirst surface 201 of theinterconnection structure 2. Afirst surface 2211 of the first metal via 221 and afirst surface 2221 of the second metal via 222 are also along (are portions of) thefirst surface 201 of theinterconnection structure 2. As noted, the second surface of themetal layer 20 is along (is a portion of) thesecond surface 202 of theinterconnection structure 2. Asecond surface 2212 of the first metal via 221 and asecond surface 2222 of the second metal via 222 are also along (are portions of) thesecond surface 202 of theinterconnection structure 2. In some embodiments, thefirst surfaces first surface 201 of the interconnection structure 2 (and the metal layer 20), and thesecond surfaces second surface 202 of the interconnection structure 2 (and the metal layer 20) - In one or more embodiments, the metal vias 22 (e.g., the first metal via 221 and the second metal via 222) are formed by etching the
metal layer 20; thus, themetal layer 20 and themetal vias 22 are, or include, a same material. In such embodiments, thefirst surfaces metal vias 22 are substantially coplanar with thefirst surface 201 of theinterconnection structure 2, and thesecond surfaces metal vias 22 are substantially coplanar with thesecond surface 202 of theinterconnection structure 2. In one or more embodiments, both themetal layer 20 and themetal vias 22 are copper. - The
isolation material 24 fills the spaces 23 (e.g., thefirst space 23 a and thesecond space 23 b) to prevent the metal vias 22 from being electrically connected to themetal layer 20. Examples of materials that may be used for theisolation material 24 include a solder mask, a material that is photo-sensitive when applied, a polyimide, another polymer, or other material or combination of materials. Afirst surface 241 of theisolation material 24 is substantially coplanar with thefirst surface 201 of the interconnection structure 2 (and the metal layer 20), and asecond surface 242 of theisolation material 24 is substantially coplanar with thesecond surface 202 of the interconnection structure 2 (and the metal layer 20). - The
first RDL 3 is disposed on thefirst surface 201 of theinterconnection structure 2, and thesecond RDL 4 is disposed on thesecond surface 202 of theinterconnection structure 2. Thefirst RDL 3 is electrically connected to thesecond RDL 4 by way of themetal vias 22. In the embodiment illustrated inFIG. 1 , thefirst RDL 3 is a relatively high density redistribution layer, and thesecond RDL 4 is a relatively low density redistribution layer. That is, a number of input or output connections (I/O counts) provided by thefirst RDL 3 can be greater than the I/O counts provided by thesecond RDL 4. For example, thefirst RDL 3 can have I/O counts in the several hundreds of thousands, whereas thesecond RDL 4 may have a same or fewer I/O counts, such as I/O counts in the several tens of thousands. In other words, a ratio of I/O counts for thefirst RDL 3 to I/O counts for thesecond RDL 4 may be equal to or greater than one, such as greater than about five, greater than about ten, greater than about twenty, or greater than about fifty. - In one or more embodiments, the
first RDL 3 and thesecond RDL 4 may be electrically connected to themetal layer 20, such as, for example, to provide a grounding path. - In one or more embodiments, the
second RDL 4 can be omitted, and thesecond surfaces 2212/2222 of themetal vias 221/222 may be used as external terminals. - In the embodiment illustrated in
FIG. 1 , thefirst RDL 3 includes one or more insulation layers (e.g., afirst insulation layer 31 and a second insulation layer 32), one or more circuit layers 33 (e.g., circuit layers 33 a, 33 b), one or more interconnection vias 34 (e.g., interconnection vias 34 a, 34 b) and one or morefirst pads 35. Thefirst insulation layer 31 is disposed on thefirst surface 201 of theinterconnection structure 2, and thesecond insulation layer 32 is disposed on thefirst insulation layer 31. A material of thesecond insulation layer 32 may be the same as or different from a material of thefirst insulation layer 31. Examples of materials that may be used for thefirst insulation layer 31 or thesecond insulation layer 32 include a solder mask, a material that is photosensitive when applied, a polyimide, another polymer, or other material or combination of materials. - In one or more embodiments, the material of the
first insulation layer 31 is the same as the material of theisolation material 24, and both are formed concurrently. That is, thefirst insulation layer 31 extends into the spaces 23 (e.g., thefirst space 23 a and thesecond space 23 b) to form theisolation material 24 of theinterconnection structure 2. - In the embodiment of
FIG. 1 , twocircuit layers 33 are shown: thecircuit layer 33 a disposed on a surface of thesecond insulation layer 32, and thecircuit layer 33 b disposed on a surface of thefirst insulation layer 31 and embedded at a surface of thesecond insulation layer 32. In other embodiments, one of the twocircuit layers 33 may be omitted, or additional circuit layers 33 may be added (with corresponding additional insulation layers). - In one or more embodiments, a line width/line space (L/S) of the
circuit layer 33 a is less than about 7 μm/about 7 μm, for example, about 5 μm/about 5 μm or about 2 μm/about 2 μm. In one or more embodiments, the L/S ofcircuit layer 33 b is also less than about 7 μm/about 7 μm. In embodiments in which thefirst RDL 3 includes additional circuit layers 33, anuppermost circuit layer 33 in the orientation shown (e.g., the farthest away from thefirst insulation layer 31, which may be exposed at thefirst surface 11 of the interposer 1) has an L/S less than about 7 μm/about 7 μm, for example, about 5 μm/about 5 μm or about 2 μm/about 2 μm; and others of the circuit layers 33 may have similar L/S values. - In the embodiment illustrated in
FIG. 1 , two groups ofinterconnection vias 34 are shown: a group of interconnection vias 34 a extending between thecircuit layer 33 a and thecircuit layer 33 b, and a group ofinterconnection vias 34 b extending between thecircuit layer 33 b and the metal vias 22 (e.g., the first metal via 221 and the second metal via 222). For embodiments with additional circuit layers 33 (and corresponding additional insulation layers), additional groups ofinterconnection vias 34 may be included for connection between the circuit layers 33 (through the additional insulation layers). - The
first pads 35 are included in theuppermost circuit layer 33 that is exposed at thefirst surface 11 of the interposer 1 (e.g., thecircuit layer 33 a in the illustration ofFIG. 1 ). Thefirst pads 35 provided input and output connections, and the number offirst pads 35 is the available I/O count for thefirst RDL 3 of theinterposer 1. - In the embodiment illustrated in
FIG. 1 , thesecond RDL 4 includes one or more insulation layers (e.g., afirst insulation layer 41 and a second insulation layer 42), one or more circuit layers 43, one or more interconnection vias 44 (e.g., interconnection vias 44 a, 44 b) and one or moresecond pads 45. Thefirst insulation layer 41 is disposed on thesecond surface 202 of theinterconnection structure 2, and thesecond insulation layer 42 is disposed on thefirst insulation layer 41. A material of thesecond insulation layer 42 may be the same as or different from a material of thefirst insulation layer 41. Examples of materials that may be used for thefirst insulation layer 41 or thesecond insulation layer 42 include a solder mask, a material that is photosensitive when applied, a polyimide, another polymer, or other material or combination of materials. - In one or more embodiments, the material of the
first insulation layer 41 is same as a material of theisolation material 24, and both are formed concurrently. That is, thefirst insulation layer 41 extends into the spaces 23 (e.g., thefirst space 23 a and thesecond space 23 b) to form theisolation material 24 of theinterconnection structure 2. - In the embodiment of
FIG. 1 , there is onecircuit layer 43 disposed on a surface of thefirst insulation layer 41 and embedded at a surface of thesecond insulation layer 42. In one or more embodiments, thesecond RDL 4 may include additional circuit layers 43 (and may further include additional insulation layers). In one or more embodiments, an L/S of the circuit layer 43 (or any one or more of additional circuit layers if applicable) is less than about 7 μm/about 7 for example, about 5 μm/about 5 μm or about 2 μm/about 2 μm. - In the embodiment illustrated in
FIG. 1 , two groups ofinterconnection vias 44 are shown: a group of interconnection vias 44 a extending between thecircuit layer 43 and thesecond pads 45, and a group ofinterconnection vias 44 b extending between thecircuit layer 43 and the metal vias 22 (e.g., the first metal via 221 and the second metal via 222). For embodiments with additional circuit layers 43 (and possibly additional insulation layers), additional groups ofinterconnection vias 44 may be included for connection between the circuit layers 43 (e.g., through the additional insulation layers). - The
second pads 45 are embedded in thesecond insulation layer 42 and are exposed by thesecond surface 12 of theinterposer 1. Thesecond pads 45 provided input and output connections, and the number ofsecond pads 45 is the available I/O count for thesecond RDL 4 of theinterposer 1. - A surface finish layer 46 (e.g., an electroless nickel immersion gold (ENIG)) is optionally plated on the
second pads 45. Theexternal connection elements 14, such as solder balls or bumps, are disposed on thesecond pads 45 or on thesurface finish layer 46. - In the embodiment illustrated in
FIG. 1 , the main body (the metal layer 20) of theinterposer 1 is metal, which reduces occurrences of warpage during thermal treatment for forming the RDL structures (e.g., thefirst RDL 3 and the second RDL 4), which is especially pronounced when the L/S of the circuit layers 33, 43 is each less than about 7/about 7 μm. Further, because the main body of theinterposer 1 is metal, which has a relatively high structural strength, a thickness of theinterposer 1 can be reduced. In addition, the metal vias 22 (e.g., the first metal via 221 and the second metal via 222) can be formed by etching the main body (the metal layer 20) rather than plating, so that the manufacturing complexity and cost can be reduced. In addition, before being etched, thefirst surface 201 and thesecond surface 202 of themetal layer 20 have excellent uniformity (e.g., uniformity less than about 3% and TTV less than about 5 μm), and etching will not influence such uniformity. Accordingly, after being etched, thefirst surface 201 and thesecond surface 202 of themetal layer 20, and thefirst surfaces second surfaces metal vias 22 retain the excellent uniformity (e.g., uniformity less than about 3% and TTV less than about 5 μm). That is, after etching, thefirst surfaces metal vias 22 are substantially coplanar with thefirst surface 201 of themetal layer 20, and thesecond surfaces metal vias 22 are substantially coplanar with thesecond surface 202 of themetal layer 20. Therefore, thefirst RDL 3 and thesecond RDL 4 are formed on even or smooth surfaces (thefirst surface 201 and thesecond surface 202, respectively), which results in high yield. In comparison, conductive through vias formed by plating result in poor uniformity (e.g., uniformity greater than 10%) on the surfaces thereof, so that yield is low when forming the RDL structure on uneven conductive through vias surfaces. -
FIG. 2 illustrates a top view of theinterconnection structure 2 ofFIG. 1 viewed at thefirst surface 201 according to an embodiment of the present disclosure. A shape of theinterconnection structure 2 inFIG. 2 is rectangular from the top view. The through holes 21 (e.g., the first throughhole 21 a and the second throughhole 21 b) of themetal layer 20 may be rectangular, square, circular, elliptical or other shape from the top view, and the metal vias 22 (e.g., the first metal via 221 and the second metal via 222) may be rectangular, square, circular, elliptical or other shape from the top view. As illustrated inFIG. 2 , the shapes of theindividual metal vias 22 may match the shapes of the corresponding throughholes 21, and inFIG. 2 , both are circular. In other embodiments, the shapes of the individual metal vias 22 do not necessarily match the shapes of the corresponding through holes 21. - A single metal via 22 is disposed in a corresponding through
hole 21, thus, each space 23 (e.g., thefirst space 23 a and thesecond space 23 b) surrounds a metal via 22. In the embodiment ofFIG. 2 , thefirst space 23 a is ring-shaped, surrounds the first metal via 221 and is filled with theisolation material 24 to prevent the first metal via 221 from contacting or electrically connecting to theside wall 211 a of the first throughhole 21 a. In the embodiment ofFIG. 2 , thesecond space 23 b is ring-shaped, surrounds the second metal via 222 and is filled with theisolation material 24 to prevent the second metal via 222 from contacting or electrically connecting to theside wall 211 b of the second throughhole 21 b. -
FIG. 3 illustrates a top view of aninterconnection structure 2 a according to an embodiment of the present disclosure. Theinterconnection structure 2 a ofFIG. 3 is similar to theinterconnection structure 2 inFIG. 2 , except that, instead of the rectangular shape of theinterconnection structure 2 inFIG. 2 , the shape of theinterconnection structure 2 a is elliptical from the top view. It should be understood that “rectangular” is inclusive of square and “elliptical” is inclusive of circular, and that shapes other than rectangular or elliptical are encompassed by the present disclosure. -
FIG. 4 illustrates an enlarged view of an area ‘A’ ofFIG. 1 according to an embodiment of the present disclosure. When the metal vias 22 (e.g., the first metal via 221 and the second metal via 222) are formed by etching, themetal vias 22 curve inward to the respectivefirst surfaces 2211/2221 and curve outward to the respectivesecond surfaces 2212/2222 as shown. The profile of the metal vias 22 ofFIG. 4 is formed by under-etching. It is noted that the cross section of the portion of themetal layer 20 between twometal vias 22 will have a similar profile to themetal vias 22. -
FIG. 5 illustrates an enlarged view ofmetal vias 22 according to an embodiment of the present disclosure. The metal vias 22 ofFIG. 5 are similar to themetal vias 22 as shown inFIG. 4 , except that themetal vias 22 curve inward (rather than outward) to the respectivesecond surfaces 2212/2222 as shown. The profile of the metal vias 22 ofFIG. 5 is formed by over-etching. -
FIG. 6 illustrates a cross-sectional view of an interposer 1 a according to an embodiment of the present disclosure. The interposer 1 a ofFIG. 6 is similar to theinterposer 1 inFIG. 1 , except that thefirst insulation layer 31 extends into and fills the space 23 (e.g., thefirst space 23 a and thesecond space 23 b) to form theisolation material 24 between themetal vias 22 and theside walls first insulation layer 31 is same as the material of theisolation material 24, and both are formed concurrently. -
FIG. 7 illustrates a cross-sectional view of aninterposer 1 b according to an embodiment of the present disclosure. Theinterposer 1 b ofFIG. 7 is similar to theinterposer 1 inFIG. 1 , except for the profile of the metal vias 22 (e.g., the first metal via 221 and the second metal via 222). Because themetal vias 22 are formed by etching, each of themetal vias 22 tapers. That is, a dimension (e.g., diameter or width) of each metal via 22 at thefirst surface second surface -
FIG. 8 illustrates a cross-sectional view of aninterposer 1 c according to an embodiment of the present disclosure. Theinterposer 1 c ofFIG. 8 is similar to theinterposer 1 inFIG. 1 , except for a structure of theinterconnection structure 2 b. In theinterconnection structure 2 b,multiple metal vias 22 are disposed in a single throughhole 21, and themetal vias 22 are spaced apart from each other. InFIG. 8 , the first metal via 221 and the second metal via 222 are disposed in the throughhole 21, and a portion of theisolation material 24 is between the first metal via 221 and the second metal via 222. That is, there is no portion of themetal layer 20 between the first metal via 221 and the second metal via 222. -
FIG. 9 illustrates a top view of theinterconnection structure 2 b ofFIG. 8 according to an embodiment of the present disclosure. As shown inFIG. 9 , the first metal via 221 and the second metal via 222 are both disposed within the throughhole 21. Before theisolation material 24 is applied, there isempty space 23 between the first metal via 221 and the second metal via 222. After theisolation material 24 is applied, there is theisolation material 24 between the first metal via 221 and the second metal via 222. A pitch between the first metal via 221 and the second metal via 222 inFIG. 8 andFIG. 9 is less than a pitch between the first metal via 221 and the second metal via 222 inFIG. 1 andFIG. 2 . It is to be understood that there may be more than twometal vias 22 disposed within a single throughhole 21. -
FIG. 10 illustrates a cross-sectional view of asemiconductor package structure 5 according to an embodiment of the present disclosure. Thesemiconductor package structure 5 includes aninterposer 1, at least one semiconductor die 52, anunderfill 53 and anencapsulant 54. Theinterposer 1 of the embodiment illustrated inFIG. 10 is theinterposer 1 ofFIG. 1 . The semiconductor die 52 is disposed on and electrically connected to thefirst RDL 3 of theinterposer 1. In the embodiment illustrated inFIG. 10 , the semiconductor die 52 includesconnection elements 521 disposed on and electrically connected to thefirst pads 35 included in the uppermost circuit layer 33 (e.g., thecircuit layer 33 a) that is disposed at thefirst surface 11 of theinterposer 1. Theconnection elements 521 may be solder balls, bumps or pillars. In other embodiments, the semiconductor die 52 may be electrically connected to thefirst RDL 3 by wire bonding. Theunderfill 53 surrounds theconnection elements 521 and fills under the semiconductor die 52. The encapsulant 54 (e.g., a molding compound) covers the semiconductor die 52, theunderfill 53 and thefirst surface 11 of theinterposer 1. It is noted that theunderfill 53 may be omitted, and theencapsulant 54 may further surround theconnection elements 521 and fill under the semiconductor die 52. In addition, theinterposer 1 of the embodiment illustrated inFIG. 10 may be replaced by the interposer 1 a ofFIG. 6 , theinterposer 1 b ofFIG. 7 or theinterposer 1 c ofFIG. 8 . -
FIG. 11 illustrates a cross-sectional view of asemiconductor package structure 5 a according to an embodiment of the present disclosure. Thesemiconductor package structure 5 a ofFIG. 11 is similar to thesemiconductor package structure 5 as shown inFIG. 10 , except that theencapsulant 54 and thesecond RDL 4 are omitted, and thesemiconductor package structure 5 a includes aprotection layer 55 and external connection elements 56 (e.g., solder balls or bumps). Theprotection layer 55 may include, for example, a solder mask or a passivation layer. Theprotection layer 55 is disposed on thesecond surface 202 of theinterconnection structure 2, and definesopenings 551 exposing thesecond surfaces external connection elements 56 are disposed in theopenings 551 to contact thesecond surfaces metal vias 22 for external connection. -
FIG. 12 illustrates a cross-sectional view of asemiconductor package structure 6 according to an embodiment of the present disclosure. Thesemiconductor package structure 6 ofFIG. 12 is similar to thesemiconductor package structure 5 inFIG. 10 , except that thesemiconductor package structure 6 inFIG. 12 is mounted to asubstrate 80 or a printed circuit board (PCB) by surface mounting technology (SMT). Thesubstrate 80 may be a core substrate or a coreless substrate, and includes acircuit layer 81. The L/S of thecircuit layer 81 is greater than 7 μm/7 μm. Theexternal connection element 14 contacts thecircuit layer 81. -
FIG. 13 illustrates a cross-sectional view of a semiconductor package structure 6 a according to an embodiment of the present disclosure. The semiconductor package structure 6 a ofFIG. 13 is similar to thesemiconductor package structure 6 as shown inFIG. 12 , except that theencapsulant 54 further covers side surfaces of theinterposer 1, and further fills a space between theinterposer 1 and thesubstrate 80 to protect theexternal connection element 14. -
FIGS. 14-19 illustrate a semiconductor process according to an embodiment of the present disclosure. Referring toFIG. 14 , ametal layer 20 is attached on acarrier 60. Thecarrier 60 has afirst surface 601 and asecond surface 602. The thickness of thecarrier 60 may be about 1 mm. The material of thecarrier 60 may be, for example, silicon, glass, metal (e.g., copper or stainless steel), a laminate structure (e.g., FR4) or a resin (e.g., bismaleimide-triazine (BT)). Themetal layer 20 is adhered to thefirst surface 601 of thecarrier 60 by afirst adhesion material 63. The thickness of themetal layer 20 may be about 3 μm to about 100 μm. A first surface (at afirst surface 201 of what will become an interconnection structure 2) and a second surface (at asecond surface 202 of what will become the interconnection structure 2) of themetal layer 20 have excellent uniformity (e.g., uniformity less than about 3% and TTV less than about 5 μm), which is an advantage for the formation of an RDL structure described below. - In addition, a reinforced
layer 66 is attached (adhered) to thesecond surface 602 of thecarrier 60 by asecond adhesion material 64. The reinforcedlayer 66 can balance a thermal expansion of themetal layer 20 during manufacturing, to avoid warpage of thecarrier 60. In one or more embodiments, a material of the reinforcedlayer 66 is same as a material of themetal layer 20. In one or more embodiments, both the reinforcedlayer 66 and themetal layer 20 are copper. In one or more embodiments, a thickness of the reinforcedlayer 66 is same as a thickness of themetal layer 20. In one or more embodiments, both the reinforcedlayer 66 and themetal layer 20 are copper, and the thickness of the reinforcedlayer 66 is same as the thickness of themetal layer 20. - In one or more embodiments, the material of the reinforced
layer 66 is a non-metal, such as an organic or ceramic material, which is different from the material of themetal layer 20, and the thickness of the reinforcedlayer 66 is different from the thickness of themetal layer 20. It is noted that, depending on rigidity of thecarrier 60, the reinforcedlayer 66 may be omitted. - Referring to
FIG. 15 , aphotoresist layer 70 is applied on themetal layer 20 at thefirst surface 201. Openings 71 (e.g., afirst opening 71 a and asecond opening 71 b) are formed in thephotoresist layer 70 to expose portions of themetal layer 20. Each of the openings 71 (e.g., thefirst opening 71 a and thesecond opening 71 b) is in a ring shape. Portions of themetal layer 20 exposed by theopenings 71 are etched from thefirst surface 201 to form through holes 21 (e.g., a first throughhole 21 a and a second throughhole 21 b) in a ring shape, leaving metal vias 22 (e.g., a first metal via 221 and a second metal via 222), such that each metal via 22 is disposed in a corresponding throughhole 21, and there is a space 23 (e.g., afirst space 23 a and asecond space 23 b) between the metal via 22 and a side wall (e.g., 211 a or 211 b) of the throughhole 21. That is, the first metal via 221 is disposed in the first throughhole 21 a, and thefirst space 23 a is between the first metal via 221 and theside wall 211 a of the first throughhole 21 a; and the second metal via 222 is disposed in the second throughhole 21 b, and thesecond space 23 b is between the second metal via 222 and theside wall 211 b of the second throughhole 21 b. - Because the metal vias 22 (e.g., the first metal via 221 and the second metal via 222) are formed by etching the
metal layer 20, themetal layer 20 and themetal vias 22 are a same material; in some embodiments they are both copper. Without any further treatment,first surfaces metal layer 20 at thefirst surface 201, andsecond surfaces metal layer 20 at thesecond surface 202. It is noted that since themetal vias 22 are formed by etching rather than plating, a surface condition of thefirst surface 601 of thecarrier 60 will not influence a surface condition of thefirst surfaces metal vias 22 and the surface of themetal layer 20 at thefirst surface 201. In addition, after the etching process, the surface of themetal vias 22 along thefirst surface 201, thefirst surfaces metal vias 22, thesecond surfaces metal vias 22 and the surface of themetal layer 20 at thesecond surface 202 retain excellent uniformity (e.g., uniformity less than about 3% and TTV less than about 5 μm). - Referring to
FIG. 16 , anisolation material 24 is filled in the spaces 23 (e.g., thefirst space 23 a and thesecond space 23 b) to form theinterconnection structure 2 having thefirst surface 201 and thesecond surface 202. Afirst surface 241 of theisolation material 24 is substantially coplanar with the surface of themetal layer 20 at thefirst surface 201, and asecond surface 242 of theisolation material 24 is substantially coplanar with the surface of themetal layer 20 at thesecond surface 202. Afirst RDL 3 is formed on thefirst surface 201 of the interconnection structure 2 (which includes thefirst surface 241 of the isolation material 24 a and a surface of the metal layer 20). Thefirst RDL 3 is electrically connected to themetal vias 22. In one or more embodiments, thefirst RDL 3 is further electrically connected to themetal layer 20, such as for grounding. Theinterconnection structure 2 and thefirst RDL 3 form theinterposer 1 ofFIG. 1 . Thefirst RDL 3 is formed on an even surface (thefirst surface 201 including the surface of themetal layer 20 and thefirst surface 241 of the isolation material 24), thus peeling of thefirst RDL 3 will not easily occur, and high yield may be obtained. Further, most of theinterconnection structure 2 is metal with a relative low CTE, which can prevent warpage of theinterposer 1. - It is noted that the first insulation layer 31 (the bottom-most insulation layer of the first RDL 3) may extend into and fill the space 23 (e.g., the
first space 23 a and thesecond space 23 b) to form theisolation material 24 between themetal vias 22 and theside walls first insulation layer 31 is the same as a material of theisolation material 24, and both are formed concurrently, to obtain the interposer 1 a ofFIG. 6 . - Referring to
FIG. 17 , at least one semiconductor die 52 is disposed on and electrically connected to thefirst RDL 3 of theinterposer 1. In the embodiment illustrated inFIG. 17 , the semiconductor die 52 includesconnection elements 521 disposed on and electrically connected to thefirst pads 35 included in the uppermost circuit layer 33 (e.g., thecircuit layer 33 a) that is disposed at thefirst surface 11 of theinterposer 1. Theconnection elements 521 may be, for example, solder balls, bumps or pillars. In other embodiments, the semiconductor die 52 may be electrically connected to thefirst RDL 3 by wire bonding. Anunderfill 53 is applied to surround theconnection elements 521 and fill under the semiconductor die 52. Then, an encapsulant 54 (e.g., a molding compound) is formed on thefirst RDL 3 to cover the semiconductor die 52, theunderfill 53 and thefirst surface 11 of theinterposer 1. It is noted that theunderfill 53 may be omitted, and theencapsulant 54 may further surround theconnection elements 521 and fill under the semiconductor die 52. - Referring to
FIG. 18 , thecarrier 60, thefirst adhesion material 63, the reinforcedlayer 66 and thesecond adhesion material 64 are separated from thesecond surface 202 of theinterconnection structure 2. In one or more embodiments, a protection layer and external connection elements (e.g., aprotection layer 55 andexternal connection elements 56 as shown inFIG. 11 ) may be formed on thesecond surface 202 of theinterconnection structure 2. - Referring to
FIG. 19 , asecond RDL 4 is formed on thesecond surface 202 of theinterconnection structure 2. Thesecond RDL 4 is electrically connected to themetal vias 22. Thefirst RDL 3 may be electrically connected to thesecond RDL 4 through themetal vias 22. In one or more embodiments, thesecond RDL 4 may be further electrically connected to themetal layer 20, such as for grounding. Asurface finish layer 46 is optionally disposed (e.g., plated) onsecond pads 45 of thesecond RDL 4. - Connection elements 14 (e.g., solder balls or bumps) may be disposed (not shown in
FIG. 19 ) on thesurface finish layer 46 or on respective ones of thesecond pads 45, to obtain thesemiconductor package structure 5 shown inFIG. 10 . Thesemiconductor package structure 5 may be mounted (not shown inFIG. 19 ) to asubstrate 80 or a printed circuit board (PCB) by surface mounting technology (SMT), to obtain thesemiconductor package structure 6 shown inFIG. 12 . -
FIGS. 20-26 illustrate a semiconductor process according to an embodiment of the present disclosure. Referring toFIG. 20 , ametal layer 20 is adhered to asecond surface 602 of acarrier 60 by asecond adhesion material 64, and a reinforcedlayer 66 is adhered to afirst surface 601 of thecarrier 60 by afirst adhesion material 63. A surface of themetal layer 20 lies along what will become afirst surface 201 of aninterconnection structure 2, and another surface of themetal layer 20 lies along what will become asecond surface 202 of theinterconnection structure 2. - Referring to
FIG. 21 , aphotoresist layer 70 is applied on themetal layer 20 at thesecond surface 202. Openings 71 (e.g., afirst opening 71 a and asecond opening 71 b) are formed in thephotoresist layer 70 to expose portions of themetal layer 20 at thesecond surface 202. Each of the openings 71 (e.g., thefirst opening 71 a and thesecond opening 71 b) is in a ring shape. Then, the portions of themetal layer 20 exposed at thesecond surface 202 by theopenings 71 are etched from themetal layer 20, so as to form through holes 21 (e.g., a first throughhole 21 a and a second throughhole 21 b) and leave metal vias 22 (e.g., a first metal via 221 and a second metal via 222). The metal vias 22 are thus disposed in respective throughholes 21, and a space 23 (e.g., afirst space 23 a and asecond space 23 b) is between themetal vias 22 andside walls hole 21 a, and thefirst space 23 a is between the first metal via 221 and theside wall 211 a of the first throughhole 21 a; and the second metal via 222 is disposed in the second throughhole 21 b, and thesecond space 23 b is between the second metal via 222 and theside wall 211 b of the second throughhole 21 b. The first metal via 221 has afirst surface 2211 and asecond surface 2212. The second metal via 222 has afirst surface 2221 andsecond surface 2222. - Referring to
FIG. 22 , anisolation material 24 is filled in the spaces 23 (e.g., thefirst space 23 a and thesecond space 23 b) to form theinterconnection structure 2 having thefirst surface 201 and thesecond surface 202. Afirst surface 241 of theisolation material 24 is substantially coplanar with the surface of themetal layer 20 at thefirst surface 201 of theinterconnection structure 2, and asecond surface 242 of theisolation material 24 is substantially coplanar with the surface of themetal layer 20 at thesecond surface 202 of theinterconnection structure 2. Asecond RDL 4 is formed on thesecond surface 202 of theinterconnection structure 2. Theinterconnection structure 2 and thesecond RDL 4 form aninterposer 1. Asurface finish layer 46 is optionally disposed (e.g., plated) onpads 45 of thesecond RDL 4. At least one external connection element 14 (e.g., solder balls or bumps) is formed on thesurface finish layer 46 or on thesecond pads 45. - It is noted that a
separate isolation material 24 may be omitted, and instead a first insulation layer 41 (e.g., an insulation layer of thesecond RDL 4 closest to the interconnection structure 2) may extend into and fill the spaces 23 (e.g., thefirst space 23 a and thesecond space 23 b) to form theisolation material 24 between themetal vias 22 and theside walls first insulation layer 41 is the same as a material of theisolation material 24, and thefirst insulation layer 41 and theisolation material 24 are formed concurrently. - Referring to
FIG. 23 , a supportingstructure 60 a is attached to thesecond RDL 4. Asecond surface 12 of the interposer 1 (e.g., a surface of asecond insulation layer 42 of the RDL 4) is adhered to afirst surface 601 a of the supportingstructure 60 a by afirst adhesion material 63 a, and a second reinforcedlayer 66 a is adhered to asecond surface 602 a of the supportingstructure 60 a by asecond adhesion material 64 a. The supportingstructure 60 a covers theexternal connection element 14 and supports theinterconnection structure 2. The supportingstructure 60 a and the second reinforcedlayer 66 a may be similar to thecarrier 60 and the reinforcedlayer 66 ofFIG. 22 , respectively. Then, thecarrier 60, thefirst adhesion material 63, the reinforcedlayer 66 and thesecond adhesion material 64 are separated from theinterconnection structure 2. - Referring to
FIG. 24 , afirst RDL 3 is formed on thefirst surface 201 of theinterconnection structure 2. Thefirst RDL 3 is electrically connected to themetal vias 22. In one or more embodiments, thefirst RDL 3 may be further electrically connected to themetal layer 20, such as for grounding. - Referring to
FIG. 25 , asemiconductor die 52 is disposed on and electrically connected to thefirst RDL 3. The semiconductor die 52 includes connection elements 521 (e.g., solder balls, bumps or pillars) disposed on and electrically connected tofirst pads 35 included in an uppermost circuit layer 33 (e.g., thecircuit layer 33 a) of theRDL 3. In other embodiments, the semiconductor die 52 may be electrically connected to thefirst RDL 3 by wire bonding. Anunderfill 53 is applied to surround theconnection elements 521 and to fill under the semiconductor die 52. Then, an encapsulant 54 (e.g., a molding compound) is formed on thefirst RDL 3 to cover the semiconductor die 52, theunderfill 53 and thefirst surface 11 of theinterposer 1. In one or more embodiments, theunderfill 53 is omitted, and theencapsulant 54 further surrounds theconnection elements 521 and fills under the semiconductor die 52. - Referring to
FIG. 26 , the supportingstructure 60 a, thefirst adhesion material 63 a, the second reinforcedlayer 66 a and thesecond adhesion material 64 a are separated from thesecond RDL 4 to form thesemiconductor package structure 5 ofFIG. 10 . - The
semiconductor package structure 5 may be mounted to a substrate or a printed circuit board (PCB) by surface mounting technology (SMT) to obtain thesemiconductor package structure 6 shown inFIG. 12 . - Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated by such arrangement.
- As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.
- Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than about 5 μm, no greater than about 2 μm, no greater than about 1 μm, or no greater than about 0.5 μm.
- Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
- While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
Claims (21)
1. An interposer, comprising:
an interconnection structure comprising:
a metal layer defining at least one through hole having a side wall;
at least one metal via disposed in the through hole, and a space defined between the at least one metal via and the side wall of the through hole; and
an isolation material filling the space; and
a redistribution layer disposed on a surface of the interconnection structure and electrically connected to the metal via, wherein the redistribution layer is electrically connected to the metal layer.
2. The interposer of claim 1 , wherein a material of the metal layer is the same as a material of the metal via.
3. The interposer of claim 1 , wherein the metal via tapers.
4. The interposer of claim 1 , wherein the at least one metal via disposed in the through hole is a single metal via disposed in the through hole, and the space has a ring shape from a top view and surrounds the metal via.
5. The interposer of claim 1 , wherein the at least one metal via disposed in the through hole is a plurality of metal vias disposed in the through hole, and the metal vias are spaced apart from each other.
6. The interposer of claim 1 , wherein the at least one metal via is formed by etching the metal layer.
7. The interposer of claim 1 , wherein the metal via curves inward towards a first surface of the metal via and curves inward or outward towards a second surface of the metal via, the second surface opposite the first surface.
8. (canceled)
9. The interposer of claim 1 , wherein the redistribution layer comprises one or more insulation layers, one or more circuit layers and one or more interconnection elements, and wherein a first insulation layer closest to the interconnection structure extends into the space and includes the isolation material.
10. The interposer of claim 1 , wherein the surface of the interconnection structure is a first surface and the interconnection structure has a second surface opposite the first surface, and the redistribution layer is a first redistribution layer on the first surface of the interconnection structure, further comprising a second redistribution layer on the second surface of the interconnection structure, the first redistribution layer being electrically connected to the second redistribution layer through the at least one metal via.
11. A semiconductor package structure, comprising:
an interposer comprising:
an interconnection structure comprising:
a metal layer defining a through hole having a side wall;
a metal via disposed in the through hole; and
an isolation material filling a space between the metal via and the side wall of the through hole;
a redistribution layer electrically connected to the metal layer; and
a semiconductor die disposed on and electrically connected to the interposer.
12. The semiconductor package structure of claim 11 , wherein the redistribution layer is disposed on a surface of the interconnection structure and is electrically connected to the metal via, and the semiconductor die is disposed on and electrically connected to the redistribution layer.
13. The semiconductor package structure of claim 11 , further comprising an encapsulant covering the semiconductor die.
14-20. (canceled)
21. The interposer of claim 1 , wherein the at least one metal via disposed in the through hole is a plurality of metal vias disposed in the through hole, and no portion of the metal layer is disposed between the metal vias of the plurality of metal vias.
22. The interposer of claim 1 , wherein the at least one metal via disposed in the through hole is a plurality of metal vias disposed in the through hole, and the metal vias are each surrounded by the isolation material.
23. The semiconductor package structure of claim 13 , wherein the encapsulant covers a side surface of the interposer.
24. An interposer, comprising:
a metal layer defining at least one through hole having a side wall, the metal layer having a first surface and a second surface opposite the first surface;
at least one metal via disposed in the through hole, and a space defined between the metal via and the side wall of the through hole;
an isolation material filling the space; and
a redistribution layer disposed on the first surface of the metal layer and electrically connected to the metal via, wherein:
the redistribution layer is electrically connected to the metal layer, and
the metal via has a first surface substantially coplanar with the first surface of the metal layer, and the metal via has a second surface substantially coplanar with the second surface of the metal layer.
25. The interposer of claim 24 , wherein a material of the metal layer is the same as a material of the metal via.
26. The interposer of claim 24 , wherein the at least one metal via disposed in the through hole is a plurality of metal vias disposed in the through hole, and the metal vias are each surrounded by the isolation material.
27. The interposer of claim 24 , wherein the metal via curves inward towards the first surface of the metal via and curves inward or outward towards the second surface of the metal via.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US15/178,066 US9852971B1 (en) | 2016-06-09 | 2016-06-09 | Interposer, semiconductor package structure, and semiconductor process |
CN201710324603.0A CN107492537A (en) | 2016-06-09 | 2017-05-10 | Intermediary layer, semiconductor package and semiconductor technology |
US15/818,337 US10388598B2 (en) | 2016-06-09 | 2017-11-20 | Interposer, semiconductor package structure, and semiconductor process |
Applications Claiming Priority (1)
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US15/178,066 US9852971B1 (en) | 2016-06-09 | 2016-06-09 | Interposer, semiconductor package structure, and semiconductor process |
Related Child Applications (1)
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US15/818,337 Division US10388598B2 (en) | 2016-06-09 | 2017-11-20 | Interposer, semiconductor package structure, and semiconductor process |
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- 2016-06-09 US US15/178,066 patent/US9852971B1/en active Active
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US9852971B1 (en) | 2017-12-26 |
CN107492537A (en) | 2017-12-19 |
US20180076122A1 (en) | 2018-03-15 |
US10388598B2 (en) | 2019-08-20 |
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