US20170323928A1 - Write current reduction in spin transfer torque memory devices - Google Patents
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- US20170323928A1 US20170323928A1 US15/658,078 US201715658078A US2017323928A1 US 20170323928 A1 US20170323928 A1 US 20170323928A1 US 201715658078 A US201715658078 A US 201715658078A US 2017323928 A1 US2017323928 A1 US 2017323928A1
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- H01L27/228—
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
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- H01L43/02—
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- H01L43/08—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
Definitions
- the present disclosure relates generally to the fabrication of microelectronic memory.
- the microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered.
- FIG. 1 a is a schematic diagram illustrating a spin transfer torque memory bit cell in accordance with an embodiment of the present description.
- FIG. 1 b is a schematic diagram illustrating a spin transfer torque memory bit cell in accordance with another embodiment of the present description.
- FIG. 1 c is a schematic diagram illustrating a spin transfer torque memory bit cell in accordance with still another embodiment of the present description.
- FIG. 2 a is a side view schematic illustrating a magnetic tunneling junction with a free magnetic layer having a magnetic orientation anti-parallel to a fixed magnetic layer in accordance with an embodiment of the present description.
- FIG. 2 b is a side view schematic illustrating a magnetic tunneling junction with a free magnetic layer having a magnetic orientation parallel to a fixed magnetic layer in accordance with an embodiment of the present description.
- FIG. 3 a illustrates a plan view along line 3 - 3 of any of FIGS. 1 a -1 c , wherein a free magnetic layer electrode substantially covers a magnetic layer as known in the art.
- FIG. 3 b illustrates a plan view along line 3 - 3 of any of FIGS. 1 a -1 c , wherein the free magnetic layer electrode comprises a stripe extending the length of the magnetic layer in accordance with an embodiment of the present description.
- FIG. 3 c illustrates a plan view along line 3 - 3 of any of FIGS. 1 a -1 c , wherein the free magnetic layer electrode comprises a ring abutting a periphery of the magnetic layer in accordance with an embodiment of the present description.
- FIG. 3 d illustrates a plan view along line 3 - 3 of any of FIGS. 1 a -1 c , wherein the free magnetic layer electrode comprises a stripe extending the width of the magnetic layer in accordance with an embodiment of the present description.
- FIG. 3 e illustrates a plan view along line 3 - 3 of any of FIGS. 1 a -1 c , wherein the free magnetic layer electrode comprises a circle adjacent the magnetic layer in accordance with an embodiment of the present description.
- FIG. 3 f illustrates a plan view along line 3 - 3 of any of FIGS. 1 a -1 c , wherein the free magnetic layer electrode comprises a circle offset a distance from a center of the magnetic layer in accordance with an embodiment of the present description.
- FIG. 4 is a graph of switching current versus a varied parameter in each of the embodiments of FIGS. 3 b , 3 c , and 3 d in accordance with embodiments of the present description.
- FIG. 5 illustrates an embodiment of a portable electronic device in accordance with an embodiment of the present description.
- FIG. 6 illustrates an embodiment of a computer system in accordance with an embodiment of the present description.
- FIG. 7 is a block diagram of an electronic system in accordance with an embodiment of the present description.
- FIG. 8 is a block diagram of another electronic system in accordance with an embodiment of the present description.
- Embodiments of the present description relate to the fabrication of spin transfer torque memory element for non-volatile microelectronic memory devices.
- the spin transfer torque memory element may include a magnetic tunneling junction with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer.
- the shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
- FIG. 1 a shows a schematic of a spin transfer torque memory bit cell 100 which includes a spin transfer torque element 110 .
- the spin transfer torque element 110 may comprise a free magnetic layer electrode 112 with a free magnetic layer 114 adjacent the free magnetic layer electrode 112 , a fixed magnetic layer electrode 116 adjacent a fixed magnetic layer 118 , and a tunneling barrier layer 122 deposed between the free magnetic layer 114 and the fixed magnetic layer 118 .
- a first dielectric element 123 and a second dielectric element 124 may be formed adjacent the fixed magnetic layer electrode 116 , the fixed magnetic layer 118 , and the tunneling barrier layer 122 .
- the fixed magnetic layer electrode 116 may be electrically connected to a bit line 132 .
- the free magnetic layer electrode 112 may be connected to a transistor 134 .
- the transistor 134 may be connected to a word line 136 and a source line 138 in a manner that will be understood to those skilled in the art.
- the spin transfer torque memory bit cell 100 may further include addition read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be understood by those skilled in the art, for the operation of the spin transfer torque memory bit cell 100 . It is understood that a plurality of the spin transfer torque memory bit cells 100 may be operably connected to one another to form a memory array (not shown), wherein the memory array can be incorporated into a non-volatile memory device.
- the portion of the spin transfer torque element 110 comprising the free magnetic layer 114 , the tunneling barrier layer 122 , and the fixed magnetic layer 118 is known as a magnetic tunneling junction 126 .
- the free magnetic layer 114 and the fixed magnetic layer 118 may be ferromagnetic layers, including but not limited to cobalt/iron alloys, nickel/iron alloys, platinum/iron alloys, and the like, which are able to hold a magnetic field or polarization.
- the tunneling barrier layer 122 which separates the free magnetic layer 114 and the fixed magnetic layer 118 , may be an oxide layer, including but not limited to magnesium oxide (MgO), aluminum oxide (Al 2 O 3 ), and the like.
- the tunneling barrier layer 122 may have a thickness, e.g.
- the free magnetic layer electrode 112 and the fixed magnetic layer electrode 116 may be fabricated from any appropriate conductive material, including but not limited to, tantalum and alloys thereof, titanium and alloys thereof, and the like.
- the fixed magnetic layer 118 may be “fixed” by being substantially thicker than the free magnetic layer 114 (e.g. two or more times thickness of the free magnetic layer 114 .
- the fixed magnetic layer 118 may be “fixed” with an antiferromagnetic layer 120 , such as an indium/manganese alloy, a platinum/manganese alloy, or the like, formed adjacent the fixed magnetic layer 118 .
- the magnetic tunneling junction 126 may have a reverse orientation, wherein the free magnetic layer electrode 112 may be electrically connected to a bit line 132 and the fixed magnetic layer electrode 116 may be connected to a transistor 134 .
- the spin transfer torque element 110 is illustrate as a free magnetic layer electrode 112 , a free magnetic layer 114 , a tunneling barrier layer 122 , a fixed magnetic layer 118 , and a fixed magnetic layer electrode 116 , it is understood the additional material layers may be present for improved performance.
- layer of ruthenium, tantalum, copper nitride, and the like may be disposed between the free magnetic layer electrode 112 and/or the fixed magnetic layer electrode 116 , and their respective free magnetic layer 114 or fixed magnetic layer 118 .
- the magnetic tunneling junction 126 functions essentially as a resistor, where the resistance of an electrical path through the magnetic tunneling junction 126 may exist in two resistive states, either “high” or “low”, depending on the direction or orientation of magnetization in the free magnetic layer 114 and in the fixed magnetic layer 118 .
- FIG. 2 a illustrates a high resistive state, wherein direction of magnetization in the free magnetic layer 114 and the fixed magnetic layer 118 are substantially opposed or anti-parallel with one another. This is illustrated with arrows 142 in the free magnetic layer 114 pointing from left to right and with arrows 144 in the fixed magnetic layer 118 aligned in opposition pointing from right to left.
- FIG. 2 b illustrates a low resistive state, wherein direction of magnetization in the free magnetic layer 114 and the fixed magnetic layer 118 are substantially aligned or parallel with one another. This is illustrated with arrows 142 in the free magnetic layer 114 and with arrows 144 in the fixed magnetic layer 118 aligned the same direction pointing from right to left.
- the terms “low” and “high” with regard to the resistive state of the magnetic tunnel junction 126 are relative to one another.
- the high resistive state is merely a detectibly higher resistance than the low resistive state, and vice versa.
- the low and high resistive states can represent different bits of information (i.e. a “0” or a “1”).
- the direction of magnetization in the free magnetic layer 114 may be switched through a process call spin transfer torque (“STT”) using a spin-polarized current.
- An electrical current is generally unpolarized (e.g. consisting of about 50% spin-up and about 50% spin-down electrons).
- a spin polarized current is one with a great number of electrons of either spin-up or spin-down, which may be generated by passing a current through the fixed magnetic layer 118 .
- the electrons of the spin polarized current from the fixed magnetic layer 118 tunnel through the tunneling barrier layer 122 and transfers its spin angular momentum to the free magnetic layer 114 , wherein to free magnetic layer 114 will orient its magnetic direction from anti-parallel, as shown in FIG. 2 a , to that of the fixed magnetic layer 118 or parallel, as shown in FIG. 2 b .
- the free magnetic layer 114 may be returned to its origin orientation, shown in FIG. 2 a , by reversing the current.
- the magnetic tunneling junction 126 may store a single bit of information (“0” or “1”) by its state of magnetization.
- the information stored in the magnetic tunneling junction 126 is sensed by driving a current through the magnetic tunneling junction 126 .
- the free magnetic layer 114 does not require power to retain its magnetic orientations; thus, the state of the magnetic tunneling junction 126 is preserved when power to the device is removed. Therefore, the spin transfer torque memory bit cell 100 of FIGS. 1 a -1 c is non-volatile.
- the amount of current needed to reorient the magnetization of the free magnetic layer 114 is relatively high. This relatively high current may present issues for commercial applications, as will be understood to those skilled in the art. In one embodiment, reducing the current needed to reorient the magnetization of the free magnetic layer 114 to about 1 MA/cm 2 or fixed magnetic layer will be necessary for a commercially acceptable spin transfer torque memory device.
- the fixed magnetic layer may be shaped and/or positioned in a manner to concentrate current in specific location(s) in the free magnetic layer.
- FIGS. 3 a -3 f illustrate plan views along line 3 - 3 of any of FIGS. 1 a -1 c of a magnetic tunneling junction 126 having the fixed magnetic layer 118 with a substantially oval cross section or domain shape comprising a length (axis “L”) and a width (axis “W”) (see FIG. 3 a ).
- the first dielectric structure 123 and the second dielectric structure 124 are not shown for the sake of clarity.
- the fixed magnetic layer 118 of FIGS. 3 a -3 f has an aspect ratio (i.e., the length (axis “L” to the width (axis “W”)) of about 2 to 1.
- 3 a -3 d have a length (axis “L”) of about 70 nm and a width (axis “W”) of about 35 nm and a 2 ns current switching pulse.
- L length
- W width
- the free magnetic layer 114 is illustrated as an oval in FIGS. 3 a -3 f , it is understood that the free magnetic layer 114 may be any appropriate “plan view” shape.
- FIG. 3 a illustrates a prior art magnetic tunneling junction 126 wherein the fixed magnetic layer 118 completely covers the free magnetic layer 114 (not visible in FIG. 3 a ).
- FIG. 3 b illustrates an embodiment of the present description, wherein the fixed magnetic layer 118 may be shaped in a specific pattern that is smaller than the free magnetic layer 114 . As shown in FIG. 3 b , the fixed magnetic layer 118 may be a “stripe” along the axis L.
- FIG. 3 c illustrates another embodiment of the present description, wherein the fixed magnetic layer 118 is shaped as a ring extending from an edge 152 toward a center portion of the free magnetic layer 114 .
- FIG. 3 a illustrates a prior art magnetic tunneling junction 126 wherein the fixed magnetic layer 118 completely covers the free magnetic layer 114 (not visible in FIG. 3 a ).
- FIG. 3 b illustrates an embodiment of the present description, wherein the fixed magnetic layer 118 may be shaped in a specific pattern that
- FIG. 3 d illustrates yet another embodiment of the present description, wherein the fixed magnetic layer 118 may be a “stripe” along the axis W.
- FIG. 3 e illustrates another embodiment of the present description, wherein the fixed magnetic layer 118 may be substantially circular approximately at a centered adjacent the free magnetic layer 114 .
- FIG. 3 f illustrates another embodiment of the present description, wherein the fixed magnetic layer 118 may be substantially circular and offset a distance 172 from the axis W.
- FIGS. 3 a -3 f are described in terms of the fixed magnetic layer 118 being patterned, it is understood that the fixed magnetic layer electrode 116 and/or the tunneling barrier layer 122 may also be patterned similarly.
- the specific patterning and positioning of the fixed magnetic layer electrode 118 may concentrate current density to be more effective in switching the polarity of the free magnetic layer 114 and, thus, may reduce that current needed to do so and/or reduce the time needed to switch the polarity.
- the efficiency of various shaped fixed magnetic layers 118 is illustrated in FIG. 4 , wherein the y-axis is the current needed for switching the polarization (“switching current”) of the free magnetic layer 114 , which is normalized to the switching current needed for the structure of FIG. 3 a (i.e. the free magnetic layer 114 being fully covered with the fixed magnetic layer electrode 118 ).
- the dash line 210 is the 100% current level of the structure of FIG. 3 a (hereinafter the “control structure”).
- the line 220 corresponds to the free magnetic layer 114 and the fixed magnetic layer 118 of FIG. 3 b .
- the varied parameter is the width 162 of the fixed magnetic layer 118 stripe, as shown in FIG. 3 b .
- the switching current was reduced to about 82% of the current required by the control structure. This represented the approximate maximum reduction in switching current and any further reduction in the varied parameter width 162 resulted in an increase in the switching current and has not been graphed. In this graph, the maximum reduction occurred with a fixed magnetic layer width 162 of about 10 nm.
- the line 230 corresponds to the free magnetic layer 114 and the fixed magnetic layer 118 of FIG. 3 c .
- the varied parameter is the width 164 of the fixed magnetic layer 118 ring, as shown in FIG. 3 c .
- the switching current was reduced to about 90% of the current required by the control structure. This represented the approximate maximum reduction in switching current and any further increase in the varied parameter width 164 resulted in an increase in switching current and has not been graphed.
- the line 240 corresponds to the free magnetic layer 114 and the fixed magnetic layer 118 of FIG. 3 d , wherein the fixed magnetic layer 118 extends along the width proximate axis W.
- the fixed magnetic layer 118 has a width 166 of about 43% of the length of the axis L.
- the varied parameter is the offset 168 of the fixed magnetic layer 118 from the axis W, as shown in FIG. 3 d .
- the switching current was reduced to about 93% of the current required by the control structure. This represented the approximate maximum reduction in switching current and any further increase in the varied parameter offset 168 resulted in an increase in switching current and has not been graphed.
- the position of the fixed magnetic layer 118 may also affect the switching current for the free magnetic layer 114 .
- the present description illustrated several examples of specifically shaped fixed magnetic layer 118 adjacent either the free magnetic layer 114 , the subject matter of the present description is not limited to those shapes. It is understood that the fixed magnetic layer 118 may be any shape smaller than the free magnetic layer 114 and/or in a position which may be most effective in reducing the switching current and/or in reducing the switching time of the magnetic tunneling junction 126 by concentrating current in the free magnetic layer 114 .
- the steps for fabrication may include standard microelectronic fabrication processes such as lithography, etch, thin films deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, and/or any other associated action with microelectronic component fabrication.
- standard microelectronic fabrication processes such as lithography, etch, thin films deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, and/or any other associated action with microelectronic component fabrication.
- CMP chemical mechanical polishing
- FIG. 5 illustrates an embodiment of a portable device 510 , such as a cellular telephone or a personal data assistant (PDA), digital media player, of the like.
- the portable device 510 may comprise a substrate 520 within a housing 530 .
- the substrate 520 may have various electronic components electrically coupled thereto including a microprocessor 540 , such as a central processing units (CPUs), chipsets, graphics processor, ASICs, or other command/data processing device, and including at least one memory device 550 , including but not limited to, a memory array, a BIOS chip, a solid state drive, and the like.
- Either the memory device 550 and/or the microprocessor 540 may have a spin transfer torque element as described in the present description.
- the substrate 520 may be attached to various peripheral devices including an input device, such as keypad 560 , and a display device, such an LCD display 570 .
- FIG. 6 illustrates an embodiment of a computer system 610 .
- the computer system 610 may comprise a substrate or motherboard 620 within a housing 630 .
- the motherboard 620 may have various electronic component electrically coupled thereto including a microprocessor 640 , such as a central processing units (CPUs), chipsets, graphics processor, ASICs, or other command/data processing device, and at least one memory device 650 , including but not limited to, a memory array, a BIOS chip, a solid state drive, and the like.
- a microprocessor 640 may have a spin transfer torque element, as described in the present description.
- the substrate or motherboard 620 may be attached to various peripheral devices including inputs devices, such as a keyboard 660 and/or a mouse 670 , and a display device, such as a monitor 680 .
- FIG. 7 illustrates a block diagram of an electronic system 700 .
- the electronic system 700 can correspond to, for example, the portable system 510 of FIG. 5 , the computer system 610 of FIG. 6 , a process control system, or any other system that utilizes a processor and an associated memory.
- the electronic system 700 may have a microprocessor 702 (having a processor 704 and control unit 706 ), a memory device 708 , and an input/output device 710 (it is, of course, understood that the electronic system 700 can have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments).
- the electronic system 700 may have a set of instructions that define operations which are to be performed on data by the processor 704 , as well as, other transactions between the processor 704 , the memory device 708 , and the input/output device 710 .
- the control unit 706 coordinates the operations of the processor 704 , the memory device 708 and the input/output device 710 by cycling through a set of operations that cause instructions to be retrieved from the memory device 708 and executed.
- the memory device 708 can include a spin transfer torque element as described in the present description.
- FIG. 8 illustrates a block diagram of an electronic system 800 which is similar to the electronic system 700 of FIG. 7 , with the exception that the memory device 708 is embedded in the process 704 . All of the operations of the electronic system 800 of FIG. 8 are similar to that of the operations of the electronic system 700 of FIG. 7 .
- any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of structures or intermediate components.
- any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable”, to each other to achieve the desired functionality.
- operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.
- an embodiment may mean that a particular feature, structure, or characteristic described in connection with one or more embodiments may be included in at least some embodiments, but not necessarily in all embodiments.
- the various uses of the terms “an embodiment,” “one embodiment,” “another embodiment,” or “other embodiments” in the detailed description are not necessarily all referring to the same embodiments.
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Abstract
The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
Description
- The present application is a Divisional patent application of pending U.S. patent application Ser. No. 14/312,125, filed on Jun. 23, 2014 entitled “WRITE CURRENT REDUCTION IN SPIN TRANSFER TORQUE MEMORY DEVICES”, which is a Divisional patent application of U.S. patent application Ser. No. 12/971,977, filed on Dec. 17, 2010 entitled “WRITE CURRENT REDUCTION IN SPIN TRANSFER TORQUE MEMORY DEVICES”, now U.S. Pat. No. 8,796,794, issued Aug. 5, 2014, the disclosures of which are incorporated by reference herein.
- The present disclosure relates generally to the fabrication of microelectronic memory. The microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered.
- The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:
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FIG. 1a is a schematic diagram illustrating a spin transfer torque memory bit cell in accordance with an embodiment of the present description. -
FIG. 1b is a schematic diagram illustrating a spin transfer torque memory bit cell in accordance with another embodiment of the present description. -
FIG. 1c is a schematic diagram illustrating a spin transfer torque memory bit cell in accordance with still another embodiment of the present description. -
FIG. 2a is a side view schematic illustrating a magnetic tunneling junction with a free magnetic layer having a magnetic orientation anti-parallel to a fixed magnetic layer in accordance with an embodiment of the present description. -
FIG. 2b is a side view schematic illustrating a magnetic tunneling junction with a free magnetic layer having a magnetic orientation parallel to a fixed magnetic layer in accordance with an embodiment of the present description. -
FIG. 3a illustrates a plan view along line 3-3 of any ofFIGS. 1a-1c , wherein a free magnetic layer electrode substantially covers a magnetic layer as known in the art. -
FIG. 3b illustrates a plan view along line 3-3 of any ofFIGS. 1a-1c , wherein the free magnetic layer electrode comprises a stripe extending the length of the magnetic layer in accordance with an embodiment of the present description. -
FIG. 3c illustrates a plan view along line 3-3 of any ofFIGS. 1a-1c , wherein the free magnetic layer electrode comprises a ring abutting a periphery of the magnetic layer in accordance with an embodiment of the present description. -
FIG. 3d illustrates a plan view along line 3-3 of any ofFIGS. 1a-1c , wherein the free magnetic layer electrode comprises a stripe extending the width of the magnetic layer in accordance with an embodiment of the present description. -
FIG. 3e illustrates a plan view along line 3-3 of any ofFIGS. 1a-1c , wherein the free magnetic layer electrode comprises a circle adjacent the magnetic layer in accordance with an embodiment of the present description. -
FIG. 3f illustrates a plan view along line 3-3 of any ofFIGS. 1a-1c , wherein the free magnetic layer electrode comprises a circle offset a distance from a center of the magnetic layer in accordance with an embodiment of the present description. -
FIG. 4 is a graph of switching current versus a varied parameter in each of the embodiments ofFIGS. 3b, 3c, and 3d in accordance with embodiments of the present description. -
FIG. 5 illustrates an embodiment of a portable electronic device in accordance with an embodiment of the present description. -
FIG. 6 illustrates an embodiment of a computer system in accordance with an embodiment of the present description. -
FIG. 7 is a block diagram of an electronic system in accordance with an embodiment of the present description. -
FIG. 8 is a block diagram of another electronic system in accordance with an embodiment of the present description. - In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.
- Embodiments of the present description relate to the fabrication of spin transfer torque memory element for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
-
FIG. 1a shows a schematic of a spin transfer torquememory bit cell 100 which includes a spintransfer torque element 110. The spintransfer torque element 110 may comprise a freemagnetic layer electrode 112 with a freemagnetic layer 114 adjacent the freemagnetic layer electrode 112, a fixedmagnetic layer electrode 116 adjacent a fixedmagnetic layer 118, and atunneling barrier layer 122 deposed between the freemagnetic layer 114 and the fixedmagnetic layer 118. A firstdielectric element 123 and a seconddielectric element 124 may be formed adjacent the fixedmagnetic layer electrode 116, the fixedmagnetic layer 118, and thetunneling barrier layer 122. The fixedmagnetic layer electrode 116 may be electrically connected to abit line 132. The freemagnetic layer electrode 112 may be connected to atransistor 134. Thetransistor 134 may be connected to aword line 136 and asource line 138 in a manner that will be understood to those skilled in the art. The spin transfer torquememory bit cell 100 may further include addition read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be understood by those skilled in the art, for the operation of the spin transfer torquememory bit cell 100. It is understood that a plurality of the spin transfer torquememory bit cells 100 may be operably connected to one another to form a memory array (not shown), wherein the memory array can be incorporated into a non-volatile memory device. - The portion of the spin
transfer torque element 110 comprising the freemagnetic layer 114, thetunneling barrier layer 122, and the fixedmagnetic layer 118 is known as amagnetic tunneling junction 126. The freemagnetic layer 114 and the fixedmagnetic layer 118 may be ferromagnetic layers, including but not limited to cobalt/iron alloys, nickel/iron alloys, platinum/iron alloys, and the like, which are able to hold a magnetic field or polarization. Thetunneling barrier layer 122, which separates the freemagnetic layer 114 and the fixedmagnetic layer 118, may be an oxide layer, including but not limited to magnesium oxide (MgO), aluminum oxide (Al2O3), and the like. Thetunneling barrier layer 122 may have a thickness, e.g. a distance between the freemagnetic layer 114 and the fixedmagnetic layer 118 of about 1 nm or less, such that electrons can tunnel therethrough, if a bias voltage is applied between the freemagnetic layer electrode 112 and the fixedmagnetic layer electrode 116. The freemagnetic layer electrode 112 and the fixedmagnetic layer electrode 116 may be fabricated from any appropriate conductive material, including but not limited to, tantalum and alloys thereof, titanium and alloys thereof, and the like. - As illustrated in
FIG. 1a , the fixedmagnetic layer 118 may be “fixed” by being substantially thicker than the free magnetic layer 114 (e.g. two or more times thickness of the freemagnetic layer 114. As shown inFIGS. 1b and 1c , the fixedmagnetic layer 118 may be “fixed” with anantiferromagnetic layer 120, such as an indium/manganese alloy, a platinum/manganese alloy, or the like, formed adjacent the fixedmagnetic layer 118. - As shown in
FIG. 1c , themagnetic tunneling junction 126 may have a reverse orientation, wherein the freemagnetic layer electrode 112 may be electrically connected to abit line 132 and the fixedmagnetic layer electrode 116 may be connected to atransistor 134. - Although the spin
transfer torque element 110 is illustrate as a freemagnetic layer electrode 112, a freemagnetic layer 114, atunneling barrier layer 122, a fixedmagnetic layer 118, and a fixedmagnetic layer electrode 116, it is understood the additional material layers may be present for improved performance. For example, layer of ruthenium, tantalum, copper nitride, and the like, may be disposed between the freemagnetic layer electrode 112 and/or the fixedmagnetic layer electrode 116, and their respective freemagnetic layer 114 or fixedmagnetic layer 118. - Referring to
FIGS. 2a and 2b , themagnetic tunneling junction 126 functions essentially as a resistor, where the resistance of an electrical path through themagnetic tunneling junction 126 may exist in two resistive states, either “high” or “low”, depending on the direction or orientation of magnetization in the freemagnetic layer 114 and in the fixedmagnetic layer 118.FIG. 2a illustrates a high resistive state, wherein direction of magnetization in the freemagnetic layer 114 and the fixedmagnetic layer 118 are substantially opposed or anti-parallel with one another. This is illustrated witharrows 142 in the freemagnetic layer 114 pointing from left to right and witharrows 144 in the fixedmagnetic layer 118 aligned in opposition pointing from right to left.FIG. 2b illustrates a low resistive state, wherein direction of magnetization in the freemagnetic layer 114 and the fixedmagnetic layer 118 are substantially aligned or parallel with one another. This is illustrated witharrows 142 in the freemagnetic layer 114 and witharrows 144 in the fixedmagnetic layer 118 aligned the same direction pointing from right to left. - It is understood that the terms “low” and “high” with regard to the resistive state of the
magnetic tunnel junction 126 are relative to one another. In other words, the high resistive state is merely a detectibly higher resistance than the low resistive state, and vice versa. Thus, with a detectible difference in resistance, the low and high resistive states can represent different bits of information (i.e. a “0” or a “1”). - The direction of magnetization in the free
magnetic layer 114 may be switched through a process call spin transfer torque (“STT”) using a spin-polarized current. An electrical current is generally unpolarized (e.g. consisting of about 50% spin-up and about 50% spin-down electrons). A spin polarized current is one with a great number of electrons of either spin-up or spin-down, which may be generated by passing a current through the fixedmagnetic layer 118. The electrons of the spin polarized current from the fixedmagnetic layer 118 tunnel through thetunneling barrier layer 122 and transfers its spin angular momentum to the freemagnetic layer 114, wherein to freemagnetic layer 114 will orient its magnetic direction from anti-parallel, as shown inFIG. 2a , to that of the fixedmagnetic layer 118 or parallel, as shown inFIG. 2b . The freemagnetic layer 114 may be returned to its origin orientation, shown inFIG. 2a , by reversing the current. - Thus, the
magnetic tunneling junction 126 may store a single bit of information (“0” or “1”) by its state of magnetization. The information stored in themagnetic tunneling junction 126 is sensed by driving a current through themagnetic tunneling junction 126. The freemagnetic layer 114 does not require power to retain its magnetic orientations; thus, the state of themagnetic tunneling junction 126 is preserved when power to the device is removed. Therefore, the spin transfer torquememory bit cell 100 ofFIGS. 1a-1c is non-volatile. However, the amount of current needed to reorient the magnetization of the freemagnetic layer 114 is relatively high. This relatively high current may present issues for commercial applications, as will be understood to those skilled in the art. In one embodiment, reducing the current needed to reorient the magnetization of the freemagnetic layer 114 to about 1 MA/cm2 or fixed magnetic layer will be necessary for a commercially acceptable spin transfer torque memory device. - In embodiments of the present description, the fixed magnetic layer may be shaped and/or positioned in a manner to concentrate current in specific location(s) in the free magnetic layer.
-
FIGS. 3a-3f illustrate plan views along line 3-3 of any ofFIGS. 1a-1c of amagnetic tunneling junction 126 having the fixedmagnetic layer 118 with a substantially oval cross section or domain shape comprising a length (axis “L”) and a width (axis “W”) (seeFIG. 3a ). Thefirst dielectric structure 123 and thesecond dielectric structure 124 are not shown for the sake of clarity. In one embodiment, the fixedmagnetic layer 118 ofFIGS. 3a-3f has an aspect ratio (i.e., the length (axis “L” to the width (axis “W”)) of about 2 to 1. In a specific embodiment the freemagnetic layer 114 ofFIGS. 3a-3d have a length (axis “L”) of about 70 nm and a width (axis “W”) of about 35 nm and a 2 ns current switching pulse. Although the free magnetic layer 114 (seeFIGS. 1a-1c ) is illustrated as an oval inFIGS. 3a-3f , it is understood that the freemagnetic layer 114 may be any appropriate “plan view” shape. -
FIG. 3a illustrates a prior artmagnetic tunneling junction 126 wherein the fixedmagnetic layer 118 completely covers the free magnetic layer 114 (not visible inFIG. 3a ).FIG. 3b illustrates an embodiment of the present description, wherein the fixedmagnetic layer 118 may be shaped in a specific pattern that is smaller than the freemagnetic layer 114. As shown inFIG. 3b , the fixedmagnetic layer 118 may be a “stripe” along the axis L.FIG. 3c illustrates another embodiment of the present description, wherein the fixedmagnetic layer 118 is shaped as a ring extending from anedge 152 toward a center portion of the freemagnetic layer 114.FIG. 3d illustrates yet another embodiment of the present description, wherein the fixedmagnetic layer 118 may be a “stripe” along the axis W.FIG. 3e illustrates another embodiment of the present description, wherein the fixedmagnetic layer 118 may be substantially circular approximately at a centered adjacent the freemagnetic layer 114.FIG. 3f illustrates another embodiment of the present description, wherein the fixedmagnetic layer 118 may be substantially circular and offset adistance 172 from the axis W. AlthoughFIGS. 3a-3f are described in terms of the fixedmagnetic layer 118 being patterned, it is understood that the fixedmagnetic layer electrode 116 and/or thetunneling barrier layer 122 may also be patterned similarly. - The specific patterning and positioning of the fixed
magnetic layer electrode 118 may concentrate current density to be more effective in switching the polarity of the freemagnetic layer 114 and, thus, may reduce that current needed to do so and/or reduce the time needed to switch the polarity. - The efficiency of various shaped fixed
magnetic layers 118 is illustrated inFIG. 4 , wherein the y-axis is the current needed for switching the polarization (“switching current”) of the freemagnetic layer 114, which is normalized to the switching current needed for the structure ofFIG. 3a (i.e. the freemagnetic layer 114 being fully covered with the fixed magnetic layer electrode 118). Thedash line 210 is the 100% current level of the structure ofFIG. 3a (hereinafter the “control structure”). - The
line 220, demarked by diamond data points and a dash-dot line, corresponds to the freemagnetic layer 114 and the fixedmagnetic layer 118 ofFIG. 3b . The varied parameter is thewidth 162 of the fixedmagnetic layer 118 stripe, as shown inFIG. 3b . InFIG. 4 , as the fixedmagnetic layer width 162 was reduced to about 14% of length of the axis L, the switching current was reduced to about 82% of the current required by the control structure. This represented the approximate maximum reduction in switching current and any further reduction in thevaried parameter width 162 resulted in an increase in the switching current and has not been graphed. In this graph, the maximum reduction occurred with a fixedmagnetic layer width 162 of about 10 nm. - The
line 230, demarked by circle data points and a dotted line, corresponds to the freemagnetic layer 114 and the fixedmagnetic layer 118 ofFIG. 3c . The varied parameter is thewidth 164 of the fixedmagnetic layer 118 ring, as shown inFIG. 3c . InFIG. 4 , as thevaried parameter width 164 was decreased to about 17% of length of the axis L, the switching current was reduced to about 90% of the current required by the control structure. This represented the approximate maximum reduction in switching current and any further increase in thevaried parameter width 164 resulted in an increase in switching current and has not been graphed. - The
line 240, demarked by triangle data points and a solid line, corresponds to the freemagnetic layer 114 and the fixedmagnetic layer 118 ofFIG. 3d , wherein the fixedmagnetic layer 118 extends along the width proximate axis W. In the illustrated embodiment, the fixedmagnetic layer 118 has awidth 166 of about 43% of the length of the axis L. The varied parameter is the offset 168 of the fixedmagnetic layer 118 from the axis W, as shown inFIG. 3d . InFIG. 4 , as the offset 168 was reduced to about 14% of the length of the axis L, the switching current was reduced to about 93% of the current required by the control structure. This represented the approximate maximum reduction in switching current and any further increase in the varied parameter offset 168 resulted in an increase in switching current and has not been graphed. Thus, the position of the fixedmagnetic layer 118 may also affect the switching current for the freemagnetic layer 114. - Although the present description illustrated several examples of specifically shaped fixed
magnetic layer 118 adjacent either the freemagnetic layer 114, the subject matter of the present description is not limited to those shapes. It is understood that the fixedmagnetic layer 118 may be any shape smaller than the freemagnetic layer 114 and/or in a position which may be most effective in reducing the switching current and/or in reducing the switching time of themagnetic tunneling junction 126 by concentrating current in the freemagnetic layer 114. - Although the method of fabricating the spin transfer torque
memory bit cell 100 has not been described herein, it is understood that the steps for fabrication may include standard microelectronic fabrication processes such as lithography, etch, thin films deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, and/or any other associated action with microelectronic component fabrication. -
FIG. 5 illustrates an embodiment of aportable device 510, such as a cellular telephone or a personal data assistant (PDA), digital media player, of the like. Theportable device 510 may comprise asubstrate 520 within ahousing 530. Thesubstrate 520 may have various electronic components electrically coupled thereto including amicroprocessor 540, such as a central processing units (CPUs), chipsets, graphics processor, ASICs, or other command/data processing device, and including at least onememory device 550, including but not limited to, a memory array, a BIOS chip, a solid state drive, and the like. Either thememory device 550 and/or themicroprocessor 540 may have a spin transfer torque element as described in the present description. Thesubstrate 520 may be attached to various peripheral devices including an input device, such askeypad 560, and a display device, such anLCD display 570. -
FIG. 6 illustrates an embodiment of acomputer system 610. Thecomputer system 610 may comprise a substrate ormotherboard 620 within ahousing 630. Themotherboard 620 may have various electronic component electrically coupled thereto including amicroprocessor 640, such as a central processing units (CPUs), chipsets, graphics processor, ASICs, or other command/data processing device, and at least onememory device 650, including but not limited to, a memory array, a BIOS chip, a solid state drive, and the like. Either thememory device 650 and/or themicroprocessor 640 may have a spin transfer torque element, as described in the present description. The substrate ormotherboard 620 may be attached to various peripheral devices including inputs devices, such as akeyboard 660 and/or amouse 670, and a display device, such as amonitor 680. -
FIG. 7 illustrates a block diagram of anelectronic system 700. Theelectronic system 700 can correspond to, for example, theportable system 510 ofFIG. 5 , thecomputer system 610 ofFIG. 6 , a process control system, or any other system that utilizes a processor and an associated memory. Theelectronic system 700 may have a microprocessor 702 (having aprocessor 704 and control unit 706), amemory device 708, and an input/output device 710 (it is, of course, understood that theelectronic system 700 can have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, theelectronic system 700 may have a set of instructions that define operations which are to be performed on data by theprocessor 704, as well as, other transactions between theprocessor 704, thememory device 708, and the input/output device 710. Thecontrol unit 706 coordinates the operations of theprocessor 704, thememory device 708 and the input/output device 710 by cycling through a set of operations that cause instructions to be retrieved from thememory device 708 and executed. Thememory device 708 can include a spin transfer torque element as described in the present description. -
FIG. 8 illustrates a block diagram of anelectronic system 800 which is similar to theelectronic system 700 ofFIG. 7 , with the exception that thememory device 708 is embedded in theprocess 704. All of the operations of theelectronic system 800 ofFIG. 8 are similar to that of the operations of theelectronic system 700 ofFIG. 7 . - The detailed description has described various embodiments of the devices and/or processes through the use of illustrations, block diagrams, flowcharts, and/or examples. Insofar as such illustrations, block diagrams, flowcharts, and/or examples contain one or more functions and/or operations, it will be understood by those skilled in the art that each function and/or operation within each illustration, block diagram, flowchart, and/or example can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof.
- The described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is understood that such illustrations are merely exemplary, and that many alternate structures can be implemented to achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Thus, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of structures or intermediate components. Likewise, any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable”, to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.
- It will be understood by those skilled in the art that terms used herein, and especially in the appended claims are generally intended as “open” terms. In general, the terms “including” or “includes” should be interpreted as “including but not limited to” or “includes but is not limited to”, respectively. Additionally, the term “having” should be interpreted as “having at least”.
- The use of plural and/or singular terms within the detailed description can be translated from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or the application.
- It will be further understood by those skilled in the art that if an indication of the number of elements is used in a claim, the intent for the claim to be so limited will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. Additionally, if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean “at least” the recited number.
- The use of the terms “an embodiment,” “one embodiment,” “some embodiments,” “another embodiment,” or “other embodiments” in the specification may mean that a particular feature, structure, or characteristic described in connection with one or more embodiments may be included in at least some embodiments, but not necessarily in all embodiments. The various uses of the terms “an embodiment,” “one embodiment,” “another embodiment,” or “other embodiments” in the detailed description are not necessarily all referring to the same embodiments.
- While certain exemplary techniques have been described and shown herein using various methods and systems, it should be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from claimed subject matter or spirit thereof. Additionally, many modifications may be made to adapt a particular situation to the teachings of claimed subject matter without departing from the central concept described herein. Therefore, it is intended that claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter also may include all implementations falling within the scope of the appended claims, and equivalents thereof.
Claims (18)
1. A non-volatile memory device, comprising:
a fixed magnetic layer electrode;
a fixed magnetic layer adjacent the fixed magnetic layer electrode;
a free magnetic layer electrode adjacent a free magnetic layer and electrically connected to a bit line, wherein the fixed magnetic layer and the fixed magnetic layer electrode have a smaller surface area than the surface area of the free magnetic layer, wherein the free magnetic layer is substantially oval and has a length and a width, and wherein the fixed magnetic layer comprises one of a stripe adjacent the free magnetic layer extending along the free magnetic layer width, a ring adjacent the free magnetic layer extending around the free magnetic layer periphery, and a circular layer adjacent the free magnetic layer
a tunneling barrier layer deposed between the fixed magnetic layer and the free magnetic layer; and
a transistor electrically connected to the fixed magnetic layer electrode, a source line, and a word line.
2. The non-volatile memory device of claim 1 , wherein the fixed magnetic layer and the fixed magnetic layer electrode are shaped to concentrate current density within the free magnetic layer
3. The non-volatile memory device of claim 1 , wherein the fixed magnetic layer and the fixed magnetic layer electrode are positioned to concentrate current density within the free magnetic layer.
4. The non-volatile memory device of claim 1 , wherein the fixed magnetic layer comprises a material selected from the group consisting of a cobalt/iron alloy, a nickel/iron alloy, and a platinum/iron alloy.
5. The non-volatile memory device of claim 1 , wherein the free magnetic layer comprises a material selected from the group consisting of a cobalt/iron alloy, a nickel/iron alloy, and a platinum/iron alloy.
6. The non-volatile memory device of claim 1 , wherein the tunnel barrier layer comprises magnesium oxide.
7. The non-volatile memory device of claim 1 , wherein the tunnel barrier layer comprises aluminum oxide.
8. The non-volatile memory device of claim 1 , wherein at least one of the fixed magnetic layer electrode and the free magnetic layer electrode comprises tantalum.
9. The non-volatile memory device of claim 1 , wherein at least one of the fixed magnetic layer electrode and the free magnetic layer electrode comprises titanium.
10. A non-volatile memory device, comprising:
a fixed magnetic layer electrode;
a fixed magnetic layer adjacent the fixed magnetic layer electrode;
a free magnetic layer electrode adjacent a free magnetic layer and electrically connected to a word line, wherein the fixed magnetic layer and the fixed magnetic layer electrode have a smaller surface area than the surface area of the free magnetic layer, wherein the free magnetic layer is substantially oval and has a length and a width, and wherein the fixed magnetic layer comprises one of a stripe adjacent the free magnetic layer extending along the free magnetic layer length, a stripe adjacent the free magnetic layer extending along the free magnetic layer width, a ring adjacent the free magnetic layer extending around the free magnetic layer periphery, and a circular layer adjacent the free magnetic layer
a tunneling barrier layer deposed between the fixed magnetic layer and the free magnetic layer; and
a transistor electrically connected to the fixed magnetic layer electrode, a source line, and a bit line.
11. The non-volatile memory device of claim 10 , wherein the fixed magnetic layer and the fixed magnetic layer electrode are shaped to concentrate current density within the free magnetic layer
12. The non-volatile memory device of claim 10 , wherein the fixed magnetic layer and the fixed magnetic layer electrode are positioned to concentrate current density within the free magnetic layer.
13. The non-volatile memory device of claim 10 , wherein the fixed magnetic layer comprises a material selected from the group consisting of a cobalt/iron alloy, a nickel/iron alloy, and a platinum/iron alloy.
14. The non-volatile memory device of claim 10 , wherein the free magnetic layer comprises a material selected from the group consisting of a cobalt/iron alloy, a nickel/iron alloy, and a platinum/iron alloy.
15. The non-volatile memory device of claim 10 , wherein the tunnel barrier layer comprises magnesium oxide.
16. The non-volatile memory device of claim 10 , wherein the tunnel barrier layer comprises aluminum oxide.
17. The non-volatile memory device of claim 10 , wherein at least one of the fixed magnetic layer electrode and the free magnetic layer electrode comprises tantalum.
18. The non-volatile memory device of claim 10 , wherein at least one of the fixed magnetic layer electrode and the free magnetic layer electrode comprises titanium.
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8450818B2 (en) | 2009-06-18 | 2013-05-28 | Dmitri E. Nikonov | Methods of forming spin torque devices and structures formed thereby |
US8796794B2 (en) | 2010-12-17 | 2014-08-05 | Intel Corporation | Write current reduction in spin transfer torque memory devices |
US9478730B2 (en) * | 2010-12-31 | 2016-10-25 | Samsung Electronics Co., Ltd. | Method and system for providing magnetic layers having insertion layers for use in spin transfer torque memories |
US9728238B2 (en) | 2011-12-19 | 2017-08-08 | Intel Corporation | Spin transfer torque memory (STTM) device with half-metal and method to write and read the device |
WO2014204492A1 (en) | 2013-06-21 | 2014-12-24 | Intel Corporation | Mtj spin hall mram bit-cell and array |
CN106463610B (en) | 2014-06-18 | 2020-07-03 | 英特尔公司 | Coupled spin hall nanooscillator with adjustable strength |
EP3189522A4 (en) * | 2014-09-03 | 2018-02-21 | Intel Corporation | Spin transfer torque memory and logic devices having an interface for inducing a strain on a magnetic layer therein |
US9978432B2 (en) * | 2014-12-22 | 2018-05-22 | Intel Corporation | Write operations in spin transfer torque memory |
US9853205B1 (en) * | 2016-10-01 | 2017-12-26 | International Business Machines Corporation | Spin transfer torque magnetic tunnel junction with off-centered current flow |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008099626A1 (en) * | 2007-02-13 | 2008-08-21 | Nec Corporation | Magnetoresistance effect element and magnetic random access memory |
WO2009110532A1 (en) * | 2008-03-07 | 2009-09-11 | 日本電気株式会社 | Semiconductor device |
WO2019110532A1 (en) * | 2017-12-05 | 2019-06-13 | Vracoop | Device for storing and dispensing at least one bulk product |
Family Cites Families (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001196661A (en) | 1999-10-27 | 2001-07-19 | Sony Corp | Magnetization control method, information storage method, magnetic function element, and information storage element |
JP2002084019A (en) | 2000-09-08 | 2002-03-22 | Canon Inc | Magnetic device and solid magnetic storage device |
JP2002170377A (en) * | 2000-09-22 | 2002-06-14 | Mitsubishi Electric Corp | Thin film magnetic storage device |
FR2817999B1 (en) | 2000-12-07 | 2003-01-10 | Commissariat Energie Atomique | MAGNETIC DEVICE WITH POLARIZATION OF SPIN AND A STRIP (S) TRI-LAYER (S) AND MEMORY USING THE DEVICE |
JP3583102B2 (en) | 2001-12-27 | 2004-10-27 | 株式会社東芝 | Magnetic switching element and magnetic memory |
WO2003098634A2 (en) | 2002-05-22 | 2003-11-27 | Koninklijke Philips Electronics N.V. | Magnetoresistive memory cell array and mram memory comprising such array |
US6714444B2 (en) | 2002-08-06 | 2004-03-30 | Grandis, Inc. | Magnetic element utilizing spin transfer and an MRAM device using the magnetic element |
US6778364B2 (en) | 2002-08-28 | 2004-08-17 | International Business Machines Corporation | Current-in-plane magnetoresistive sensor with longitudinal biasing layer having a nonmagnetic oxide central region and method for fabrication of the sensor |
JP4219141B2 (en) * | 2002-09-13 | 2009-02-04 | 株式会社ルネサステクノロジ | Thin film magnetic memory device |
JP4576791B2 (en) | 2002-12-27 | 2010-11-10 | Tdk株式会社 | Memory device |
JP2004235443A (en) * | 2003-01-30 | 2004-08-19 | Renesas Technology Corp | Thin film magnetic storage device and its manufacturing method |
US7573737B2 (en) * | 2003-08-19 | 2009-08-11 | New York University | High speed low power magnetic devices based on current induced spin-momentum transfer |
US7026673B2 (en) | 2003-12-11 | 2006-04-11 | International Business Machines Corporation | Low magnetization materials for high performance magnetic memory devices |
JP4819316B2 (en) | 2004-02-23 | 2011-11-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US7233039B2 (en) | 2004-04-21 | 2007-06-19 | Grandis, Inc. | Spin transfer magnetic elements with spin depolarization layers |
JP2006018862A (en) | 2004-06-30 | 2006-01-19 | Hitachi Global Storage Technologies Netherlands Bv | Magneto-resistance effect type head and its manufacturing method |
US7855860B2 (en) | 2004-07-12 | 2010-12-21 | Nec Corporation | Magnetoresistance element magnetic random access memory, magnetic head and magnetic storage device |
US7098495B2 (en) | 2004-07-26 | 2006-08-29 | Freescale Semiconducor, Inc. | Magnetic tunnel junction element structures and methods for fabricating the same |
JP2006269885A (en) * | 2005-03-25 | 2006-10-05 | Sony Corp | Spin injection type magnetoresistance effect element |
US7158407B2 (en) * | 2005-04-29 | 2007-01-02 | Freescale Semiconductor, Inc. | Triple pulse method for MRAM toggle bit characterization |
WO2007020823A1 (en) | 2005-08-15 | 2007-02-22 | Nec Corporation | Magnetic memory cell, magnetic random access memory and method for reading/writing data in magnetic random access memory |
JP2007081280A (en) | 2005-09-16 | 2007-03-29 | Fujitsu Ltd | Magnetoresistance effect element and magnetic memory apparatus |
US7646627B2 (en) | 2006-05-18 | 2010-01-12 | Renesas Technology Corp. | Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance |
US7430135B2 (en) * | 2005-12-23 | 2008-09-30 | Grandis Inc. | Current-switched spin-transfer magnetic devices with reduced spin-transfer switching current density |
US8084835B2 (en) | 2006-10-20 | 2011-12-27 | Avalanche Technology, Inc. | Non-uniform switching based non-volatile magnetic based memory |
US7616412B2 (en) | 2006-07-21 | 2009-11-10 | Carnegie Melon University | Perpendicular spin-torque-driven magnetic oscillator |
JP2008066479A (en) | 2006-09-06 | 2008-03-21 | Osaka Univ | Spin transistor |
FR2907587B1 (en) | 2006-10-23 | 2008-12-26 | Commissariat Energie Atomique | MAGNETIC DEVICE WITH PERPENDICULAR ANIMATION AND INTERCOUNTING COMPENSATORY INTERCONNECTIVE LAYER. |
US7589600B2 (en) | 2006-10-31 | 2009-09-15 | Seagate Technology Llc | Spin oscillator device |
WO2008115291A2 (en) | 2006-11-03 | 2008-09-25 | New York University | Electronic devices based on current induced magnetization dynamics in single magnetic layers |
US7572645B2 (en) | 2006-11-15 | 2009-08-11 | Everspin Technologies, Inc. | Magnetic tunnel junction structure and method |
US7869266B2 (en) | 2007-10-31 | 2011-01-11 | Avalanche Technology, Inc. | Low current switching magnetic tunnel junction design for magnetic memory using domain wall motion |
JP4435189B2 (en) | 2007-02-15 | 2010-03-17 | 株式会社東芝 | Magnetic storage element and magnetic storage device |
US7480173B2 (en) | 2007-03-13 | 2009-01-20 | Magic Technologies, Inc. | Spin transfer MRAM device with novel magnetic free layer |
US7957179B2 (en) * | 2007-06-27 | 2011-06-07 | Grandis Inc. | Magnetic shielding in magnetic multilayer structures |
EP2234269B1 (en) | 2007-12-19 | 2015-10-14 | III Holdings 3 LLC | Spin-valve element driving method |
JP5036585B2 (en) | 2008-02-13 | 2012-09-26 | 株式会社東芝 | Magnetic oscillation element, magnetic head having the magnetic oscillation element, and magnetic recording / reproducing apparatus |
US7936597B2 (en) | 2008-03-25 | 2011-05-03 | Seagate Technology Llc | Multilevel magnetic storage device |
US7888167B2 (en) | 2008-04-25 | 2011-02-15 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and method for manufacturing the same |
US8416539B2 (en) | 2008-08-07 | 2013-04-09 | HGST Netherlands B.V. | Magnetic field sensing system using spin-torque diode effect |
US7935435B2 (en) * | 2008-08-08 | 2011-05-03 | Seagate Technology Llc | Magnetic memory cell construction |
US8053244B2 (en) | 2008-08-13 | 2011-11-08 | Seagate Technology Llc | Magnetic oscillator based biosensor |
US7727778B2 (en) | 2008-08-28 | 2010-06-01 | Kabushiki Kaisha Toshiba | Magnetoresistive element and method of manufacturing the same |
US7880209B2 (en) | 2008-10-09 | 2011-02-01 | Seagate Technology Llc | MRAM cells including coupled free ferromagnetic layers for stabilization |
US8503222B2 (en) | 2009-01-27 | 2013-08-06 | Nec Corporation | Non-volatile logic circuit |
JP5117421B2 (en) | 2009-02-12 | 2013-01-16 | 株式会社東芝 | Magnetoresistive element and manufacturing method thereof |
JP5416992B2 (en) | 2009-03-04 | 2014-02-12 | 株式会社東芝 | Cluster and spin RAM and spin torque oscillator using the same |
US8344433B2 (en) | 2009-04-14 | 2013-01-01 | Qualcomm Incorporated | Magnetic tunnel junction (MTJ) and methods, and magnetic random access memory (MRAM) employing same |
US8450818B2 (en) | 2009-06-18 | 2013-05-28 | Dmitri E. Nikonov | Methods of forming spin torque devices and structures formed thereby |
US8063460B2 (en) | 2009-12-18 | 2011-11-22 | Intel Corporation | Spin torque magnetic integrated circuits and devices therefor |
KR101676809B1 (en) | 2010-08-13 | 2016-11-16 | 삼성전자주식회사 | Oscillator and method of operating the same |
US8203389B1 (en) | 2010-12-06 | 2012-06-19 | Headway Technologies, Inc. | Field tunable spin torque oscillator for RF signal generation |
US8796794B2 (en) | 2010-12-17 | 2014-08-05 | Intel Corporation | Write current reduction in spin transfer torque memory devices |
US8604886B2 (en) | 2010-12-20 | 2013-12-10 | Intel Corporation | Spin torque oscillator having multiple fixed ferromagnetic layers or multiple free ferromagnetic layers |
US8933521B2 (en) | 2011-03-30 | 2015-01-13 | Intel Corporation | Three-dimensional magnetic circuits including magnetic connectors |
US9306151B2 (en) | 2012-05-25 | 2016-04-05 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Threshold gate and threshold logic array |
KR101929983B1 (en) | 2012-07-18 | 2018-12-17 | 삼성전자주식회사 | Semiconductor memory device having resistive memory cells and method of testing the same |
-
2010
- 2010-12-17 US US12/971,977 patent/US8796794B2/en not_active Expired - Fee Related
-
2011
- 2011-12-02 KR KR1020137015417A patent/KR101505343B1/en active IP Right Grant
- 2011-12-02 WO PCT/US2011/063072 patent/WO2012082403A2/en active Application Filing
- 2011-12-02 CN CN201180060785.6A patent/CN103262241B/en not_active Expired - Fee Related
- 2011-12-13 TW TW100145965A patent/TWI511130B/en not_active IP Right Cessation
- 2011-12-13 TW TW104130790A patent/TWI576837B/en active
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2014
- 2014-06-23 US US14/312,125 patent/US9754996B2/en active Active
-
2017
- 2017-07-24 US US15/658,078 patent/US20170323928A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008099626A1 (en) * | 2007-02-13 | 2008-08-21 | Nec Corporation | Magnetoresistance effect element and magnetic random access memory |
WO2009110532A1 (en) * | 2008-03-07 | 2009-09-11 | 日本電気株式会社 | Semiconductor device |
WO2019110532A1 (en) * | 2017-12-05 | 2019-06-13 | Vracoop | Device for storing and dispensing at least one bulk product |
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US9754996B2 (en) | 2017-09-05 |
TWI576837B (en) | 2017-04-01 |
TWI511130B (en) | 2015-12-01 |
US8796794B2 (en) | 2014-08-05 |
TW201624484A (en) | 2016-07-01 |
CN103262241A (en) | 2013-08-21 |
CN103262241B (en) | 2016-08-10 |
KR20130086244A (en) | 2013-07-31 |
KR101505343B1 (en) | 2015-03-23 |
WO2012082403A3 (en) | 2012-08-16 |
WO2012082403A2 (en) | 2012-06-21 |
US20120153412A1 (en) | 2012-06-21 |
TW201230028A (en) | 2012-07-16 |
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