US20170263577A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- US20170263577A1 US20170263577A1 US15/300,603 US201515300603A US2017263577A1 US 20170263577 A1 US20170263577 A1 US 20170263577A1 US 201515300603 A US201515300603 A US 201515300603A US 2017263577 A1 US2017263577 A1 US 2017263577A1
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- US
- United States
- Prior art keywords
- power supply
- electrode layer
- thin
- bump
- metal resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 239000002184 metal Substances 0.000 claims abstract description 152
- 229910052751 metal Inorganic materials 0.000 claims abstract description 152
- 239000010409 thin film Substances 0.000 claims abstract description 105
- 239000003990 capacitor Substances 0.000 claims abstract description 96
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000010408 film Substances 0.000 description 26
- 230000003247 decreasing effect Effects 0.000 description 22
- 238000005516 engineering process Methods 0.000 description 14
- 238000004544 sputter deposition Methods 0.000 description 14
- 238000004088 simulation Methods 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 229910001120 nichrome Inorganic materials 0.000 description 3
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 3
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- NWLCFADDJOPOQC-UHFFFAOYSA-N [Mn].[Cu].[Sn] Chemical compound [Mn].[Cu].[Sn] NWLCFADDJOPOQC-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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Definitions
- the present invention relates to a semiconductor device, and more particularly to a technology for decreasing, in a semiconductor device equipped with a semiconductor integrated circuit, power supply impedance with respect to the semiconductor integrated circuit.
- Patent Document 1 a technology disclosed in Patent Document 1 is known, for example, as a technology for decreasing power supply impedance with respect to the semiconductor integrated circuit.
- the antiresonance impedance of power supply impedance is decreased by configuring a series resonance circuit from a pattern unit including three conductor patterns between a power supply terminal and a ground terminal of a semiconductor element (semiconductor integrated circuit).
- Patent Document 1 Japanese Patent Application Laid-Open No. 2014-175628
- the series resonance circuit includes linear conductor patterns for forming an inductance component.
- Such linear conductor patterns may possibly constitute a noise emitting source at the time of high speed operation of the semiconductor integrated circuit where harmonic components included in the operation frequency exceed 1 GHz, and may prove disadvantageous in terms of noise suppression. Accordingly, a technology for decreasing power supply impedance while suppressing the generation of noise at the time of high speed operation is desired.
- a semiconductor device disclosed by the present description includes a semiconductor integrated circuit having a bump mounting surface; and a thin-film capacitor portion connected to the bump mounting surface via a bump.
- the semiconductor integrated circuit includes a first power supply pad formed on the bump mounting surface and to which a power supply voltage of one polarity is applied, and a second power supply pad formed on the bump mounting surface and to which a power supply voltage of another polarity is applied.
- the thin-film capacitor portion includes a first electrode layer connected to the first power supply pad via the bump, a second electrode layer connected to the second power supply pad via the bump, and a dielectric layer formed between the first electrode layer and the second electrode layer.
- the semiconductor device includes: an electric power supply path including the first and second power supply pads, the bump, and the thin-film capacitor portion, and configured to supply electric power to the semiconductor integrated circuit; and a thin plate-shaped metal resistor portion provided in the electric power supply path and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer.
- the thin plate-shaped metal resistor portion made from the metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer. That is, the metal resistor portion is connected in series with the electric power supply path. It has been confirmed through a simulation that by adjusting the resistance value of the metal resistor portion, the antiresonance impedance of the power supply impedance of the semiconductor integrated circuit can be decreased; that is to say that the power supply impedance can be decreased.
- the metal resistor portion because of its thin-plate shape, does not readily constitute a noise emitting source at the time of high speed operation of the semiconductor integrated circuit. Accordingly, the present configuration can decrease the power supply impedance while suppressing the generation of noise at the time of high speed operation.
- the metal based high-resistance material may include metal simple substance, a metal compound, a metal oxide, and the like.
- the electric power supply path may include the first and second power supply pads, the bump, and the thin-film capacitor portion.
- the metal resistor portion may be provided between the bump mounting surface of the semiconductor integrated circuit and the thin-film capacitor portion.
- the electric power supply path can be formed so as to be short, and the connection wiring for the metal resistor portion can be minimized in length. Accordingly, the generation of parasitic inductance and the like associated with the connection wiring for the metal resistor portion can be suppressed.
- the first electrode layer may include a first supply portion constituting the electric power supply path and electrically connected to the bump.
- the second electrode layer may include a second supply portion constituting the electric power supply path and electrically connected to the bump.
- the metal resistor portion may be provided at least one of between the bump and the first supply portion, and between the bump and the second supply portion.
- the metal resistor portion can be formed, as a pad portion of the bump connecting the thin-film capacitor portion and the semiconductor integrated circuit, on the first supply portion of the first electrode layer of the thin-film capacitor portion or on the second supply portion of the second electrode layer, using a thin-film formation technology, such as sputtering. Accordingly, the formation of the metal resistor portion can be performed using a similar method to the method for forming the thin-film capacitor portion. That is, the formation of the metal resistor portion can be performed easily.
- the metal resistor portion may be provided at the first power supply pad and the second power supply pad.
- the metal resistor portion is provided on the semiconductor integrated circuit side.
- the power supply impedance can be decreased while suppressing the generation of noise at the time of high speed operation.
- the semiconductor integrated circuit may further include an external connection portion electrically connecting, on an opposite side from the semiconductor integrated circuit, the thin-film capacitor portion to an outside.
- the electric power supply path may include the first and second power supply pads, the bump, the thin-film capacitor portion, and the external connection portion.
- the metal resistor portion may be provided between the external connection portion and the thin-film capacitor portion.
- the electric power supply path can be formed so as to be short, and the connection wiring for the metal resistor portion can be made short. Accordingly, the generation of parasitic inductance and the like associated with the connection wiring for the metal resistor portion can be suppressed.
- the first electrode layer may include a first supply portion constituting the electric power supply path and electrically connected to the bump.
- the second electrode layer may include a second supply portion constituting the electric power supply path and electrically connected to the bump.
- the metal resistor portion may be provided at least one of between the external connection portion and the first supply portion, and between the external connection portion and the second supply portion.
- the metal resistor portion can be formed on the first supply portion of the first electrode layer of the thin-film capacitor portion or on the second supply portion of the second electrode layer, using a thin-film formation technology, such as sputtering. It has also been confirmed through a simulation that the power supply impedance can be decreased.
- the thin-film capacitor portion may include a metal resistor layer formed between the first electrode layer and the dielectric layer, or between the second electrode layer and the dielectric layer, and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer.
- the resistor connected in series with the thin-film capacitor can be formed without connection wiring. It has been confirmed that by adding the metal resistor layer to the metal resistor portion formed in the electric power supply path, the power supply impedance decreasing effect by the metal resistor portion alone is reinforced.
- the resistor connected in series with the thin-film capacitor can be formed using the thin-film formation technology for forming the thin-film capacitor, such as sputtering.
- the metal resistor portion and the metal resistor layer may have a volume resistivity of not smaller than 70 ⁇ cm.
- the thin-film capacitor may have a planar shape equal to a planar shape of the semiconductor integrated circuit.
- the capacitance of the thin-film capacitor can be maximized while the planar shape size of the semiconductor device is equal to the planar shape of the semiconductor integrated circuit.
- the semiconductor integrated circuit may be further provided with a multilayer ceramic capacitor connected in parallel with the thin-film capacitor.
- the generation of noise at the time of high speed operation can be further suppressed by the multilayer ceramic capacitor (MLCC) provided as a bypass capacitor.
- MLCC multilayer ceramic capacitor
- a semiconductor device disclosed by the present description includes a semiconductor integrated circuit having a bump mounting surface; and a thin-film capacitor portion connected to the bump mounting surface via a bump.
- the semiconductor integrated circuit includes a first power supply pad formed on the bump mounting surface and to which a power supply voltage of one polarity is applied, and a second power supply pad formed on the bump mounting surface and to which a power supply voltage of another polarity is applied.
- the thin-film capacitor portion includes a first electrode layer connected to the first power supply pad via the bump, a second electrode layer connected to the second power supply pad via the bump, a dielectric layer formed between the first electrode layer and the second electrode layer, and a metal resistor layer formed between the first electrode layer and the dielectric layer or between the second electrode layer and the dielectric layer, and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer.
- the resistor connected in series with the thin-film capacitor can be formed without connection wiring. It has been confirmed that the metal resistor layer decreases the power supply impedance.
- the resistor connected in series with the thin-film capacitor can be formed using the thin-film formation technology for forming the thin-film capacitor, such as sputtering.
- power supply impedance can be decreased while the generation of noise at the time of high speed operation is suppressed.
- FIG. 1 is a schematic cross sectional view of a semiconductor device according to a first embodiment
- FIG. 2 is a schematic perspective view of a metal resistor portion
- FIG. 3 is a schematic cross sectional view taken along line A-A of FIG. 2 ;
- FIG. 4 is a schematic perspective view of another metal resistor portion
- FIG. 5 is a schematic equivalent circuit diagram of a power supply system for the semiconductor device according to the first embodiment
- FIGS. 6A and 6B are graphs of power supply impedance characteristics depending on the resistance value of the metal resistor portion
- FIG. 7 is a graph of power supply impedance characteristics in the absence of the metal resistor portion
- FIGS. 8A to 8E are schematic diagrams describing a method for fabricating a thin-film capacitor portion
- FIG. 9 is a plan view of the thin-film capacitor portion
- FIG. 10 is a schematic cross sectional view of a semiconductor device according to a second embodiment
- FIG. 11 is a schematic equivalent circuit diagram of a power supply system for the semiconductor device according to the second embodiment.
- FIGS. 12A and 12B are graphs of power supply impedance characteristics depending on the resistance value of a metal resistor portion
- FIG. 13 is a schematic cross sectional view of a semiconductor device according to a third embodiment
- FIG. 14 is a schematic equivalent circuit diagram of a power supply system for the semiconductor device according to the third embodiment.
- FIGS. 15A and 15B are graphs of power supply impedance characteristics depending on the resistance value of the metal resistor portion
- FIGS. 16A to 16F are schematic diagrams describing a method for fabricating a thin-film capacitor portion according to the third embodiment
- FIG. 17 is a schematic cross sectional view of a semiconductor device according to a fourth embodiment.
- FIG. 18 is a schematic equivalent circuit diagram of a power supply system for the semiconductor device according to the fourth embodiment.
- FIG. 19 is a diagram schematically illustrating the configuration of a thin-film capacitor portion according to the fourth embodiment.
- FIG. 20 is a graph of power supply impedance characteristics according to the fourth embodiment.
- FIG. 1 to FIG. 9 A first embodiment will be described with reference to FIG. 1 to FIG. 9 , in which like reference symbols designate like or corresponding parts throughout the drawings. Designation of similar components with reference numerals may be omitted.
- a semiconductor device 100 generally includes a thin-film capacitor portion 1 , an LSI chip (an example of “semiconductor integrated circuit”) 2 , and electric power supply paths 30 .
- the LSI is a CPU or MPU, for example.
- FIG. 1 is a cross sectional view of the semiconductor device 100 corresponding to the position indicated by a dot-and-dash line B-B in FIG. 9 .
- letter “V” suffixed to reference numerals means that the designated member and the like pertain to a positive power supply voltage (an example of “power supply voltage of one polarity”) applied to the LSI chip 2 ;
- letter “G” means that the designated member and the like pertain to a ground voltage that is a negative power supply voltage (an example of “power supply voltage of another polarity”) applied to the LSI chip 2 .
- Letter “S” indicates a member and the like pertaining to signals input to or output from the LSI chip 2 .
- the LSI chip 2 is an area array type LSI (see FIG. 9 ) and, as illustrated in FIG. 1 , includes a bump mounting surface 2 S.
- a plurality of electrode pads 21 is formed on the bump mounting surface 2 S.
- the electrode pads 21 include power supply pads for power supply voltage (an example of “first power supply pads”) 21 V; ground pads for ground voltage (an example of “second power supply pads”) 21 G; and signal pads 21 S.
- a bump 22 for connecting the LSI chip 2 and the thin-film capacitor portion 1 is formed on each of the electrode pads 21 .
- the bumps 22 according to the present embodiment are gold (Au) stud bumps, for example.
- the thin-film capacitor portion 1 includes a thin-film capacitor 10 ; organic insulating layers 14 , 15 ; and metal resistor portions 17 .
- the thin-film capacitor portion 1 includes a first electrode layer 11 connected to the power supply pads 21 V via the bumps 22 ; a second electrode layer 12 connected to the ground pads 21 G via the bumps 22 ; and a dielectric layer 13 formed between the first electrode layer 11 and the second electrode layer 12 .
- the first electrode layer 11 and the second electrode layer 12 are made of a copper (Cu) thin-film, for example.
- the dielectric layer 13 is made of a strontium titanate (STO) film, for example.
- the first electrode layer 11 includes a first electrode portion 11 C constituting one electrode of the thin-film capacitor 10 , and first supply portions ( 11 G, 11 V) constituting the electric power supply paths 30 .
- the second electrode layer 12 includes a second electrode portion 12 C constituting the other electrode of the thin-film capacitor 10 , and second supply portions ( 12 G, 12 V) constituting the electric power supply paths 30 .
- the thin-film capacitor 10 includes the first electrode portion 11 C, the second electrode layer 12 , and the second electrode portion 12 C.
- the thin-film capacitor portion 1 has a planar shape equal to a planar shape of the LSI chip 2 .
- the planar shape of the thin-film capacitor 10 is equal to the planar shape of the LSI chip 2 . Accordingly, the capacitance of the thin-film capacitor 10 can be maximized while the planar shape size of the semiconductor device 100 is equal to the planar shape of the LSI chip 2 .
- the metal resistor portions 17 are provided on the first supply portions ( 11 G, 11 V) of the first electrode layer 11 , as illustrated in FIG. 1 . That is, according to the first embodiment, the metal resistor portions 17 are provided between the bump mounting surface 2 S of the LSI chip 2 and the thin-film capacitor portion 1 .
- the metal resistor portions 17 are made from a metal based high-resistance material and have a thin-plate shape.
- the metal resistor portions 17 are made of an annular metal thin plate.
- the metal resistor portions 17 are made from a metal based high-resistance material with a volume resistivity higher than the volume resistivity of the first electrode layer 11 and the second electrode layer 12 .
- the metal resistor portions 17 are made from tantalum nitride (TaN).
- the metal resistor portion 17 as illustrated in FIG. 2 and FIG. 3 , have a thickness of 0.05 micrometers ( ⁇ m), for example, and corresponds to a region (annular region) between a circle with a diameter of 20 ⁇ m and a circle with a diameter of 50 ⁇ m. If the volume resistivity of TaN is 135 ⁇ cm, the annular metal resistor portion 17 has a resistance value of approximately 1.4 ohms ( ⁇ ).
- the upper surface of the metal resistor portion 17 (bumps 22 connecting surface), as illustrated in FIG. 2 , is flash-coated with a film 18 of highly conductive metal (such as Au or Pt) having a diameter of 40 ⁇ m and a film thickness on the order of 0.1 ⁇ m, for example.
- the upper surface of the first supply portion 11 G of the first electrode layer 11 is also flash-coated with a conductive film 18 A of Au, for example, having a diameter of 40 ⁇ m and a film thickness on the order of 0.1 ⁇ m, for example.
- the resistance value of the metal resistor portion 17 can be controlled depending on the material, film thickness, and the like of the metal films 18 , 18 A.
- an insulating film 16 for example, an organic insulating film of polyimide, bismaleimide-triazine (BT) resin, or Ajinomoto Build-up Film (ABF) having a diameter of 50 ⁇ m and a film thickness on the order of 15 ⁇ m.
- the metal resistor portions 17 are formed by sputtering TaN.
- the TaN on the insulating film 16 corresponds to the metal resistor portions 17 , of which the thickness is 0.05 ⁇ m, for example.
- the metal based high-resistance material of the metal resistor portions 17 is not limited to TaN, and may preferably be a material with a volume resistivity of not less than 70 ⁇ cm.
- Examples of the metal based high-resistance material include nichrome (NiCr), SUS304 (stainless steel), CuMn7Sn (copper manganese tin), NCF800 (stainless steel), and bismuth (Bi).
- the thin-plate shape of the metal resistor portions 17 is not limited to the annular shape, as illustrated in FIG. 2 .
- the shape of the metal resistor portions 17 may be rectangular as viewed in plan.
- the metal resistor portions 17 are formed on the conductive film 18 A and the insulating film 16 by sputtering TaN, for example, where the TaN on the insulating film 16 corresponds to the metal resistor portions 17 A.
- the metal resistor portions 17 have the shape of a thin plate with a thickness of 1.0 ⁇ m, a width of 40 ⁇ m, and a length of 60 ⁇ m.
- the metal based high-resistance material is TaN as in this case, the metal resistor portions 17 A have a resistance value of approximately 2.0 ⁇ (ohms).
- two metal resistor portions 17 A are connected in parallel, so that the resistance value of the metal resistor portion in the example of FIG. 4 is approximately 1.0 ⁇ (ohms).
- external connection bumps 19 are connected for connecting the thin-film capacitor portion 1 to an external board 4 , such as a motherboard.
- the external connection bumps 19 are solder micro bumps, or Au stud bumps, for example.
- the electric power supply paths 30 include the power supply pads 21 V, the ground pads 21 G, the bumps 22 , the first supply portions ( 11 G, 11 V) and the second supply portions ( 12 G, 12 V) of the thin-film capacitor portion 1 , and the external connection bumps 19 .
- FIG. 5 is a schematic equivalent circuit diagram of power supply impedance (impedance on the electric power supply side as seen from the LSI chip 2 ) Zs of the LSI chip 2 .
- parasitic capacitances C 1 are present between power supply voltage Vdd and ground Gnd.
- the thin-film capacitor 10 of the thin-film capacitor portion 1 is described as distributed capacitances Cs.
- parasitic capacitances C 2 are present between the power supply voltage Vdd and ground Gnd.
- parasitic inductances L 2 are present.
- the parasitic capacitances C 2 include a bypass capacitor and the like.
- a smoothing capacitor C 3 and parasitic inductances L 3 are present.
- FIGS. 6A and 6B illustrate the results of simulation of the power supply impedance Zs of the LSI chip 2 .
- FIG. 6A illustrates the case where the resistance value due to the metal resistor portions 17 and the like is assumed to be 1 ⁇ .
- FIG. 6B illustrates the case where the resistance value is assumed to be 2 ⁇ .
- the vertical axis shows the S parameter, and the linear level indicated at around ⁇ 28 dB corresponds to the power supply impedance Zs of approximately 1 ⁇ .
- FIG. 7 illustrates the results of simulation of the power supply impedance Zs in the case of only the thin-film capacitor (TFC) 10 without the metal resistor portions 17 .
- TFC thin-film capacitor
- the resistance value of the metal resistor portions 17 may be adjusted between 1 ⁇ and 2 ⁇ .
- an organic insulating film 14 is formed as a first layer (see FIG. 8A ).
- through holes 14 A are formed at positions corresponding to the electrode pads 21 of the area array type LSI chip 2 .
- the organic insulating film 14 is made from BT resin or ABF, for example.
- the second electrode layer 12 is formed, as a second layer, from a Cu thin-film by CVD, for example (see FIG. 8B ).
- the second electrode layer 12 there are formed the second supply portions (power supply voltage islands) 12 V at positions corresponding to the power supply pads 21 V of the LSI chip 2 , and the signal islands 12 S, which are rectangular in plan, at positions corresponding to the signal pads 21 S.
- the positions of the second electrode layer 12 corresponding to the ground pads 21 G of the LSI chip 2 correspond to the second supply portions 12 G.
- the dielectric layer 13 is formed, as a third layer, from a STO (SrTio3) thin-film by sputtering, for example (see FIG. 8C ).
- STO Spin-Tio3
- through holes 13 A are formed in the dielectric layer 13 .
- through holes 13 B having a rectangular cross section are formed in the dielectric layer 13 .
- the dielectric layer 13 has a thickness of 0.4 ⁇ m, for example.
- the first electrode layer 11 is formed, as a fourth layer, from a Cu thin-film by sputtering, for example (see FIG. 8D ).
- the first supply portions (ground islands) 11 G are formed at positions corresponding to the ground pads 21 G of the LSI chip 2
- the signal islands 11 S having a rectangular planar shape are formed at positions corresponding to the signal pads 21 S.
- the positions of the first electrode layer 11 corresponding to the power supply pads 21 V of the LSI chip 2 correspond to the first supply portions 11 V.
- the metal resistor portions 17 illustrated in FIG. 2 are formed by sputtering or the like.
- the organic insulating film 15 similar to the organic insulating film 14 of the first layer is fabricated as a fifth layer (see FIG. 8E ).
- the through holes 15 A having a hexagonal cross section are formed at positions corresponding to the electrode pads 21 of the LSI chip 2 . In this way, the thin-film capacitor portion 1 as illustrated in the plan view of FIG. 9 is formed.
- the thin annular metal resistor portions 17 made from NiCr (metal based high-resistance material with a volume resistivity of not smaller than 70 ⁇ cm), for example. That is, the metal resistor portions 17 are connected in series with the electric power supply paths 30 .
- the antiresonance impedance of the power supply impedance Zs of the semiconductor integrated circuit 2 can be decreased; that is to say that the power supply impedance Zs can be decreased.
- the metal resistor portions 17 because of their thin annular (thin plate-like) shape, do not readily constitute a noise emitting source at the time of high speed operation of the semiconductor integrated circuit 2 . Accordingly, in the present configuration, the power supply impedance Zs can be decreased while suppressing the generation of noise at the time of high speed operation.
- the metal resistor portions 17 are provided between the bump mounting surface 2 S of the LSI chip 2 and the thin-film capacitor portion 1 , or specifically, between the bumps 22 and the first supply portions ( 11 G, 11 V) of the first electrode layer 11 . Accordingly, the electric power supply paths 30 can be formed so as to be short, and the connection wiring for the metal resistor portions 17 can be minimized in length, whereby the generation of parasitic inductance and the like associated with the connection wiring for the metal resistor portions 17 can be suppressed.
- the metal resistor portions 17 can be formed, as pad portions for the bumps 22 connecting the thin-film capacitor portion 1 and the semiconductor integrated circuit 2 , on the first supply portions ( 11 V, 11 G) of the first electrode layer 11 of the thin-film capacitor portion 1 , using a thin-film formation technology such as sputtering. Accordingly, the formation of the metal resistor portions 17 can be performed using a similar method to the method for the thin-film capacitor portion 1 . That is, the formation of the metal resistor portions 17 can be performed easily.
- a second embodiment will be described with reference to FIG. 10 to FIG. 12 .
- components similar to those of the first embodiment are designated with similar reference symbols, and their description is omitted.
- the following embodiment differs from the first embodiment only in the position of the metal resistor portions 17 . Accordingly, only the difference will be described.
- the metal resistor portions 17 are provided in the electric power supply paths 30 between the external connection bumps (an example of “external connection portion”) 19 and the second supply portions ( 12 G, 12 V) of the second electrode layer 12 .
- the metal resistor portions 17 are provided between the power supply voltage electrode pads (an example of “second supply portion”) 12 V and the external connection bumps 19 , and between the ground electrode pads (an example of “second supply portion”) 12 G and the external connection bumps 19 .
- the external connection portions are not limited to the external connection bumps 19 .
- the external connection portions may include connection pads provided on the intermediate board for connecting the thin-film capacitor portion 1 and the intermediate board.
- results of a simulation of the power supply impedance in the second embodiment are illustrated in FIGS. 12A and 12B .
- the peak of an antiresonance point exhibited at around 60 MHz decreases as the resistance value of the metal resistor portions 17 increases, and, correspondingly, the power supply impedance Zs at 10 MHz or below increases.
- the peak of an antiresonance point exhibited at around 1.3 GHz is not much decreased.
- the metal resistor portions 17 are provided between the external connection bumps 19 and the thin-film capacitor portion 1 or, specifically, between the external connection bumps 19 and the second supply portions ( 12 G, 12 V). Accordingly, the electric power supply paths 30 can be formed so as to be short, and the connection wiring for the metal resistor portions 17 can be made short, whereby the generation of parasitic inductance and the like associated with the connection wiring for the metal resistor portions 17 can be suppressed.
- the metal resistor portions 17 can be formed on the second supply portions ( 12 G, 12 V) of the second electrode layer of the thin-film capacitor portion 1 , using a thin-film formation technology such as sputtering.
- resistors corresponding to the metal resistor portions 17 are made of a metal resistor layer 17 F provided, as illustrated in FIG. 14 , at a position of being connected in series with the thin-film capacitor 10 (Cs).
- the metal resistor layer 17 F as illustrated in FIG. 16 , is formed, in the thin-film capacitor portion 1 , on the dielectric layer 13 , which is the third layer, by sputtering a high-resistance metal oxide, for example (see FIG. 16D ).
- the metal resistor layer 17 F has a film thickness of 0.01 ⁇ m to 20 ⁇ m.
- the planar shape of the dielectric layer 13 is identical with the planar shape of the metal resistor layer 17 F.
- the first electrode layer 11 is formed as the fifth layer on the metal resistor layer 17 F.
- FIGS. 15A and 15B Results of a simulation of the power supply impedance Zs in this case are illustrated in FIGS. 15A and 15B . It has been confirmed that, compared with FIG. 7 , as the resistance value of the metal resistor portions 17 increases, the region in the high-frequency region of 10 GHz or above in which the power supply impedance Zs is not more than 1 ⁇ is extended.
- the resistors (metal resistor layer 17 F) connected in series with the thin-film capacitor 10 are formed without connection wiring.
- the metal resistor layer 17 F can be formed using the thin-film formation technology for forming the thin-film capacitor 10 , such as sputtering.
- FIG. 19 is a schematic, enlarged view illustrating the configuration of a thin-film capacitor portion 1 C according to the fourth embodiment.
- the annular (thin plate-like) metal resistor portions 17 according to the first embodiment are combined with the metal resistor layer 17 F according to the third embodiment. That is, in the fourth embodiment, as illustrated in FIG. 17 and FIG. 18 , both the metal resistor portions 17 and the metal resistor layer 17 F are provided, of which the resistance values are each 1 ⁇ . Results of a simulation of the power supply impedance Zs in this case are illustrated in FIG. 20 . It can be confirmed that, when the resistance values are 1 ⁇ , power supply impedance characteristics similar to those according to the first embodiment when the metal resistor portions 17 have 2 ⁇ can be obtained.
- the peak of the antiresonance point exhibited at around 60 MHz can be decreased to a similar degree to when the metal resistor portions 17 have 2 ⁇ , and the generation of antiresonance at around 1.3 GHz can be suppressed.
- the power supply impedance characteristics at 10 MHz or below are similar to those in FIG. 6A .
- the resistors connected in series with the thin-film capacitor 10 can be formed without connection wiring. It has also been confirmed that, by adding the metal resistor layer 17 F to the metal resistor portions 17 formed in the electric power supply paths 30 , the power supply impedance decreasing effect by the metal resistor portions 17 alone is reinforced.
- the resistors (metal resistor layer 17 F) connected in series with the thin-film capacitor 10 can be formed using the thin-film formation technology for forming the thin-film capacitor 10 , such as sputtering.
- the metal resistor portions 17 when provided between the bump mounting surface 2 S of the semiconductor integrated circuit 2 and the thin-film capacitor portion 1 , are provided between the bumps 22 and an the first supply portions ( 11 G, 11 V) of the first electrode layer 11 byway of example.
- the metal resistor portions 17 may be provided between the bumps 22 and the second supply portions ( 12 G, 12 V) of the second electrode layer 12 .
- the metal resistor portions 17 when provided between the bump mounting surface 2 S of the semiconductor integrated circuit 2 and the thin-film capacitor portion 1 , may be provided at least one of between the bumps 22 and the first supply portions ( 11 G, 11 V), and between the bumps 22 and the second supply portions ( 12 G, 12 V).
- the metal resistor portions 17 may be provided at only one of the first supply portions ( 11 G, 11 V) of the first electrode layer 11 . That is, the number of the metal resistor portions 17 provided in the electric power supply paths 30 may be determined as needed.
- the metal resistor portions 17 when provided between the bump mounting surface 2 S of the semiconductor integrated circuit 2 and the thin-film capacitor portion 1 , maybe provided at the power supply pads (first power supply pads) 21 V and the ground pads (second power supply pads) 21 G on the LSI chip 2 .
- the electric power supply paths 30 can be formed so as to be short, and the connection wiring for the metal resistor portions 17 can be minimized in length, whereby the generation of parasitic inductance and the like associated with the connection wiring for the metal resistor portions 17 can be suppressed. That is, the power supply impedance can be decreased while suppressing the generation of noise at the time of high speed operation of the LSI chip 2 .
- the metal resistor portions 17 when provided between the external connection bumps 19 and the thin-film capacitor portion 1 , are provided between the external connection bumps 19 and the first supply portions ( 12 G, 12 V) of the second electrode layer 12 by way of example.
- the metal resistor portions 17 may be provided between the external connection bumps 19 and the first supply portions ( 11 G, 11 V) of the first electrode layer 11 . That is, the metal resistor portions 17 , when provided between the external connection bumps 19 and the thin-film capacitor portion 1 , may be provided at least one of between the external connection bumps 19 and the first supply portions ( 11 G, 11 V), and between the external connection bumps 19 and the second supply portions ( 12 G, 12 V).
- the metal resistor portions 17 may be provided at only one of the second supply portions ( 12 G, 12 V) of the second electrode layer 12 . That is, the number of the metal resistor portions 17 provided in the electric power supply paths 30 may be determined as needed.
- the second embodiment may be further provided with the metal resistor layer 17 F according to the fourth embodiment.
- the metal resistor layer 17 F is formed on the dielectric layer 13 , i.e., between the first electrode layer 11 and the dielectric layer 13 by way of example. However, this is not a limitation.
- the metal resistor layer 17 F may be formed on the second electrode layer 12 , i.e., between the second electrode layer 12 and the dielectric layer 13 .
- the configuration of the semiconductor device 100 includes the thin-film capacitor portion 1 and the LSI chip 2 .
- the semiconductor device 100 may be provided with an intermediate board under the thin-film capacitor portion 1 for extending the electrode pitch of the LSI chip 2 .
- the configuration of the semiconductor device 100 includes the thin-film capacitor portion 1 and the LSI chip 2 .
- the semiconductor device 100 maybe provided with an intermediate board under the thin-film capacitor portion 1 for expanding the electrode pitch of the LSI chip 2 or, in other words, the pitch of the bumps 22 .
- the thin-film capacitor portion 1 has the same planar shape as the planar shape of the LSI chip 2 by way of example. However, this is not a limitation, and the planar shape of the thin-film capacitor portion 1 may be larger than the planar shape of the LSI chip 2 .
- the first electrode layer 11 is the electrode to which the positive power supply voltage is applied
- the second electrode layer 12 is the electrode to which the negative power supply voltage (ground voltage) is applied.
- the first electrode layer 11 may be the electrode to which the ground voltage is applied while the second electrode layer 12 maybe the electrode to which the positive power supply voltage is applied.
Abstract
Description
- The present invention relates to a semiconductor device, and more particularly to a technology for decreasing, in a semiconductor device equipped with a semiconductor integrated circuit, power supply impedance with respect to the semiconductor integrated circuit.
- Conventionally, in a semiconductor device equipped with a semiconductor integrated circuit, a technology disclosed in
Patent Document 1 is known, for example, as a technology for decreasing power supply impedance with respect to the semiconductor integrated circuit. According to the technology disclosed inPatent Document 1, the antiresonance impedance of power supply impedance is decreased by configuring a series resonance circuit from a pattern unit including three conductor patterns between a power supply terminal and a ground terminal of a semiconductor element (semiconductor integrated circuit). - Patent Document 1: Japanese Patent Application Laid-Open No. 2014-175628
- While according to the technology disclosed in
Patent Document 1, the antiresonance impedance of power supply impedance can be decreased, the series resonance circuit includes linear conductor patterns for forming an inductance component. Such linear conductor patterns may possibly constitute a noise emitting source at the time of high speed operation of the semiconductor integrated circuit where harmonic components included in the operation frequency exceed 1 GHz, and may prove disadvantageous in terms of noise suppression. Accordingly, a technology for decreasing power supply impedance while suppressing the generation of noise at the time of high speed operation is desired. - Accordingly, in the present description, there is provided a semiconductor device in which power supply impedance is decreased while the generation of noise at the time of high speed operation is suppressed.
- A semiconductor device disclosed by the present description includes a semiconductor integrated circuit having a bump mounting surface; and a thin-film capacitor portion connected to the bump mounting surface via a bump. The semiconductor integrated circuit includes a first power supply pad formed on the bump mounting surface and to which a power supply voltage of one polarity is applied, and a second power supply pad formed on the bump mounting surface and to which a power supply voltage of another polarity is applied. The thin-film capacitor portion includes a first electrode layer connected to the first power supply pad via the bump, a second electrode layer connected to the second power supply pad via the bump, and a dielectric layer formed between the first electrode layer and the second electrode layer. The semiconductor device includes: an electric power supply path including the first and second power supply pads, the bump, and the thin-film capacitor portion, and configured to supply electric power to the semiconductor integrated circuit; and a thin plate-shaped metal resistor portion provided in the electric power supply path and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer.
- According to the present configuration, in the electric power supply path including the first and second power supply pads, the bump, and the thin-film capacitor portion, there may be provided the thin plate-shaped metal resistor portion made from the metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer. That is, the metal resistor portion is connected in series with the electric power supply path. It has been confirmed through a simulation that by adjusting the resistance value of the metal resistor portion, the antiresonance impedance of the power supply impedance of the semiconductor integrated circuit can be decreased; that is to say that the power supply impedance can be decreased. In addition, the metal resistor portion, because of its thin-plate shape, does not readily constitute a noise emitting source at the time of high speed operation of the semiconductor integrated circuit. Accordingly, the present configuration can decrease the power supply impedance while suppressing the generation of noise at the time of high speed operation. The metal based high-resistance material may include metal simple substance, a metal compound, a metal oxide, and the like.
- In the semiconductor integrated circuit, the electric power supply path may include the first and second power supply pads, the bump, and the thin-film capacitor portion. The metal resistor portion may be provided between the bump mounting surface of the semiconductor integrated circuit and the thin-film capacitor portion.
- According to the present configuration, the electric power supply path can be formed so as to be short, and the connection wiring for the metal resistor portion can be minimized in length. Accordingly, the generation of parasitic inductance and the like associated with the connection wiring for the metal resistor portion can be suppressed.
- In the foregoing, the first electrode layer may include a first supply portion constituting the electric power supply path and electrically connected to the bump. The second electrode layer may include a second supply portion constituting the electric power supply path and electrically connected to the bump. The metal resistor portion may be provided at least one of between the bump and the first supply portion, and between the bump and the second supply portion.
- In this case, the metal resistor portion can be formed, as a pad portion of the bump connecting the thin-film capacitor portion and the semiconductor integrated circuit, on the first supply portion of the first electrode layer of the thin-film capacitor portion or on the second supply portion of the second electrode layer, using a thin-film formation technology, such as sputtering. Accordingly, the formation of the metal resistor portion can be performed using a similar method to the method for forming the thin-film capacitor portion. That is, the formation of the metal resistor portion can be performed easily.
- In the foregoing, alternatively, the metal resistor portion may be provided at the first power supply pad and the second power supply pad.
- In this case, the metal resistor portion is provided on the semiconductor integrated circuit side. In this configuration, also, the power supply impedance can be decreased while suppressing the generation of noise at the time of high speed operation.
- The semiconductor integrated circuit may further include an external connection portion electrically connecting, on an opposite side from the semiconductor integrated circuit, the thin-film capacitor portion to an outside. The electric power supply path may include the first and second power supply pads, the bump, the thin-film capacitor portion, and the external connection portion. The metal resistor portion may be provided between the external connection portion and the thin-film capacitor portion.
- In the present configuration, also, the electric power supply path can be formed so as to be short, and the connection wiring for the metal resistor portion can be made short. Accordingly, the generation of parasitic inductance and the like associated with the connection wiring for the metal resistor portion can be suppressed.
- In the foregoing, the first electrode layer may include a first supply portion constituting the electric power supply path and electrically connected to the bump. The second electrode layer may include a second supply portion constituting the electric power supply path and electrically connected to the bump. The metal resistor portion may be provided at least one of between the external connection portion and the first supply portion, and between the external connection portion and the second supply portion.
- In this case, also, the metal resistor portion can be formed on the first supply portion of the first electrode layer of the thin-film capacitor portion or on the second supply portion of the second electrode layer, using a thin-film formation technology, such as sputtering. It has also been confirmed through a simulation that the power supply impedance can be decreased.
- In the semiconductor integrated circuit, the thin-film capacitor portion may include a metal resistor layer formed between the first electrode layer and the dielectric layer, or between the second electrode layer and the dielectric layer, and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer.
- According to the present configuration, it can be said that, due to the metal resistor layer, the resistor connected in series with the thin-film capacitor can be formed without connection wiring. It has been confirmed that by adding the metal resistor layer to the metal resistor portion formed in the electric power supply path, the power supply impedance decreasing effect by the metal resistor portion alone is reinforced. In addition, the resistor connected in series with the thin-film capacitor can be formed using the thin-film formation technology for forming the thin-film capacitor, such as sputtering.
- In the semiconductor integrated circuit, the metal resistor portion and the metal resistor layer may have a volume resistivity of not smaller than 70 μΩcm.
- It has been confirmed through a simulation that, according to the present configuration, the power supply impedance can be decreased reliably.
- In the semiconductor integrated circuit, the thin-film capacitor may have a planar shape equal to a planar shape of the semiconductor integrated circuit.
- According to the present configuration, the capacitance of the thin-film capacitor can be maximized while the planar shape size of the semiconductor device is equal to the planar shape of the semiconductor integrated circuit.
- The semiconductor integrated circuit may be further provided with a multilayer ceramic capacitor connected in parallel with the thin-film capacitor.
- According to the present configuration, the generation of noise at the time of high speed operation can be further suppressed by the multilayer ceramic capacitor (MLCC) provided as a bypass capacitor.
- A semiconductor device disclosed by the present description includes a semiconductor integrated circuit having a bump mounting surface; and a thin-film capacitor portion connected to the bump mounting surface via a bump. The semiconductor integrated circuit includes a first power supply pad formed on the bump mounting surface and to which a power supply voltage of one polarity is applied, and a second power supply pad formed on the bump mounting surface and to which a power supply voltage of another polarity is applied. The thin-film capacitor portion includes a first electrode layer connected to the first power supply pad via the bump, a second electrode layer connected to the second power supply pad via the bump, a dielectric layer formed between the first electrode layer and the second electrode layer, and a metal resistor layer formed between the first electrode layer and the dielectric layer or between the second electrode layer and the dielectric layer, and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer.
- According to the present configuration, it can be said that due to the metal resistor layer, the resistor connected in series with the thin-film capacitor can be formed without connection wiring. It has been confirmed that the metal resistor layer decreases the power supply impedance. In addition, the resistor connected in series with the thin-film capacitor can be formed using the thin-film formation technology for forming the thin-film capacitor, such as sputtering.
- According to the present invention, power supply impedance can be decreased while the generation of noise at the time of high speed operation is suppressed.
-
FIG. 1 is a schematic cross sectional view of a semiconductor device according to a first embodiment; -
FIG. 2 is a schematic perspective view of a metal resistor portion; -
FIG. 3 is a schematic cross sectional view taken along line A-A ofFIG. 2 ; -
FIG. 4 is a schematic perspective view of another metal resistor portion; -
FIG. 5 is a schematic equivalent circuit diagram of a power supply system for the semiconductor device according to the first embodiment; -
FIGS. 6A and 6B are graphs of power supply impedance characteristics depending on the resistance value of the metal resistor portion; -
FIG. 7 is a graph of power supply impedance characteristics in the absence of the metal resistor portion; -
FIGS. 8A to 8E are schematic diagrams describing a method for fabricating a thin-film capacitor portion; -
FIG. 9 is a plan view of the thin-film capacitor portion; -
FIG. 10 is a schematic cross sectional view of a semiconductor device according to a second embodiment; -
FIG. 11 is a schematic equivalent circuit diagram of a power supply system for the semiconductor device according to the second embodiment; -
FIGS. 12A and 12B are graphs of power supply impedance characteristics depending on the resistance value of a metal resistor portion; -
FIG. 13 is a schematic cross sectional view of a semiconductor device according to a third embodiment; -
FIG. 14 is a schematic equivalent circuit diagram of a power supply system for the semiconductor device according to the third embodiment; -
FIGS. 15A and 15B are graphs of power supply impedance characteristics depending on the resistance value of the metal resistor portion; -
FIGS. 16A to 16F are schematic diagrams describing a method for fabricating a thin-film capacitor portion according to the third embodiment; -
FIG. 17 is a schematic cross sectional view of a semiconductor device according to a fourth embodiment; -
FIG. 18 is a schematic equivalent circuit diagram of a power supply system for the semiconductor device according to the fourth embodiment; -
FIG. 19 is a diagram schematically illustrating the configuration of a thin-film capacitor portion according to the fourth embodiment; and -
FIG. 20 is a graph of power supply impedance characteristics according to the fourth embodiment. - A first embodiment will be described with reference to
FIG. 1 toFIG. 9 , in which like reference symbols designate like or corresponding parts throughout the drawings. Designation of similar components with reference numerals may be omitted. - 1. Configuration of Semiconductor Device
- As illustrated in
FIG. 1 , asemiconductor device 100 generally includes a thin-film capacitor portion 1, an LSI chip (an example of “semiconductor integrated circuit”) 2, and electricpower supply paths 30. The LSI is a CPU or MPU, for example. -
FIG. 1 is a cross sectional view of thesemiconductor device 100 corresponding to the position indicated by a dot-and-dash line B-B inFIG. 9 . In the following, letter “V” suffixed to reference numerals means that the designated member and the like pertain to a positive power supply voltage (an example of “power supply voltage of one polarity”) applied to theLSI chip 2; letter “G” means that the designated member and the like pertain to a ground voltage that is a negative power supply voltage (an example of “power supply voltage of another polarity”) applied to theLSI chip 2. Letter “S” indicates a member and the like pertaining to signals input to or output from theLSI chip 2. - The
LSI chip 2 according to the present embodiment is an area array type LSI (seeFIG. 9 ) and, as illustrated inFIG. 1 , includes abump mounting surface 2S. On thebump mounting surface 2S, a plurality of electrode pads 21 is formed. The electrode pads 21 include power supply pads for power supply voltage (an example of “first power supply pads”) 21V; ground pads for ground voltage (an example of “second power supply pads”) 21G; andsignal pads 21S. On each of the electrode pads 21, abump 22 for connecting theLSI chip 2 and the thin-film capacitor portion 1 is formed. Thebumps 22 according to the present embodiment are gold (Au) stud bumps, for example. - The thin-
film capacitor portion 1, as illustrated inFIG. 1 , includes a thin-film capacitor 10; organic insulatinglayers metal resistor portions 17. - The thin-
film capacitor portion 1 includes afirst electrode layer 11 connected to thepower supply pads 21V via thebumps 22; asecond electrode layer 12 connected to theground pads 21G via thebumps 22; and adielectric layer 13 formed between thefirst electrode layer 11 and thesecond electrode layer 12. Thefirst electrode layer 11 and thesecond electrode layer 12 are made of a copper (Cu) thin-film, for example. Thedielectric layer 13 is made of a strontium titanate (STO) film, for example. - The
first electrode layer 11 includes afirst electrode portion 11C constituting one electrode of the thin-film capacitor 10, and first supply portions (11G, 11V) constituting the electricpower supply paths 30. Thesecond electrode layer 12 includes asecond electrode portion 12C constituting the other electrode of the thin-film capacitor 10, and second supply portions (12G, 12V) constituting the electricpower supply paths 30. The thin-film capacitor 10 includes thefirst electrode portion 11C, thesecond electrode layer 12, and thesecond electrode portion 12C. - The thin-
film capacitor portion 1 has a planar shape equal to a planar shape of theLSI chip 2. In other words, the planar shape of the thin-film capacitor 10 is equal to the planar shape of theLSI chip 2. Accordingly, the capacitance of the thin-film capacitor 10 can be maximized while the planar shape size of thesemiconductor device 100 is equal to the planar shape of theLSI chip 2. - According to the first embodiment, the
metal resistor portions 17 are provided on the first supply portions (11G, 11V) of thefirst electrode layer 11, as illustrated inFIG. 1 . That is, according to the first embodiment, themetal resistor portions 17 are provided between thebump mounting surface 2S of theLSI chip 2 and the thin-film capacitor portion 1. - The
metal resistor portions 17 are made from a metal based high-resistance material and have a thin-plate shape. In the first embodiment, specifically, as illustrated inFIG. 2 andFIG. 3 , themetal resistor portions 17 are made of an annular metal thin plate. Themetal resistor portions 17 are made from a metal based high-resistance material with a volume resistivity higher than the volume resistivity of thefirst electrode layer 11 and thesecond electrode layer 12. For example, themetal resistor portions 17 are made from tantalum nitride (TaN). - Specifically, the
metal resistor portion 17, as illustrated inFIG. 2 andFIG. 3 , have a thickness of 0.05 micrometers (μm), for example, and corresponds to a region (annular region) between a circle with a diameter of 20 μm and a circle with a diameter of 50 μm. If the volume resistivity of TaN is 135 μΩ·cm, the annularmetal resistor portion 17 has a resistance value of approximately 1.4 ohms (Ω). - In this case, the upper surface of the metal resistor portion 17 (
bumps 22 connecting surface), as illustrated inFIG. 2 , is flash-coated with afilm 18 of highly conductive metal (such as Au or Pt) having a diameter of 40 μm and a film thickness on the order of 0.1 μm, for example. The upper surface of thefirst supply portion 11G of thefirst electrode layer 11 is also flash-coated with aconductive film 18A of Au, for example, having a diameter of 40 μm and a film thickness on the order of 0.1 μm, for example. The resistance value of themetal resistor portion 17 can be controlled depending on the material, film thickness, and the like of themetal films - On the
conductive film 18A, there is formed an insulating film 16 (for example, an organic insulating film of polyimide, bismaleimide-triazine (BT) resin, or Ajinomoto Build-up Film (ABF)) having a diameter of 50 μm and a film thickness on the order of 15 μm. On theconductive film 18A and the insulatingfilm 16, themetal resistor portions 17 are formed by sputtering TaN. In this case, the TaN on the insulatingfilm 16 corresponds to themetal resistor portions 17, of which the thickness is 0.05 μm, for example. - The metal based high-resistance material of the
metal resistor portions 17 is not limited to TaN, and may preferably be a material with a volume resistivity of not less than 70 μΩ·cm. Examples of the metal based high-resistance material include nichrome (NiCr), SUS304 (stainless steel), CuMn7Sn (copper manganese tin), NCF800 (stainless steel), and bismuth (Bi). The thin-plate shape of themetal resistor portions 17 is not limited to the annular shape, as illustrated inFIG. 2 . - For example, as illustrated in
FIG. 4 , the shape of themetal resistor portions 17 may be rectangular as viewed in plan. In this case, also, themetal resistor portions 17 are formed on theconductive film 18A and the insulatingfilm 16 by sputtering TaN, for example, where the TaN on the insulatingfilm 16 corresponds to themetal resistor portions 17A. In this case, as illustrated inFIG. 4 , themetal resistor portions 17 have the shape of a thin plate with a thickness of 1.0 μm, a width of 40 μm, and a length of 60 μm. When the metal based high-resistance material is TaN as in this case, themetal resistor portions 17A have a resistance value of approximately 2.0 Ω(ohms). In the example ofFIG. 4 , twometal resistor portions 17A are connected in parallel, so that the resistance value of the metal resistor portion in the example ofFIG. 4 is approximately 1.0 Ω(ohms). - To the
second electrode layer 12 of the thin-film capacitor portion 1, external connection bumps 19 are connected for connecting the thin-film capacitor portion 1 to anexternal board 4, such as a motherboard. The external connection bumps 19 are solder micro bumps, or Au stud bumps, for example. - The electric
power supply paths 30 include thepower supply pads 21V, theground pads 21G, thebumps 22, the first supply portions (11G, 11V) and the second supply portions (12G, 12V) of the thin-film capacitor portion 1, and the external connection bumps 19. - 2. Simulation of Power Supply Impedance
-
FIG. 5 is a schematic equivalent circuit diagram of power supply impedance (impedance on the electric power supply side as seen from the LSI chip 2) Zs of theLSI chip 2. In theLSI chip 2, parasitic capacitances C1 are present between power supply voltage Vdd and ground Gnd. - The thin-film capacitor 10 of the thin-
film capacitor portion 1 is described as distributed capacitances Cs. In apackage 3 of thesemiconductor device 100, parasitic capacitances C2 are present between the power supply voltage Vdd and ground Gnd. In power supply lines and ground lines, parasitic inductances L2 are present. The parasitic capacitances C2 include a bypass capacitor and the like. - In a power supply board (such as a motherboard) 4 including a power supply Vs that supplies electric power to the
semiconductor device 100, a smoothing capacitor C3 and parasitic inductances L3 are present. - On the basis of such equivalent circuit,
FIGS. 6A and 6B illustrate the results of simulation of the power supply impedance Zs of theLSI chip 2.FIG. 6A illustrates the case where the resistance value due to themetal resistor portions 17 and the like is assumed to be 1Ω.FIG. 6B illustrates the case where the resistance value is assumed to be 2Ω. InFIG. 6 , the vertical axis shows the S parameter, and the linear level indicated at around −28 dB corresponds to the power supply impedance Zs of approximately 1Ω. -
FIG. 7 illustrates the results of simulation of the power supply impedance Zs in the case of only the thin-film capacitor (TFC) 10 without themetal resistor portions 17. Compared withFIG. 7 , when themetal resistor portions 17 are provided, the peak of an antiresonance point exhibited at around 60 MHz is lowered as the resistance value of themetal resistor portions 17 increases, and, correspondingly, the power supply impedance Zs at 10 MHz or below increases. In addition, the antiresonance caused at around 1.3 GHz inFIG. 7 is suppressed. Also, in a high-frequency region of 10 GHz or above, the region in which the power supply impedance Zs is not more than 1Ω is extended. It has been learned from the simulation results that, in the configuration of the first embodiment, in order to decrease the power supply impedance Zs (for example, 1Ω or below) in the entire frequency bandwidth, and to lower the peak of the antiresonance point, the resistance value of themetal resistor portions 17 may be adjusted between 1Ω and 2Ω. - 3. Method for Fabricating Thin-Film Capacitor Portion
- With reference to
FIG. 8 , a method for fabricating the thin-film capacitor portion 1 will be described. First, an organic insulatingfilm 14 is formed as a first layer (seeFIG. 8A ). In the organic insulatingfilm 14, throughholes 14A are formed at positions corresponding to the electrode pads 21 of the area arraytype LSI chip 2. The organic insulatingfilm 14 is made from BT resin or ABF, for example. - Then, on the organic insulating
film 14, thesecond electrode layer 12 is formed, as a second layer, from a Cu thin-film by CVD, for example (seeFIG. 8B ). In thesecond electrode layer 12, there are formed the second supply portions (power supply voltage islands) 12V at positions corresponding to thepower supply pads 21V of theLSI chip 2, and thesignal islands 12S, which are rectangular in plan, at positions corresponding to thesignal pads 21S. The positions of thesecond electrode layer 12 corresponding to theground pads 21G of theLSI chip 2 correspond to thesecond supply portions 12G. - Then, on the
second electrode layer 12, thedielectric layer 13 is formed, as a third layer, from a STO (SrTio3) thin-film by sputtering, for example (seeFIG. 8C ). In thedielectric layer 13, at positions corresponding to the electrode pads 21 of theLSI chip 2, throughholes 13A are formed. At positions corresponding to thesignal pads 21S, throughholes 13B having a rectangular cross section are formed. Thedielectric layer 13 has a thickness of 0.4 μm, for example. - Then, on the
dielectric layer 13, thefirst electrode layer 11 is formed, as a fourth layer, from a Cu thin-film by sputtering, for example (seeFIG. 8D ). In thefirst electrode layer 11, the first supply portions (ground islands) 11G are formed at positions corresponding to theground pads 21G of theLSI chip 2, and thesignal islands 11S having a rectangular planar shape are formed at positions corresponding to thesignal pads 21S. The positions of thefirst electrode layer 11 corresponding to thepower supply pads 21V of theLSI chip 2 correspond to thefirst supply portions 11V. On thefirst supply portions metal resistor portions 17 illustrated inFIG. 2 are formed by sputtering or the like. - Then, on the
first electrode layer 11, the organic insulatingfilm 15 similar to the organic insulatingfilm 14 of the first layer is fabricated as a fifth layer (seeFIG. 8E ). In the organic insulatingfilm 15, the throughholes 15A having a hexagonal cross section are formed at positions corresponding to the electrode pads 21 of theLSI chip 2. In this way, the thin-film capacitor portion 1 as illustrated in the plan view ofFIG. 9 is formed. - 4. Effects of First Embodiment
- In the electric
power supply paths 30 including thepower supply pads 21V, theground pads 21G, thebumps 22, and the thin-film capacitor portion 1, there are provided the thin annularmetal resistor portions 17 made from NiCr (metal based high-resistance material with a volume resistivity of not smaller than 70 μ·cm), for example. That is, themetal resistor portions 17 are connected in series with the electricpower supply paths 30. - It has been confirmed through the simulation that, by adjusting the resistance value of the
metal resistor portions 17, the antiresonance impedance of the power supply impedance Zs of the semiconductor integratedcircuit 2 can be decreased; that is to say that the power supply impedance Zs can be decreased. Themetal resistor portions 17, because of their thin annular (thin plate-like) shape, do not readily constitute a noise emitting source at the time of high speed operation of the semiconductor integratedcircuit 2. Accordingly, in the present configuration, the power supply impedance Zs can be decreased while suppressing the generation of noise at the time of high speed operation. - The
metal resistor portions 17 are provided between thebump mounting surface 2S of theLSI chip 2 and the thin-film capacitor portion 1, or specifically, between thebumps 22 and the first supply portions (11G, 11V) of thefirst electrode layer 11. Accordingly, the electricpower supply paths 30 can be formed so as to be short, and the connection wiring for themetal resistor portions 17 can be minimized in length, whereby the generation of parasitic inductance and the like associated with the connection wiring for themetal resistor portions 17 can be suppressed. In addition, themetal resistor portions 17 can be formed, as pad portions for thebumps 22 connecting the thin-film capacitor portion 1 and the semiconductor integratedcircuit 2, on the first supply portions (11V, 11G) of thefirst electrode layer 11 of the thin-film capacitor portion 1, using a thin-film formation technology such as sputtering. Accordingly, the formation of themetal resistor portions 17 can be performed using a similar method to the method for the thin-film capacitor portion 1. That is, the formation of themetal resistor portions 17 can be performed easily. - A second embodiment will be described with reference to
FIG. 10 toFIG. 12 . In the following embodiment, components similar to those of the first embodiment are designated with similar reference symbols, and their description is omitted. The following embodiment differs from the first embodiment only in the position of themetal resistor portions 17. Accordingly, only the difference will be described. - In a
semiconductor device 100A according to the second embodiment, as illustrated inFIG. 10 andFIG. 11 , themetal resistor portions 17 are provided in the electricpower supply paths 30 between the external connection bumps (an example of “external connection portion”) 19 and the second supply portions (12G, 12V) of thesecond electrode layer 12. Specifically, themetal resistor portions 17 are provided between the power supply voltage electrode pads (an example of “second supply portion”) 12V and the external connection bumps 19, and between the ground electrode pads (an example of “second supply portion”) 12G and the external connection bumps 19. - The external connection portions are not limited to the external connection bumps 19. For example, when the
semiconductor device 100A is provided with an intermediate board under the thin-film capacitor portion 1 for expanding the electrode pitch of theLSI chip 2, the external connection portions may include connection pads provided on the intermediate board for connecting the thin-film capacitor portion 1 and the intermediate board. - Results of a simulation of the power supply impedance in the second embodiment are illustrated in
FIGS. 12A and 12B . As in the first embodiment, the peak of an antiresonance point exhibited at around 60 MHz decreases as the resistance value of themetal resistor portions 17 increases, and, correspondingly, the power supply impedance Zs at 10 MHz or below increases. In the configuration of the second embodiment, the peak of an antiresonance point exhibited at around 1.3 GHz is not much decreased. - 5. Effects of Second Embodiment
- As illustrated in
FIGS. 12A and 12B , it has been confirmed through the simulation that the power supply impedance Zs can be decreased by means of themetal resistor portions 17. - The
metal resistor portions 17 are provided between the external connection bumps 19 and the thin-film capacitor portion 1 or, specifically, between the external connection bumps 19 and the second supply portions (12G, 12V). Accordingly, the electricpower supply paths 30 can be formed so as to be short, and the connection wiring for themetal resistor portions 17 can be made short, whereby the generation of parasitic inductance and the like associated with the connection wiring for themetal resistor portions 17 can be suppressed. In addition, themetal resistor portions 17 can be formed on the second supply portions (12G, 12V) of the second electrode layer of the thin-film capacitor portion 1, using a thin-film formation technology such as sputtering. - A third embodiment will be described with reference to
FIG. 13 toFIG. 16 . In asemiconductor device 100B according to the third embodiment, resistors corresponding to themetal resistor portions 17 are made of ametal resistor layer 17F provided, as illustrated inFIG. 14 , at a position of being connected in series with the thin-film capacitor 10 (Cs). Specifically, themetal resistor layer 17F, as illustrated inFIG. 16 , is formed, in the thin-film capacitor portion 1, on thedielectric layer 13, which is the third layer, by sputtering a high-resistance metal oxide, for example (seeFIG. 16D ). Themetal resistor layer 17F has a film thickness of 0.01 μm to 20 μm. As illustrated inFIG. 16C and 16D , the planar shape of thedielectric layer 13 is identical with the planar shape of themetal resistor layer 17F. According to the third embodiment, thefirst electrode layer 11 is formed as the fifth layer on themetal resistor layer 17F. - Results of a simulation of the power supply impedance Zs in this case are illustrated in
FIGS. 15A and 15B . It has been confirmed that, compared withFIG. 7 , as the resistance value of themetal resistor portions 17 increases, the region in the high-frequency region of 10 GHz or above in which the power supply impedance Zs is not more than 1Ω is extended. - 6. Effects of Third Embodiment
- It has been confirmed through the simulation that, by means of the
metal resistor layer 17F, the region in the high-frequency region of 10 GHz or above in which the power supply impedance Zs is not more than 1Ω is extended, that is, that the power supply impedance is decreased. - It can also be said that the resistors (
metal resistor layer 17F) connected in series with the thin-film capacitor 10 are formed without connection wiring. In addition, themetal resistor layer 17F can be formed using the thin-film formation technology for forming the thin-film capacitor 10, such as sputtering. - A fourth embodiment will be described with reference to
FIG. 17 toFIG. 20 .FIG. 19 is a schematic, enlarged view illustrating the configuration of a thin-film capacitor portion 1C according to the fourth embodiment. - In the semiconductor device 100C according to the fourth embodiment, the annular (thin plate-like)
metal resistor portions 17 according to the first embodiment are combined with themetal resistor layer 17F according to the third embodiment. That is, in the fourth embodiment, as illustrated inFIG. 17 andFIG. 18 , both themetal resistor portions 17 and themetal resistor layer 17F are provided, of which the resistance values are each 1Ω. Results of a simulation of the power supply impedance Zs in this case are illustrated inFIG. 20 . It can be confirmed that, when the resistance values are 1Ω, power supply impedance characteristics similar to those according to the first embodiment when themetal resistor portions 17 have 2Ω can be obtained. That is, the peak of the antiresonance point exhibited at around 60 MHz can be decreased to a similar degree to when themetal resistor portions 17 have 2Ω, and the generation of antiresonance at around 1.3 GHz can be suppressed. In addition, the power supply impedance characteristics at 10 MHz or below are similar to those inFIG. 6A . - 7. Effects of Fourth Embodiment
- It can be said that by means of the
metal resistor layer 17F, the resistors connected in series with the thin-film capacitor 10 can be formed without connection wiring. It has also been confirmed that, by adding themetal resistor layer 17F to themetal resistor portions 17 formed in the electricpower supply paths 30, the power supply impedance decreasing effect by themetal resistor portions 17 alone is reinforced. In addition, the resistors (metal resistor layer 17F) connected in series with the thin-film capacitor 10 can be formed using the thin-film formation technology for forming the thin-film capacitor 10, such as sputtering. - The present invention is not limited to the embodiments described in the above description and the drawings, and may include the following embodiments in the technical scope of the present invention.
- (1) In the first embodiment, the
metal resistor portions 17, when provided between thebump mounting surface 2S of the semiconductor integratedcircuit 2 and the thin-film capacitor portion 1, are provided between thebumps 22 and an the first supply portions (11G, 11V) of thefirst electrode layer 11 byway of example. However, this is not a limitation. For example, themetal resistor portions 17 may be provided between thebumps 22 and the second supply portions (12G, 12V) of thesecond electrode layer 12. That is, themetal resistor portions 17, when provided between thebump mounting surface 2S of the semiconductor integratedcircuit 2 and the thin-film capacitor portion 1, may be provided at least one of between thebumps 22 and the first supply portions (11G, 11V), and between thebumps 22 and the second supply portions (12G, 12V). - In the first embodiment, the
metal resistor portions 17 may be provided at only one of the first supply portions (11G, 11V) of thefirst electrode layer 11. That is, the number of themetal resistor portions 17 provided in the electricpower supply paths 30 may be determined as needed. - (2) In the first embodiment, further, the
metal resistor portions 17, when provided between thebump mounting surface 2S of the semiconductor integratedcircuit 2 and the thin-film capacitor portion 1, maybe provided at the power supply pads (first power supply pads) 21V and the ground pads (second power supply pads) 21G on theLSI chip 2. In this case, also, the electricpower supply paths 30 can be formed so as to be short, and the connection wiring for themetal resistor portions 17 can be minimized in length, whereby the generation of parasitic inductance and the like associated with the connection wiring for themetal resistor portions 17 can be suppressed. That is, the power supply impedance can be decreased while suppressing the generation of noise at the time of high speed operation of theLSI chip 2. - (3) In the second embodiment, the
metal resistor portions 17, when provided between the external connection bumps 19 and the thin-film capacitor portion 1, are provided between the external connection bumps 19 and the first supply portions (12G, 12V) of thesecond electrode layer 12 by way of example. However, this is not a limitation. For example, themetal resistor portions 17 may be provided between the external connection bumps 19 and the first supply portions (11G, 11V) of thefirst electrode layer 11. That is, themetal resistor portions 17, when provided between the external connection bumps 19 and the thin-film capacitor portion 1, may be provided at least one of between the external connection bumps 19 and the first supply portions (11G, 11V), and between the external connection bumps 19 and the second supply portions (12G, 12V). - In the second embodiment, the
metal resistor portions 17 may be provided at only one of the second supply portions (12G, 12V) of thesecond electrode layer 12. That is, the number of themetal resistor portions 17 provided in the electricpower supply paths 30 may be determined as needed. In addition, the second embodiment may be further provided with themetal resistor layer 17F according to the fourth embodiment. - (4) In the third embodiment and the fourth embodiment, the
metal resistor layer 17F is formed on thedielectric layer 13, i.e., between thefirst electrode layer 11 and thedielectric layer 13 by way of example. However, this is not a limitation. Themetal resistor layer 17F may be formed on thesecond electrode layer 12, i.e., between thesecond electrode layer 12 and thedielectric layer 13. - (5) In the foregoing embodiments, the configuration of the
semiconductor device 100 includes the thin-film capacitor portion 1 and theLSI chip 2. However, this is not a limitation, and thesemiconductor device 100 may be provided with an intermediate board under the thin-film capacitor portion 1 for extending the electrode pitch of theLSI chip 2. - (6) In the foregoing embodiments, the configuration of the
semiconductor device 100 includes the thin-film capacitor portion 1 and theLSI chip 2. However, this is not a limitation, and for example, thesemiconductor device 100 maybe provided with an intermediate board under the thin-film capacitor portion 1 for expanding the electrode pitch of theLSI chip 2 or, in other words, the pitch of thebumps 22. - (7) In the foregoing embodiments, the thin-
film capacitor portion 1 has the same planar shape as the planar shape of theLSI chip 2 by way of example. However, this is not a limitation, and the planar shape of the thin-film capacitor portion 1 may be larger than the planar shape of theLSI chip 2. - (8) In the foregoing embodiments, the
first electrode layer 11 is the electrode to which the positive power supply voltage is applied, while thesecond electrode layer 12 is the electrode to which the negative power supply voltage (ground voltage) is applied. However, this is not a limitation, and the reverse may be the case. That is, thefirst electrode layer 11 may be the electrode to which the ground voltage is applied while thesecond electrode layer 12 maybe the electrode to which the positive power supply voltage is applied. -
- 1: Thin-film capacitor portion
- 2: LSI chip (Semiconductor integrated circuit)
- 2S: Bump mounting surface
- 10: Thin-film capacitor
- 11: First electrode layer
- 11G, 11V: First supply portion
- 12: Second electrode layer
- 12G, 12V: Second supply portion
- 13: Dielectric layer
- 17: Metal resistor portion
- 17F: Metal resistor layer
- 19: Micro solder ball
- 22: Bump
- 21G: Ground pad (Second power supply pad)
- 21V: Power supply pad (First power supply pad)
- 30: Electric power supply path
- 100: Semiconductor device
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-
2015
- 2015-11-13 JP JP2016507938A patent/JP5974421B1/en not_active Expired - Fee Related
- 2015-11-13 US US15/300,603 patent/US9761544B1/en not_active Expired - Fee Related
- 2015-11-13 KR KR1020167027133A patent/KR101703261B1/en active IP Right Grant
- 2015-11-13 CN CN201580016424.XA patent/CN107210262B/en not_active Expired - Fee Related
- 2015-11-13 WO PCT/JP2015/082028 patent/WO2017081823A1/en active Application Filing
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Also Published As
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WO2017081823A1 (en) | 2017-05-18 |
CN107210262A (en) | 2017-09-26 |
TW201717344A (en) | 2017-05-16 |
US9761544B1 (en) | 2017-09-12 |
TWI582931B (en) | 2017-05-11 |
JP5974421B1 (en) | 2016-08-23 |
CN107210262B (en) | 2018-12-28 |
JPWO2017081823A1 (en) | 2017-11-16 |
KR101703261B1 (en) | 2017-02-06 |
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