US20170148985A1

US20170148985A1 - Semiconductor apparatus and method for fabricating the same

Info

Publication number: US20170148985A1
Application number: US15/423,201
Authority: US
Inventors: Hae Chan PARK
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2014-06-24
Filing date: 2017-02-02
Publication date: 2017-05-25
Also published as: US9601691B2; KR20160000299A; US20150372059A1

Abstract

A semiconductor apparatus includes a variable resistor including a variable resistance layer, which is formed to surround on an inner surface of a resistive region, and an insert layer which is formed in the variable resistance layer and has a resistivity being different from that of the variable resistance layer.

Description

CROSS-REFERENCES TO RELATED APPLICATION

This application claims priority under 35 U.S.C. 119(a) to Korean application No. 10-2014-0077504, filed on Jun. 24, 2014, which is incorporated by reference in its entirety.

BACKGROUND

1. Technical Field
Various embodiments of the inventive concept relate to a semiconductor apparatus having variable resistance characteristics, and a method for fabricating the same.
2. Related Art
With the rapid development of mobile and digital information communication and the consumer-electronics industry, studies on existing electronic charge-controlled devices have encountered limitations. Thus, new functional memory devices other than the existing electronic charge-controlled devices need to be developed. In particular, next-generation memory devices with large capacity, ultra-high speed, and ultra-low power consumption need to be developed to satisfy the demand of large capacity memories in main information apparatuses.
Variable resistive memory devices, which use resistive properties as a memory medium, have been suggested as the next-generation of memory devices. Typical examples of variable resistance memory devices are resistive random access memories (ReRAMs), phase-change RAMs (PCRAMs), magneto-resistive RAMs (MRAMs), and spin-transfer torque magnetoresistive RAMs (STTMRAMs).
Each of the variable resistive memory devices may include a switch and a resistor, and store data “0” or “1” according to the state of the resistor.
In particular, the PCRAM may include a phase-change material which is stabilized to either a crystalline state or an amorphous state by heat and has a switching characteristic between the different resistive states. For example, the phase-change material may be a chalcogenide material, such as germanium-antimony-tellurium (Ge—Sb—Te, GST).
A resistance of the conventional resistive element, such as a variable resistance layer, increases over time. Thus, there is high demand for a method for avoiding the resistance of the variable resistance layer increase over time.

SUMMARY

According to an embodiment of the present invention, a semiconductor apparatus may include a variable resistor including a variable resistance layer, which is formed to surround on an inner surface of a resistive region, and an insert layer which is formed in the variable resistance layer and has a resistivity being different from that of the variable resistance layer.
According to an embodiment of the present invention a method for fabricating a semiconductor apparatus may include forming a resistive region, forming a variable resistor in the resistive region. The forming of the variable resistor includes forming a variable resistance material on an inner surface of the resistive region, forming an insert material has a resistivity being different from that of the variable resistance material and is in the variable resistance material and forming a variable resistance layer and an insert layer by etching back the variable resistance material and the insert material to a predetermined height.
These and other features, aspects, and embodiments are described below.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view illustrating a semiconductor apparatus according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view illustrating a method for fabricating a semiconductor apparatus according to an embodiment of the present invention;

FIG. 3 is a cross-sectional view illustrating a method for fabricating a semiconductor apparatus according to an embodiment of the present invention;

FIG. 4 is a cross-sectional view illustrating a method for fabricating a semiconductor apparatus according to an embodiment of the present invention;

FIG. 5 is a cross-sectional view illustrating a method for fabricating a semiconductor apparatus according to an embodiment of the present invention;

FIG. 6 is a cross-sectional view illustrating a method for fabricating a semiconductor apparatus according to an embodiment of the present invention;

FIG. 7 is a cross-sectional view illustrating a method for fabricating a semiconductor apparatus according to an embodiment of the present invention;

FIG. 8 is a cross-sectional view illustrating a method for fabricating a semiconductor apparatus according to an embodiment of the present invention;

FIG. 9 is a view illustrating resistance drift of different semiconductor apparatuses including an embodiment of the present invention;

FIG. 10 is an equipvalent circuit diagram illustrating a variable resistor of a semiconductor apparatus according to an embodiment of the present invention;

FIG. 11 is a cross-sectional view illustrating a semiconductor apparatus according to another embodiment of the present invention;

FIG. 12 is a perspective view illustrating a portion of a semiconductor apparatus according to an embodiment of the present invention; and

FIG. 13 is a perspective view illustrating a portion of a semiconductor apparatus according to another embodiment of the present invention.

DETAILED DESCRIPTION

Exemplary embodiments will be described in greater detail with reference to the accompanying drawings. Variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes illustrated, but may include deviations in shapes that result, for example, from manufacturing and even design. In the drawings, lengths, widths, and heights of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements. It is also understood that when a layer is referred to as being “on” another layer or substrate, it may be directly on the layer or substrate, or intervening layers may be present. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form, and vice versa, as long as it is not specifically mentioned.
The present invention is described herein through the use of preferred embodiments. However, the present invention should not be construed as limited to the disclosed embodiments. It should be appreciated by those of ordinary skill in the art that changes may be made to these exemplary embodiments without departing from the principles and spirit of the present invention. Finally, in this document, all “embodiment(s)” refer to embodiments of the present invention or the disclosed inventive concept, unless stated otherwise.
Referring to FIGS. 1 and 11, a semiconductor apparatus having resistance variable characteristics may include a lower electrode 30, a variable resistor 60, and an upper electrode 70.
The lower electrode 30 may be formed in a first insulating layer 20, formed on a semiconductor substrate 10, which is a base insulating layer. A switch (not shown) may be formed in the semiconductor substrate 10 and the first insulating layer 20. The lower electrode 30 may include a doped polysilicon layer or a metal material having high resistivity.
The variable resistor 60 may include a variable resistance layer 61 a and an insert layer 63 a.
The variable resistance layer 61 a may be formed of a variable resistance material. The variable resistance material may include various materials, such as, a PCMO (Pr_1-xCa_xMnO₃) layer for a ReRAM, a chalcogenide layer for a PCRAM, a magnetic layer for a MRAM, a magnetization reversal device layer for a spin-transfer torque magnetoresistive RAM (STTMRAM), or a polymer layer for a polymer RAM (PoRAM). However, the material for the variable resistance layer is not limited thereto, and may include any material having variable resistance characteristics which are suitable for switching between different resistive states by applying a voltage or current.
For example, the variable resistance material may include a phase-change material. The phase-change material may be a chalcogenide material, such as, GST (Ge—Sb—Te). The variable resistance layer 61 a including the phase-change material may be stabilized to either a crystalline state or an amorphous state by heat. This state change is responsible for the difference in resistive states.
The variable resistance layer 61 a may be formed in a second insulating layer 40 and on the lower electrode 30. The second insulating layer 40 may include a variable resistor region in which the variable resistor 60 is formed, and the variable resistor region may form of a hole (see 45 of FIG. 2) exposing the lower electrode 30. The variable resistance layer 61 a may be formed by a thin film on an inner surface of the variable resistor region in the second insulating layer 40.
The insert layer 63 a may be formed in a space surrounded with the variable resistance layer 61 a. That is, when the variable resistance layer 61 a is formed in a thin film form in the hole 45, a space may be formed in the variable resistance layer 61 a, and an insert material may be deposited in the empty space to form the insert layer 63 a. The insert layer 63 a may be formed to have substantially the same height as the variable resistance layer 61 a. A bottom of the insert layer 63 a may be located higher than that of the variable resistance layer 61 a.
The insert layer 63 a may include a catalyst layer. The catalyst layer may include at least one of an aluminum nitride (AlN) layer, a boron nitride (BN) layer, an aluminum oxide (AlO) layer, a tantalum nitride (TaN) layer, a tungsten (W) layer, a tungsten nitride (WN) layer, a cobalt tungsten (CoW) layer, a nickel tungsten (NiW) layer, and an yttrium oxide layer.
The upper electrode 70 may be formed on the variable resistance layer 61 a and the insert layer 63 a. Specifically, the upper electrode 70 may be formed to cover upper surfaces of the variable resistance layer 61 a and the insert layer 63 a and to surround a portion of a lateral surface of the variable resistance layer 61 a bordering the upper surface of the variable resistance layer 61 a.
In the semiconductor apparatus having the above-described structure, the insert layer 63 a is formed in the variable resistance layer 61 a which is formed by a thin film, and thus the variable resistance layer 61 a may be formed without defects such as voids or seams.
A method for fabricating a semiconductor apparatus according to an embodiment of the present invention will be described with reference to FIGS. 2 to 8.
Referring to FIG. 2, a base insulating layer 20 is formed on a semiconductor substrate 10 including a switching layer (not shown), and a contact hole 25 is formed by etching a predetermined portion of the base insulating layer 20. A lower electrode 30 is formed by filling the contact hole 25 with a conductive material. The lower electrode 30 may be electrically coupled to the switching layer.
An interlayer insulating layer 40 is formed on the semiconductor substrate on which the lower electrode 30 is formed. A hole 45 is formed to expose a surface of the lower electrode 30 by etching the interlayer insulating layer 40.
Referring to FIG. 3, an insulating material is deposited on the semiconductor substrate in which the hole 45 is formed, to gap-fill the hole 45. The insulating material is recessed by a predetermined thickness in such a manner that a gap-fill insulating layer 50 having a predetermined height is left in a lower portion of the hole 45. The gap-fill insulating layer 50 may be a spin on dielectric (SOD) layer, but the material for the gap-fill insulating layer 50 is not limited thereto. Through the recess process on the gap-fill insulating layer 50, an upper sidewall of the hole 45 is exposed.
Referring to FIG. 4, a conductive material is deposited on the gap-fill insulating layer 50 then spacer-etched to form a first upper electrode 71 on an upper inner sidewall of the hole 45. The first upper electrode 71 functions to surround a portion of a lateral surface of a variable resistance layer 61 a to be described later.
Referring to FIG. 5, the gap-fill insulating layer 50 shown in FIG. 4, is removed and a variable resistance material 61 is deposited in the hole 45 in which the first upper electrode 71 is left. In the process of forming the variable resistance material 61, the variable resistance material 61 may be deposited in a thin film form on an inner surface of the hole 45 through an atomic layer deposition (ALD) method. For example, the variable resistance material 61 may be deposited in a temperature range of 200 to 400° C. The ALD-variable resistance material 61 may have an amorphous phase.
As the variable resistance material 61 is deposited in a thin film form in the hole 45, an empty space 61 b may be formed in the variable resistance material 61.
Referring to FIG. 6, an insert material 63 is deposited in the empty space (see 61 b of FIG. 5) of the variable resistance material 61. The insert material 63 may be deposited through an ALD method. The insert material 63 may include at least one of an aluminum nitride (AIN) layer, a boron nitride (BN) layer, an aluminum oxide (AlO) layer, a tantalum nitride (TaN) layer, a tungsten (W) layer, a tungsten nitride (WN) layer, a cobalt tungsten (CoW) layer, a nickel tungsten (NiW) layer, and an yttrium oxide layer.
Referring to FIG. 7, the variable resistance material 61 and the insert material 63 are etched back to a predetermined height to form a region for an upper electrode (see 70 of FIG. 8) as well as a variable resistor 60 including the variable resistance layer 61 a and an insert layer 63 a.
Referring to FIG. 8, after the variable resistor 60 is formed, a second upper electrode 73 is formed through a process of gap-filling a region from which the variable resistance material 61 and the insert material 63 were etched back in FIG. 7, with a conductive material, and planarizing the conductive material. The upper electrode 70 may include a second upper electrode 73 together with a first upper electrode 71, which was previously formed. That is, the upper electrode 70 may include the first electrode 71 surrounding a portion of a lateral surface of the variable resistance layer 61 a and bordering an upper surface thereof, and the second upper electrode 73 covering the upper surfaces of the variable resistance layer 61 a and the insert layer 63 a. As the contact area between the upper electrode 70 and the variable resistor 60 is increased, contact resistance between the upper electrode 70 and the variable resistor 60 may be reduced, thus current efficiency may be improved.
Referring to FIG. 9, (a) indicates resistance drift of a conventional variable resistance layer, that is, resistance change over time, (b) indicates resistance drift of a conventional insert layer, and (c) indicates resistance drift of the variable resistor (see 60 of FIG. 1) according to an embodiment of the present invention.
It can be seen that the resistance of the conventional variable resistance layer (a) increases over time, and the resistance of the insert layer (b) changes slightly over time.
In the variable resistor 60 including the variable resistance layer and the insert layer, when the variable resistor includes a fixed resistor such as the insert layer, the resistance of the variable resistor may be represented as the sum of resistances of parallel resistors in a read operation. Therefore, the resistance drift (c) of the semiconductor apparatus in the embodiment of the present invention may be improved compared to a semiconductor apparatus having only a variable resistance layer.
Referring to FIGS. 10 and 12, a semiconductor apparatus may include a lower electrode 30, a variable resistor 160, and an upper electrode 70. The lower electrode 30 and the upper electrode 70 are the same as the lower electrode 30 and the upper electrode 70 illustrated in FIG.1, and thus a detailed description thereof will be omitted.
The variable resistor 160 may include an insert layer 163 and a variable resistance layer 161. The insert layer 163 in the embodiment may be formed on an inner sidewall of a hole (not shown) formed in a second insulating layer 40 in a thin film form and, specifically, only on the inner sidewall of the hole. The surfactant layer 163 may be formed on the inner sidewall of the hole. The insert layer 163 may be formed through a process of forming a surfactant material in thin film form in the hole, followed by removing a portion of the insert material on the bottom of the hole through an etch back method.
The variable resistance layer 161 may be formed to fill the inside of the hole surrounded with the insert layer 163. That is, the insert layer 163 surrounds a lateral surface of the variable resistance layer 161.
The variable resistor 160 may be heat-treated during the process for fabricating the semiconductor apparatus. In the heat-treatment process, the insert layer 163 may react with the variable resistance layer 161, thus the variable resistance layer 161 may be densely formed without defects.
Since the insert layer 163 has the above-described structure, the variable resistance layer 163 is in direct contact with the lower electrode 30, and thus voltage drop, which could occur through the insert layer 163 interposed between the variable resistance layer 161 and the lower electrode 30, may be avoided.
As described above, in the semiconductor apparatus according to the embodiment of the present invention, as a variable resistor includes a variable resistance layer and an insert layer, the variable resistance layer may be represented as the sum of resistance of parallel resistors in read operation, and the resistance of the variable resistance layer changes slightly over time.
The above embodiments of the present invention are illustrative and not imitative. Various alternatives and equivalents are possible. The invention is not limited by the embodiments described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.

Claims

1-7. (canceled)

8. A method for fabricating a semiconductor apparatus, the method comprising:

forming a resistive region;

forming a variable resistor in the resistive region,

wherein the forming of the variable resistor includes:

forming a variable resistance material on an inner surface of the resistive region;

forming an insert material has a resistivity being different from that of the variable resistance material and is in the variable resistance material; and

forming a variable resistance layer and an insert layer by etching back the variable resistance material and the insert material to a predetermined height.

9. The method of claim 8, wherein the forming of the resistive region includes:

forming a lower electrode on a semiconductor substrate;

forming an interlayer insulating layer on the semiconductor substrate; and

etching the interlayer insulating layer to form a hole exposing the lower electrode.

10. The method of claim 8, wherein the variable resistance material is deposited through an atomic layer deposition (ALD) method.

11. The method of claim 8, wherein the insert material is deposited through an ALD method.

12. The method of claim 9, further comprising, between the forming of the hole and the forming of the variable resistor, forming a first upper electrode on a sidewall of the hole.

13. The method of claim 12, wherein the forming of the first upper electrode includes:

forming a gap-fill insulating layer in the hole;

forming the first upper electrode, which is located in the sidewall of the hole and on the gap-fill insulating layer; and

removing the gap-fill insulating layer.

14. The method of claim 13, wherein the variable resistor is formed in the hole from which the gap-fill insulating layer is removed.

15. The method of claim 13, further comprising, after the forming of the variable resistance layer and insert layer, forming a second upper electrode on the variable resistance layer and the insert layer.

16. The method of claim 8, the resistance of the variable resistor may be represented as the sum of resistances of parallel resistors in a read operation.