US20170141122A1 - A three-dimensional memory device - Google Patents
A three-dimensional memory device Download PDFInfo
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- US20170141122A1 US20170141122A1 US15/052,140 US201615052140A US2017141122A1 US 20170141122 A1 US20170141122 A1 US 20170141122A1 US 201615052140 A US201615052140 A US 201615052140A US 2017141122 A1 US2017141122 A1 US 2017141122A1
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Definitions
- Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.
- a three-dimensional memory device having a structure in which a plurality of columnar parts including a charge storage film and a semiconductor body penetrate a plurality of electrode layers stacked with an insulator.
- a contact structure for connecting the electrode layers of the three-dimensional memory device to a control circuit.
- the plurality of electrode layers are processed in a staircase shape.
- An air gap may be formed also in the portion of the stacked body in which the staircase structure is formed. This also requires support by the columnar parts. The contact via reaching the staircase-shaped electrode layers from above may interfere with the semiconductor body of the columnar part.
- FIG. 1 is a schematic plan view showing an example of a planar layout of a semiconductor device of an embodiment
- FIG. 2 is a schematic perspective view of a memory cell array of the semiconductor device of the embodiment
- FIG. 3 is a schematic sectional view of the memory cell array of the semiconductor device of the embodiment.
- FIG. 4A is a partial enlarged view of the cross section shown in FIG. 3
- FIG. 4B is a sectional view taken along A-A′ in FIG. 4A ;
- FIG. 5A is a schematic plan view showing an example of a planar layout of a staircase section of the semiconductor device of the embodiment, and FIG. 5B is a schematic sectional view of the staircase section;
- FIGS. 6A to 13B are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the embodiment
- FIG. 14A is a schematic plan view showing a method for manufacturing the semiconductor device of the embodiment.
- FIGS. 14B to 23B are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the embodiment.
- FIG. 24A is a schematic plan view showing another example of a planar layout of a staircase section of the semiconductor device of the embodiment, and FIG. 24B is a schematic sectional view of the another example of the staircase section;
- FIGS. 25A and 25B are schematic sectional views of another example of a memory cell array of the semiconductor device of the embodiment.
- a semiconductor device includes a substrate, a stacked body provided above the substrate, a first columnar part, an insulating layer, a plurality of contact vias, and a plurality of second columnar parts.
- the stacked body includes a plurality of electrode layers stacked with an insulator.
- the electrode layers have a plurality of end parts formed in a staircase shape.
- the stacked body includes a first stacked part and a second stacked part including the end parts.
- the first columnar part includes a first semiconductor body extending in a stacking direction in the first stacked part, and a stacked film provided between the first semiconductor body and one of the electrode layers.
- the stacked film includes a charge storage part.
- the insulating layer is provided above the second stacked part.
- the plurality of contact vias extend in the stacking direction in the insulating layer, and are in contact with the end parts of the electrode layers.
- the plurality of second columnar parts extend in the stacking direction in the second stacked part, and include a plurality of second semiconductor bodies being different in length in the stacking direction.
- the semiconductor device is described with reference to e.g. a semiconductor memory device including a memory cell array having a three-dimensional structure.
- FIG. 1 is a schematic plan view showing an example of the planar layout of the semiconductor device of the embodiment.
- the semiconductor device of the embodiment includes a memory cell array 1 and a staircase section 2 provided outside the memory cell array 1 .
- the memory cell array 1 and the staircase section 2 are provided on the same substrate.
- FIG. 2 is a schematic perspective view of the memory cell array 1 .
- X-direction and Y-direction two directions parallel to the major surface of the substrate 10 and orthogonal to each other are referred to as X-direction and Y-direction.
- the direction orthogonal to both the X-direction and the Y-direction is referred to as Z-direction (stacking direction),
- the X-direction and the Y-direction shown in FIG. 1 correspond to the X-direction and the Y-direction shown in FIG. 2 .
- the staircase section 2 is provided outside the memory cell array 1 in the X-direction.
- the X-direction, the Y-direction, and the Z-direction shown in the other figures also correspond to the X-direction, the Y-direction, and the Z-direction shown in FIG. 2 .
- the memory cell array 1 includes a substrate 10 , a first stacked part 100 a provided on the major surface of the substrate 10 , a plurality of first columnar parts CL 1 , a plurality of separation parts 9 , and an upper interconnect provided on the first stacked part 100 a .
- FIG. 2 shows e.g. a bit line BL and a source line SL as the upper interconnect.
- the first columnar part CL 1 is formed like a circular column or elliptical column extending in the stacking direction (Z-direction) in the first stacked part 100 a .
- the separation part 9 spreads in the stacking direction (Z-direction) and the X-direction of the first stacked part 100 a ,
- the separation part 9 separates the first stacked part 100 a into a plurality of blocks in the Y-direction.
- the plurality of first columnar parts CL 1 are arranged in e.g. a staggered arrangement.
- the plurality of first columnar parts CL 1 may be arranged in a square lattice along the X-direction and the Y-direction.
- a plurality of bit lines BL are provided on the first stacked part 100 a .
- the bit lines BL are e.g. metal films extending in the Y-direction.
- the bit lines BL are separated from each other in the X-direction.
- the upper end of the first columnar part CL 1 is connected to the bit line BL via a contact part Cb,
- the plurality of first columnar parts CL 1 each of which is selected from each of blocks separated in the Y-direction by the separation part 9 , are connected to one common bit line BL.
- FIG. 3 is a schematic sectional view of the memory cell array 1 .
- the first stacked part 100 a includes a plurality of electrode layers 70 stacked on the major surface of the substrate 10 .
- the plurality of electrode layers 70 are stacked with an air gap 40 interposed in the direction (Z-direction) perpendicular to the major surface of the substrate 10 .
- an insulating layer may be provided as an insulator between the electrode layers 70 .
- the electrode layer 70 is a metal layer such as a tungsten layer or molybdenum layer.
- the stacked body including the plurality of electrode layers 70 is provided also in the staircase section 2 described later with reference to FIG. 5B .
- the portion provided in the memory cell array 1 is referred to as first stacked part 100 a
- the portion provided in the staircase section 2 is referred to as second stacked part 100 b.
- An insulating film 41 is provided between the major surface of the substrate 10 and the lowermost electrode layer 70 .
- An insulating film 42 is provided on the uppermost electrode layer 70 .
- An insulating film 43 is provided on the insulating film 42 .
- FIG. 4A is a partial enlarged view of the cross section shown in FIG. 3 .
- FIG. 4B is a sectional view taken along A-A′ in FIG. 4A .
- the first columnar part CL 1 includes a memory film 30 , a first semiconductor body 20 , and an insulating core film 50 .
- the first semiconductor body 20 extends like a pipe in the stacking direction (Z-direction) in the first stacked part 100 a .
- the memory film 30 is provided between the electrode layer 70 and the first semiconductor body 20 .
- the memory film 30 surrounds the first semiconductor body 20 from the outer peripheral side.
- the core film 50 is provided inside the pipe-shaped first semiconductor body 20 .
- the upper end of the first semiconductor body 20 is electrically connected to the bit line BL via the contact part Cb shown in FIG. 2 .
- the memory film 30 is a stacked film including a tunnel insulating film 31 , a charge storage film (charge storage part) 32 , and a block insulating film 33 .
- the block insulating film 33 , the charge storage film 32 , and the tunnel insulating film 31 are provided between the electrode layer 70 and the first semiconductor body 20 sequentially from the electrode layer 70 side.
- the tunnel insulating film 31 is in contact with the first semiconductor body 20 .
- the block insulating film 33 is in contact with the electrode layer 70 .
- the charge storage film 32 is provided between the block insulating film 33 and the tunnel insulating film 31 .
- the first semiconductor body 20 extends continuously in the stacking direction of the first stacked part 100 a .
- the air gap 40 between the vertically adjacent electrode layers 70 extends to the first semiconductor body 20 side so as to divide at least the block insulating film 33 and the charge storage film 32 of the memory film 30 in the stacking direction. That is, the block insulating film 33 and the charge storage film 32 are separated in the stacking direction via the air gap 40 .
- the tunnel insulating film 31 may be continued or divided in the stacking direction.
- the memory film 30 is provided between the inner peripheral surface of the electrode layer 70 surrounding the first columnar part CL 1 , and the outer peripheral surface of the first semiconductor body 20 continuously in the direction connecting the inner peripheral surface and the outer peripheral surface.
- the plurality of electrode layers 70 are physically connected to the first columnar part CL 1 via the memory film 30 and supported by the first columnar part CL 1 .
- the outer peripheral surface of the first semiconductor body 20 , and the upper surface and the lower surface of the electrode layer 70 are not exposed to the air gap 40 , but covered and protected with a protective film 56 .
- the protective film 56 is an insulating film such as silicon oxide film.
- the first semiconductor body 20 , the memory film 30 , and the electrode layer 70 constitute a memory cell MC.
- one memory cell MC is schematically shown by the broken line.
- the memory cell MC has a vertical transistor structure in which the first semiconductor body 20 is surrounded with the electrode layer 70 via the memory film 30 .
- the first semiconductor body 20 is e.g. a channel body of silicon.
- the electrode layer 70 functions as a control gate.
- the charge storage film 32 functions as a data storage layer for storing charge injected from the first semiconductor body 20 .
- the semiconductor memory device of the embodiment is a nonvolatile semiconductor memory device capable of electrically and freely erasing/writing data and retaining its memory content even when powered off.
- the memory cell MC is e.g. a charge trap type memory cell.
- the charge storage film 32 includes a large number of trap sites for trapping charge in the insulating film, and includes e.g. silicon nitride film.
- the charge storage film 32 may be a conductive floating gate surrounded with an insulator.
- the tunnel insulating film 31 serves as a potential barrier when charge is injected from the first semiconductor body 20 into the charge storage film 32 , or when the charge stored in the charge storage film 32 is released into the first semiconductor body 20 .
- the tunnel insulating film 31 includes e.g. silicon oxide film.
- the block insulating film 33 prevents the charge stored in the charge storage film 32 from being released into the electrode layer 70 .
- the block insulating film 33 suppresses back tunneling of electrons from the electrode layer 70 at the time of erase operation.
- the block insulating film 33 includes e.g. at least one of silicon oxide film and metal oxide film.
- a drain side select transistor STD is provided in the upper end part of the first columnar part CL 1 .
- a source side select transistor STS is provided in the lower end part of the first columnar part CL 1 .
- the lowermost electrode layer 70 functions as a control gate of the source side select transistor STS.
- the uppermost electrode layer 70 functions as a control gate of the drain side select transistor STD.
- a plurality of memory cells MC are provided between the drain side select transistor STD and the source side select transistor STS.
- the memory cells MC, the drain side select transistor STD, and the source side select transistor STS are series connected through the first semiconductor body 20 and constitute one memory string.
- Such memory strings are arranged in e.g. a staggered arrangement in the plane direction parallel to the X-Y plane.
- the plurality of memory cells MC are provided three-dimensionally in the X-direction, the Y-direction, and the Z-direction.
- the separation part 9 separating the first stacked part 100 a in the Y-direction includes an interconnect part LI.
- the interconnect part LI is e.g. a metal-containing film spread in the Z-direction and the X-direction.
- an insulating film 44 is provided on the sidewall of the interconnect part LI. The insulating film 44 is provided between the first stacked part 100 a and the interconnect part LI.
- the upper end of the interconnect part LI is connected to the source line SL, shown in FIG. 2 , provided on the first stacked part 100 a .
- the lower end of the interconnect part LI is in contact with the substrate 10 as shown in FIG. 3 .
- the lower end of the first semiconductor body 20 is in contact with the substrate 10 .
- the substrate 10 is e.g. a silicon substrate doped with impurity and having conductivity.
- the lower end of the first semiconductor body 20 is electrically connectable to the source line SL via the substrate 10 and the interconnect part LI.
- a channel is induced in the surface of the substrate 10 between the lower end of the interconnect part LI and the lower end of the first semiconductor body 20 .
- a current can be passed between the lower end of the interconnect part LI and the lower end of the first semiconductor body 20 .
- the lowermost electrode layer 70 functions as a control gate for inducing a channel in the surface of the substrate 10 .
- the insulating film 41 functions as a gate insulating film.
- the portion between the surface of the substrate 10 and the lowermost electrode layer 70 is not an air gap, but the insulating film 41 having higher dielectric constant than air. This enables fast driving by capacitive coupling between the lowermost electrode layer 70 and the surface of the substrate 10 .
- an air gap 40 is formed between the electrode layers 70 , which are control gates of the memory cells MC adjacent in the stacking direction. This can reduce the interconnect capacitance between the vertically adjacent electrode layers 70 and enables fast operation of the memory cell MC. Furthermore, this can suppress interference between adjacent cells such as threshold variation due to capacitive coupling between the vertically adjacent electrode layers 70 .
- the charge storage films 32 are separated in the stacking direction.
- the charge stored in the charge storage film 32 is not released in the stacking direction. Accordingly, the memory cell MC is superior in charge retention characteristics.
- FIG. 5A is a schematic plan view showing an example of the planar layout of the staircase section 2 .
- FIG. 5B is a schematic sectional view of the staircase section 2 .
- FIG. 5B corresponds to a cross section taken along B-B′ in FIG. 5A .
- the plurality of electrode layers 70 extend in the X-direction from the region with the memory cell array 1 formed therein to the region with the staircase section 2 formed therein.
- a second stacked part 100 b is provided on the substrate 10 in the region with the staircase section 2 formed therein.
- the second stacked part 100 b includes the plurality of electrode layers 70 stacked in the Z-direction with the air gap 40 .
- the insulating film 41 is provided between the lowermost electrode layer 70 and the substrate 10 in the second stacked part 100 b.
- the plurality of electrode layers 70 of the second stacked part 100 b have a plurality of end parts (or terrace parts) 70 a formed in a staircase shape.
- the end parts 70 a of the electrode layers 70 are arranged in a staircase shape along the X-direction.
- the second stacked part 100 b is also separated into a plurality of blocks in the Y-direction by the separation part 9 extending in the X-direction as shown in FIG. 5A .
- a first cover layer 61 is provided on the second stacked part 100 b so as to cover the plurality of staircase-shaped end parts 70 a .
- An insulating layer 46 is provided on the first cover layer 61 so as to eliminate or reduce the step difference with the memory cell array 1 .
- the first cover layer 61 and the insulating layer 46 are not shown in FIG. 5A .
- a plurality of contact vias 91 extending in the Z-direction are provided in the insulating layer 46 . Each lower end of the contact vias 91 is connected to the corresponding end part 70 a of the electrode layers 70 .
- the contact via 91 is a metal-containing conductor. Each contact via 91 is connected to the upper interconnect, not shown, provided above the second stacked part 100 b.
- Each electrode layer 70 of the staircase section 2 is integrally connected to the corresponding electrode layer 70 of the memory cell array 1 .
- the electrode layer 70 of the memory cell array 1 is electrically connected to the upper interconnect via the contact via 91 of the staircase section 2 .
- the upper interconnect is electrically connected to e.g. a control circuit formed on the surface of the substrate 10 .
- the air gap 40 is formed between the plurality of electrode layers 70 .
- the second stacked part 100 b also includes a plurality of second columnar parts CL 2 supporting the plurality of electrode layers 70 stacked with the air gap 40 .
- At least one contact via 91 is provided per one end part 70 a of one electrode layer 70 in one block separated from the other blocks by the separation part 9 .
- one contact via 91 and a plurality of second columnar parts CL 2 placed around that contact via 91 are provided per one end part 70 a of one electrode layer 70 in one block.
- four second columnar parts CL 2 are equally spaced around the one contact via 91 .
- the second columnar parts CL 2 are formed at the same time as the first columnar parts CL 1 of the memory cell array 1 are formed.
- the second columnar part CL 2 is formed like a circular column or elliptical column extending in the stacking direction (Z-direction) in the second stacked part 100 b.
- the second columnar part CL 2 includes an insulating film 130 , a second semiconductor body 120 , and a core film 150 .
- the insulating film 130 is formed at the same time as the memory film 30 of the first columnar part CL 1 is formed.
- the insulating film 130 includes a film of the same stacked structure or the same material as the memory film 30 .
- the second semiconductor body 120 is formed at the same time from the same material as the first semiconductor body 20 of the first columnar part CL 1 is formed.
- the core film 150 is formed at the same time from the same material as the core film 50 of the first columnar part CL 1 is formed.
- the second semiconductor body 120 extends like a pipe in the stacking direction (Z-direction) in the second stacked part 100 b .
- the insulating film 130 is provided between the electrode layer 70 and the second semiconductor body 120 .
- the insulating film 130 surrounds the second semiconductor body 120 from the outer peripheral side.
- the core film 150 is provided inside the pipe-shaped second semiconductor body 120 .
- the lower end of the second semiconductor body 120 is in contact with the substrate 10 . However, the upper end of the second semiconductor body 120 is electrically connected to nowhere.
- the second semiconductor body 120 functions as a mere strut supporting the plurality of electrode layers 70 .
- the insulating film 130 is provided between the inner peripheral surface of the electrode layer 70 surrounding the second columnar part CL 2 and the outer peripheral surface of the second semiconductor body 120 continuously in the direction connecting the inner peripheral surface and the outer peripheral surface.
- the plurality of electrode layers 70 are physically connected to the second columnar part CL 2 via the insulating film 130 and supported by the second columnar part CL 2 .
- the position of the upper end of the second columnar part CL 2 is lower than the position of the upper end of the first columnar part CL 1 .
- the length (Z-direction length) of the second columnar part CL 2 is shorter than the length of the first columnar part CL 1 .
- the position of the upper end of the second semiconductor body 120 is lower than the position of the upper end of the first semiconductor body 20 .
- the length (Z-direction length) of the second semiconductor body 120 is shorter than the length of the first semiconductor body 20 .
- the plurality of second columnar parts CL 2 are not equal in length.
- the plurality of second columnar parts CL 2 provided in the second stacked part 100 b include a plurality of second columnar parts CL 2 different in length.
- the plurality of second semiconductor bodies 120 are not equal in length.
- the plurality of second semiconductor bodies 120 provided in the second stacked part 100 b include a plurality of second semiconductor bodies 120 different in length.
- the plurality of second semiconductor bodies 120 include a second semiconductor body 120 having a protrusion 120 a protruding above the second stacked part 100 b . That second semiconductor body 120 penetrates through the end part 70 a of the electrode layer 70 and through the electrode layers 70 between that end part 70 a and the substrate 10 . The protrusion 120 a protrudes above the end part 70 a.
- the length of the protrusion 120 a is shorter than the length of the portion of the second semiconductor body 120 extending below that protrusion 120 a in the second stacked part 100 b.
- the second stacked part 100 b includes the end parts 70 a of the electrode layers 70 formed in a staircase shape.
- the second stacked part 100 b includes a lower stage part and an upper stage part.
- the number of stacked electrode layers 70 is relatively small.
- the number of stacked electrode layers 70 is larger than that in the lower stage part.
- the relationship between the lower stage part and the upper stage part is also applicable to the relationship between the stage parts adjacent in the X-direction, and the relationship between the stage parts spaced in the X-direction.
- the length of the lower-stage second columnar part CL 2 provided in the lower stage part is shorter than the length of the upper-stage second columnar part CL 2 provided in the upper stage part.
- the length of the lower-stage second semiconductor body 120 provided in the lower stage part is shorter than the length of the upper-stage second semiconductor body 120 provided in the upper stage part.
- the plurality of contact vias 91 include lower-stage contact vias 91 in contact with the end parts 70 a of relatively lower electrode layers 70 , and upper-stage contact vias 91 in contact with the end parts 70 a of relatively upper electrode layers 70 .
- the upper ends of the plurality of contact vias 91 are located at a generally equal height.
- the lower ends of the contact vias 91 on the relatively lower stage side are located on the relatively lower side.
- the length of the upper-stage contact via 91 is shorter than the length of the lower-stage contact via 91 .
- the length of the lower-stage contact via 91 is longer than the length of the upper-stage contact via 91 .
- the length of the lower-stage second columnar part CL 2 placed adjacent to or around the lower-stage contact via 91 is shorter than the length of the upper-stage second columnar part CL 2 placed adjacent to or around the upper-stage contact via 91 .
- the length of the lower-stage second semiconductor body 120 placed adjacent to or around the lower-stage contact via 91 is shorter than the length of the upper-stage second semiconductor body 120 placed adjacent to or around the upper-stage contact via 91 .
- the side surface of the contact via 91 is spaced from the side surface of the second columnar part CL 2 placed adjacent to or around that contact via 91 .
- the contact via 91 is not in contact with the second semiconductor body 120 .
- the contact via 91 and the substrate 10 are not electrically connected (short-circuited) through the second semiconductor body 120 .
- the contact via 91 is also not in contact with the insulating film 130 of the second columnar part CL 2 .
- the insulating film 130 includes a film of the same material as the memory film 30 of the first columnar part CL 1 .
- the insulating film 130 includes a film of the same material as the block insulating film 33 at the outermost periphery, and includes a film of the same material as the charge storage film 32 inside.
- the contact via 91 may be in contact with the film in the insulating film 130 of the same material as the block insulating film 33 .
- the charge storage film 32 has a lower mobility than the semiconductor film. However, migration of electrons may occur in the charge storage film 32 . Thus, it is not desirable that the contact via 91 be in contact with the film in the insulating film 130 of the same material as the charge storage film 32 .
- the contact via 91 extends upward from the end part 70 a of the electrode layer 70 of the connection target.
- the protrusion 120 a protruding above the end part 70 a of the electrode layer 70 may contact with the contact via 91 .
- the contact via 91 is formed in a hole formed by reactive ion etching (RIE) technique in the insulating layer 46 and the first cover layer 61 .
- RIE reactive ion etching
- the hole side surface may be tapered so that the hole diameter decreases with the depth.
- a portion 91 a thicker (larger in diameter) than the lower end part 91 b is formed above the lower end part 91 b in contact with the end part 70 a of the electrode layer 70 .
- the contact via 91 may be in contact with the second semiconductor body 120 in the upper part 91 a even though the contact via 91 is not in contact with the second semiconductor body 120 in the lower end part 91 b.
- the second semiconductor body 120 is formed at the same time as the first semiconductor body 20 of the memory cell array 1 is formed. Then, in the second semiconductor body 120 , the protrusion 120 a protruding above the end part 70 a of the electrode layer 70 is etched as described later to shorten the length of the protrusion 120 a.
- the second semiconductor body 120 can be excluded from the region adjacent to or around the upper part of the contact via 91 , which tends to be thicker than the lower end part.
- the possibility of contact is reduced between the contact via 91 and the second semiconductor body 120 . This can prevent current leakage between the contact via 91 and the substrate 10 through the second semiconductor body 120 .
- the contact via 91 is less likely to be in contact with the second semiconductor body 120 .
- This structure enables reduction of the distance between the contact via 91 and the second semiconductor body 120 .
- the terrace region (area of the end part 70 a ) shown in FIG. 5A can be reduced.
- the terrace region includes, for example, one contact via 91 and four second semiconductor bodies 120 therearound. This leads to the reduction of the chip size.
- FIG. 24A is a schematic plan view showing the planar layout of an alternative example of the staircase section 2 .
- FIG. 24 B is a schematic sectional view of the alternative example of the staircase section 2 .
- FIG. 24B corresponds to a cross section taken along C-C′ in FIG. 24A .
- the contact via 91 includes an upper part 91 a located above the upper end of the second semiconductor body 120 .
- the thickness (diameter) of the upper part 91 a is larger than the thickness (diameter) of the lower end part 91 b in contact with the end part 70 a of the electrode layer 70 .
- the side surface of the contact via 91 is tapered so that the contact via 91 is thinned toward the lower end part 91 b.
- FIG. 24B the extension line extending upward from the upper end of the second semiconductor body 120 is virtually shown by the broken line.
- the side surface of the upper part 91 a of the contact via 91 overlaps the region in which the second semiconductor body 120 placed adjacent to or around that contact via 91 is extended upward.
- the outline 91 aa of the upper end of the contact via 91 spreads to part of the placement region of the second semiconductor body 120 therearound.
- the length of the protrusion 120 a of the second semiconductor body 120 is shortened.
- the upper part 91 a of the contact via 91 is made thicker, the upper part 91 a is not in contact with the second semiconductor body 120 .
- the resistance of the contact via 91 can be reduced by forming a thick portion (upper part 91 a ) in the contact via 91 .
- FIG. 23B is a schematic sectional view showing a further alternative example of the staircase section 2 .
- FIG. 25B is a schematic sectional view of a memory cell array in a semiconductor device including the staircase section 2 shown in FIG. 23B .
- an insulating layer 72 rather than an air gap is provided between the plurality of electrode layers 70 .
- An insulating film 48 is provided as a separation part separating the first stacked part 100 a into a plurality in the Y-direction.
- the memory film 30 is not divided in the vertical direction (Z-direction).
- the plurality of second semiconductor bodies 120 include a second semiconductor body 120 with the upper end located in the second stacked part 100 b without protruding from the second stacked part 100 b .
- An insulating layer 65 doubling as a cover layer is provided on the second stacked part 100 b so as to eliminate or reduce the step difference with the memory cell array 1 .
- an insulating layer 72 rather than an air gap is provided between the plurality of electrode layers 70 .
- the plurality of electrode layers 70 can maintain the stacked state with a prescribed spacing even without the support of the second columnar parts CL 2 .
- a sacrificial layer 71 is formed in the portion in which the electrode layer 70 is to be formed. Then, the sacrificial layer 71 is removed, and an air gap 73 is formed between the insulating layers 72 as shown in FIG. 18B . At this time, the second columnar part CL 2 supports the insulating layer 72 .
- the electrode layer 70 is formed in the air gap 73 , if the insulating layer 72 is not removed, the electrode layer 70 is supported by the insulating layer 72 .
- the upper end may be retracted downward from the end part 70 a of the electrode layer 70 .
- the second semiconductor body 120 may be eliminated.
- the protrusion 120 a of the second semiconductor body 120 likely to be in contact with the contact via 91 is eliminated. This can enlarge the contact area between the contact via 91 and the end part 70 a of the electrode layer 70 . Furthermore, the diameter of the contact via 91 can be increased. There are no restrictions to the placement of the second semiconductor body 120 . This can further reduce the resistance of the contact via 91 .
- a first stacked part 100 a is formed on a substrate 10 .
- the substrate 10 is e.g. a semiconductor substrate such as a silicon substrate.
- An insulating film 41 is formed on the major surface (front surface) of the substrate 10 .
- a first layer 71 and a second layer 72 are alternately stacked on the insulating film 41 .
- the step of alternately stacking a first layer 71 and a second layer 72 is repeated to form a plurality of first layers 71 and a plurality of second layers 72 on the substrate 10 .
- the first layer 71 is a sacrificial layer to be removed in a later step.
- the first layer 71 is e.g. a silicon nitride layer.
- the second layer 72 is a sacrificial layer to be removed in a later step.
- the second layer 72 is e.g. a silicon oxide layer.
- the second layer 72 may be an insulating layer (e.g., silicon oxide layer) left without being removed.
- the lowermost first layer 71 is formed on the insulating film 41 .
- the lowermost second layer 72 is formed on the lowermost first layer 71 .
- An insulating film 42 is formed on the uppermost first layer 71 .
- the uppermost first layer 71 is formed between the uppermost second layer 72 and the insulating film 42 .
- a plurality of memory holes MH are formed in the first stacked part 100 a .
- the memory holes MH are formed by RIE technique using a mask, not shown.
- the memory hole MH penetrates through the first stacked part 100 a to the substrate 10 .
- a memory film 30 is formed on the side surface and bottom of the memory hole MH.
- the memory film 30 formed at the bottom of the memory hole MH is removed as shown in FIG. 7B by e.g. RIE technique using a mask, not shown.
- a first semiconductor body 20 is formed inside the memory film 30 .
- the first semiconductor body 20 is formed on the side surface of the memory film 30 and at the bottom of the memory hole MH where the substrate 10 is exposed.
- the first semiconductor body 20 is formed as e.g. an amorphous silicon film, and then crystallized into a polycrystalline silicon film by heat treatment.
- a core film 50 is formed inside the first semiconductor body 20 .
- a first columnar part CL 1 is formed.
- the films deposited on the insulating film 42 shown in FIG. 8B are removed by chemical mechanical polishing (CMP) or etch-back. Then, as shown in FIG. 9A , an insulating film 43 is formed on the insulating film 42 .
- the insulating film 43 covers the upper end of the first columnar part CL 1 .
- a plurality of slits ST are formed in the first stacked part 100 a including the insulating film 43 , the insulating film 42 , the first layers 71 , the second layers 72 , and the insulating film 41 .
- the slit ST penetrates through the first stacked part 100 a to the substrate 10 .
- the first layer 71 is removed with an etchant or etching gas supplied through the slit ST.
- the first layer 71 being a silicon nitride layer is removed with an etchant containing phosphoric acid.
- an air gap 73 is formed between the vertically adjacent second layers 72 by the removal of the first layer 71 .
- the air gap 73 is formed also between the insulating film 41 and the lowermost second layer 72 , and between the uppermost second layer 72 and the insulating film 42 .
- the insulating film 43 , the insulating film 42 , the second layers 72 , the insulating film 41 , and the substrate 10 have high etching resistance to phosphoric acid, and remain without being removed.
- the plurality of second layers 72 stacked with the air gap 73 are supported by the first columnar part CL 1 .
- the lower end of the first columnar part CL 1 is supported by the substrate 10 .
- the upper end of the first columnar part CL 1 is supported by the insulating film 42 and the insulating film 43 .
- an electrode layer 70 shown in FIG. 10A is formed in the air gap 73 .
- the electrode layer 70 is formed by chemical vapor deposition (CVD) technique.
- a source gas is supplied to the air gap 73 through the slit ST.
- the electrode layer 70 is formed in the air gap 73 .
- the electrode layer 70 is a metal layer such as a tungsten layer or molybdenum layer.
- the second layer 72 is removed with an etchant or etching gas supplied through the slit ST.
- the second layer 72 being a silicon oxide layer is removed with an etchant containing hydrofluoric acid.
- an air gap 40 is formed between the vertically adjacent electrode layers 70 by the removal of the second layer 72 .
- the insulating film 43 , the insulating film 42 , the electrode layers 70 , the insulating film 41 , and the substrate 10 have high etching resistance to hydrofluoric acid, and remain without being removed.
- the memory film 30 exposed to the air gap 40 is removed.
- the memory film 30 is removed with an etchant or etching gas supplied through the slit ST and the air gap 40 .
- the block insulating film 33 and the charge storage film 32 are sequentially etched.
- the tunnel insulating film 31 may be left.
- At least the block insulating film 33 and the charge storage film 32 are divided in the stacking direction (Z-direction).
- the upper end of the first columnar part CL 1 is covered with the insulating film 43 .
- etching of the first columnar part CL 1 does not proceed from the upper end side.
- the plurality of electrode layers 70 stacked with the air gap 40 are supported by the first columnar part CL 1 .
- the protective film 56 shown in FIG. 4A may be formed on the inner wall surface of the air gap 40 .
- an insulating film 44 is formed on the side surface and bottom of the slit ST.
- the insulating film 44 has low coverage.
- the insulating film 44 can be configured to occlude the opening on the slit ST side of the air gap 40 while the air gap 40 is not filled with the insulating film 44 .
- an insulating film 49 may be formed on the insulating film 43 so as to occlude the upper end of the slit ST without forming an insulating film in the slit ST.
- An air gap communicating with the air gap 40 between the electrode layers 70 is left in the slit ST.
- the insulating film 44 formed at the bottom of the slit ST is removed by RIE technique as shown in FIG. 11B . Then, an interconnect part LI is buried in the slit ST as shown in FIG. 3 . Then, the bit line BL, the source line SL and the like shown in FIG. 2 are formed.
- a second stacked part 100 b is formed also on the substrate 10 in the region in which the staircase section 2 is to be formed.
- the second stacked part 100 b includes the same insulating film 41 , first layers 71 , second layers 72 , and insulating film 42 as those of the first stacked part 100 a.
- the staircase section 2 is formed as shown in FIG. 12A .
- anisotropic etching of the first layers 71 and the second layers 72 using a resist film as a mask, reduction of the planar size of the resist film, and anisotropic etching of the first layers 71 and the second layers 72 using the reduced resist film as a mask are repeated.
- the first layers 71 and the second layers 72 are processed into a staircase shape arranged in the X-direction.
- a first cover layer 61 is formed on the staircase section 2 .
- the first cover layer 61 is formed along the staircase shape of the staircase section 2 and covers the surface of the staircase section 2 .
- a second cover layer 62 is formed on the first cover layer 61 .
- a step difference is formed between the first stacked part 100 a and the second stacked part 100 b .
- the first cover layer 61 and the second cover layer 62 are formed so as to reduce or eliminate the step difference.
- the upper surface of the second cover layer 62 is planarized. This improves the ease and accuracy of lithography and RIE in simultaneously performing the process of forming the first columnar part CL 1 in the memory cell array 1 and the process of forming the second columnar part CL 2 in the staircase section 2 .
- the second cover layer 62 is a sacrificial layer to be removed later. At the time of etching for removing the second cover layer 62 , the first cover layer 61 covers and protects the staircase section 2 .
- the first cover layer 61 is an insulating layer to be left without being removed.
- the first cover layer 61 is e.g. a layer of silicon oxide-based material.
- the second cover layer 62 is also e.g. a layer of silicon oxide-based material. However, the second cover layer 62 has etching selectivity with respect to the first cover layer 61 .
- the first cover layer 61 and the second cover layer 62 are likewise made of silicon oxide-based material.
- the contained elements and their composition ratio can be made different between the first cover layer 61 and the second cover layer 62 by the difference in e.g. the film formation method such as coating technique and CVD technique.
- the etching rate for e.g. the etchant containing hydrofluoric acid can be made different between the first cover layer 61 and the second cover layer 62 to provide etching selectivity.
- a plurality of second columnar parts CL 2 are formed in the second stacked part 100 b , the first cover layer 61 , and the second cover layer 62 .
- the second columnar part CL 2 penetrates through the second cover layer 62 , the first cover layer 61 , and the second stacked part 100 b to the substrate 10 .
- the second columnar parts CL 2 are formed at the same time as the first columnar parts CL 1 of the memory cell array 1 are formed.
- the memory holes MH shown in FIG. 6B are formed, a plurality of holes having the same depth as the memory holes MH are formed also in the second cover layer 62 , the first cover layer 61 , and the second stacked part 100 b .
- the insulating film 130 of the second columnar part CL 2 is formed from the same material.
- the first semiconductor body 20 of the first columnar part CL 1 is formed, the second semiconductor body 120 of the second columnar part CL 2 is formed from the same material.
- the core film 50 of the first columnar part CL 1 is formed, the core film 150 of the second columnar part CL 2 is formed from the same material. At this time, the length (Z-direction length) of the first columnar part CL 1 and the second columnar part CL 2 is equal.
- the slit ST shown in FIG. 9A is formed in the first stacked part 100 a
- the slit ST is formed also in the second cover layer 62 , the first cover layer 61 , and the second stacked part 100 b as shown in FIG. 14A .
- the second cover layer 62 , the first cover layer 61 , and the second stacked part 100 b are divided by the slit ST into a plurality of blocks in the Y-direction.
- the first layer 71 of the first stacked part 100 a is removed by etching through the slit ST to form the air gap 73 as shown in FIG. 9B
- the first layer 71 of the second stacked part 100 b is also removed by etching through the slit ST.
- the air gap 73 is formed also between the second layers 72 of the second stacked part 100 b.
- the electrode layer 70 is formed in the air gap 73 of the first stacked part 100 a
- the electrode layer 70 is formed also in the air gap 73 of the second stacked part 100 b as shown in FIG. 15A .
- the plurality of electrode layers 70 of the second stacked part 100 b have a plurality of end parts (terrace parts) 70 a arranged in a staircase shape in the X-direction.
- the second layer 72 between the electrode layers 70 of the first stacked part 100 a is removed, the second layer 72 of the second stacked part 100 b is also removed by etching through the slit ST. As shown in FIG. 15B , the air gap 40 is formed between the electrode layers 70 of the second stacked part 100 b.
- the second layer 72 is a silicon oxide layer.
- the second layer 72 is removed with e.g. an etchant containing hydrofluoric acid.
- the second cover layer 62 of the silicon oxide-based material is also removed with the etchant containing hydrofluoric acid as shown in FIG. 15B .
- the first cover layer 61 is a layer of the silicon oxide-based material having higher etching resistance to the etchant containing hydrofluoric acid than the second layer 72 and the second cover layer 62 . Thus, the first cover layer 61 is left without being removed.
- the second layer 72 is removed, and part of the second columnar part CL 2 in the length direction (Z-direction) is exposed as shown in FIG. 15B .
- part of the protrusion CL 2 a protruding above the end part 70 a of the electrode layer 70 is exposed.
- the portion below the exposed part is covered with the first cover layer 61 and the second stacked part 100 b .
- the lower part of the protrusion CL 2 a of the second columnar part CL 2 on the near side of the end part 70 a of the electrode layer 70 is covered with the first cover layer 61 .
- the portion above that lower part is exposed.
- the memory film 30 of the first columnar part CL 1 exposed to the air gap 40 is removed by etching through the slit ST.
- the memory film 30 of the second columnar part CL 2 exposed to the air gap 40 is also removed as shown in FIG. 16A .
- the memory film 30 of the protrusion CL 2 a exposed above the first cover layer 61 is also removed at this time.
- part of the second semiconductor body 120 is exposed by the removal of the memory film 30 of the protrusion CL 2 a .
- part of the protrusion 120 a protruding above the end part 70 a of the electrode layer 70 is exposed.
- the portion below the exposed part is covered with the first cover layer 61 and the second stacked part 100 b .
- the lower part of the protrusion 120 a of the second semiconductor body 120 on the near side of the end part 70 a of the electrode layer 70 is covered with the first cover layer 61 via the memory film 30 .
- the portion above that lower part is exposed.
- the exposed part of the second semiconductor body 120 being a silicon body is removed with e.g. an alkaline etchant.
- the length of the second semiconductor body 120 is shortened.
- the position of the upper end of the second semiconductor body 120 is retracted below the upper surface of the first cover layer 61 .
- the core film 150 protruding above the first cover layer 61 is removed before or after removing the exposed part of the second semiconductor body 120 .
- the core film 150 protruding above the first cover layer 61 may be left.
- an insulating layer 46 is formed on the first cover layer 61 as shown in FIG. 17A .
- a plurality of contact holes 81 are formed in the insulating layer 46 and the first cover layer 61 .
- the contact holes 81 are formed by RIE technique using a mask, not shown.
- the plurality of contact holes 81 penetrate through the insulating layer 46 and the first cover layer 61 to the end parts 70 a of the corresponding electrode layers 70 .
- FIGS. 18A to 21B are schematic sectional views showing an alternative example of the method for forming a contact structure in the staircase section 2 .
- a cover layer 63 is formed on the staircase section 2 as shown in FIG. 18A . Furthermore, a second columnar part CL 2 penetrating through the cover layer 63 and the second stacked part 100 b to the substrate 10 is formed.
- the cover layer 63 is e.g. a layer of silicon oxide-based material.
- the cover layer 63 of the same silicon oxide-based material as the second layer 72 is also removed. As shown in FIG. 19B , the second columnar part CL 2 is exposed in the portion except the portion surrounded circumferentially with the electrode layer 70 .
- the memory film 30 exposed to the air gap 40 is removed.
- the memory film 30 of the second columnar part CL 2 protruding above the second stacked part 100 b is also removed.
- the protrusion 120 a protruding above the second stacked part 100 b is exposed.
- an insulating film 64 is formed on the staircase section 2 .
- the insulating film 64 is e.g. a silicon oxide film.
- the insulating film 64 is deposited on the staircase section 2 , and formed also on the side surface and the upper surface of the protrusion 120 a of the second semiconductor body 120 .
- the insulating film 64 is formed by e.g. plasma CVD technique in which the deposition is thicker in the Z-direction than on the side surface of the protrusion 120 a of the second semiconductor body 120 .
- the insulating film 64 formed thinly on the side surface of the protrusion 120 a of the second semiconductor body 120 and the insulating film 64 deposited on the upper surface of the protrusion 120 a are removed with an etchant or etching gas. As shown in FIG. 21A , part of the protrusion 120 a of the second semiconductor body 120 is exposed.
- the insulating film 64 deposited on the staircase section 2 is also retracted downward. However, the insulating film 64 deposited on the staircase section 2 is thicker in film thickness than the insulating film 64 formed on the side surface of the protrusion 120 a . Thus, the insulating film 64 deposited on the staircase section 2 remains in the state of covering the second stacked part 100 b.
- the core film 150 inside the protrusion 120 a of the second semiconductor body 120 is removed during or after the aforementioned etching of the insulating film 64 .
- the exposed part of the second semiconductor body 120 being a silicon body is removed with e.g. an alkaline etchant.
- the length of the second semiconductor body 120 is shortened.
- the position of the upper end of the second semiconductor body 120 is retracted below the upper surface of the insulating film 64 .
- the core film 150 protruding above the insulating film 64 deposited on the staircase section 2 may be removed after this etching of the second semiconductor body 120 .
- that core film 150 may be left.
- FIGS. 22A to 23B are schematic sectional views showing a further alternative example of the method for forming a contact structure in the staircase section 2 .
- an insulating layer 65 doubling as a cover layer shown in FIG. 22A is formed on the staircase section 2 . Furthermore, the second columnar part CL 2 penetrating through the insulating layer 65 and the second stacked part 100 b to the substrate 10 is formed.
- the insulating layer 65 is e.g. a layer of silicon oxide-based material.
- the first layer 71 has not yet been replaced by an electrode layer 70 . Then, replacement of the first layer 71 by the electrode layer 70 is performed like the aforementioned steps.
- a resist film 66 is formed on the insulating layer 65 and patterned. Some of the plurality of second columnar parts CL 2 formed on the lower stage side are not covered with the resist film 66 . The second columnar parts CL 2 on the upper stage side above the second columnar parts CL 2 on the lower stage side are covered with the resist film 66 . In the second columnar parts CL 2 not covered with the resist film 66 , the upper end of the second semiconductor body 120 is exposed from the resist film 66 .
- the second semiconductor body 120 of the second columnar part CL 2 not covered with the resist film 66 is etched by e.g. RIE technique.
- the upper end of the second semiconductor body 120 is retracted downward.
- a process for reducing the planar size of the resist film 66 (slimming process) is performed.
- the edge 66 a of the resist film 66 is retracted in the X-direction from the lower stage side to the upper stage side of the staircase section 2 .
- the upper end of the second semiconductor body 120 formed in the region adjacent on the upper stage side of the stage in which the second semiconductor body 120 is etched in the previous step is exposed from the slimmed resist film 66 .
- the second semiconductor body 120 not covered with the resist film 66 is etched by RIE technique.
- the upper end of the second semiconductor body 120 is retracted downward.
- the upper end of the semiconductor body 120 on the lower stage side etched in the previous step is further retracted downward.
- the slimming process of the resist film 66 and the etching of the second semiconductor body 120 are repeated.
- the upper end of the second semiconductor body 120 on the lower stage side may be retracted below the electrode layer 70 .
- the second semiconductor body 120 may be eliminated.
- the second layer 72 is left intact as an insulating layer without forming an air gap between the electrode layers 70 , including the memory cell array shown in FIG. 25B .
- the second columnar part CL 2 including the second semiconductor body 120 only needs to function as a support for the second stacked part 100 b including an air gap produced in the process of replacing the first layer 71 by an electrode layer 70 . Subsequently, the second semiconductor body 120 may be eliminated.
- the core film 150 in the portion in which the second semiconductor body 120 is etched may be left or removed.
- the second semiconductor body 120 is etched, and a void is formed inside the memory film 30 .
- an insulating film 67 is buried in the void.
- an electrode layer may be formed as the first layer 71 , and a sacrificial layer may be formed as the second layer 72 . Then, the electrode layer may be left intact, and the sacrificial layer may be removed to form an air gap between the electrode layers.
- the second layer 72 as a sacrificial layer may be replaced by an insulating layer. This also applies to the second stacked part 100 b .
- the electrode layer is a metal layer.
- the sacrificial layer is a silicon oxide layer, or a metal layer different from the electrode layer.
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Abstract
Description
- This application is based upon and claims the benefit of priority from U.S.
Provisional Patent Application 62/256,956, filed on Nov. 18, 2015; the entire contents of which are incorporated herein by reference. - Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.
- There is proposed a three-dimensional memory device having a structure in which a plurality of columnar parts including a charge storage film and a semiconductor body penetrate a plurality of electrode layers stacked with an insulator.
- There is also proposed a structure in which an air gap is formed as the insulator between the electrode layers. The plurality of electrode layers stacked with the air gap are supported by the columnar parts.
- There is also proposed a method for stacking a plurality of sacrificial layers with interlayer films to form a stacked body, forming the columnar parts in the stacked body, and then removing the sacrificial layers to replace them by electrode layers. After removing the sacrificial layers and before replacing them by electrode layers, the plurality of interlayer films stacked with the air gap are supported by the columnar parts.
- There is also proposed a contact structure for connecting the electrode layers of the three-dimensional memory device to a control circuit. In this structure, the plurality of electrode layers are processed in a staircase shape. An air gap may be formed also in the portion of the stacked body in which the staircase structure is formed. This also requires support by the columnar parts. The contact via reaching the staircase-shaped electrode layers from above may interfere with the semiconductor body of the columnar part.
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FIG. 1 is a schematic plan view showing an example of a planar layout of a semiconductor device of an embodiment; -
FIG. 2 is a schematic perspective view of a memory cell array of the semiconductor device of the embodiment; -
FIG. 3 is a schematic sectional view of the memory cell array of the semiconductor device of the embodiment; -
FIG. 4A is a partial enlarged view of the cross section shown inFIG. 3 , andFIG. 4B is a sectional view taken along A-A′ inFIG. 4A ; -
FIG. 5A is a schematic plan view showing an example of a planar layout of a staircase section of the semiconductor device of the embodiment, andFIG. 5B is a schematic sectional view of the staircase section; -
FIGS. 6A to 13B are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the embodiment; -
FIG. 14A is a schematic plan view showing a method for manufacturing the semiconductor device of the embodiment; -
FIGS. 14B to 23B are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the embodiment; -
FIG. 24A is a schematic plan view showing another example of a planar layout of a staircase section of the semiconductor device of the embodiment, andFIG. 24B is a schematic sectional view of the another example of the staircase section; and -
FIGS. 25A and 25B are schematic sectional views of another example of a memory cell array of the semiconductor device of the embodiment. - According to one embodiment, a semiconductor device includes a substrate, a stacked body provided above the substrate, a first columnar part, an insulating layer, a plurality of contact vias, and a plurality of second columnar parts. The stacked body includes a plurality of electrode layers stacked with an insulator. The electrode layers have a plurality of end parts formed in a staircase shape. The stacked body includes a first stacked part and a second stacked part including the end parts. The first columnar part includes a first semiconductor body extending in a stacking direction in the first stacked part, and a stacked film provided between the first semiconductor body and one of the electrode layers. The stacked film includes a charge storage part. The insulating layer is provided above the second stacked part. The plurality of contact vias extend in the stacking direction in the insulating layer, and are in contact with the end parts of the electrode layers. The plurality of second columnar parts extend in the stacking direction in the second stacked part, and include a plurality of second semiconductor bodies being different in length in the stacking direction.
- In the embodiment, the semiconductor device is described with reference to e.g. a semiconductor memory device including a memory cell array having a three-dimensional structure.
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FIG. 1 is a schematic plan view showing an example of the planar layout of the semiconductor device of the embodiment. - The semiconductor device of the embodiment includes a
memory cell array 1 and astaircase section 2 provided outside thememory cell array 1. Thememory cell array 1 and thestaircase section 2 are provided on the same substrate. -
FIG. 2 is a schematic perspective view of thememory cell array 1. - In
FIG. 2 , two directions parallel to the major surface of thesubstrate 10 and orthogonal to each other are referred to as X-direction and Y-direction. The direction orthogonal to both the X-direction and the Y-direction is referred to as Z-direction (stacking direction), - The X-direction and the Y-direction shown in
FIG. 1 correspond to the X-direction and the Y-direction shown inFIG. 2 . Thestaircase section 2 is provided outside thememory cell array 1 in the X-direction. - The X-direction, the Y-direction, and the Z-direction shown in the other figures also correspond to the X-direction, the Y-direction, and the Z-direction shown in
FIG. 2 . - As shown in
FIG. 2 , thememory cell array 1 includes asubstrate 10, a firststacked part 100 a provided on the major surface of thesubstrate 10, a plurality of first columnar parts CL1, a plurality ofseparation parts 9, and an upper interconnect provided on the firststacked part 100 a.FIG. 2 shows e.g. a bit line BL and a source line SL as the upper interconnect. - The first columnar part CL1 is formed like a circular column or elliptical column extending in the stacking direction (Z-direction) in the first
stacked part 100 a. Theseparation part 9 spreads in the stacking direction (Z-direction) and the X-direction of the firststacked part 100 a, Theseparation part 9 separates the firststacked part 100 a into a plurality of blocks in the Y-direction. - The plurality of first columnar parts CL1 are arranged in e.g. a staggered arrangement. Alternatively, the plurality of first columnar parts CL1 may be arranged in a square lattice along the X-direction and the Y-direction.
- A plurality of bit lines BL are provided on the first
stacked part 100 a. The bit lines BL are e.g. metal films extending in the Y-direction. The bit lines BL are separated from each other in the X-direction. - The upper end of the first columnar part CL1 is connected to the bit line BL via a contact part Cb, The plurality of first columnar parts CL1, each of which is selected from each of blocks separated in the Y-direction by the
separation part 9, are connected to one common bit line BL. -
FIG. 3 is a schematic sectional view of thememory cell array 1. - The first
stacked part 100 a includes a plurality of electrode layers 70 stacked on the major surface of thesubstrate 10. The plurality of electrode layers 70 are stacked with anair gap 40 interposed in the direction (Z-direction) perpendicular to the major surface of thesubstrate 10. Instead of theair gap 40, an insulating layer may be provided as an insulator between the electrode layers 70. Theelectrode layer 70 is a metal layer such as a tungsten layer or molybdenum layer. - The stacked body including the plurality of electrode layers 70 is provided also in the
staircase section 2 described later with reference toFIG. 5B . In the stacked body, the portion provided in thememory cell array 1 is referred to as firststacked part 100 a, and the portion provided in thestaircase section 2 is referred to as secondstacked part 100 b. - An insulating
film 41 is provided between the major surface of thesubstrate 10 and thelowermost electrode layer 70. An insulatingfilm 42 is provided on theuppermost electrode layer 70. An insulatingfilm 43 is provided on the insulatingfilm 42. -
FIG. 4A is a partial enlarged view of the cross section shown inFIG. 3 .FIG. 4B is a sectional view taken along A-A′ inFIG. 4A . - The first columnar part CL1 includes a
memory film 30, afirst semiconductor body 20, and an insulatingcore film 50. Thefirst semiconductor body 20 extends like a pipe in the stacking direction (Z-direction) in the firststacked part 100 a. Thememory film 30 is provided between theelectrode layer 70 and thefirst semiconductor body 20. Thememory film 30 surrounds thefirst semiconductor body 20 from the outer peripheral side. Thecore film 50 is provided inside the pipe-shapedfirst semiconductor body 20. The upper end of thefirst semiconductor body 20 is electrically connected to the bit line BL via the contact part Cb shown inFIG. 2 . - The
memory film 30 is a stacked film including atunnel insulating film 31, a charge storage film (charge storage part) 32, and ablock insulating film 33. Theblock insulating film 33, thecharge storage film 32, and thetunnel insulating film 31 are provided between theelectrode layer 70 and thefirst semiconductor body 20 sequentially from theelectrode layer 70 side. Thetunnel insulating film 31 is in contact with thefirst semiconductor body 20. Theblock insulating film 33 is in contact with theelectrode layer 70. Thecharge storage film 32 is provided between theblock insulating film 33 and thetunnel insulating film 31. - The
first semiconductor body 20 extends continuously in the stacking direction of the firststacked part 100 a. Theair gap 40 between the vertically adjacent electrode layers 70 extends to thefirst semiconductor body 20 side so as to divide at least theblock insulating film 33 and thecharge storage film 32 of thememory film 30 in the stacking direction. That is, theblock insulating film 33 and thecharge storage film 32 are separated in the stacking direction via theair gap 40. Thetunnel insulating film 31 may be continued or divided in the stacking direction. - The
memory film 30 is provided between the inner peripheral surface of theelectrode layer 70 surrounding the first columnar part CL1, and the outer peripheral surface of thefirst semiconductor body 20 continuously in the direction connecting the inner peripheral surface and the outer peripheral surface. The plurality of electrode layers 70 are physically connected to the first columnar part CL1 via thememory film 30 and supported by the first columnar part CL1. - The outer peripheral surface of the
first semiconductor body 20, and the upper surface and the lower surface of theelectrode layer 70 are not exposed to theair gap 40, but covered and protected with aprotective film 56. Theprotective film 56 is an insulating film such as silicon oxide film. - The
first semiconductor body 20, thememory film 30, and theelectrode layer 70 constitute a memory cell MC. InFIG. 4A , one memory cell MC is schematically shown by the broken line. The memory cell MC has a vertical transistor structure in which thefirst semiconductor body 20 is surrounded with theelectrode layer 70 via thememory film 30. - In the memory cell MC having the vertical transistor structure, the
first semiconductor body 20 is e.g. a channel body of silicon. Theelectrode layer 70 functions as a control gate. Thecharge storage film 32 functions as a data storage layer for storing charge injected from thefirst semiconductor body 20. - The semiconductor memory device of the embodiment is a nonvolatile semiconductor memory device capable of electrically and freely erasing/writing data and retaining its memory content even when powered off.
- The memory cell MC is e.g. a charge trap type memory cell. The
charge storage film 32 includes a large number of trap sites for trapping charge in the insulating film, and includes e.g. silicon nitride film. Alternatively, thecharge storage film 32 may be a conductive floating gate surrounded with an insulator. - The
tunnel insulating film 31 serves as a potential barrier when charge is injected from thefirst semiconductor body 20 into thecharge storage film 32, or when the charge stored in thecharge storage film 32 is released into thefirst semiconductor body 20. Thetunnel insulating film 31 includes e.g. silicon oxide film. - The
block insulating film 33 prevents the charge stored in thecharge storage film 32 from being released into theelectrode layer 70. Theblock insulating film 33 suppresses back tunneling of electrons from theelectrode layer 70 at the time of erase operation. Theblock insulating film 33 includes e.g. at least one of silicon oxide film and metal oxide film. - As shown in
FIG. 2 , a drain side select transistor STD is provided in the upper end part of the first columnar part CL1. A source side select transistor STS is provided in the lower end part of the first columnar part CL1. For instance, thelowermost electrode layer 70 functions as a control gate of the source side select transistor STS. For instance, theuppermost electrode layer 70 functions as a control gate of the drain side select transistor STD. - A plurality of memory cells MC are provided between the drain side select transistor STD and the source side select transistor STS. The memory cells MC, the drain side select transistor STD, and the source side select transistor STS are series connected through the
first semiconductor body 20 and constitute one memory string. Such memory strings are arranged in e.g. a staggered arrangement in the plane direction parallel to the X-Y plane. Thus, the plurality of memory cells MC are provided three-dimensionally in the X-direction, the Y-direction, and the Z-direction. - As shown in
FIGS. 2 and 3 , theseparation part 9 separating the firststacked part 100 a in the Y-direction includes an interconnect part LI. The interconnect part LI is e.g. a metal-containing film spread in the Z-direction and the X-direction. As shown inFIG. 3 , an insulatingfilm 44 is provided on the sidewall of the interconnect part LI. The insulatingfilm 44 is provided between the firststacked part 100 a and the interconnect part LI. - The upper end of the interconnect part LI is connected to the source line SL, shown in
FIG. 2 , provided on the firststacked part 100 a. The lower end of the interconnect part LI is in contact with thesubstrate 10 as shown inFIG. 3 . The lower end of thefirst semiconductor body 20 is in contact with thesubstrate 10. Thesubstrate 10 is e.g. a silicon substrate doped with impurity and having conductivity. Thus, the lower end of thefirst semiconductor body 20 is electrically connectable to the source line SL via thesubstrate 10 and the interconnect part LI. - By controlling the potential applied to the
lowermost electrode layer 70 provided on the surface of thesubstrate 10 via the insulatingfilm 41, a channel is induced in the surface of thesubstrate 10 between the lower end of the interconnect part LI and the lower end of thefirst semiconductor body 20. Thus, a current can be passed between the lower end of the interconnect part LI and the lower end of thefirst semiconductor body 20. - The
lowermost electrode layer 70 functions as a control gate for inducing a channel in the surface of thesubstrate 10. The insulatingfilm 41 functions as a gate insulating film. The portion between the surface of thesubstrate 10 and thelowermost electrode layer 70 is not an air gap, but the insulatingfilm 41 having higher dielectric constant than air. This enables fast driving by capacitive coupling between thelowermost electrode layer 70 and the surface of thesubstrate 10. - On the other hand, an
air gap 40 is formed between the electrode layers 70, which are control gates of the memory cells MC adjacent in the stacking direction. This can reduce the interconnect capacitance between the vertically adjacent electrode layers 70 and enables fast operation of the memory cell MC. Furthermore, this can suppress interference between adjacent cells such as threshold variation due to capacitive coupling between the vertically adjacent electrode layers 70. - According to the embodiment, the
charge storage films 32 are separated in the stacking direction. Thus, the charge stored in thecharge storage film 32 is not released in the stacking direction. Accordingly, the memory cell MC is superior in charge retention characteristics. - Next, the
staircase section 2 is described. -
FIG. 5A is a schematic plan view showing an example of the planar layout of thestaircase section 2.FIG. 5B is a schematic sectional view of thestaircase section 2.FIG. 5B corresponds to a cross section taken along B-B′ inFIG. 5A . - The plurality of electrode layers 70 extend in the X-direction from the region with the
memory cell array 1 formed therein to the region with thestaircase section 2 formed therein. A secondstacked part 100 b is provided on thesubstrate 10 in the region with thestaircase section 2 formed therein. The secondstacked part 100 b includes the plurality of electrode layers 70 stacked in the Z-direction with theair gap 40. The insulatingfilm 41 is provided between thelowermost electrode layer 70 and thesubstrate 10 in the secondstacked part 100 b. - The plurality of electrode layers 70 of the second
stacked part 100 b have a plurality of end parts (or terrace parts) 70 a formed in a staircase shape. Theend parts 70 a of the electrode layers 70 are arranged in a staircase shape along the X-direction. - As in the
memory cell array 1, the secondstacked part 100 b is also separated into a plurality of blocks in the Y-direction by theseparation part 9 extending in the X-direction as shown inFIG. 5A . - A
first cover layer 61 is provided on the secondstacked part 100 b so as to cover the plurality of staircase-shapedend parts 70 a. An insulatinglayer 46 is provided on thefirst cover layer 61 so as to eliminate or reduce the step difference with thememory cell array 1. Thefirst cover layer 61 and the insulatinglayer 46 are not shown inFIG. 5A . - A plurality of contact vias 91 extending in the Z-direction are provided in the insulating
layer 46. Each lower end of the contact vias 91 is connected to thecorresponding end part 70 a of the electrode layers 70. - The contact via 91 is a metal-containing conductor. Each contact via 91 is connected to the upper interconnect, not shown, provided above the second
stacked part 100 b. - Each
electrode layer 70 of thestaircase section 2 is integrally connected to thecorresponding electrode layer 70 of thememory cell array 1. Thus, theelectrode layer 70 of thememory cell array 1 is electrically connected to the upper interconnect via the contact via 91 of thestaircase section 2. The upper interconnect is electrically connected to e.g. a control circuit formed on the surface of thesubstrate 10. - Also in the second
stacked part 100 b, theair gap 40 is formed between the plurality of electrode layers 70. The secondstacked part 100 b also includes a plurality of second columnar parts CL2 supporting the plurality of electrode layers 70 stacked with theair gap 40. - At least one contact via 91 is provided per one
end part 70 a of oneelectrode layer 70 in one block separated from the other blocks by theseparation part 9. In the example shown inFIG. 5A , one contact via 91 and a plurality of second columnar parts CL2 placed around that contact via 91 are provided per oneend part 70 a of oneelectrode layer 70 in one block. In the example shown inFIG. 5A , four second columnar parts CL2 are equally spaced around the one contact via 91. - The second columnar parts CL2 are formed at the same time as the first columnar parts CL1 of the
memory cell array 1 are formed. The second columnar part CL2 is formed like a circular column or elliptical column extending in the stacking direction (Z-direction) in the secondstacked part 100 b. - The second columnar part CL2 includes an insulating
film 130, asecond semiconductor body 120, and acore film 150. The insulatingfilm 130 is formed at the same time as thememory film 30 of the first columnar part CL1 is formed. The insulatingfilm 130 includes a film of the same stacked structure or the same material as thememory film 30. Thesecond semiconductor body 120 is formed at the same time from the same material as thefirst semiconductor body 20 of the first columnar part CL1 is formed. Thecore film 150 is formed at the same time from the same material as thecore film 50 of the first columnar part CL1 is formed. - The
second semiconductor body 120 extends like a pipe in the stacking direction (Z-direction) in the secondstacked part 100 b. The insulatingfilm 130 is provided between theelectrode layer 70 and thesecond semiconductor body 120. The insulatingfilm 130 surrounds thesecond semiconductor body 120 from the outer peripheral side. Thecore film 150 is provided inside the pipe-shapedsecond semiconductor body 120. - The lower end of the
second semiconductor body 120 is in contact with thesubstrate 10. However, the upper end of thesecond semiconductor body 120 is electrically connected to nowhere. Thesecond semiconductor body 120 functions as a mere strut supporting the plurality of electrode layers 70. - The insulating
film 130 is provided between the inner peripheral surface of theelectrode layer 70 surrounding the second columnar part CL2 and the outer peripheral surface of thesecond semiconductor body 120 continuously in the direction connecting the inner peripheral surface and the outer peripheral surface. The plurality of electrode layers 70 are physically connected to the second columnar part CL2 via the insulatingfilm 130 and supported by the second columnar part CL2. - The position of the upper end of the second columnar part CL2 is lower than the position of the upper end of the first columnar part CL1. The length (Z-direction length) of the second columnar part CL2 is shorter than the length of the first columnar part CL1. The position of the upper end of the
second semiconductor body 120 is lower than the position of the upper end of thefirst semiconductor body 20. The length (Z-direction length) of thesecond semiconductor body 120 is shorter than the length of thefirst semiconductor body 20. - The plurality of second columnar parts CL2 are not equal in length. The plurality of second columnar parts CL2 provided in the second
stacked part 100 b include a plurality of second columnar parts CL2 different in length. In particular, the plurality ofsecond semiconductor bodies 120 are not equal in length. The plurality ofsecond semiconductor bodies 120 provided in the secondstacked part 100 b include a plurality ofsecond semiconductor bodies 120 different in length. - The plurality of
second semiconductor bodies 120 include asecond semiconductor body 120 having aprotrusion 120 a protruding above the secondstacked part 100 b. Thatsecond semiconductor body 120 penetrates through theend part 70 a of theelectrode layer 70 and through the electrode layers 70 between thatend part 70 a and thesubstrate 10. Theprotrusion 120 a protrudes above theend part 70 a. - The length of the
protrusion 120 a is shorter than the length of the portion of thesecond semiconductor body 120 extending below thatprotrusion 120 a in the secondstacked part 100 b. - The second
stacked part 100 b includes theend parts 70 a of the electrode layers 70 formed in a staircase shape. The secondstacked part 100 b includes a lower stage part and an upper stage part. In the lower stage part, the number of stacked electrode layers 70 is relatively small. In the upper stage part, the number of stacked electrode layers 70 is larger than that in the lower stage part. The relationship between the lower stage part and the upper stage part is also applicable to the relationship between the stage parts adjacent in the X-direction, and the relationship between the stage parts spaced in the X-direction. - The length of the lower-stage second columnar part CL2 provided in the lower stage part is shorter than the length of the upper-stage second columnar part CL2 provided in the upper stage part. The length of the lower-stage
second semiconductor body 120 provided in the lower stage part is shorter than the length of the upper-stagesecond semiconductor body 120 provided in the upper stage part. - The plurality of contact vias 91 include lower-stage contact vias 91 in contact with the
end parts 70 a of relatively lower electrode layers 70, and upper-stage contact vias 91 in contact with theend parts 70 a of relatively upper electrode layers 70. The upper ends of the plurality of contact vias 91 are located at a generally equal height. The lower ends of the contact vias 91 on the relatively lower stage side are located on the relatively lower side. Thus, the length of the upper-stage contact via 91 is shorter than the length of the lower-stage contact via 91. The length of the lower-stage contact via 91 is longer than the length of the upper-stage contact via 91. - The length of the lower-stage second columnar part CL2 placed adjacent to or around the lower-stage contact via 91 is shorter than the length of the upper-stage second columnar part CL2 placed adjacent to or around the upper-stage contact via 91. The length of the lower-stage
second semiconductor body 120 placed adjacent to or around the lower-stage contact via 91 is shorter than the length of the upper-stagesecond semiconductor body 120 placed adjacent to or around the upper-stage contact via 91. - As shown in
FIG. 5A , the side surface of the contact via 91 is spaced from the side surface of the second columnar part CL2 placed adjacent to or around that contact via 91. The contact via 91 is not in contact with thesecond semiconductor body 120. - Thus, the contact via 91 and the
substrate 10 are not electrically connected (short-circuited) through thesecond semiconductor body 120. - In the example shown in
FIG. 5A , the contact via 91 is also not in contact with the insulatingfilm 130 of the second columnar part CL2. The insulatingfilm 130 includes a film of the same material as thememory film 30 of the first columnar part CL1. The insulatingfilm 130 includes a film of the same material as theblock insulating film 33 at the outermost periphery, and includes a film of the same material as thecharge storage film 32 inside. The contact via 91 may be in contact with the film in the insulatingfilm 130 of the same material as theblock insulating film 33. - The
charge storage film 32 has a lower mobility than the semiconductor film. However, migration of electrons may occur in thecharge storage film 32. Thus, it is not desirable that the contact via 91 be in contact with the film in the insulatingfilm 130 of the same material as thecharge storage film 32. - The contact via 91 extends upward from the
end part 70 a of theelectrode layer 70 of the connection target. Thus, in thesecond semiconductor body 120, theprotrusion 120 a protruding above theend part 70 a of theelectrode layer 70 may contact with the contact via 91. - The contact via 91 is formed in a hole formed by reactive ion etching (RIE) technique in the insulating
layer 46 and thefirst cover layer 61. In the RIE, the hole side surface may be tapered so that the hole diameter decreases with the depth. In this case, as shown inFIG. 24B described later, in the contact via 91, aportion 91 a thicker (larger in diameter) than thelower end part 91 b is formed above thelower end part 91 b in contact with theend part 70 a of theelectrode layer 70. If thesecond semiconductor body 120 extends to the upper end of the contact via 91, the contact via 91 may be in contact with thesecond semiconductor body 120 in theupper part 91 a even though the contact via 91 is not in contact with thesecond semiconductor body 120 in thelower end part 91 b. - According to the embodiment, the
second semiconductor body 120 is formed at the same time as thefirst semiconductor body 20 of thememory cell array 1 is formed. Then, in thesecond semiconductor body 120, theprotrusion 120 a protruding above theend part 70 a of theelectrode layer 70 is etched as described later to shorten the length of theprotrusion 120 a. - Thus, the
second semiconductor body 120 can be excluded from the region adjacent to or around the upper part of the contact via 91, which tends to be thicker than the lower end part. The possibility of contact is reduced between the contact via 91 and thesecond semiconductor body 120. This can prevent current leakage between the contact via 91 and thesubstrate 10 through thesecond semiconductor body 120. - In the structure of the embodiment, the contact via 91 is less likely to be in contact with the
second semiconductor body 120. This structure enables reduction of the distance between the contact via 91 and thesecond semiconductor body 120. Thus, the terrace region (area of theend part 70 a) shown inFIG. 5A can be reduced. The terrace region includes, for example, one contact via 91 and foursecond semiconductor bodies 120 therearound. This leads to the reduction of the chip size. -
FIG. 24A is a schematic plan view showing the planar layout of an alternative example of thestaircase section 2. FIG. 24B is a schematic sectional view of the alternative example of thestaircase section 2.FIG. 24B corresponds to a cross section taken along C-C′ inFIG. 24A . - The contact via 91 includes an
upper part 91 a located above the upper end of thesecond semiconductor body 120. The thickness (diameter) of theupper part 91 a is larger than the thickness (diameter) of thelower end part 91 b in contact with theend part 70 a of theelectrode layer 70. The side surface of the contact via 91 is tapered so that the contact via 91 is thinned toward thelower end part 91 b. - In
FIG. 24B , the extension line extending upward from the upper end of thesecond semiconductor body 120 is virtually shown by the broken line. The side surface of theupper part 91 a of the contact via 91 overlaps the region in which thesecond semiconductor body 120 placed adjacent to or around that contact via 91 is extended upward. As shown in the planar layout ofFIG. 24A , theoutline 91 aa of the upper end of the contact via 91 spreads to part of the placement region of thesecond semiconductor body 120 therearound. - According to the embodiment, the length of the
protrusion 120 a of thesecond semiconductor body 120 is shortened. Thus, even if theupper part 91 a of the contact via 91 is made thicker, theupper part 91 a is not in contact with thesecond semiconductor body 120. The resistance of the contact via 91 can be reduced by forming a thick portion (upper part 91 a) in the contact via 91. -
FIG. 23B is a schematic sectional view showing a further alternative example of thestaircase section 2. -
FIG. 25B is a schematic sectional view of a memory cell array in a semiconductor device including thestaircase section 2 shown inFIG. 23B . - As shown in
FIG. 25B , an insulatinglayer 72 rather than an air gap is provided between the plurality of electrode layers 70. An insulatingfilm 48 is provided as a separation part separating the firststacked part 100 a into a plurality in the Y-direction. Thememory film 30 is not divided in the vertical direction (Z-direction). - In the example shown in
FIG. 23B , the plurality ofsecond semiconductor bodies 120 include asecond semiconductor body 120 with the upper end located in the secondstacked part 100 b without protruding from the secondstacked part 100 b. An insulatinglayer 65 doubling as a cover layer is provided on the secondstacked part 100 b so as to eliminate or reduce the step difference with thememory cell array 1. - Also in the second
stacked part 100 b, as in the firststacked part 100 a shown inFIG. 25B , an insulatinglayer 72 rather than an air gap is provided between the plurality of electrode layers 70. Thus, the plurality of electrode layers 70 can maintain the stacked state with a prescribed spacing even without the support of the second columnar parts CL2. - As shown in
FIG. 18A described later, asacrificial layer 71 is formed in the portion in which theelectrode layer 70 is to be formed. Then, thesacrificial layer 71 is removed, and anair gap 73 is formed between the insulatinglayers 72 as shown inFIG. 18B . At this time, the second columnar part CL2 supports the insulatinglayer 72. - After the
electrode layer 70 is formed in theair gap 73, if the insulatinglayer 72 is not removed, theelectrode layer 70 is supported by the insulatinglayer 72. Thus, as in part of thesecond semiconductor bodies 120 shown inFIG. 23A , the upper end may be retracted downward from theend part 70 a of theelectrode layer 70. Alternatively, thesecond semiconductor body 120 may be eliminated. - Thus, the
protrusion 120 a of thesecond semiconductor body 120 likely to be in contact with the contact via 91 is eliminated. This can enlarge the contact area between the contact via 91 and theend part 70 a of theelectrode layer 70. Furthermore, the diameter of the contact via 91 can be increased. There are no restrictions to the placement of thesecond semiconductor body 120. This can further reduce the resistance of the contact via 91. - Next, a method for manufacturing a semiconductor device of the embodiment is described.
- First, a method for forming the
memory cell array 1 is described with reference toFIGS. 6A to 11B . - As shown in
FIG. 6A , a firststacked part 100 a is formed on asubstrate 10. Thesubstrate 10 is e.g. a semiconductor substrate such as a silicon substrate. - An insulating
film 41 is formed on the major surface (front surface) of thesubstrate 10. Afirst layer 71 and asecond layer 72 are alternately stacked on the insulatingfilm 41. The step of alternately stacking afirst layer 71 and asecond layer 72 is repeated to form a plurality offirst layers 71 and a plurality ofsecond layers 72 on thesubstrate 10. Thefirst layer 71 is a sacrificial layer to be removed in a later step. Thefirst layer 71 is e.g. a silicon nitride layer. Thesecond layer 72 is a sacrificial layer to be removed in a later step. Thesecond layer 72 is e.g. a silicon oxide layer. Alternatively, as shown inFIG. 25B , thesecond layer 72 may be an insulating layer (e.g., silicon oxide layer) left without being removed. - The lowermost
first layer 71 is formed on the insulatingfilm 41. The lowermostsecond layer 72 is formed on the lowermostfirst layer 71. An insulatingfilm 42 is formed on the uppermostfirst layer 71. The uppermostfirst layer 71 is formed between the uppermostsecond layer 72 and the insulatingfilm 42. - Next, as shown in
FIG. 6B , a plurality of memory holes MH are formed in the firststacked part 100 a. The memory holes MH are formed by RIE technique using a mask, not shown. The memory hole MH penetrates through the firststacked part 100 a to thesubstrate 10. - As shown in
FIG. 7A , amemory film 30 is formed on the side surface and bottom of the memory hole MH. Thememory film 30 formed at the bottom of the memory hole MH is removed as shown inFIG. 7B by e.g. RIE technique using a mask, not shown. - Next, as shown in
FIG. 8A , afirst semiconductor body 20 is formed inside thememory film 30. Thefirst semiconductor body 20 is formed on the side surface of thememory film 30 and at the bottom of the memory hole MH where thesubstrate 10 is exposed. Thefirst semiconductor body 20 is formed as e.g. an amorphous silicon film, and then crystallized into a polycrystalline silicon film by heat treatment. - As shown in
FIG. 8B , acore film 50 is formed inside thefirst semiconductor body 20. Thus, a first columnar part CL1 is formed. - The films deposited on the insulating
film 42 shown inFIG. 8B are removed by chemical mechanical polishing (CMP) or etch-back. Then, as shown inFIG. 9A , an insulatingfilm 43 is formed on the insulatingfilm 42. The insulatingfilm 43 covers the upper end of the first columnar part CL1. - Then, by RIE technique using a mask, not shown, a plurality of slits ST are formed in the first
stacked part 100 a including the insulatingfilm 43, the insulatingfilm 42, thefirst layers 71, thesecond layers 72, and the insulatingfilm 41. The slit ST penetrates through the firststacked part 100 a to thesubstrate 10. - Next, the
first layer 71 is removed with an etchant or etching gas supplied through the slit ST. For instance, thefirst layer 71 being a silicon nitride layer is removed with an etchant containing phosphoric acid. - As shown in
FIG. 9B , anair gap 73 is formed between the vertically adjacentsecond layers 72 by the removal of thefirst layer 71. Theair gap 73 is formed also between the insulatingfilm 41 and the lowermostsecond layer 72, and between the uppermostsecond layer 72 and the insulatingfilm 42. - The insulating
film 43, the insulatingfilm 42, thesecond layers 72, the insulatingfilm 41, and thesubstrate 10 have high etching resistance to phosphoric acid, and remain without being removed. - The plurality of
second layers 72 stacked with theair gap 73 are supported by the first columnar part CL1. The lower end of the first columnar part CL1 is supported by thesubstrate 10. The upper end of the first columnar part CL1 is supported by the insulatingfilm 42 and the insulatingfilm 43. - After the
first layer 71 is removed, anelectrode layer 70 shown inFIG. 10A is formed in theair gap 73. For instance, theelectrode layer 70 is formed by chemical vapor deposition (CVD) technique. A source gas is supplied to theair gap 73 through the slit ST. Thus, theelectrode layer 70 is formed in theair gap 73. Theelectrode layer 70 is a metal layer such as a tungsten layer or molybdenum layer. - Next, the
second layer 72 is removed with an etchant or etching gas supplied through the slit ST. For instance, thesecond layer 72 being a silicon oxide layer is removed with an etchant containing hydrofluoric acid. As shown inFIG. 10B , anair gap 40 is formed between the vertically adjacent electrode layers 70 by the removal of thesecond layer 72. - The insulating
film 43, the insulatingfilm 42, the electrode layers 70, the insulatingfilm 41, and thesubstrate 10 have high etching resistance to hydrofluoric acid, and remain without being removed. - Then, the
memory film 30 exposed to theair gap 40 is removed. Thememory film 30 is removed with an etchant or etching gas supplied through the slit ST and theair gap 40. Theblock insulating film 33 and thecharge storage film 32 are sequentially etched. Thetunnel insulating film 31 may be left. At least theblock insulating film 33 and thecharge storage film 32 are divided in the stacking direction (Z-direction). At the time of this etching of thememory film 30, the upper end of the first columnar part CL1 is covered with the insulatingfilm 43. Thus, etching of the first columnar part CL1 does not proceed from the upper end side. - The plurality of electrode layers 70 stacked with the
air gap 40 are supported by the first columnar part CL1. Theprotective film 56 shown inFIG. 4A may be formed on the inner wall surface of theair gap 40. - Then, as shown in
FIG. 11A , an insulatingfilm 44 is formed on the side surface and bottom of the slit ST. The insulatingfilm 44 has low coverage. Thus, depending on the Z-direction height of theair gap 40, the film thickness of the insulatingfilm 44, and other film formation conditions, the insulatingfilm 44 can be configured to occlude the opening on the slit ST side of theair gap 40 while theair gap 40 is not filled with the insulatingfilm 44. - Alternatively, as shown in
FIG. 25A , an insulatingfilm 49 may be formed on the insulatingfilm 43 so as to occlude the upper end of the slit ST without forming an insulating film in the slit ST. An air gap communicating with theair gap 40 between the electrode layers 70 is left in the slit ST. - The insulating
film 44 formed at the bottom of the slit ST is removed by RIE technique as shown inFIG. 11B . Then, an interconnect part LI is buried in the slit ST as shown inFIG. 3 . Then, the bit line BL, the source line SL and the like shown inFIG. 2 are formed. - Next, a method for forming a contact structure in the
staircase section 2 is described with reference toFIGS. 12A to 17B . - When the first
stacked part 100 a shown inFIG. 6A is formed on thesubstrate 10 in the memory cell array region, a secondstacked part 100 b is formed also on thesubstrate 10 in the region in which thestaircase section 2 is to be formed. The secondstacked part 100 b includes the same insulatingfilm 41, first layers 71, second layers 72, and insulatingfilm 42 as those of the firststacked part 100 a. - In the second
stacked part 100 b, thestaircase section 2 is formed as shown inFIG. 12A . For instance, anisotropic etching of thefirst layers 71 and thesecond layers 72 using a resist film as a mask, reduction of the planar size of the resist film, and anisotropic etching of thefirst layers 71 and thesecond layers 72 using the reduced resist film as a mask are repeated. Thus, thefirst layers 71 and thesecond layers 72 are processed into a staircase shape arranged in the X-direction. - As shown in
FIG. 12B , afirst cover layer 61 is formed on thestaircase section 2. Thefirst cover layer 61 is formed along the staircase shape of thestaircase section 2 and covers the surface of thestaircase section 2. - As shown in
FIG. 13A , asecond cover layer 62 is formed on thefirst cover layer 61. When thestaircase section 2 is formed in the secondstacked part 100 b, a step difference is formed between the firststacked part 100 a and the secondstacked part 100 b. Thefirst cover layer 61 and thesecond cover layer 62 are formed so as to reduce or eliminate the step difference. The upper surface of thesecond cover layer 62 is planarized. This improves the ease and accuracy of lithography and RIE in simultaneously performing the process of forming the first columnar part CL1 in thememory cell array 1 and the process of forming the second columnar part CL2 in thestaircase section 2. - The
second cover layer 62 is a sacrificial layer to be removed later. At the time of etching for removing thesecond cover layer 62, thefirst cover layer 61 covers and protects thestaircase section 2. Thefirst cover layer 61 is an insulating layer to be left without being removed. Thefirst cover layer 61 is e.g. a layer of silicon oxide-based material. Thesecond cover layer 62 is also e.g. a layer of silicon oxide-based material. However, thesecond cover layer 62 has etching selectivity with respect to thefirst cover layer 61. - The
first cover layer 61 and thesecond cover layer 62 are likewise made of silicon oxide-based material. However, the contained elements and their composition ratio can be made different between thefirst cover layer 61 and thesecond cover layer 62 by the difference in e.g. the film formation method such as coating technique and CVD technique. Thus, the etching rate for e.g. the etchant containing hydrofluoric acid can be made different between thefirst cover layer 61 and thesecond cover layer 62 to provide etching selectivity. - As shown in
FIG. 13B , a plurality of second columnar parts CL2 are formed in the secondstacked part 100 b, thefirst cover layer 61, and thesecond cover layer 62. The second columnar part CL2 penetrates through thesecond cover layer 62, thefirst cover layer 61, and the secondstacked part 100 b to thesubstrate 10. The second columnar parts CL2 are formed at the same time as the first columnar parts CL1 of thememory cell array 1 are formed. - That is, when the memory holes MH shown in
FIG. 6B are formed, a plurality of holes having the same depth as the memory holes MH are formed also in thesecond cover layer 62, thefirst cover layer 61, and the secondstacked part 100 b. When thememory film 30 of the first columnar part CL1 is formed, the insulatingfilm 130 of the second columnar part CL2 is formed from the same material. When thefirst semiconductor body 20 of the first columnar part CL1 is formed, thesecond semiconductor body 120 of the second columnar part CL2 is formed from the same material. When thecore film 50 of the first columnar part CL1 is formed, thecore film 150 of the second columnar part CL2 is formed from the same material. At this time, the length (Z-direction length) of the first columnar part CL1 and the second columnar part CL2 is equal. - When the slit ST shown in
FIG. 9A is formed in the firststacked part 100 a, the slit ST is formed also in thesecond cover layer 62, thefirst cover layer 61, and the secondstacked part 100 b as shown inFIG. 14A . Thesecond cover layer 62, thefirst cover layer 61, and the secondstacked part 100 b are divided by the slit ST into a plurality of blocks in the Y-direction. - Next, when the
first layer 71 of the firststacked part 100 a is removed by etching through the slit ST to form theair gap 73 as shown inFIG. 9B , thefirst layer 71 of the secondstacked part 100 b is also removed by etching through the slit ST. Thus, as shown inFIG. 14B , theair gap 73 is formed also between thesecond layers 72 of the secondstacked part 100 b. - Furthermore, when the
electrode layer 70 is formed in theair gap 73 of the firststacked part 100 a, theelectrode layer 70 is formed also in theair gap 73 of the secondstacked part 100 b as shown inFIG. 15A . The plurality of electrode layers 70 of the secondstacked part 100 b have a plurality of end parts (terrace parts) 70 a arranged in a staircase shape in the X-direction. - Next, when the
second layer 72 between the electrode layers 70 of the firststacked part 100 a is removed, thesecond layer 72 of the secondstacked part 100 b is also removed by etching through the slit ST. As shown inFIG. 15B , theair gap 40 is formed between the electrode layers 70 of the secondstacked part 100 b. - The
second layer 72 is a silicon oxide layer. Thesecond layer 72 is removed with e.g. an etchant containing hydrofluoric acid. At this time, thesecond cover layer 62 of the silicon oxide-based material is also removed with the etchant containing hydrofluoric acid as shown inFIG. 15B . Thefirst cover layer 61 is a layer of the silicon oxide-based material having higher etching resistance to the etchant containing hydrofluoric acid than thesecond layer 72 and thesecond cover layer 62. Thus, thefirst cover layer 61 is left without being removed. - The
second layer 72 is removed, and part of the second columnar part CL2 in the length direction (Z-direction) is exposed as shown inFIG. 15B . In the second columnar part CL2, part of the protrusion CL2 a protruding above theend part 70 a of theelectrode layer 70 is exposed. The portion below the exposed part is covered with thefirst cover layer 61 and the secondstacked part 100 b. The lower part of the protrusion CL2 a of the second columnar part CL2 on the near side of theend part 70 a of theelectrode layer 70 is covered with thefirst cover layer 61. The portion above that lower part is exposed. - Next, in the step shown in
FIG. 10B , thememory film 30 of the first columnar part CL1 exposed to theair gap 40 is removed by etching through the slit ST. In this step, thememory film 30 of the second columnar part CL2 exposed to theair gap 40 is also removed as shown inFIG. 16A . Furthermore, thememory film 30 of the protrusion CL2 a exposed above thefirst cover layer 61 is also removed at this time. - As shown in
FIG. 16A , part of thesecond semiconductor body 120 is exposed by the removal of thememory film 30 of the protrusion CL2 a. In thesecond semiconductor body 120, part of theprotrusion 120 a protruding above theend part 70 a of theelectrode layer 70 is exposed. The portion below the exposed part is covered with thefirst cover layer 61 and the secondstacked part 100 b. The lower part of theprotrusion 120 a of thesecond semiconductor body 120 on the near side of theend part 70 a of theelectrode layer 70 is covered with thefirst cover layer 61 via thememory film 30. The portion above that lower part is exposed. - The exposed part of the
second semiconductor body 120 being a silicon body is removed with e.g. an alkaline etchant. As shown inFIG. 16B , the length of thesecond semiconductor body 120 is shortened. The position of the upper end of thesecond semiconductor body 120 is retracted below the upper surface of thefirst cover layer 61. Thecore film 150 protruding above thefirst cover layer 61 is removed before or after removing the exposed part of thesecond semiconductor body 120. Alternatively, thecore film 150 protruding above thefirst cover layer 61 may be left. - After the length of the
second semiconductor body 120 is shortened, an insulatinglayer 46 is formed on thefirst cover layer 61 as shown inFIG. 17A . - As shown in
FIG. 17B , a plurality of contact holes 81 are formed in the insulatinglayer 46 and thefirst cover layer 61. The contact holes 81 are formed by RIE technique using a mask, not shown. - The plurality of contact holes 81 penetrate through the insulating
layer 46 and thefirst cover layer 61 to theend parts 70 a of the corresponding electrode layers 70. - Then, a metal material is buried in the
contact hole 81. Thus, the contact via 91 shown inFIG. 5B is formed. - Next,
FIGS. 18A to 21B are schematic sectional views showing an alternative example of the method for forming a contact structure in thestaircase section 2. - After the step of
FIG. 12A described above, acover layer 63 is formed on thestaircase section 2 as shown inFIG. 18A . Furthermore, a second columnar part CL2 penetrating through thecover layer 63 and the secondstacked part 100 b to thesubstrate 10 is formed. Thecover layer 63 is e.g. a layer of silicon oxide-based material. - Then, replacement of the
first layer 71 by theelectrode layer 70 shown inFIGS. 18B and 19A is performed like the aforementioned steps. - Then, when the
second layer 72 is removed to form theair gap 40 between the electrode layers 70, thecover layer 63 of the same silicon oxide-based material as thesecond layer 72 is also removed. As shown inFIG. 19B , the second columnar part CL2 is exposed in the portion except the portion surrounded circumferentially with theelectrode layer 70. - Next, the
memory film 30 exposed to theair gap 40 is removed. At this time, thememory film 30 of the second columnar part CL2 protruding above the secondstacked part 100 b is also removed. As shown inFIG. 20A , in thesecond semiconductor body 120, theprotrusion 120 a protruding above the secondstacked part 100 b is exposed. - Next, as shown in
FIG. 20B , an insulatingfilm 64 is formed on thestaircase section 2. The insulatingfilm 64 is e.g. a silicon oxide film. The insulatingfilm 64 is deposited on thestaircase section 2, and formed also on the side surface and the upper surface of theprotrusion 120 a of thesecond semiconductor body 120. The insulatingfilm 64 is formed by e.g. plasma CVD technique in which the deposition is thicker in the Z-direction than on the side surface of theprotrusion 120 a of thesecond semiconductor body 120. - Next, the insulating
film 64 formed thinly on the side surface of theprotrusion 120 a of thesecond semiconductor body 120 and the insulatingfilm 64 deposited on the upper surface of theprotrusion 120 a are removed with an etchant or etching gas. As shown inFIG. 21A , part of theprotrusion 120 a of thesecond semiconductor body 120 is exposed. - The insulating
film 64 deposited on thestaircase section 2 is also retracted downward. However, the insulatingfilm 64 deposited on thestaircase section 2 is thicker in film thickness than the insulatingfilm 64 formed on the side surface of theprotrusion 120 a. Thus, the insulatingfilm 64 deposited on thestaircase section 2 remains in the state of covering the secondstacked part 100 b. - The
core film 150 inside theprotrusion 120 a of thesecond semiconductor body 120 is removed during or after the aforementioned etching of the insulatingfilm 64. - The exposed part of the
second semiconductor body 120 being a silicon body is removed with e.g. an alkaline etchant. As shown inFIG. 21B , the length of thesecond semiconductor body 120 is shortened. The position of the upper end of thesecond semiconductor body 120 is retracted below the upper surface of the insulatingfilm 64. InFIG. 20B , thecore film 150 protruding above the insulatingfilm 64 deposited on thestaircase section 2 may be removed after this etching of thesecond semiconductor body 120. Alternatively, thatcore film 150 may be left. - Then, the steps as in
FIGS. 17A and 17B are continued. - Next,
FIGS. 22A to 23B are schematic sectional views showing a further alternative example of the method for forming a contact structure in thestaircase section 2. - After the step of
FIG. 12A described above, an insulatinglayer 65 doubling as a cover layer shown inFIG. 22A is formed on thestaircase section 2. Furthermore, the second columnar part CL2 penetrating through the insulatinglayer 65 and the secondstacked part 100 b to thesubstrate 10 is formed. The insulatinglayer 65 is e.g. a layer of silicon oxide-based material. At this time, thefirst layer 71 has not yet been replaced by anelectrode layer 70. Then, replacement of thefirst layer 71 by theelectrode layer 70 is performed like the aforementioned steps. - Then, as shown in
FIG. 22A , a resistfilm 66 is formed on the insulatinglayer 65 and patterned. Some of the plurality of second columnar parts CL2 formed on the lower stage side are not covered with the resistfilm 66. The second columnar parts CL2 on the upper stage side above the second columnar parts CL2 on the lower stage side are covered with the resistfilm 66. In the second columnar parts CL2 not covered with the resistfilm 66, the upper end of thesecond semiconductor body 120 is exposed from the resistfilm 66. - Then, the
second semiconductor body 120 of the second columnar part CL2 not covered with the resistfilm 66 is etched by e.g. RIE technique. The upper end of thesecond semiconductor body 120 is retracted downward. - Then, a process for reducing the planar size of the resist film 66 (slimming process) is performed. The
edge 66 a of the resistfilm 66 is retracted in the X-direction from the lower stage side to the upper stage side of thestaircase section 2. The upper end of thesecond semiconductor body 120 formed in the region adjacent on the upper stage side of the stage in which thesecond semiconductor body 120 is etched in the previous step is exposed from the slimmed resistfilm 66. - Then, the
second semiconductor body 120 not covered with the resistfilm 66 is etched by RIE technique. Thus, the upper end of thesecond semiconductor body 120 is retracted downward. The upper end of thesemiconductor body 120 on the lower stage side etched in the previous step is further retracted downward. - Subsequently, the slimming process of the resist
film 66 and the etching of thesecond semiconductor body 120 are repeated. By this repetition, as shown inFIG. 23A , the upper end of thesecond semiconductor body 120 on the lower stage side may be retracted below theelectrode layer 70. Alternatively, thesecond semiconductor body 120 may be eliminated. - In this example, the
second layer 72 is left intact as an insulating layer without forming an air gap between the electrode layers 70, including the memory cell array shown inFIG. 25B . Thus, the second columnar part CL2 including thesecond semiconductor body 120 only needs to function as a support for the secondstacked part 100 b including an air gap produced in the process of replacing thefirst layer 71 by anelectrode layer 70. Subsequently, thesecond semiconductor body 120 may be eliminated. - The
core film 150 in the portion in which thesecond semiconductor body 120 is etched may be left or removed. Thesecond semiconductor body 120 is etched, and a void is formed inside thememory film 30. As shown inFIG. 23B , an insulatingfilm 67 is buried in the void. - In the step of forming the first
stacked part 100 a shown inFIG. 6A , an electrode layer may be formed as thefirst layer 71, and a sacrificial layer may be formed as thesecond layer 72. Then, the electrode layer may be left intact, and the sacrificial layer may be removed to form an air gap between the electrode layers. Thesecond layer 72 as a sacrificial layer may be replaced by an insulating layer. This also applies to the secondstacked part 100 b. In this case, for instance, the electrode layer is a metal layer. The sacrificial layer is a silicon oxide layer, or a metal layer different from the electrode layer. - While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions.
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