US20170098654A1 - Non-volatile split gate memory cells with integrated high k metal gate, and method of making same - Google Patents
Non-volatile split gate memory cells with integrated high k metal gate, and method of making same Download PDFInfo
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/7881—Programmable transistors with only two possible levels of programmation
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
Abstract
Description
- This application claims the benefit of U.S. Provisional Application No. 62/236,101 filed Oct. 1, 2015, and which is incorporated herein by reference.
- The present invention relates to non-volatile memory devices.
- Split gate non-volatile memory devices are well known in the art. For example, U.S. Pat. No. 7,927,994 (which is incorporated herein by reference for all purposes) discloses a split gate non-volatile memory cell.
FIG. 1 illustrates an example of such a split gate memory cell formed on asemiconductor substrate 12. Source anddrain regions substrate 12, and define achannel region 18 therebetween. The memory cell includes four conductive gates: afloating gate 22 disposed over and insulated from a first portion of thechannel region 18 and a portion of thesource region 16, acontrol gate 26 disposed over and insulated from thefloating gate 22, anerase gate 24 disposed over and insulated from thesource region 16, and aselect gate 20 disposed over and insulated from a second portion of thechannel region 18. A conductive contact 10 can be formed to electrically connect to thedrain region 14. - The memory cells are arranged in an array, with columns of such memory cells separated by columns of isolation regions. Isolation regions are portions of the substrate in which insulation material is formed. Logic (core) devices and high voltage devices can be formed on the same chip as the memory array, often formed sharing some of the same processing steps. It is also known to make the memory cell gates and the gates of the logic and high voltage gates of a high K metal material (HKMG—high K dielectric underneath metal layer). However, it has been discovered that during logic device processing, the stacks of memory cell structure can be degraded.
- The present invention is a technique for forming a split gate non-volatile memory device on the same chip as logic and high voltage devices with less memory cell structure degradation.
- The aforementioned problems and needs are addressed by a method of forming a pair of memory cells that includes:
-
- forming a polysilicon layer over and insulated from a semiconductor substrate;
- forming a pair of spaced apart conductive control gates over and insulated from the polysilicon layer, wherein the control gates having inner side surfaces facing each other and outer side surfaces facing away from each other;
- forming a first insulation layer that extends directly along the inner and outer side surfaces of the control gates;
- forming a second insulation layer that extends directly along the first insulation layer;
- removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates;
- forming first insulation spacers that extend directly along the second insulation layer and indirectly along the outer side surfaces of the control gates;
- forming second insulation spacers that extend directly along the second insulation and indirectly along the inner side surfaces of the control gates;
- forming an HKMG layer extending along the first and second insulation spacers and along portions of the substrate adjacent the outer side surfaces of the control gates, wherein the HKMG layer includes:
- a layer of high K insulation material, and
- a layer of metal material on the layer of high K insulation material;
- removing portions of the HKMG layer extending along the second insulation spacers;
- removing the second insulation spacers;
- removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates;
- forming a source region in the substrate adjacent the inner side surfaces of the control gates;
- forming a conductive erase gate over and insulated from the source region, wherein the erase gate is insulated from each of the control gates by at least the first insulation layer and the second insulation layer;
- forming conductive word line gates laterally adjacent to the first insulation spacers, wherein for each of the word line gates, the HKMG layer includes a first portion disposed between the word line gate and one of the first insulation spacers and a second portion disposed between the word line gate and the substrate; and
- forming drain regions in the substrate each disposed adjacent to one of the word line gates.
- Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
-
FIG. 1 is a side cross sectional view of a conventional non-volatile memory cell. -
FIGS. 2A and 2C are top views of a semiconductor substrate. -
FIGS. 2B and 2D-2F are side cross sectional views illustrating the steps in forming active and isolation regions in the semiconductor substrate. -
FIGS. 3A-3R are side cross sectional views illustrating the steps in forming non-volatile memory cells. - The present invention solves the above mentioned problems by protecting the memory cell structure during the formation and processing of logic devices formed on the same chip. The method of forming such a memory cell is illustrated in
FIGS. 2A to 2F, 3A to 3R . The method begins with asemiconductor substrate 12, which is preferably of P type and is well known in the art. -
FIGS. 2A to 2F illustrate the well-known STI method of forming isolation regions on a substrate. Referring toFIG. 2A there is shown a top plan view of a semiconductor substrate 12 (or a semiconductor well), which is preferably of P type and is well known in the art. First and second layers ofmaterial first layer 30 can be silicon dioxide (hereinafter “oxide”), which is formed on thesubstrate 12 by any well known technique such as oxidation or oxide deposition (e.g. chemical vapor deposition or CVD). Nitrogen doped oxide or other insulation dielectrics can also be used.Second layer 31 can be silicon nitride (hereinafter “nitride”), which is formed overoxide layer 30 preferably by CVD or PECVD (Plasma Enhanced CVD).FIG. 2B illustrates a cross-section of the resulting structure. - Once the first and
second layers 30/31 have been formed, suitable photo resistmaterial 32 is applied on thenitride layer 31 and a masking step is performed to selectively remove the photo resist material from certain regions (stripes 33) that extend in the Y or column direction, as shown inFIG. 2C . Where the photo-resist material 32 is removed, the exposednitride layer 31 andoxide layer 30 are etched away instripes 33 using standard etching techniques (i.e. anisotropic nitride and oxide/dielectric etch processes) to formtrenches 34 in the structure. A silicon etch process is then used to extendtrenches 34 down into thesilicon substrate 12, as shown inFIG. 2D . Where the photo resist 32 is not removed, thenitride layer 31 andoxide layer 30 are maintained. The resulting structure illustrated inFIG. 2D now definesactive regions 35 interlaced withisolation regions 36. - The structure is further processed to remove the remaining photo resist 32. Then, an isolation material such as silicon dioxide is formed in
trenches 34 by depositing a thick oxide layer, followed by a Chemical-Mechanical-Polishing or CMP etch (usingnitride layer 31 as an etch stop) to remove the oxide layer except for oxide blocks 38 intrenches 34, as shown inFIG. 2E . The remaining nitride andoxide layers 31/30 are then removed using nitride/oxide etch processes, leaving STI oxide blocks 38 extending alongisolation regions 36, as shown inFIG. 2F . -
FIGS. 2A to 2F illustrate the memory cell array region of the substrate, in which columns of memory cells will be formed in theactive regions 35 which are separated by theisolation regions 36. It should be noted that thesubstrate 12 also includes at least one periphery region in which control circuitry is formed that will be used to operate the memory cells formed in the memory cell array region. Preferably, isolation blocks 38 are also formed in the periphery region during the same STI process described above. - The structure shown in
FIG. 2F is further processed as follows.FIGS. 3A to 3R show the cross sections of the structure in theactive regions 35 from a view orthogonal to that ofFIG. 2F (alongline 3A-3A as shown inFIGS. 2C and 2F ), as the next steps in the process of the present invention are performed. - Commencing with
FIG. 3A , there is shown the formation of a layer ofsilicon dioxide 40 on thesubstrate 12. Thereafter, afirst layer 42 of polysilicon (or amorphous silicon) is deposited or formed on thelayer 40 of silicon dioxide. Thefirst layer 42 of polysilicon is subsequently patterned in a direction parallel to the active region 35 (to remove the polysilicon from the isolation regions 36). - Referring to
FIG. 3B , another insulatinglayer 44, such as silicon dioxide (or even a composite insulation layer, such as ONO—oxide, nitride, oxide sublayers) is deposited or formed on thefirst layer 42 of polysilicon. Asecond layer 46 of polysilicon is then deposited or formed on thelayer 44. Anotherlayer 48 of insulator is deposited or formed on thesecond layer 46 of polysilicon and used as a hard mask during subsequent dry etching. In the preferred embodiment, thelayer 48 is a composite layer, comprising silicon nitride, silicon dioxide, and silicon nitride. However,layer 48 could instead be a single layer of nitride. - Referring to
FIG. 3C , photoresist material (not shown) is deposited on the structure shown inFIG. 3B , and a masking step is formed exposing selected portions of the photoresist material. The photoresist is developed and using the photoresist as a mask, the structure is etched. Thecomposite layer 48, thesecond layer 46 of polysilicon, and the composite insulatinglayer 44 are then anisotropically etched, until thefirst layer 42 of polysilicon is exposed. A poly etch can be used to remove a top portion ofpoly layer 42, with the upper surface thereof sloping up at each stack S1 and S2. The resultant structure is shown inFIG. 3C . Although only two “stacks” S1 and S2 are shown, it should be clear that there are number of such “stacks” that are separated from one another. - The structure is then covered with insulation layers, preferably silicon oxide (HTO) 50 and silicon nitride 52 (i.e., different insulation materials for better device isolation and protection as set forth below), as shown in
FIG. 3D . An optional SiGe process module can be performed at this time, in which a channel SiGe may be formed on the PMOS device to enhance its mobility, and therefore, drive current. The process would include the deposition of a thin layer of nitride. A masking and etch process can then be used to open and remove the nitride and remaining oxide in PMOS area. SiGe can then be selectively grown on the PMOS silicon. The nitride is then removed from the non-PMOS areas. - Referring to
FIG. 3E , a photolithography masking step is then performed to form photo resist 54 partially covering stacks S1 and S2 and the region between stacks S1/S2. For the purpose of this discussion, the region between the stacks S1 and S2 will be called the “inner region,” and the regions on the other sides of the stacks not covered by the photoresist shall be referred to as the “outer regions,” for each pair of stacks S1 and S2. A nitride etch is then performed to formspacers 52 a of thenitride 52 covering sides of stacks S1/S2 in the outer regions. - A poly etch is then performed to remove exposed portions of the
poly layer 42 in the outer regions not protected by thenitride spacers 52, as shown inFIG. 3F . Thepoly silicon 42 in the logic device areas will also be removed. The photo resist 54 is then removed. An oxide deposition (e.g. HTO) and anisotropic etch is performed to formoxide spacers 56 alongnitride spacers 52 a in the outer regions, and along thenitride layer 52 in the inner regions, as shown inFIG. 3G . The oxide etch removes the exposed portions of theoxide layer 40 on the substrate as well in the outer regions. - Referring to
FIG. 3H , a high K metalgate layer HKMG 58 is then formed over the structure, which comprises aninsulation layer 58 a of a high K material (i.e. having a dielectric constant K greater than that of oxide, such as HfO2, ZrO2, TiO2, Ta2O5, or other adequate materials, etc.), underneath aconductive metal layer 58 b. This formation can be done using an atomic layer chemical vapor deposition. The high K metal gate layer will also be formed in logic device areas. A masking step is then performed to cover the outer regions withphotoresist 60, but the leaving the inner regions exposed. Then, an HKMG etch is performed to remove the exposed portions ofHKMG layer 58 from the inner regions. An oxide etch is then used to remove theoxide spacers 56 from the inner regions. Then, a nitride etch is performed to remove remaining portions of thenitride layer 52 except forspacers 52 b thereof covering sides of stacks S1/S2 in the inner region, as shown inFIG. 31 . A poly etch is then performed to remove the exposed portions of thepoly layer 42 in the inner regions (which are not protected bynitride spacers 52 b) exposingoxide layer 40, as shown inFIG. 3J . - After the photo resist 60 is removed, an HV
HTO oxide layer 62 is formed over the structure, which will serve as a screen oxide for subsequent implantation. Photo resist 64 is then formed over the structure, except for the inner regions. An implantation process is then performed to form source region (source line region) 66 in the substrate under the inner regions, as shown inFIG. 3K . An oxide etch is then used to remove theHV HTO oxide 62 in the inner regions, as shown inFIG. 3L . After the photo resist 64 is removed, an HTO oxide deposition is then performed to form atunnel oxide layer 68 over the structure, as shown inFIG. 3M . Photo resist 70 is then formed over the inner regions, leaving the outer regions exposed. An oxide etch is used to remove the exposed portions of thetunnel oxide layer 68 and HVHTO oxide layer 62 in the outer regions, as shown inFIG. 3N . Parallel removal of oxide from the logic device areas is performed during this same oxide etch. - After the photo resist 70 is removed, a thick layer of
polysilicon 72 is deposited over the structure (including over the structure in the logic device areas), as shown inFIG. 30 . The initial poly thickness in the memory cell area is the same as that of the logic device areas. Dummy poly may be deposited and kept in memory cell area for subsequent poly planarization. The dummy poly in the logic device areas can later be removed by poly CMP or poly etching back. Thepoly layer 72 is planarized by a chemical mechanical polish (CMP), followed by a further poly etch back, leaving apoly block 72 a in the inner region which will be the erase gate EG, and poly blocks 72 b in the outer regions which eventually will be the word line gates WL. SeeFIG. 3P . Photo resist 74 is formed and patterned to cover the inner region and portions of the outer regions, leaving outer portions of the outer regions exposed. A poly etch is used to remove the exposed portions ofpoly layer 72, defining the outer edges of theword line gates 72 b, as shown inFIG. 3Q . Parallel photolithography poly etch is also used to define logic gates. - After photo resist 74 is removed, an implantation process is used to form
drain regions 76 in the outer regions aligned to theword line gates 72 b. Spacers of insulation material (e.g. oxide or nitride) 78 are formed along the sides of theword line gates 72 b.Silicide 80 is then formed on the exposed surface portions of the erasegate 72 a,word line gates 72 b and substrate (drain region portion). The final structure is shown inFIG. 3R . Source anddrain regions 66/76 define achannel region 82 therebetween. The conductivity of the first portion of the channel region (underneath the floating gate 42) is controlled by the floatinggate 42, and the conductivity of the second portion of the channel region (underneath theword line gate 72 b) is controlled by theword line gate 72 b. - The
oxide 50 andnitride 52 described above and shown starting inFIG. 3D has many advantages.Oxide 50 andnitride 52 formed on the outer regions of the stack pair will be the main isolation between thecontrol gate 46 and the yet to be formed high K metalgate layer HKMG 58.Oxide 50 andnitride 52 formed in the inner region of the stack pair will be the main isolation between thecontrol gate 46 and the yet to formed erasegate 72 a. In addition, theoxide 50 andnitride 52 protect thecontrol gate 46 and the floatinggate 42 during HKMG removal from the inner stack region (seeFIG. 31 ). This allows thetunnel oxide 68 to be HKMG free in the inner stack region (seeFIG. 3M ). - It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more claims.
- Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the memory cells of the present invention. Single layers of material could be formed as multiple layers of such or similar materials, and vice versa. The terms “forming” and “formed” as used herein shall include material deposition, material growth, or any other technique in providing the material as disclosed or claimed.
- It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.
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US15/225,393 US9634019B1 (en) | 2015-10-01 | 2016-08-01 | Non-volatile split gate memory cells with integrated high K metal gate, and method of making same |
EP16753518.6A EP3357092B1 (en) | 2015-10-01 | 2016-08-02 | Non-volatile split gate memory cells with integrated high k metal gate, and method of making same |
KR1020187010952A KR101941829B1 (en) | 2015-10-01 | 2016-08-02 | Nonvolatile separable gate memory cells with integrated high-K metal gate and method of manufacturing same |
PCT/US2016/045208 WO2017058353A1 (en) | 2015-10-01 | 2016-08-02 | Non-volatile split gate memory cells with integrated high k metal gate, and method of making same |
CN201680058271.XA CN108140669B (en) | 2015-10-01 | 2016-08-02 | Non-volatile separate gate storage unit with integrated high-K metal gate and preparation method thereof |
JP2018516062A JP6407488B1 (en) | 2015-10-01 | 2016-08-02 | Non-volatile split-gate memory cell with integrated high-K metal gate and method of making the same |
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WO2017058353A1 (en) | 2017-04-06 |
KR101941829B1 (en) | 2019-01-23 |
KR20180045044A (en) | 2018-05-03 |
CN108140669A (en) | 2018-06-08 |
TW201715588A (en) | 2017-05-01 |
TWI618124B (en) | 2018-03-11 |
EP3357092B1 (en) | 2020-09-30 |
CN108140669B (en) | 2019-06-07 |
EP3357092A1 (en) | 2018-08-08 |
US9634019B1 (en) | 2017-04-25 |
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JP6407488B1 (en) | 2018-10-17 |
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