US20170092771A1 - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
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- US20170092771A1 US20170092771A1 US14/953,036 US201514953036A US2017092771A1 US 20170092771 A1 US20170092771 A1 US 20170092771A1 US 201514953036 A US201514953036 A US 201514953036A US 2017092771 A1 US2017092771 A1 US 2017092771A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 126
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000001257 hydrogen Substances 0.000 claims abstract description 58
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 58
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 57
- 230000000903 blocking effect Effects 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000010410 layer Substances 0.000 claims description 281
- 238000000034 method Methods 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 43
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 229910044991 metal oxide Inorganic materials 0.000 claims description 14
- 150000004706 metal oxides Chemical class 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims 2
- 230000008569 process Effects 0.000 description 23
- 238000010586 diagram Methods 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 16
- 239000011229 interlayer Substances 0.000 description 15
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 10
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- 230000004888 barrier function Effects 0.000 description 9
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 9
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 9
- 239000010936 titanium Substances 0.000 description 9
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 6
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 6
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 5
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- 239000004020 conductor Substances 0.000 description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 4
- 229910005555 GaZnO Inorganic materials 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- -1 hafnium oxide (HfOx) Chemical class 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000000226 double patterning lithography Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region. The oxide semiconductor structure is disposed over a hydrogen blocking layer, in the second region of the substrate.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device having an oxide semiconductor structure and a method for forming the same.
- 2. Description of the Prior Art
- In the modern society, the micro-processor systems comprising integrated circuits (IC) are ubiquitous devices, being utilized in diverse fields such as automatic control electronics, mobile communication devices and personal computers. With the development of technology and the increase of original applications for electronic products, the IC devices are becoming smaller, more delicate and more diversified.
- In a wide variety of materials, indium oxide (In2O3), tin oxide (SnO2) and zinc oxide (ZnO) are generally known transparent conductive oxides. Indium tin oxide (ITO), when being formed of a thin film, can be used as a transparent electrode in a flat panel display or a touch sensor of a capacitance type touch panel. Tin oxide and zinc oxide can be used in a transparent solar cell electrode. However, these materials are essentially semiconductor materials, and it is desired for the researchers to develop a semiconductor device by using their semiconductor material property, such as an oxide semiconductor transistor.
- However, due to oxidation of the semiconductor material itself, when using of this oxide semiconductor material, it is easy to damage the oxide semiconductor layer during the production process, thus affecting the performance of the product. Therefore, for a semiconductor device having an oxide semiconductor material, there is still a need for a better design or a manufacturing method, thereto gain better quality.
- The present invention therefore provides a semiconductor device having an oxide semiconductor structure and a method for forming the same, in order to gain a better product performance.
- To achieve the purpose described above, the present invention provides a semiconductor device including a substrate, an interconnect structure and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region, wherein the interconnect structure includes a plug disposed in a dielectric layer on the substrate and a hydrogen blocking layer disposed on the plug. The oxide semiconductor structure is disposed over the hydrogen blocking layer, in the second region of the substrate, wherein the oxide semiconductor structure includes an oxide semiconductor layer, two source/drain structures and a first gate. The oxide semiconductor layer is disposed on a first insulating layer. The source/drain structures are disposed on the oxide semiconductor layer. The first gate is disposed between the source/drain structures, on the oxide semiconductor layer, wherein the first gate overlaps the oxide semiconductor layer.
- To achieve the purpose described above, the present invention provides a method of forming a semiconductor device including following steps. First of all, a substrate having a first region and a second region is provided. Then, an interconnect structure is formed on the substrate, in the first region, wherein the interconnect structure includes a plug disposed in a dielectric layer on the substrate and a hydrogen blocking layer disposed on the plug. Next, an oxide semiconductor structure is formed over the hydrogen blocking layer, in the second region, wherein the oxide semiconductor structure includes an oxide semiconductor layer, two source/drain structures and a first gate. The oxide semiconductor layer is formed on a first insulating layer. The source/drain structures are formed on the oxide semiconductor layer. The first gate is formed between the source/drain structures, on the oxide semiconductor layer, wherein the first gate overlaps the oxide semiconductor layer.
- According to the above, the semiconductor device and the forming method thereof in the present invention is at least characterized by disposing a multilayer structure of hydrogen blocking layers (including oxide metal) in the metal interconnect structure between a metal oxide semiconductor (MOS) transistor and an oxide semiconductor (OS) structure. The hydrogen blocking layer for example includes silicon oxynitride or earth metal oxide, like hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, aluminum oxide, lanthanum oxide or hafnium zirconium oxide for example, and which is formed on each plug structure and damascene structure to block out-diffusion mist and hydrogen in the device, so as to avoid such out-diffusion mist and hydrogen flowing along the metal interconnect structure and affecting the device or the subsequent forming processes. Also, if the plug structure or the damascene structure includes a copper layer, an additional capping layer, like a silicon oxide layer, silicon nitride layer, a silicon oxynitride layer, or a silicon carbonitride layer for example, may be further disposed before the hydrogen blocking layer is formed, to further prevent copper from diffusing into periphery dielectric layer and to further improve the reliability of the device thereby.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 toFIG. 10 are schematic diagrams illustrating a method of forming a semiconductor device according to a first embodiment of the present invention, wherein: -
FIG. 1 is a schematic diagram showing a semiconductor device at the beginning of the forming method; -
FIG. 2 is a schematic diagram showing a semiconductor device after forming a contact plug; -
FIG. 3 is a schematic diagram showing a semiconductor device after forming a damascene structure; -
FIG. 4 is a schematic diagram showing a semiconductor device after forming another damascene structure; -
FIG. 5 is a schematic diagram showing a semiconductor device after forming an oxide semiconductor structure; -
FIG. 6 is a schematic diagram showing an enlarged view of the semiconductor device inFIG. 5 after forming an oxide semiconductor material layer; -
FIG. 7 is a schematic diagram showing an enlarged view of the semiconductor device inFIG. 5 after performing a patterning process; -
FIG. 8 is a schematic diagram showing an enlarged view of the semiconductor device inFIG. 5 after performing another patterning process; -
FIG. 9 is a schematic diagram showing an enlarged view of the semiconductor device inFIG. 5 after forming a high-k dielectric layer, a dielectric material layer and a gate material layer; and -
FIG. 10 is a schematic diagram showing an enlarged view of the semiconductor device inFIG. 5 after patterning the high-k dielectric layer, the dielectric material layer and the gate material layer. -
FIG. 11 is a schematic diagram illustrating a method of forming a semiconductor device according to a second embodiment of the present invention. -
FIG. 12 is a schematic diagram illustrating a method of forming a semiconductor device according to a third embodiment of the present invention. - To provide a better understanding of the presented invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.
- Please refer to
FIG. 1 toFIG. 10 , showing schematic diagrams of the method of forming a semiconductor structure according to the first embodiment of the present invention. Firstly, asubstrate 300 is provided, and which may be any component that can serve as a base for forming devices, like a semiconductor substrate for example, such as silicon substrate, epitaxial silicon substrate, or silicon on insulator (SOI), but is not limited thereto. Also, thesubstrate 300 includes afirst region 100 and asecond region 200. - At least one
transistor 301 is formed on thesubstrate 300, and a contact etch stop layer (CESL) 400 and an interlayer dielectric (ILD)layer 410 are formed on thesubstrate 300, to cover thetransistor 301 and thesubstrate 300. Precisely, thetransistor 301 is formed in thefirst region 100 of thesubstrate 300, and includes a gatedielectric layer 303, agate electrode 305, a capping layer 307 aspacer 309, two light dopeddrain regions 311 and two source/drain regions 313. In one embodiment, the gatedielectric layer 303 may include silicon oxide or high dielectric constant (high-k) dielectric material (greater than 4). Thegate electrode 305 may include polysilicon or metal, but is not limited thereto. Thecapping layer 307 may include silicon nitride (SiN). Thespacer 309 is a monolayer structure or a multilayer structure optionally, for example including high temperature oxide (HTO), SiN, silicon oxide or SiN formed by hexachlorodisilane (Si2Cl6) (HCD-SiN), as shown inFIG. 1 . - In the present embodiment, the
transistor 301 may include any active component, like complementary metal oxide semiconductor (CMOS) or photo-diode for example, and the forming method may include following steps. First of all, a gate dielectric material layer (not shown in the drawings), a gate material layer (not shown in the drawings) and a capping material layer (not shown in the drawings) are sequentially stacked on thesubstrate 300, and then the stacked layers are patterned to form thecapping layer 309, thegate electrode 305 and the gatedielectric layer 303. Then, the light dopeddrain regions 311, thespacer 309, and the source/drain regions 313 are formed at two sides of thegate electrode 305. However, people in the art shall easily realize that the formation of thetransistor 301 may also include other process, which may be well known by one skilled in the art. For example, in one embodiment of the present invention, after thetransistor 301 shown inFIG. 1 is formed, a selective epitaxial growth (SEG) process and/or replacement metal gate (RMG) process is optionally performed, and the detailed steps thereof may be similar to general processes of forming a transistor and will not be redundantly described herein. - Next, a metal interconnection system is formed in the
first region 100 of thesubstrate 300. In the present embodiment, contact plugs 401 directly electrically connected to the source/drain regions 313 and contact plugs 411 electrically connected to the contact plugs 401 are formed sequentially. The contact plugs 401 are disposed through aninterlayer dielectric layer 410, like a low dielectric constant (low-k) dielectric layer for example, to directly contact the source/drain regions 313, and the contact plugs 411 are disposed sequentially through adielectric layer 430 on theinterlayer dielectric layer 410, such as a low-k dielectric layer, and ahydrogen blocking layer 420, to directly contact the contact plugs 401. - Precisely, each of the contact plugs 401 may include a
barrier layer 403, like a titanium/titanium nitride layer for example, disposed peripherally and ametal layer 405, like tungsten for example, disposed internally but is not limited thereto. In one embodiment, slot patterns (not shown in the drawings) of the contact plugs 401 may be respectively defined through a double patterning lithography, but is not limited thereto. It is worth noting that, in the present embodiment, after forming the contact plugs 401, thehydrogen blocking layer 420 may be formed to entirely cover the contact plugs 401, as shown inFIG. 2 . With such performance, thehydrogen blocking layer 420 may block out-diffusion mist and hydrogen in the device, so as to avoid such out-diffusion mist and hydrogen flowing along the metal interconnect structure and affecting the device or the subsequent forming processes. In one embodiment, thehydrogen blocking layer 420 may include silicon oxynitride (SiON) or a high-k dielectric material, such as a metal oxide layer, preferably an earth metal oxide layer, like hafnium oxide (HfOx), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3) or hafnium zirconium oxide (HfZrO), but is not limited thereto. - On the other hand, the contact plugs 411 may include a barrier layer, like a titanium/titanium nitride layer for example, disposed peripherally and a
metal layer 415, like tungsten for example, disposed internally but is not limited thereto. In the present embodiment, ahydrogen blocking layer 440 may be also formed after the contact plugs 411 are formed, to entirely cover the contact plugs 411, as shown inFIG. 2 . In this manner, thehydrogen blocking layer 440 may block out-diffusion mist and hydrogen in the device, so as to avoid such out-diffusion mist and hydrogen flowing along the metal interconnect structure and affecting the device or the subsequent forming processes. Please note that, detailed forming processes and materials of thehydrogen blocking layer 440 are substantially similar to those of the aforementionedhydrogen blocking layer 420, and will not be redundantly described herein. - Next, at least one
damascene structure 421 is formed to electrically connect the contact plugs 411. In one embodiment, thedamascene structure 421, like a via-first damascene structure for example, is formed in an interlayer dielectric layer 450 (for example a low-k dielectric layer), as shown inFIG. 3 . The formation of thedamascene structure 421 may include following steps. Firstly, a via opening (not shown in the drawings) may be defined in theinterlayer dielectric layer 450 through a patterned mask layer (not shown in the drawings), and a trench (not shown in the drawings) is then defined also in theinterlayer dielectric layer 450. Thus, thedamascene structure 421 may simultaneously form in the via opening and the trench, and which includes a plug (not shown in the drawings) and a metal wire (not shown in the drawings). Thedamascene structure 421 may also include abarrier layer 423, like a titanium/titanium nitride layer for example, disposed peripherally and ametal layer 425, like tungsten for example, disposed internally, but is not limited thereto. However, people in the art shall easily realize that the damascene structure of the present invention may not be limited to the aforementioned, and in another embodiment, the damascene structure may also be formed through other processes which may be well known in the art, such as a self-aligned damascene process, or a trench-first damascene structure (not shown in the drawings) may also be formed. - It is noted that, since copper has diffusion property, a
capping layer 460, like a silicon oxide layer, silicon nitride layer, a silicon oxynitride (SiON) layer, or a silicon carbonitride (SiCN) layer for example, is firstly formed after thedamascene structure 421 is formed, for the sake of preventing copper from diffusing into periphery dielectric layer. Then, ahydrogen blocking layer 470 may be formed, and which may also include silicon oxynitride (SiON) or a high-k dielectric layer, like a metal oxide layer for example, preferably an earth metal oxide layer, like hafnium oxide (HfOx), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3) or hafnium zirconium oxide (HfZrO). In this way, copper diffusion and out-diffusion mist and hydrogen may be blocked respectively by thecapping layer 460 and thehydrogen blocking layer 470. Also, in another embodiment of the present invention (not shown in the drawings), the metal layer of thedamascene structure 421 may also include other metal, such as tungsten, such that, thecapping layer 460 may be omitted accordingly and only thehydrogen blocking layer 470 is formed on thedamascene structure 421. - Following these, a damascene structure 341 disposed in interlayer
dielectric layers barrier layer 433, like a titanium/titanium nitride layer for example, and ametal layer 435, like copper for example, as shown inFIG. 4 . In one embodiment, the formation of thedamascene structure 431 for example includes firstly defining a via opening (not shown in the drawings) in theinterlayer dielectric layer 510 and astop layer 490, further defining a trench (not shown in the drawings) in theinterlayer dielectric layer 510 by using thestop layer 490 as an etching stop layer, and finally forming thedamascene structure 431 in the via opening and the trench, wherein thedamascene structure 431 is also consisted of a plug (not shown in the drawings) and a metal wire (not shown in the drawings). - Through the aforementioned process, the contact plugs 401, 411 and
damascene structures first region 100 of thesubstrate 300, and the metal interconnection structure are formed thereby, so that, the metal interconnection structure may electrically connect to thetransistor 301, for receiving or delivering any input/output signals from thetransistor 301. - The forming method of the present embodiment for example is characterized by forming the hydrogen blocking layer on the plug structures and the damascene structures, after each of the plug structures and the damascene structures is formed. The hydrogen blocking layer may include silicon oxynitride or earth metal oxide, like hafnium oxide (HfOx), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3) or hafnium zirconium oxide (HfZrO), such that, the hydrogen blocking layer may effectively block out-diffusion mist and hydrogen in the device, so as to avoid such out-diffusion mist and hydrogen flowing along the metal interconnect structure and affecting the device or the subsequent forming processes. It is noted that, if the plug structures or the damascene structures include a copper layer, an additional capping layer, like silicon oxide, silicon oxynitride or silicon carbonitride for example, may be formed before the hydrogen blocking layer is formed, for further preventing copper from diffusing into periphery dielectric layer and improving the reliability of the device thereby.
- On the other hand, while the metal interconnect structure is formed in the
first region 100, an oxide semiconductor structure may be optionally formed in thesecond region 200. For example, a conductive layer, which includes the same metal material (such as copper) to that of the metal layers 415, 425, 435 of the contact plugs 411 and thedamascene structures interlayer dielectric layer 430 or other interlayer dielectric layers in thesecond region 200, to function like aback gate electrode 340 of a dual gate structure, as shown inFIG. 4 . - Then, an insulating
layer 520 may be formed on theinterlayer dielectric layer 520, wherein the insulatinglayer 520 may include a monolayer structure or a multilayer structure and the material thereof may include general low-k dielectric material, like silicon oxide for example, or high-k dielectric material, like metal oxide, preferably an earth metal oxide, like hafnium oxide, but is not limited thereto. Next, please referFIGS. 6-10 . In order to illustrate the present invention conveniently,FIGS. 6-10 illustrate the enlarged region A shown inFIG. 5 . - In addition, an oxide semiconductor (OS)
material layer 306 and aconductive material layer 310 are formed on the insulatinglayer 520. TheOS material layer 306 may be a single layer or have a multilayered structure, wherein each may contain the same or different materials, e.g., indium gallium zinc oxide (InGaZnO), InGaO2, InZnO2, ZnInO or GaZnO. Preferably, it contains C-axis aligned crystal InGaZn (CAAC-InGaZnO), such that, theOS material layer 306 may exhibit high carrier mobility and low leakage current to serve as a channel layer of thebottom gate electrode 340. It is understood for one skilled in the art that the OS material layer in the present invention may have other material or may have multi-layers, wherein each layer has the same or different material, which is not limited to the above embodiment. - In one embodiment, an insulating
layer 308 may further be formed on theOS material layer 306, as shown inFIG. 6 . It is worth noting that the insulatinglayer 308 is preferably composed of an oxide semiconductor (OS) material, such as InGaZnO, InGaO2, InZnO2 or ZnInO or GaZnO, and is not limited thereto. Preferably, the material of the OS material in the insulatinglayer 308 is different than that of theOS material layer 306, and a thickness of the insulatinglayer 308 is less than that of theOS material layer 306, but is not limited thereto. By doing this, the insulatinglayer 308 may serve as a barrier layer. - Next, the
OS material layer 306 and theconductive material layer 310 are patterned to form anOS layer 316 and a patternedconductive layer 320. The patterning process may be carried out by one single photo-etching-process (PEP) or a plurality of PEPs. In the embodiment of forming the insulatinglayer 308, theOS material layer 306, the insulatinglayer 308 and theconductive material layer 310 may be patterned simultaneously wherein the insulatinglayer 520 is used as an etch stop layer. Accordingly, the sidewall of theOS layer 316, the sidewall of the patterned insulatinglayer 318 and the sidewall of the patternedconductive layer 320 are vertically aligned with each other, as shown inFIG. 7 . It is noted that theOS layer 316 is disposed correspondingly to thebottom gate electrode 340, preferably, a projection of thebottom gate electrode 340 along a vertical direction of thesubstrate 300 is disposed at a center of theOS layer 316, as shown inFIG. 7 . - Then, the patterned
conductive layer 320 is patterned again by using the insulatinglayer 318 and theOS layer 316 as etch stop layers, to form two separate parts, preferably two source/drain structures (S/D region) 330 with the same width, wherein a part of theOS layer 316 or the insulatinglayer 318 is exposed by the two S/D regions 330 (FIG. 8 only illustrates the embodiment of exposing the insulating layer 318). On the other hand, as described above, the outer sidewalls of the S/D region 330 are vertically aligned with the sidewall of theOS layer 316 and the sidewalls of the insulatinglayer 318. Also, in one embodiment of the present invention, the patterning process may be carried out by one single PEP or a plurality of PEPs, but is not limited thereto. - Thereafter, a high-
k dielectric layer 324 is formed comprehensively on thesubstrate 300 and the S/D regions 330, in which it may be one single layer or have a multi-layered structure. Preferably, the high-k dielectric layer may include metal oxide, preferably earth metal oxide, like hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, aluminum oxide, lanthanum oxide or hafnium zirconium oxide for example, but is not limited thereto. After that, a dielectric material 326 and a gate material layer 328 are conformally formed on thesubstrate 300. In one embodiment, the dielectric material layer 326 preferably includes a low-dielectric material, such as SiO2, or a high-k dielectric material; and the gate material layer 328 may include any conductive material, such as metal, like aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), cadmium (Cd), a nitride thereof, an oxide thereof, alloys thereof, or a combination thereof. - However, in one embodiment, after forming the high-
k dielectric layer 324, an oxygen ambience treatment (not shown in the drawings) is performed on the high-k dielectric layer 324, wherein the oxygen ambience treatment may include an annealing process, a plasma treatment or a chemical solution process. With such oxygen ambience treatment, the oxygen atom in the high-k dielectric layer 324 may be released, and the high-k dielectric layer 324 can be tuned by the oxygen ambience treatment, so as to avoid the oxygen vacancy phenomenon. In another embodiment, another insulatinglayer 322 may be optionally formed, between the source/drain structures 330 and the high-k dielectric layer 324, as shown inFIG. 9 . The insulatinglayer 322 is preferably composed of an oxide semiconductor (OS) material, such as InGaZnO, InGaO2, InZnO2 or ZnInO or GaZnO, and is not limited thereto. Preferably, the material of the OS material in the insulatinglayer 322 is different than that of theOS layer 316, and a thickness of the insulatinglayer 322 is less than that of theOS layer 316, but is not limited thereto. By doing this, the insulatinglayer 322 may directly contact the source/drain structures 330 and the exposed insulatinglayer 318 to serve as a barrier layer, for protecting the patterned sidewalls of the source/drain structures (also known as S/D regions) 330 and the exposed insulatinglayer 318. Also, in the embodiments without the insulatinglayer 318, the insulatinglayer 322 may directly contact the S/D regions 330 and the exposedOS layer 316. - Following these, the gate material layer 328, the dielectric material layer 326 and the high-
k dielectric layer 324 are patterned simultaneously to form atop gate electrode 338, agate dielectric layer 336 and a patterned high-k dielectric layer 334 respectively. It is noted that the sidewall of the topgate electrode layer 336, the sidewall of the gate dielectric layer and the sidewalls of the patterned high-k dielectric layer 334 are vertically aligned with each other. Also, in the embodiment of forming the insulatinglayer 322, the insulatinglayer 322 may be also patterned optionally, or may be used as an etch stop layer while the patterning process is performed, as shown inFIG. 10 . - According to the above description, the semiconductor device according to the first embodiment of the present invention is provided. In the subsequent processes, a plug process may be optionally performed, to further form at least one plug 338 (not shown in the drawings) to electrically connect to the source/
drain structures 330 and/or thetop gate electrode 338, but is not limited thereto. As shown inFIG. 10 , the semiconductor device includes thesubstrate 300, the metal interconnect structure disposed in thefirst region 100 of thesubstrate 300, and the oxide semiconductor structure disposed in thesecond region 200 of thesubstrate 300. The metal interconnect structure includes the contact plugs 401, 411 and thedamascene structures back gate electrode 340 disposed below the insulatinglayer 520 and thetop gate electrode 338 disposed on the insulatinglayer 520. - People skilled in the art shall easily realize that the semiconductor device of the present invention is not limited to being formed through the aforementioned steps, and may include other forming methods. Thus, the following description will detail other different embodiments or variant embodiments of the manufacturing method of the semiconductor device of the present invention. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.
- Please refer to
FIG. 11 , which is a schematic diagram illustrating a method of forming a semiconductor device according to the second embodiment of the present invention. The formal steps in the present embodiment are substantially similar toFIGS. 1-10 shown in the aforementioned first embodiment, including sequentially forming thesubstrate 300, at least onetransistor 301, the metal interconnect structure disposed in thefirst region 100 of thesubstrate 300 and the oxide semiconductor structure disposed in thesecond region 200 of thesubstrate 300. The differences between the present embodiment and the aforementioned first embodiment are that, after forming the structure shown inFIG. 5 , adielectric layer 530 may be formed additionally, and a plug structure, such as adamascene structure 441, may be formed in thedielectric layer 530, as shown inFIG. 11 . Thedamascene structure 441 includes abarrier layer 443, such as Ti/TiN and ametal layer 443, such as copper. Precisely speaking thedamascene structure 441 for example also includes a trench-first damascene structure, and consists of a plug (not shown in the drawings) and a metal wire (not shown in the drawings). The formation and the detailed materials of thedamascene structure 441 are substantially similar to those of thedamascene structure 421 in the aforementioned first embodiment or are well known in the art, and will not be redundantly described herein. Then acapping layer 540 and thehydrogen blocking layer 550 are sequentially formed, to block the copper diffusion and the out diffusion mist and hydrogen in the device respectively. Please note that, the detailed forming methods and materials of thecapping layer 540 and thehydrogen blocking layer 550 in the present embodiment may be substantially similar to those of thecapping layer 460 and thehydrogen blocking layer 470 in the aforementioned first embodiment or are well known in the art, and may not be redundantly described herein. - According to the above description, the semiconductor device according to the second embodiment of the present invention is provided. In other words, the present invention further forms a plug structure, and a hydrogen blocking layer disposed thereon, after forming the metal interconnect structure and the oxide semiconductor structure respectively in two different regions of the substrate. It is noted that, the hydrogen blocking layer in the present embodiment may also be formed on the plug structure disposed over the oxide semiconductor structure, such that, the mist and hydrogen diffused in the device may be further sufficiently blocked, so as to avoid such out-diffusion mist and hydrogen flowing along the metal interconnect structure and affecting the oxide semiconductor device in the subsequent forming processes.
- Please refer to
FIG. 12 , which is a schematic diagram illustrating a method of forming a semiconductor device according to the third embodiment of the present invention. The formal steps in the present embodiment are substantially similar toFIGS. 1-11 shown in the aforementioned second embodiment, and the differences between the present embodiment and the aforementioned second embodiment are that, after forming the structure shown inFIG. 3 , adamascene structure 451 shown inFIG. 12 may be formed in thedielectric layers damascene structure 451 includes abarrier layer 453, such as Ti/TiN and ametal layer 453, such as copper. Precisely speaking, the formation of thedamascene structure 451 may include following steps. Firstly, a via opening (not shown in the drawings) may be defined in theinterlayer dielectric layer 480 through a patterned mask layer (not shown in the drawings), and a trench (not shown in the drawings) is then defined in theinterlayer dielectric layer 510 to penetrate through thestop layer 490 and a portion of theinterlayer dielectric layer 480. Thus, thedamascene structure 451 may simultaneously form in the via opening and the trench, and which includes a plug (not shown in the drawings) and a metal wire (not shown in the drawings). Thedamascene structure 451 may also include abarrier layer 453, like a titanium/titanium nitride layer for example, and ametal layer 455, like tungsten, as shown inFIG. 12 . Except for the aforementioned difference, other forming processes and materials are all similar to those in the second embodiment or are well known in the art, and will not be redundantly described herein. - In summary, the present invention provides a semiconductor device, in which the hydrogen blocking layer, like hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, aluminum oxide, lanthanum oxide or hafnium zirconium oxide for example, may be further formed on each plug structure and damascene structure, after those plug structures and damascene structures are formed. In other words, the present invention disposes a multilayer structure of hydrogen blocking layers (including oxide metal) in the metal interconnect structure either between a metal oxide semiconductor (MOS) transistor and an oxide semiconductor (OS) structure, or above the OS structure. With such arrangement of the hydrogen blocking layer to block out-diffusion mist and hydrogen in the device, this can avoid such out-diffusion mist and hydrogen flowing along the metal interconnect structure and avoid affecting the device or the subsequent forming processes. Also, if the plug structure or the damascene structure includes a copper layer, an additional capping layer, like a silicon oxide layer, silicon nitride layer, a silicon oxynitride layer, or a silicon carbonitride layer for example, may be further disposed before the hydrogen blocking layer is formed, to further prevent copper from diffusing into periphery dielectric layer and to further improve the reliability of the device thereby.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (20)
1: A semiconductor device, comprising:
a substrate having a first region and a second region;
an interconnect structure, disposed on the substrate, in the first region, wherein the interconnect structure comprises:
a plug disposed in a dielectric layer on the substrate;
a hydrogen blocking layer disposed on the plug; and
a capping layer disposed between the hydrogen blocking layer and the plug; and
an oxide semiconductor structure disposed over the hydrogen blocking layer, in the second region of the substrate, wherein the oxide semiconductor structure comprises:
an oxide semiconductor layer disposed on a first insulating layer;
two source/drain structures disposed on the oxide semiconductor layer; and
a first gate disposed between the source/drain structures, on the oxide semiconductor layer, wherein the first gate overlaps the oxide semiconductor layer.
2: The semiconductor device of claim 1 , wherein the hydrogen blocking layer comprises a high dielectric constant (high-k) material.
3: The semiconductor device of claim 1 , wherein the hydrogen blocking layer comprises a metal oxide material.
4: The semiconductor device of claim 1 , wherein the high-k material comprises HfO2 or AlO2.
5: The semiconductor device of claim 1 , wherein the plug comprises copper or tungsten.
6. (canceled)
7: The semiconductor device of claim 1 , wherein the capping layer comprises at least one of SiN, SiCN, or SiON.
8: The semiconductor device of claim 1 , further comprising:
a second insulating layer disposed between the oxide semiconductor layer and the source/drain structures, wherein the second insulating layer comprises a oxide semiconductor material different from the oxide semiconductor layer.
9: The semiconductor device of claim 8 , wherein the second insulating layer has a thickness being smaller than that of the oxide semiconductor layer.
10: The semiconductor device of claim 1 , wherein the oxide semiconductor structure further comprises a second gate electrode disposed below the oxide semiconductor layer, and the second gate electrode overlaps the oxide semiconductor layer.
11: The semiconductor device of claim 10 , wherein the oxide semiconductor structure further comprises:
another hydrogen blocking layer, disposed over the oxide semiconductor structure, the another hydrogen blocking layer including HfO2.
12: The semiconductor device of claim 1 , wherein the oxide semiconductor layer comprises a monolayer structure or a multilayer structure.
13: The semiconductor device of claim 1 , further comprising:
a high dielectric constant (high-k) dielectric layer, disposed between the first gate electrode and the source/drain structures.
14: A semiconductor device, comprising:
a low dielectric constant (low-k) dielectric layer, disposed on a substrate;
a metal layer disposed in the low-k dielectric layer;
a hydrogen blocking layer, covered on the low-k layer; and
a capping layer disposed between the hydrogen blocking layer and the metal layer, wherein the capping layer comprises at least one of SiN, SiCN or SiON.
15: A method of forming a semiconductor device, comprising:
providing a substrate having a first region and a second region;
forming an interconnect structure on the substrate, in the first region, wherein the interconnect structure comprises:
a plug disposed in a dielectric layer on the substrate;
a hydrogen blocking layer disposed on the plug; and
a capping layer disposed between the hydrogen blocking layer and the plug, wherein the capping layer comprises silicon nitride, silicon carbonitride, or silicon oxynitride; and
forming an oxide semiconductor structure over the hydrogen blocking layer, in the second region, wherein the oxide semiconductor structure comprises:
an oxide semiconductor layer disposed on a first insulating layer;
two source/drain structures disposed on the oxide semiconductor layer; and
a first gate disposed between the source/drain structures, on the oxide semiconductor layer, wherein the first gate overlaps the oxide semiconductor layer.
16. (canceled)
17: The method of forming a semiconductor device of claim 15 , wherein the forming of the oxide semiconductor structure comprises:
forming a second insulating layer between the oxide semiconductor layer and the source/drain structures, and the second insulating layer comprises a oxide semiconductor material different from that of the oxide semiconductor layer.
18: The method of forming a semiconductor device of claim 15 , wherein the forming of the oxide semiconductor structure comprises:
forming a second gate electrode below the oxide semiconductor layer, and the second gate electrode overlaps the oxide semiconductor layer.
19: The method of forming a semiconductor device of claim 15 , wherein the forming of the oxide semiconductor structure comprises:
forming another high-k dielectric layer covering the source/drain structures, and between the first gate electrode and the source/drain structures.
20: The method of forming a semiconductor device of claim 19 , wherein the forming of the oxide semiconductor structure comprises:
forming a third insulating layer covering the source/drain structures, and between the high-k dielectric layer and the source/drain structures.
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