US20170040450A1 - Bulex contacts in advanced fdsoi techniques - Google Patents
Bulex contacts in advanced fdsoi techniques Download PDFInfo
- Publication number
- US20170040450A1 US20170040450A1 US14/816,337 US201514816337A US2017040450A1 US 20170040450 A1 US20170040450 A1 US 20170040450A1 US 201514816337 A US201514816337 A US 201514816337A US 2017040450 A1 US2017040450 A1 US 2017040450A1
- Authority
- US
- United States
- Prior art keywords
- region
- forming
- bulk
- soi
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 claims abstract description 111
- 239000000463 material Substances 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 239000011810 insulating material Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims 3
- 238000002955 isolation Methods 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 description 23
- 125000006850 spacer group Chemical group 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 230000000873 masking effect Effects 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000007772 electrode material Substances 0.000 description 7
- 238000000059 patterning Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- CVRXLMUYFMERMJ-UHFFFAOYSA-N N,N,N',N'-tetrakis(2-pyridylmethyl)ethylenediamine Chemical compound C=1C=CC=NC=1CN(CC=1N=CC=CC=1)CCN(CC=1N=CC=CC=1)CC1=CC=CC=N1 CVRXLMUYFMERMJ-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- -1 oxide Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000004043 responsiveness Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
Definitions
- the present disclosure generally relates to advanced FDSOI techniques and, more particularly, to the fabrication of BULEX contacts in advanced FDSOI techniques.
- FDSOI fully depleted silicon-on-isolator
- fabrication processes as employed in FDSOI techniques are comparatively simple and actually represent a low risk evolution of conventional planar bulk CMOS techniques when compared to three-dimensional transistor designs, such as FinFETs.
- SOI techniques make use of a special kind of substrate being formed by a semiconductor layer, such as silicon, germanium or silicon germanium, formed on a buried oxide (BOX) layer, which is in turn formed on a semiconductor substrate.
- a semiconductor layer such as silicon, germanium or silicon germanium
- BOX buried oxide
- SOI devices there are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI MOSFETs (fully depleted SOI).
- PDSOI partially depleted SOI
- FDSOI MOSFETs fully depleted SOI
- a P-type film is sandwiched between a gate oxide (GOX) and the BOX, where a thickness of the P-type film is such that the depletion region cannot cover the whole P-region. Therefore, to some extent, PDSOI devices may behave like bulk MOSFETs.
- the thickness of the semiconductor layer is such that the depletion region covers the whole semiconductor layer.
- the GOX in FDSOI techniques supports fewer depletion charges than a bulk substrate and an increase in the inversion charges occurs in the fully depleted semiconductor layer, resulting in higher switching speeds.
- back biasing was suggested for FDSOI devices.
- a voltage is applied just under the BOX of target semiconductor devices.
- the electrostatic control of the semiconductor device is changed and the threshold voltage is shifted to either obtain more drive current (hence, higher performance) at the expense of increased leakage current (forward back bias, FBB) or to cut leakage current at the expense of reduced performance.
- FBB forward back bias
- back bias in planar FDSOI techniques is somewhat similar to body bias as implemented in bulk CMOS technologies, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied.
- back biasing can be utilized in a dynamic way on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue.
- BULEX bulk exposed' regions
- the bulk substrate has a height difference relative to an upper surface of the active semiconductor layer of an SOI substrate. Accordingly, a step height exists between BULEX regions and SOI substrates in the form of the BOX layer and the active semiconductor layer. In advanced technologies, the step height may be on the order of 30 nm, which raises big challenges in front end of line (FEOL) processing of advanced semiconductor devices.
- FEOL front end of line
- the step height between the bulk semiconductor material (at the BULEX regions) and the upper surface of the active layer of an SOI substrate (at transistor devices) leads to uncontrollable variations in the critical dimensions, to large offsets between FDSOI and bulk structure critical dimensions and, particularly, in lithographical processes, to divots and crevices where film residues are hard to remove and which can cause shorts and leaks in the final circuit.
- FIGS. 1 a -1 d and 2 a -2 c One conventional fabrication process for forming BULEX contacts besides SOI semiconductor devices will be explained with regard to FIGS. 1 a -1 d and 2 a -2 c below.
- FIGS. 1 a -1 d schematically show, in a cross-sectional view, a known FEOL process for implementing a back bias contact via contacting a BULEX area beside an active region according to SOI techniques.
- a known SOI substrate region is schematically illustrated.
- an SOI substrate is formed by a base substrate material 101 , on which a buried oxide (BOX) material 103 , and an active silicon film 105 is provided.
- BOX buried oxide
- a bulk exposed region 120 is formed adjacent to an SOI region 110 by techniques implemented for locally removing the BOX material 103 and the active silicon film 105 , as shown in Figure lb.
- a mask pattern may be formed via lithographical techniques, e.g., by forming a resist material (not illustrated) on a thin oxide liner 107 (passivation oxide) provided on the active silicon film 105 and lithographically patterning the resist material (not illustrated) such that a region, where the BULEX region 120 is to be provided, is not covered by the masking pattern (not illustrated).
- a bulk exposed region 120 is locally formed.
- a process of re-growing silicon material on the BULEX region 120 is preformed such that the step height between the BULEX region 120 and the active silicon film 105 in the SOI region 110 is reduced.
- the height level of the re-grown silicon material 121 on the BULEX region 120 may not totally match the height level of the active silicon film 105 , the re-grown silicon material 121 is overgrown and, as a consequence, a dislocation portion 123 is formed at the interface of the SOI region 110 and the BULEX region 120 .
- an STI region of sufficient width is formed at the interface by matching a trench 125 with a width dimension d 1 into the SOI material and the re-grown silicon material 121 at the interface between the SOI region 110 and the BULEX region 120 , as shown in FIG. 1 d. Therefore, a separation between the BULEX region 120 and the SOI region 110 has to be implemented in order to remove the dislocation 123 , therefore leading to an increased distance between a BULEX contact (not illustrated), which is to be formed on the BULEX region 120 , relative to a semiconductor device (not illustrated), which is to be formed on and in the SOI region 110 during subsequent fabrication steps.
- a width of the trench 125 is greater than a width of normally formed STI trenches 126 , i.e., d 1 >d 2 .
- FIG. 2 a schematically illustrates a semiconductor device structure at an early stage during fabrication, particularly before any gate structure is formed and an STI region 207 is provided within an SOI substrate structure (base substrate 201 , BOX material 203 and active silicon film 205 ), where the STI structure 207 separates a first SOI region 210 and a second SOI region 220 .
- the first SOI region 210 and the second SOI region 220 are herein covered by a thin oxide liner.
- a BULEX region is formed in the second SOI region 220 by locally removing the BOX material 203 and the active silicon film 205 in the second SOI region 220 . Accordingly, a step height h (see FIG. 2 b ) is provided between the BULEX region 220 and the SOI region 210 . As the STI 207 is partially exposed when the BOX material 203 and the active silicon film 205 in the bulk exposed (BULEX) region 220 are removed, a step 230 is formed in the STI 207 resulting in a stepped STI structure 207 ′.
- a gate structure 211 is formed on the SOI region 210 , as shown in FIG. 2 c .
- the gate structure 211 is formed by depositing a gate dielectric material 215 and a gate electrode material 213 over the SOI region 210 and the BULEX region 220 , forming a gate mask pattern (not illustrated) on the deposited materials and removing the deposited material in accordance with the gate mask pattern (not illustrated).
- sidewall spacers 217 and the gate cap 219 are formed by depositing the spacer forming material and anisotropically etching the spacer forming material.
- the gate stack patterning herein, the anisotropic etching of the gate material
- the spacer forming process herein, the anisotropic etching of the spacer forming material
- residual material 232 of the gate stack and the spacer remains at the step 230 in the stepped STI structure 207 ′.
- the residual material 232 leads to a large BULEX-to-SOI distance and could possibly induce an undesired conducting structure at the stepped STI structure 207 ′.
- a method of forming a semiconductor device includes providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.
- the method includes providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming an STI structure separating a first SOI region and a second SOI region, forming a gate structure on the active semiconductor layer in the first SOI region, and forming a diode structure in the second SOI region after the gate structure is formed.
- the method includes providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming an STI structure separating a first SOI region and a second SOI region, forming a gate structure on the active semiconductor layer in the first SOI region, and partially exposing the bulk substrate in the first SOI region at one side of the gate structure and contacting the exposed bulk region in the first SOI region for forming a back bias contact for the gate structure in the first SOI region.
- FIGS. 1 a -1 d schematically illustrate, in a cross-sectional view, a fabrication process for forming a BULEX region in SOI techniques in accordance with a first known technique
- FIGS. 2 a -2 c schematically illustrate, in a cross-sectional view, a fabrication process for providing a BULEX region in SOI techniques in accordance with a second known technique
- FIGS. 3 a -3 n schematically illustrate, in cross-sectional views, a process for fabricating contacts to BULEX regions in SOI techniques in accordance with various illustrative embodiments of the present disclosure.
- the present disclosure relates to a method of forming a semiconductor device and to semiconductor devices, wherein the semiconductor devices are integrated on or in a chip.
- the semiconductor devices may substantially represent FETs, e.g., MOSFETs or MOS devices.
- MOSFETs e.g., MOSFETs
- MOS device no limitation to a metal-containing gate material and/or to an oxide-containing gate dielectric material is intended.
- Semiconductor devices of the present disclosure concern devices which may be fabricated by using advanced technologies, i.e., the semiconductor devices may be fabricated by technologies applied to approach technology nodes smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm, e.g., at 28 nm or below.
- the semiconductor devices may be fabricated by technologies applied to approach technology nodes smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm, e.g., at 28 nm or below.
- ground rules smaller or equal to 45 nm, e.g., at 28 nm or below may be imposed.
- the present disclosure proposes semiconductor devices that may have structures of minimal length dimensions and/or width dimensions smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm or smaller than 28 nm.
- the present disclosure may provide semiconductor devices fabricated by using 45 nm technologies or below, e.g., 28 nm or even below.
- the semiconductor devices disclosed herein may be fabricated as P-channel MOS transistors or PMOS transistors and N-channel transistors or NMOS transistors; both types of transistors may be fabricated with or without mobility-enhancing stressor features or strain-inducing features. It is noted that a circuit designer can mix and match device types, using PMOS and NMOS devices, stressed and unstressed, to take advantage of the best characteristics of each device type as they best suit the semiconductor device under design.
- SOI devices have an active semiconductor layer disposed on a buried insulating material layer, which, in turn, is formed on a base substrate material.
- the active semiconductor layer may comprise one of silicon, germanium, silicon germanium and the like.
- the buried insulating material layer may comprise an insulating material, e.g., silicon oxide or silicon nitride.
- the base substrate material may be a base material that may be used as a substrate as known in the art, e.g., silicon and the like.
- the active semiconductor layer may have a thickness of about 20 nm or less, while the buried insulating material layer may have a thickness of about 145 nm or, in accordance with advanced techniques, the buried insulating material layer may have a thickness in a range from about 10 to about 30 nm.
- the active semiconductor layer may have a thickness of about 3 to about 10 nm.
- a crystalline plane orientation of the base substrate material similar to that of an ordinary silicon device, an SOI substrate whose surface is a face (100) may be used. However, in order to improve the performance of a PMOS semiconductor device, a surface of the PMOS semiconductor device may be used as a face (110). Alternatively, a hybrid plane orientation substrate whose surface may be mixed by a face (100) and a face (110) may be used. With regard to a varactor device, there is no restriction on a crystal plane orientation such that an impurity concentration, film thickness, dimension ratio of the device, and the like can be appropriately adjusted to obtain a capacitance characteristic that is suitable according to the plane orientation set by other requirements. In alternative embodiments, the base substrate material may be of an N-type when N-accumulation and/or N-inversion devices are considered (otherwise P-type for P-accumulation and/or P-inversion).
- a semiconductor device may be formed by providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure above the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.
- a well implantation process may be performed prior to forming the contact structure for implanting dopants into the bulk exposed region so as to form bulk well regions.
- an STI structure may be further provided in the SOI substrate prior to forming the gate structure and forming two bulk exposed regions, wherein the bulk exposed regions and the active region are separated by the STI structure.
- a diode structure may be formed upon forming a contact structure contacting the bulk exposed regions.
- a well implantation process may be performed prior to forming the contact structure for implanting dopants into the bulk exposed region so as to form bulk well regions, wherein the bulk exposed region is provided in the active region and a silicide contact is formed in the bulk well regions.
- the silicide contact may be subsequently contacted by the contact structure for forming a back bias contact for the gate structure.
- raised source/drain regions may be formed adjacent to the gate structure in the active region before exposing the base substrate, wherein the bulk exposed region is formed by etching a trench into the RSD region at one side of the gate structure so as to expose the bulk substrate in the trench.
- germanium may be implanted into the active semiconductor layer of the active region for forming a silicon-germanium region in the active semiconductor layer prior to forming the gate structure.
- the base substrate may be exposed by etching a trench into the active semiconductor layer and the buried insulating material layer.
- the contact structure may be formed by forming a PEN liner in the trench and depositing a contact material in the trench in alignment with the PEN liner.
- a silicide region may be formed in the bulk exposed region, before the PEN liner is formed.
- a semiconductor device may be formed by providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming an STI structure separating a first SOI region and a second SOI region, forming a gate structure on the active semiconductor layer in the first SOI region, and forming a diode structure in the second SOI region after the gate structure is formed.
- the diode structure may be formed by etching a first trench and a second trench into the second SOI region, wherein each trench exposes the base substrate such that a first bulk exposed region and a second bulk exposed region are provided in the second SOI region, implanting well regions into the first and second bulk exposed regions for forming bulk well regions, and forming a contact structure contacting the bulk well regions.
- the bulk substrate may be partially exposed in the first SOI region at one side of the gate structure and the exposed bulk region in the first SOI region may be contacted for forming a back bias contact for the gate structure in the first SOI region.
- a raised source/drain region may be formed at both sides of the gate structure, before the bulk exposed regions are formed in the first and second SOI regions, and the raised source/drain region may be removed at the one side of the gate structure, when the exposed bulk region is formed in the first region.
- the raised source/drain region may be removed by etching a trench into the raised source/drain region at the one side of the gate structure, followed by forming a PEN liner in the trench and depositing a contact material in the trench in alignment with the PEN liner for forming a back bias contact in the trench.
- a semiconductor device may be formed by providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming an STI structure separating a first SOI region and a second SOI region, forming a gate structure on the active semiconductor layer in the first SOI region, and partially exposing the bulk substrate in the first SOI region at one side of the gate structure and contacting the exposed bulk region in the first SOI region for forming a back bias contact for the gate structure in the first SOI region.
- a raised source/drain region may be formed at both sides of the gate structure on the first SOI region prior to forming the bulk exposed regions, and the raised source/drain region may be partially removed at the one side of the gate structure, when the exposed bulk region is formed in the first region.
- the raised source/drain region may be removed by etching a trench into the raised source/drain region at the one side of the gate structure, followed by forming a PEN liner in the trench and depositing a contact material in the trench in alignment with the PEN liner for forming a back bias contact in the trench.
- a diode structure may be formed in the second SOI region by etching a first trench and a second trench into the second SOI region, each trench exposing the base substrate such that a first bulk exposed region and a second bulk exposed region are provided in the second SOI region, implanting well regions into the first and second bulk exposed regions for forming bulk well regions, and forming a contact structure contacting the bulk well regions.
- FIGS. 3 a to 3 n Further illustrative embodiments will be apparent from the description of FIGS. 3 a to 3 n below.
- FIG. 3 a schematically illustrates a semiconductor device structure at an early stage during fabrication, particularly at a stage when an SOI substrate is provided.
- the SOI substrate is formed by an active semiconductor layer 305 provided on a buried insulating material layer 303 , which is, in turn, disposed on a base semiconductor material 301 .
- the active semiconductor layer 305 may be a semiconductor material such as silicon, silicon germanium, or the like.
- the buried insulating material layer 303 may be provided by an oxide material or a nitride material.
- the base substrate material 301 may be formed by silicon or any other appropriate semiconductor material.
- the active semiconductor material 305 may have a thickness in a range from about 3-10 nm, while the buried insulating material 303 may have a thickness in a range from about 10-30 nm, or in a range from about 130-160 nm, e.g., at about 149 nm.
- the base semiconductor material 301 may be doped or undoped.
- the base semiconductor material 301 may be P-doped or N-doped.
- FIG. 3 b schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after a silicon germanium region 307 is provided in the active semiconductor layer 305 , and a thin oxide layer 309 is formed over the semiconductor device structure.
- the silicon germanium region 307 may be provided by locally removing the active semiconductor layer 305 , e.g., by means of an appropriate masking pattern (not illustrated), and epitaxially growing silicon germanium material in accordance with the masking pattern.
- a germanium layer may be formed on a portion of the active semiconductor material layer 305 and germanium material is subsequently diffused into the active semiconductor material layer 305 below the germanium layer by means of an appropriate annealing process.
- germanium material may be implanted into the silicon germanium region 307 by means of an appropriate masking pattern (not illustrated).
- the semiconductor device structure is schematically illustrated at a more advanced stage during fabrication, particularly during a fabrication process for forming STI structures.
- trenches 310 defining and separating SOI regions A, B and C are etched into the SOI substrate in accordance with appropriate masking patterns (not illustrated).
- the trenches 310 are etched into the active semiconductor material 305 and the buried insulating material 303 so as to stop at an upper surface region of the base substrate material 301 .
- a thin oxide liner 315 may be deposited over the semiconductor device structure.
- the trenches 310 may be formed by depositing a pad oxide 311 and a nitride material 313 on the semiconductor device structure as illustrated in FIG. 3 b , followed by a resist material (not illustrated) which is then subjected to a lithographical process for patterning the resist material (not illustrated). In selectively etching the nitride material, oxide material, material of the active semiconductor material layer 305 , and the buried insulating material layer 303 in one or more etching steps, the trenches 310 are formed. Afterwards, the resist material is removed and a passivating oxide liner 315 is formed.
- the semiconductor device structure is schematically illustrated at a more advanced stage during fabrication, particularly after a deep STI structure 310 ′ is formed in addition to the shallow STI structure 310 and the trenches are filled, followed by a polishing process, e.g., CMP, removing the layers 311 to 315 and exposing upper surfaces of the active semiconductor material layer 305 in the SOI regions A, B and C.
- a polishing process e.g., CMP
- FIG. 3 e schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after gate materials 320 , e.g., gate dielectric material 322 and gate electrode material 324 , are deposited over the SOI regions A, B and C.
- gate materials 320 e.g., gate dielectric material 322 and gate electrode material 324
- at least one of a silicon oxide material and a high-k material is deposited when depositing the gate dielectric and metal gate material 322 , followed by depositing one of amorphous silicon, polysilicon and an appropriate gate electrode metal as the gate electrode material 324 .
- a masking structure is formed over the semiconductor device structure, e.g., a hard mask formed by a nitride, oxide, or nitride/oxide stack material 331 and a patterned resist material 333 .
- gate structures 340 , 350 (schematically illustrated in FIG. 30 are formed in the SOI regions B and C.
- the gate structures 340 , 350 are obtained after spacer structures 345 , 355 are formed at the respective gate stacks 341 , 343 and 351 , 353 .
- the gate stacks 341 , 343 and 351 , 353 are formed, when the process 334 is completed and the mask 331 , 333 is removed.
- a spacer forming material layer (not illustrated) is deposited over the semiconductor device structure, e.g., by blanket-deposition processes, and an anisotropic etching process (not illustrated) is performed for anisotropically etching the spacer forming material layer (not illustrated) such that sidewall spacers covering sidewalls of the gate stacks 341 , 343 and 351 , 353 are formed.
- an anisotropic etching process (not illustrated) is performed for anisotropically etching the spacer forming material layer (not illustrated) such that sidewall spacers covering sidewalls of the gate stacks 341 , 343 and 351 , 353 are formed.
- FIG. 3 g schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after a semiconductor material is grown on exposed surfaces of the active semiconductor material layer 305 and 307 , respectively, such that a grown semiconductor material 361 is formed on the active semiconductor material layer 305 in the SOI region A, and raised source/drain regions 362 , 363 are provided adjacent to the gate structures 340 , 350 in the SOI regions B, C.
- the grown material 361 is optional and may be omitted in alternative embodiments of the present disclosure.
- FIG. 3 h schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after a sidewall spacer extension structure 347 , 357 is formed at an upper portion of the gate structures 340 , 350 , which upper portion is not covered by the raised source/drain regions 362 , 363 , and after the gate cap is removed to expose an upper surface of the gate electrode materials 341 , 351 of the gate structures 340 , 350 .
- one of an oxide material and a nitride material may be deposited over the semiconductor device structure and anisotropically etched in accordance with spacer etching techniques to form the sidewall spacer extension structures 347 , 357 and to expose an upper surface of the gate electrode material 341 , 351 .
- an etching process for opening the gate structures to expose upper surfaces of the gate electrode material 341 , 351 may be performed, followed by the deposition of material for forming the sidewall spacer extension portions 347 , 357 .
- FIG. 3 i schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after an insulating material layer 367 , e.g., one of an oxide material and a nitride material, is deposited, followed by the formation of a pattern mask structure 370 covering the SOI region C and partially covering the SOI regions A and B.
- an insulating material layer 367 e.g., one of an oxide material and a nitride material
- FIG. 3 j schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after an etching process through the masking pattern 370 is completed and the masking pattern 370 is removed.
- trenches 371 , 373 are formed in the SOI region A, the trenches 371 and 373 being separated by an SOI portion 372 and the trenches 371 , 373 partially exposing an upper surface of the base substrate material 301 in the SOI region A.
- a trench 375 is formed in the SOI region B at one side of the gate structure 340 , the trench 375 partially exposing an upper surface of the base substrate material in the SOI region B.
- a distance between the trench 375 and the gate structure 340 is adjusted such that there is still enough landing space for a contact to the raised source/drain region 362 in between the trench 375 and the gate structure 340 .
- an implantation process may be performed in order to form bulk well regions 377 , 379 and 381 in the base substrate material 301 at the bottom of the trenches 371 , 373 and 375 .
- one of the wells 377 and 379 is doped with dopants of the same conductivity type as the surrounding base substrate material.
- the other of the bulk well regions 377 , 379 are doped with dopants of an opposite conductivity type to the surrounding conductivity of the base substrate material.
- one of the bulk well regions 377 and 379 e.g., the bulk well region 379
- the other of the bulk well regions 377 , 379 e.g., the bulk well region 377
- a diode structure may be provided when contacting the bulk well regions 377 and 379 in the SOI region A.
- FIG. 3 k schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after the trenches 371 , 373 and 375 in the SOI regions A and B are covered by a masking structure 383 , while the remaining portion of the SOI region B and the SOI region C are exposed to further processing.
- the semiconductor device structure as illustrated in FIG. 3 k Upon exposing the semiconductor device structure as illustrated in FIG. 3 k to an anisotropic etching process, the semiconductor device structure as illustrated in FIG. 31 is obtained after the anisotropic etching process is completed and the masking pattern 383 is removed.
- upper surface regions 391 , 393 and 395 of the raised source/drain regions 362 , 363 are exposed and a separation between the upper surface regions 391 , 393 and 395 to the gate structures 340 , 350 is further adjusted by further additional spacer elements 385 and 387 .
- the semiconductor device structure is schematically illustrated at a more advanced stage during fabrication, particularly after a silicidation process is performed for forming silicide regions 383 which are formed at the bottom of the trenches 371 , 373 and 375 and on the upper surface regions of the raised source/drain region 362 , 363 and exposed upper surfaces of the gate electrode material 341 , 351 .
- Silicidation processes are well known in the art and comprise depositing a metal material, subjecting the metal material to an annealing step for forming silicide material and removing the un-reacted metal by known etch chemistries.
- the semiconductor device structure is schematically illustrated at a more advanced stage during fabrication, particularly after a plasma-enhanced nitride (PEN) material 385 , e.g., TPEN/CPEN (tensile PEN/compressive PEN), a contact dielectric 386 and contact structures 387 , 389 , 391 , 393 , 395 and 397 are formed.
- PEN plasma-enhanced nitride
- TPEN/CPEN tensile PEN/compressive PEN
- contact structure 387 comprises two contacts contacting the silicide region 383 on the bulk well regions 377 , 379 in the SOI region A for providing a diode structure between the contacts 387 .
- the contact structure 389 contacts the silicide region 383 on the bulk well region 381 for providing a back bias contact to the gate structure 340 in the SOI structure B.
- the contacts 391 represent source/drain contacts, while the contact 393 contacts the gate structure 340 .
- the contact 395 is a source/drain contact, while the contact 397 is contacting the gate structure 350 .
- the contact structures may comprise contact liners, e.g., TiN, and contact material, such as tungsten.
- the semiconductor device structure as fabricated in accordance with the process described above with regard to FIGS. 3 a -3 n provides PEN liners that allow for contact self-alignment in contact holes. Furthermore, no epi re-growth of BULEX material is performed. Therefore, issues as discussed above with regard to FIGS. 1 a -1 d are not arising.
- standard BULEX (before gate) may be used on the same chip for making other passive devices like resistors, DCAPs, etc.
- raised source/drain regions are described above in the various illustrative embodiments of the present disclosure, the raised source/drain regions are optional and may also be omitted.
- back bias contact and semiconductor device contacts are achieved. Furthermore, back bias bulk contact and the implementation of diode structures in the bulk are possible at the same time in some of the above described illustrative embodiments.
- the present disclosure provides fabrication processes where gate patterning processes are performed and FDSOI MOSFET formation is applied before steps working on BULEX areas are employed. Particularly, STI/RX patterning, gate stack formation and gate stack patterning, spacer formation, formation of raised source/drain regions, spacer/implant steps and gate nitride cap removal is performed, before a BULEX area is patterned via an additional masking pattern.
- STI/RX patterning, gate stack formation and gate stack patterning, spacer formation, formation of raised source/drain regions, spacer/implant steps and gate nitride cap removal is performed, before a BULEX area is patterned via an additional masking pattern.
- appropriate N- and P-masks and implant steps may be subjected to the bulk structures in order to implement appropriate diode and back bias configurations.
- the fabrication process is continued by silicidation techniques, TPEN, CPEN deposition, contact formation and the like.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
- 1. Field of the Invention The present disclosure generally relates to advanced FDSOI techniques and, more particularly, to the fabrication of BULEX contacts in advanced FDSOI techniques.
- 2. Description of the Related Art
- In the ongoing task to comply with constraints imposed by Moore's Law, FDSOI (“fully depleted silicon-on-isolator”) is currently favored as the basis for next generation technologies in the fabrication of semiconductor devices at technology nodes of 22 nm and beyond. Aside from FDSOI allowing the combination of high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques, fabrication processes as employed in FDSOI techniques are comparatively simple and actually represent a low risk evolution of conventional planar bulk CMOS techniques when compared to three-dimensional transistor designs, such as FinFETs.
- In general, SOI techniques make use of a special kind of substrate being formed by a semiconductor layer, such as silicon, germanium or silicon germanium, formed on a buried oxide (BOX) layer, which is in turn formed on a semiconductor substrate. Conventionally, there are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI MOSFETs (fully depleted SOI). For example, in an N-type PDSOI MOSFET, a P-type film is sandwiched between a gate oxide (GOX) and the BOX, where a thickness of the P-type film is such that the depletion region cannot cover the whole P-region. Therefore, to some extent, PDSOI devices may behave like bulk MOSFETs.
- In FDSOI substrates, the thickness of the semiconductor layer is such that the depletion region covers the whole semiconductor layer. Herein, the GOX in FDSOI techniques supports fewer depletion charges than a bulk substrate and an increase in the inversion charges occurs in the fully depleted semiconductor layer, resulting in higher switching speeds.
- In recent attempts to provide a simple way of meeting power/performance targets, back biasing was suggested for FDSOI devices. When adopting the concept of back biasing, a voltage is applied just under the BOX of target semiconductor devices. In doing so, the electrostatic control of the semiconductor device is changed and the threshold voltage is shifted to either obtain more drive current (hence, higher performance) at the expense of increased leakage current (forward back bias, FBB) or to cut leakage current at the expense of reduced performance. While back bias in planar FDSOI techniques is somewhat similar to body bias as implemented in bulk CMOS technologies, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. For example, back biasing can be utilized in a dynamic way on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue.
- The effects of process and temperature variations can be reduced when using back biasing techniques are employed. As a result, the design of circuits including such devices becomes much easier by greatly reducing the spread of performance that the designers have to address when designing a circuit. As back biasing further allows operation at consistently lower (and more constant) supply voltages, the power consumption of FDSOI devices is also reduced and electromigration and power density problems are eased.
- The implementation of back bias in the setup of FDSOI techniques involves a local exposure of the bulk substrate, so-called BULEX (bulk exposed') regions, that are to be contacted. Naturally, the bulk substrate has a height difference relative to an upper surface of the active semiconductor layer of an SOI substrate. Accordingly, a step height exists between BULEX regions and SOI substrates in the form of the BOX layer and the active semiconductor layer. In advanced technologies, the step height may be on the order of 30 nm, which raises big challenges in front end of line (FEOL) processing of advanced semiconductor devices. For example, the step height between the bulk semiconductor material (at the BULEX regions) and the upper surface of the active layer of an SOI substrate (at transistor devices) leads to uncontrollable variations in the critical dimensions, to large offsets between FDSOI and bulk structure critical dimensions and, particularly, in lithographical processes, to divots and crevices where film residues are hard to remove and which can cause shorts and leaks in the final circuit.
- One conventional fabrication process for forming BULEX contacts besides SOI semiconductor devices will be explained with regard to
FIGS. 1a-1d and 2a-2c below. -
FIGS. 1a-1d schematically show, in a cross-sectional view, a known FEOL process for implementing a back bias contact via contacting a BULEX area beside an active region according to SOI techniques. With regard toFIG. 1 a, a known SOI substrate region is schematically illustrated. As indicated above, an SOI substrate is formed by abase substrate material 101, on which a buried oxide (BOX)material 103, and anactive silicon film 105 is provided. - Starting from the SOI substrate as schematically illustrated in
FIG. 1 a, a bulk exposedregion 120 is formed adjacent to anSOI region 110 by techniques implemented for locally removing theBOX material 103 and theactive silicon film 105, as shown in Figure lb. Herein, a mask pattern (not illustrated) may be formed via lithographical techniques, e.g., by forming a resist material (not illustrated) on a thin oxide liner 107 (passivation oxide) provided on theactive silicon film 105 and lithographically patterning the resist material (not illustrated) such that a region, where the BULEXregion 120 is to be provided, is not covered by the masking pattern (not illustrated). In removing theactive silicon film 105 and theBOX material 103 in accordance with the masking pattern (not illustrated), a bulk exposedregion 120 is locally formed. - Regarding
FIG. 1 c, a process of re-growing silicon material on the BULEXregion 120 is preformed such that the step height between the BULEXregion 120 and theactive silicon film 105 in theSOI region 110 is reduced. However, as the height level of there-grown silicon material 121 on the BULEXregion 120 may not totally match the height level of theactive silicon film 105, there-grown silicon material 121 is overgrown and, as a consequence, adislocation portion 123 is formed at the interface of theSOI region 110 and the BULEXregion 120. - In order to avoid possible disadvantageous effects resulting from the
dislocation 123, an STI region of sufficient width is formed at the interface by matching atrench 125 with a width dimension d1 into the SOI material and there-grown silicon material 121 at the interface between theSOI region 110 and the BULEXregion 120, as shown inFIG. 1 d. Therefore, a separation between the BULEXregion 120 and theSOI region 110 has to be implemented in order to remove thedislocation 123, therefore leading to an increased distance between a BULEX contact (not illustrated), which is to be formed on the BULEXregion 120, relative to a semiconductor device (not illustrated), which is to be formed on and in theSOI region 110 during subsequent fabrication steps. Conventionally, a width of thetrench 125 is greater than a width of normally formedSTI trenches 126, i.e., d1>d2. - With regard to
FIGS. 2a -2 c, issues appearing with the step height difference between BULEX regions and SOI regions are illustrated.FIG. 2a schematically illustrates a semiconductor device structure at an early stage during fabrication, particularly before any gate structure is formed and anSTI region 207 is provided within an SOI substrate structure (base substrate 201,BOX material 203 and active silicon film 205), where theSTI structure 207 separates afirst SOI region 210 and asecond SOI region 220. Thefirst SOI region 210 and thesecond SOI region 220 are herein covered by a thin oxide liner. - Subsequently, a BULEX region is formed in the
second SOI region 220 by locally removing theBOX material 203 and theactive silicon film 205 in thesecond SOI region 220. Accordingly, a step height h (seeFIG. 2b ) is provided between the BULEXregion 220 and the SOIregion 210. As the STI 207 is partially exposed when theBOX material 203 and theactive silicon film 205 in the bulk exposed (BULEX)region 220 are removed, astep 230 is formed in theSTI 207 resulting in astepped STI structure 207′. - Subsequent to providing the BULEX
region 220, agate structure 211 is formed on theSOI region 210, as shown inFIG. 2c . Thegate structure 211 is formed by depositing a gatedielectric material 215 and agate electrode material 213 over theSOI region 210 and the BULEXregion 220, forming a gate mask pattern (not illustrated) on the deposited materials and removing the deposited material in accordance with the gate mask pattern (not illustrated). After thegate stack sidewall spacers 217 and thegate cap 219 are formed by depositing the spacer forming material and anisotropically etching the spacer forming material. - As a result of the gate stack patterning (herein, the anisotropic etching of the gate material) and the spacer forming process (herein, the anisotropic etching of the spacer forming material),
residual material 232 of the gate stack and the spacer remains at thestep 230 in thestepped STI structure 207′. Theresidual material 232 leads to a large BULEX-to-SOI distance and could possibly induce an undesired conducting structure at thestepped STI structure 207′. - In view of the above-described situation, it is desirable to provide a BULEX contact in FDSOI techniques without the issues as discussed above with regard to
FIGS. 1a -2 c. - The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
- In a first aspect of the present disclosure, a method of forming a semiconductor device is provided. In accordance with some illustrative embodiments herein, the method includes providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.
- In accordance with a second aspect of the present disclosure, a method of forming a semiconductor device is provided. In accordance with some illustrative embodiments herein, the method includes providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming an STI structure separating a first SOI region and a second SOI region, forming a gate structure on the active semiconductor layer in the first SOI region, and forming a diode structure in the second SOI region after the gate structure is formed.
- In a third aspect of the present disclosure, a method of forming a semiconductor device is provided. In accordance with some illustrative embodiments herein, the method includes providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming an STI structure separating a first SOI region and a second SOI region, forming a gate structure on the active semiconductor layer in the first SOI region, and partially exposing the bulk substrate in the first SOI region at one side of the gate structure and contacting the exposed bulk region in the first SOI region for forming a back bias contact for the gate structure in the first SOI region.
- The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
-
FIGS. 1a-1d schematically illustrate, in a cross-sectional view, a fabrication process for forming a BULEX region in SOI techniques in accordance with a first known technique; -
FIGS. 2a-2c schematically illustrate, in a cross-sectional view, a fabrication process for providing a BULEX region in SOI techniques in accordance with a second known technique; and -
FIGS. 3a-3n schematically illustrate, in cross-sectional views, a process for fabricating contacts to BULEX regions in SOI techniques in accordance with various illustrative embodiments of the present disclosure. - While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
- The present disclosure will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details which are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary or customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition shall be expressively set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
- The present disclosure relates to a method of forming a semiconductor device and to semiconductor devices, wherein the semiconductor devices are integrated on or in a chip. In accordance with some illustrative embodiments of the present disclosure, the semiconductor devices may substantially represent FETs, e.g., MOSFETs or MOS devices. When referring to MOS devices, the person skilled in the art will appreciate that, although the expression “MOS device” is used, no limitation to a metal-containing gate material and/or to an oxide-containing gate dielectric material is intended.
- Semiconductor devices of the present disclosure concern devices which may be fabricated by using advanced technologies, i.e., the semiconductor devices may be fabricated by technologies applied to approach technology nodes smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm, e.g., at 28 nm or below. After a complete reading of the present application, a person skilled in the art will appreciate that, according to the present disclosure, ground rules smaller or equal to 45 nm, e.g., at 28 nm or below, may be imposed. The present disclosure proposes semiconductor devices that may have structures of minimal length dimensions and/or width dimensions smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm or smaller than 28 nm. For example, the present disclosure may provide semiconductor devices fabricated by using 45 nm technologies or below, e.g., 28 nm or even below.
- The semiconductor devices disclosed herein may be fabricated as P-channel MOS transistors or PMOS transistors and N-channel transistors or NMOS transistors; both types of transistors may be fabricated with or without mobility-enhancing stressor features or strain-inducing features. It is noted that a circuit designer can mix and match device types, using PMOS and NMOS devices, stressed and unstressed, to take advantage of the best characteristics of each device type as they best suit the semiconductor device under design.
- In general, SOI devices have an active semiconductor layer disposed on a buried insulating material layer, which, in turn, is formed on a base substrate material. In accordance with some illustrative embodiments herein, the active semiconductor layer may comprise one of silicon, germanium, silicon germanium and the like. The buried insulating material layer may comprise an insulating material, e.g., silicon oxide or silicon nitride. The base substrate material may be a base material that may be used as a substrate as known in the art, e.g., silicon and the like. In accordance with illustrative embodiments employing FDSOI substrates disclosed herein, the active semiconductor layer may have a thickness of about 20 nm or less, while the buried insulating material layer may have a thickness of about 145 nm or, in accordance with advanced techniques, the buried insulating material layer may have a thickness in a range from about 10 to about 30 nm. For example, in some special illustrative embodiments of the present disclosure, the active semiconductor layer may have a thickness of about 3 to about 10 nm.
- As to a crystalline plane orientation of the base substrate material, similar to that of an ordinary silicon device, an SOI substrate whose surface is a face (100) may be used. However, in order to improve the performance of a PMOS semiconductor device, a surface of the PMOS semiconductor device may be used as a face (110). Alternatively, a hybrid plane orientation substrate whose surface may be mixed by a face (100) and a face (110) may be used. With regard to a varactor device, there is no restriction on a crystal plane orientation such that an impurity concentration, film thickness, dimension ratio of the device, and the like can be appropriately adjusted to obtain a capacitance characteristic that is suitable according to the plane orientation set by other requirements. In alternative embodiments, the base substrate material may be of an N-type when N-accumulation and/or N-inversion devices are considered (otherwise P-type for P-accumulation and/or P-inversion).
- In accordance with one illustrative embodiment of the present disclosure, as described above, a semiconductor device may be formed by providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure above the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region. In accordance with some illustrative embodiments herein, a well implantation process may be performed prior to forming the contact structure for implanting dopants into the bulk exposed region so as to form bulk well regions. In accordance with yet another example disclosed herein, an STI structure may be further provided in the SOI substrate prior to forming the gate structure and forming two bulk exposed regions, wherein the bulk exposed regions and the active region are separated by the STI structure. For example, a diode structure may be formed upon forming a contact structure contacting the bulk exposed regions.
- In accordance with some illustrative embodiments disclosed herein, a well implantation process may be performed prior to forming the contact structure for implanting dopants into the bulk exposed region so as to form bulk well regions, wherein the bulk exposed region is provided in the active region and a silicide contact is formed in the bulk well regions. The silicide contact may be subsequently contacted by the contact structure for forming a back bias contact for the gate structure. In accordance with one illustrative embodiment, raised source/drain regions (RSD) may be formed adjacent to the gate structure in the active region before exposing the base substrate, wherein the bulk exposed region is formed by etching a trench into the RSD region at one side of the gate structure so as to expose the bulk substrate in the trench.
- In accordance with other illustrative embodiments, germanium may be implanted into the active semiconductor layer of the active region for forming a silicon-germanium region in the active semiconductor layer prior to forming the gate structure.
- In accordance with yet other illustrative embodiments, the base substrate may be exposed by etching a trench into the active semiconductor layer and the buried insulating material layer. In one illustrative embodiment depicted herein, the contact structure may be formed by forming a PEN liner in the trench and depositing a contact material in the trench in alignment with the PEN liner. For example, a silicide region may be formed in the bulk exposed region, before the PEN liner is formed.
- In accordance with yet another illustrative embodiment of the present disclosure, as described above, a semiconductor device may be formed by providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming an STI structure separating a first SOI region and a second SOI region, forming a gate structure on the active semiconductor layer in the first SOI region, and forming a diode structure in the second SOI region after the gate structure is formed.
- In accordance with some illustrative embodiments, the diode structure may be formed by etching a first trench and a second trench into the second SOI region, wherein each trench exposes the base substrate such that a first bulk exposed region and a second bulk exposed region are provided in the second SOI region, implanting well regions into the first and second bulk exposed regions for forming bulk well regions, and forming a contact structure contacting the bulk well regions.
- In accordance with still other illustrative embodiments, the bulk substrate may be partially exposed in the first SOI region at one side of the gate structure and the exposed bulk region in the first SOI region may be contacted for forming a back bias contact for the gate structure in the first SOI region. In one illustrative embodiment herein, a raised source/drain region may be formed at both sides of the gate structure, before the bulk exposed regions are formed in the first and second SOI regions, and the raised source/drain region may be removed at the one side of the gate structure, when the exposed bulk region is formed in the first region. For example, the raised source/drain region may be removed by etching a trench into the raised source/drain region at the one side of the gate structure, followed by forming a PEN liner in the trench and depositing a contact material in the trench in alignment with the PEN liner for forming a back bias contact in the trench.
- In accordance with yet another embodiment of the present disclosure, as described above, a semiconductor device may be formed by providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming an STI structure separating a first SOI region and a second SOI region, forming a gate structure on the active semiconductor layer in the first SOI region, and partially exposing the bulk substrate in the first SOI region at one side of the gate structure and contacting the exposed bulk region in the first SOI region for forming a back bias contact for the gate structure in the first SOI region.
- In accordance with some illustrative embodiments, a raised source/drain region may be formed at both sides of the gate structure on the first SOI region prior to forming the bulk exposed regions, and the raised source/drain region may be partially removed at the one side of the gate structure, when the exposed bulk region is formed in the first region. In one illustrative embodiment herein, the raised source/drain region may be removed by etching a trench into the raised source/drain region at the one side of the gate structure, followed by forming a PEN liner in the trench and depositing a contact material in the trench in alignment with the PEN liner for forming a back bias contact in the trench.
- In accordance with some illustrative embodiments, a diode structure may be formed in the second SOI region by etching a first trench and a second trench into the second SOI region, each trench exposing the base substrate such that a first bulk exposed region and a second bulk exposed region are provided in the second SOI region, implanting well regions into the first and second bulk exposed regions for forming bulk well regions, and forming a contact structure contacting the bulk well regions.
- Further illustrative embodiments will be apparent from the description of
FIGS. 3a to 3n below. -
FIG. 3a schematically illustrates a semiconductor device structure at an early stage during fabrication, particularly at a stage when an SOI substrate is provided. The SOI substrate is formed by anactive semiconductor layer 305 provided on a buried insulatingmaterial layer 303, which is, in turn, disposed on abase semiconductor material 301. In accordance with some illustrative examples of the present disclosure, theactive semiconductor layer 305 may be a semiconductor material such as silicon, silicon germanium, or the like. Furthermore, the buried insulatingmaterial layer 303 may be provided by an oxide material or a nitride material. Thebase substrate material 301 may be formed by silicon or any other appropriate semiconductor material. In accordance with some illustrative examples, theactive semiconductor material 305 may have a thickness in a range from about 3-10 nm, while the buried insulatingmaterial 303 may have a thickness in a range from about 10-30 nm, or in a range from about 130-160 nm, e.g., at about 149 nm. - In accordance with some illustrative embodiments, the
base semiconductor material 301 may be doped or undoped. For example, thebase semiconductor material 301 may be P-doped or N-doped. -
FIG. 3b schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after asilicon germanium region 307 is provided in theactive semiconductor layer 305, and athin oxide layer 309 is formed over the semiconductor device structure. - In accordance with illustrative embodiments of the present disclosure, the
silicon germanium region 307 may be provided by locally removing theactive semiconductor layer 305, e.g., by means of an appropriate masking pattern (not illustrated), and epitaxially growing silicon germanium material in accordance with the masking pattern. Alternatively, a germanium layer may be formed on a portion of the activesemiconductor material layer 305 and germanium material is subsequently diffused into the activesemiconductor material layer 305 below the germanium layer by means of an appropriate annealing process. Still alternatively, germanium material may be implanted into thesilicon germanium region 307 by means of an appropriate masking pattern (not illustrated). - With regard to
FIG. 3c , the semiconductor device structure is schematically illustrated at a more advanced stage during fabrication, particularly during a fabrication process for forming STI structures. At the stage illustrated inFIG. 3c ,trenches 310 defining and separating SOI regions A, B and C are etched into the SOI substrate in accordance with appropriate masking patterns (not illustrated). Thetrenches 310 are etched into theactive semiconductor material 305 and the buried insulatingmaterial 303 so as to stop at an upper surface region of thebase substrate material 301. Subsequently, athin oxide liner 315 may be deposited over the semiconductor device structure. - In accordance with some illustrative embodiments of the present disclosure, the
trenches 310 may be formed by depositing apad oxide 311 and anitride material 313 on the semiconductor device structure as illustrated inFIG. 3b , followed by a resist material (not illustrated) which is then subjected to a lithographical process for patterning the resist material (not illustrated). In selectively etching the nitride material, oxide material, material of the activesemiconductor material layer 305, and the buried insulatingmaterial layer 303 in one or more etching steps, thetrenches 310 are formed. Afterwards, the resist material is removed and apassivating oxide liner 315 is formed. - With regard to
FIG. 3d , the semiconductor device structure is schematically illustrated at a more advanced stage during fabrication, particularly after adeep STI structure 310′ is formed in addition to theshallow STI structure 310 and the trenches are filled, followed by a polishing process, e.g., CMP, removing thelayers 311 to 315 and exposing upper surfaces of the activesemiconductor material layer 305 in the SOI regions A, B and C. -
FIG. 3e schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after gate materials 320, e.g., gate dielectric material 322 and gate electrode material 324, are deposited over the SOI regions A, B and C. In accordance with some illustrative embodiments of the present disclosure, at least one of a silicon oxide material and a high-k material (e.g. hafnium oxide and the like) is deposited when depositing the gate dielectric and metal gate material 322, followed by depositing one of amorphous silicon, polysilicon and an appropriate gate electrode metal as the gate electrode material 324. - Next, a masking structure is formed over the semiconductor device structure, e.g., a hard mask formed by a nitride, oxide, or nitride/oxide stack material 331 and a patterned resist material 333. After performing a gate structuring process 334 by anisotropically etching the deposited gate material 320 via the masking pattern 331, 333,
gate structures 340, 350 (schematically illustrated inFIG. 30 are formed in the SOI regions B and C. The person skilled in the art will appreciate that thegate structures - Next, after completing the process 334, a spacer forming material layer (not illustrated) is deposited over the semiconductor device structure, e.g., by blanket-deposition processes, and an anisotropic etching process (not illustrated) is performed for anisotropically etching the spacer forming material layer (not illustrated) such that sidewall spacers covering sidewalls of the gate stacks 341, 343 and 351, 353 are formed. After formation of a gate cap, the spacer structure 345 and 355 (illustrated in
FIG. 3f ) are obtained. -
FIG. 3g schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after a semiconductor material is grown on exposed surfaces of the activesemiconductor material layer grown semiconductor material 361 is formed on the activesemiconductor material layer 305 in the SOI region A, and raised source/drain regions gate structures grown material 361 is optional and may be omitted in alternative embodiments of the present disclosure. -
FIG. 3h schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after a sidewallspacer extension structure gate structures drain regions gate structures - In accordance with some illustrative embodiments of the present disclosure, one of an oxide material and a nitride material may be deposited over the semiconductor device structure and anisotropically etched in accordance with spacer etching techniques to form the sidewall
spacer extension structures spacer extension portions -
FIG. 3i schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after an insulatingmaterial layer 367, e.g., one of an oxide material and a nitride material, is deposited, followed by the formation of apattern mask structure 370 covering the SOI region C and partially covering the SOI regions A and B. -
FIG. 3j schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after an etching process through themasking pattern 370 is completed and themasking pattern 370 is removed. As a result of the etching process,trenches trenches SOI portion 372 and thetrenches base substrate material 301 in the SOI region A. - Furthermore, a
trench 375 is formed in the SOI region B at one side of thegate structure 340, thetrench 375 partially exposing an upper surface of the base substrate material in the SOI region B. The person skilled in the art will appreciate that a distance between thetrench 375 and thegate structure 340 is adjusted such that there is still enough landing space for a contact to the raised source/drain region 362 in between thetrench 375 and thegate structure 340. After thetrenches regions base substrate material 301 at the bottom of thetrenches - In accordance with some illustrative embodiments of the present disclosure, one of the
wells bulk well region 381, is doped with dopants of the same conductivity type as the surrounding base substrate material. The other of the bulk wellregions regions bulk well region 379, together with thebulk well region 381 may be strongly P-doped, while the other of the bulk wellregions bulk well region 377, may be strongly N-doped. The person skilled in the art will appreciate that this does not pose any limitations on the present disclosure and other conductivity types and/or configurations may be applied. However, when using bulk wellregions regions -
FIG. 3k schematically illustrates the semiconductor device structure at a more advanced stage during fabrication, particularly after thetrenches structure 383, while the remaining portion of the SOI region B and the SOI region C are exposed to further processing. Upon exposing the semiconductor device structure as illustrated inFIG. 3k to an anisotropic etching process, the semiconductor device structure as illustrated inFIG. 31 is obtained after the anisotropic etching process is completed and themasking pattern 383 is removed. With regard toFIG. 31 ,upper surface regions drain regions upper surface regions gate structures additional spacer elements - With regard to
FIG. 3m , the semiconductor device structure is schematically illustrated at a more advanced stage during fabrication, particularly after a silicidation process is performed for formingsilicide regions 383 which are formed at the bottom of thetrenches drain region - With regard to
FIG. 3n , the semiconductor device structure is schematically illustrated at a more advanced stage during fabrication, particularly after a plasma-enhanced nitride (PEN)material 385, e.g., TPEN/CPEN (tensile PEN/compressive PEN), acontact dielectric 386 andcontact structures contact structure 387 comprises two contacts contacting thesilicide region 383 on the bulk wellregions contacts 387. - The
contact structure 389 contacts thesilicide region 383 on thebulk well region 381 for providing a back bias contact to thegate structure 340 in the SOI structure B. Thecontacts 391 represent source/drain contacts, while thecontact 393 contacts thegate structure 340. With regard to the SOI region C, thecontact 395 is a source/drain contact, while thecontact 397 is contacting thegate structure 350. The contact structures may comprise contact liners, e.g., TiN, and contact material, such as tungsten. - The semiconductor device structure as fabricated in accordance with the process described above with regard to
FIGS. 3a-3n provides PEN liners that allow for contact self-alignment in contact holes. Furthermore, no epi re-growth of BULEX material is performed. Therefore, issues as discussed above with regard toFIGS. 1a-1d are not arising. Of course, if desired, standard BULEX (before gate) may be used on the same chip for making other passive devices like resistors, DCAPs, etc. - Although raised source/drain regions are described above in the various illustrative embodiments of the present disclosure, the raised source/drain regions are optional and may also be omitted.
- As no complete exposure of bulk material is performed in a complete active region, e.g., one of the regions A, B and C, no topography issues as discussed above with regard to
FIGS. 2a-2c arise. - In accordance with the present disclosure, a smaller distance between back bias contact and semiconductor device contacts are achieved. Furthermore, back bias bulk contact and the implementation of diode structures in the bulk are possible at the same time in some of the above described illustrative embodiments.
- In summary, the present disclosure provides fabrication processes where gate patterning processes are performed and FDSOI MOSFET formation is applied before steps working on BULEX areas are employed. Particularly, STI/RX patterning, gate stack formation and gate stack patterning, spacer formation, formation of raised source/drain regions, spacer/implant steps and gate nitride cap removal is performed, before a BULEX area is patterned via an additional masking pattern. After a complete reading of the present application, a person skilled in the art will appreciate that appropriate N- and P-masks and implant steps may be subjected to the bulk structures in order to implement appropriate diode and back bias configurations. After the BULEX working steps, the fabrication process is continued by silicidation techniques, TPEN, CPEN deposition, contact formation and the like.
- The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/816,337 US9608112B2 (en) | 2015-08-03 | 2015-08-03 | BULEX contacts in advanced FDSOI techniques |
US15/042,547 US9698179B2 (en) | 2015-08-03 | 2016-02-12 | Capacitor structure and method of forming a capacitor structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/816,337 US9608112B2 (en) | 2015-08-03 | 2015-08-03 | BULEX contacts in advanced FDSOI techniques |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/042,547 Continuation-In-Part US9698179B2 (en) | 2015-08-03 | 2016-02-12 | Capacitor structure and method of forming a capacitor structure |
Publications (2)
Publication Number | Publication Date |
---|---|
US20170040450A1 true US20170040450A1 (en) | 2017-02-09 |
US9608112B2 US9608112B2 (en) | 2017-03-28 |
Family
ID=58053093
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/816,337 Active US9608112B2 (en) | 2015-08-03 | 2015-08-03 | BULEX contacts in advanced FDSOI techniques |
Country Status (1)
Country | Link |
---|---|
US (1) | US9608112B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180374880A1 (en) * | 2017-06-21 | 2018-12-27 | Samsung Electronics Co, Ltd. | Semiconductor device and fabricating method of the same |
CN112382605A (en) * | 2020-11-11 | 2021-02-19 | 上海华力集成电路制造有限公司 | Method for manufacturing FDSOI |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10114919B2 (en) * | 2016-02-12 | 2018-10-30 | Globalfoundries Inc. | Placing and routing method for implementing back bias in FDSOI |
US10593674B1 (en) | 2018-09-12 | 2020-03-17 | Globalfoundries Inc. | Deep fence isolation for logic cells |
US10910375B2 (en) | 2018-09-28 | 2021-02-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of fabrication thereof |
US10714577B2 (en) | 2018-10-02 | 2020-07-14 | Globalfoundries Inc. | Etch stop layer for use in forming contacts that extend to multiple depths |
US20200152661A1 (en) * | 2018-11-08 | 2020-05-14 | Nxp Usa, Inc. | Standard cell having mixed flip-well and conventional well transistors |
US10727253B1 (en) * | 2019-02-04 | 2020-07-28 | Globalfoundries Inc. | Simplified memory cells based on fully-depleted silicon-on-insulator transistors |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6887798B2 (en) * | 2003-05-30 | 2005-05-03 | International Business Machines Corporation | STI stress modification by nitrogen plasma treatment for improving performance in small width devices |
US7382023B2 (en) | 2004-04-28 | 2008-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fully depleted SOI multiple threshold voltage application |
JP2006261455A (en) | 2005-03-17 | 2006-09-28 | Fujitsu Ltd | Semiconductor device and mim caspacitor |
US7851859B2 (en) * | 2006-11-01 | 2010-12-14 | Samsung Electronics Co., Ltd. | Single transistor memory device having source and drain insulating regions and method of fabricating the same |
US7875919B2 (en) * | 2008-03-31 | 2011-01-25 | International Business Machines Corporation | Shallow trench capacitor compatible with high-K / metal gate |
US8828816B2 (en) * | 2011-05-25 | 2014-09-09 | Globalfoundries Inc. | PMOS threshold voltage control by germanium implantation |
US8709890B2 (en) * | 2011-12-12 | 2014-04-29 | International Business Machines Corporation | Method and structure for forming ETSOI capacitors, diodes, resistors and back gate contacts |
US8890247B2 (en) | 2012-10-15 | 2014-11-18 | International Business Machines Corporation | Extremely thin semiconductor-on-insulator with back gate contact |
US9023688B1 (en) | 2013-06-09 | 2015-05-05 | Monolithic 3D Inc. | Method of processing a semiconductor device |
US9257530B1 (en) * | 2014-08-28 | 2016-02-09 | GlobalFoundries, Inc. | Methods of making integrated circuits and components thereof |
-
2015
- 2015-08-03 US US14/816,337 patent/US9608112B2/en active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180374880A1 (en) * | 2017-06-21 | 2018-12-27 | Samsung Electronics Co, Ltd. | Semiconductor device and fabricating method of the same |
CN109103202A (en) * | 2017-06-21 | 2018-12-28 | 三星电子株式会社 | Semiconductor devices and its manufacturing method |
US11075233B2 (en) * | 2017-06-21 | 2021-07-27 | Samsung Electronics Co., Ltd. | Semiconductor device and fabricating method of the same |
CN112382605A (en) * | 2020-11-11 | 2021-02-19 | 上海华力集成电路制造有限公司 | Method for manufacturing FDSOI |
Also Published As
Publication number | Publication date |
---|---|
US9608112B2 (en) | 2017-03-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9608112B2 (en) | BULEX contacts in advanced FDSOI techniques | |
US8853038B2 (en) | Raised source/drain structure for enhanced strain coupling from stress liner | |
US8003458B2 (en) | Methods of manufacturing a semiconductor device with active regions of different heights | |
US8377761B2 (en) | SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device | |
US20100127333A1 (en) | novel layout architecture for performance enhancement | |
US9064799B2 (en) | Method of forming edge devices for improved performance | |
US9064972B2 (en) | Method of forming a gated diode structure for eliminating RIE damage from cap removal | |
US9502564B2 (en) | Fully depleted device with buried insulating layer in channel region | |
US9698179B2 (en) | Capacitor structure and method of forming a capacitor structure | |
US20120267724A1 (en) | Mos semiconductor device and methods for its fabrication | |
TWI684281B (en) | High voltage transistor using buried insulating layer as gate dielectric | |
US20160329326A1 (en) | Sub-fin doped bulk fin field effect transistor (finfet), integrated circuit (ic) and method of manufacture | |
US9514942B1 (en) | Method of forming a gate mask for fabricating a structure of gate lines | |
US20140256135A1 (en) | Methods of removing gate cap layers in cmos applications | |
US10395987B2 (en) | Transistor with source-drain silicide pullback | |
US9466717B1 (en) | Complex semiconductor devices of the SOI type | |
US9425189B1 (en) | Compact FDSOI device with Bulex contact extending through buried insulating layer adjacent gate structure for back-bias | |
US9082662B2 (en) | SOI semiconductor device comprising a substrate diode and a film diode formed by using a common well implantation mask | |
US10170614B2 (en) | Method of forming a semiconductor device | |
US10453754B1 (en) | Diffused contact extension dopants in a transistor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOENTSCHEL, JAN;BEYER, SVEN;HASCHE, TOM;AND OTHERS;SIGNING DATES FROM 20150724 TO 20150729;REEL/FRAME:036237/0255 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |