US20160379883A1 - Integrated circuit (ic) chips with through silicon vias (tsv) and method of forming the ic - Google Patents
Integrated circuit (ic) chips with through silicon vias (tsv) and method of forming the ic Download PDFInfo
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- US20160379883A1 US20160379883A1 US14/749,843 US201514749843A US2016379883A1 US 20160379883 A1 US20160379883 A1 US 20160379883A1 US 201514749843 A US201514749843 A US 201514749843A US 2016379883 A1 US2016379883 A1 US 2016379883A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Definitions
- the present invention is related to manufacturing Integrated Circuit (IC) chips, and more particularly, to forming through silicon vias (TSV) in IC chips.
- IC Integrated Circuit
- TSV through silicon vias
- TSV Through silicon vias
- IC Integrated Circuit
- TSV etching requires etching vias completely through a stack of back end of line (BEOL) layers to the silicon (Si) chip surface, sometimes considered or called a hard mask open (HMO), followed by a silicon specific reactive ion etch (RIE) to etch into and through the Si substrate.
- BEOL back end of line
- HMO hard mask open
- RIE silicon specific reactive ion etch
- a dielectric film residue remains at the bottom of the vias.
- This dielectric film residue acts as an etch mask at the bottom of the vias, inhibiting complete Si removal.
- the dielectric film residual can compromise TSV integrity causing mis-formed TSVs, e.g., during a TSV copper fill step. Mis-formed and/or shallow TSVs can be mis-shapen and lead to what is known as TSV “pistoning” when copper is annealed to form the TSVs.
- pistoning occurs when the metal (e.g., Cu) filled into a misformed and/or improperly filled TSVs (e.g., containing voids) shifts due to subsequent thermal processing, which often pushes upward, fracturing overlying films.
- etching typically is not uniform across a chip or wafer.
- the HMO via pattern may open completely towards the center of a chip, with varying levels of residue remaining in the vias around the periphery. In some cases across the chip etch depth variability may be as much as one micron ( ⁇ 2%) from center-to-edge.
- One approach to eliminating residue extends the HMO into the silicon, e.g., etching longer.
- opening the HMO may consume significant additional resist to guarantee fully etching into the Si for edge TSVs that normally under etch.
- This additional resist consumption can prevent further processing, i.e., Si RIE, that may be necessary to make long extensions into the silicon.
- Si RIE further processing
- Complete removal of the resist carries the risk of etching through top field dielectric layers and copper, wires and/or vias, which would have detrimental effects on the etch chamber.
- Integrated Circuit (IC) chip fabrication yield is improved
- TSV silicon via
- IC chip TSV are uniformly produced to minimize TSV defects for improved IC chip yield.
- Embodiments of the invention relate to a method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips.
- TSVs through silicon vias
- IC integrated circuit
- a TSV pattern on a stack of wiring layers on the surface of the IC chip identifies TSV locations.
- Etching the IC chip TSV pattern opens a cup shaped through hole through the stack to the silicon substrate at each TSV pattern location.
- the etched stack forms a TSV hard mask open (HMO) for the silicon substrate.
- Via through holes etched through the silicon substrate masked by the HMO are filled with conductor connecting IC circuits, e.g., to signal lines on the bottom of the chip.
- FIG. 1 shows an example of the cross section through an integrated circuit (IC) chip during through silicon via (TSV) formation, after hard mask open (HMO) definition using a prior definition step;
- FIG. 2 shows an example of a preferred method of forming through silicon vias (TSV) in integrated circuit (IC) chips according to preferred embodiments of the invention
- FIG. 3 shows a simple example of a silicon wafer with circuits on a circuit layer connected in MOL and BEOL layers;
- FIGS. 4A-B show an example of the two-step TSV etch to form TSV in a clear path through the wafer in an enlarged cross sectional example of area 4 in FIG. 2 ;
- FIG. 5 shows an example of a TSV formed through the wafer.
- FIG. 1 shows an example of the cross section through an integrated circuit (IC) chip 50 during through silicon via (TSV) 52 formation, after hard mask open (HMO) 54 definition using a prior definition step.
- IC integrated circuit
- TSV through silicon via
- HMO hard mask open
- FIG. 2 shows an example of a preferred method 100 of forming through silicon vias (TSV) in integrated circuit (IC) chips according to preferred embodiments of the invention.
- Fabrication begins in step 102 with providing a typical silicon wafer.
- chip circuits are defined on the silicon wafer.
- step 106 chip processing continues through normal middle of the line (MOL) and back end of the line (BEOL) steps.
- MOL normal middle of the line
- BEOL back end of the line
- a TSVs are formed in a two-step TSV etch, a preferred dielectric etch (hard mask open) 108 through all BEOL layers, followed by silicon Bosch etch 110 .
- Resulting through vias may exhibit a stair-step profile with a step at the HMO-silicon transition.
- step 112 the metal TSVs are formed.
- the present invention has application to forming so-called “blind” vias, where connection to the via end is made after formation.
- chip manufacturing continues 114 normally, e.g., forming a final metal layer above the TSV layer connecting the TSVs to chip circuits there beneath, passivating and dicing the completed chips.
- FIG. 3 shows a simple example of a silicon wafer 120 provided in step 102 of FIG. 2 with a circuit layer 122 with circuits formed in step 104 and after MOL and BEOL layers 124 in step 106 .
- TSVs are to be formed at multiple locations, e.g., at 130 , between the upper surface 126 to land on bottom metal 128 , e.g., off-chip signal pads.
- Wiring in the BEOL layers 124 may be oriented orthogonally to each other, e.g., oriented in the layer x-direction on one layer and the layer y-direction next layer (i.e., above or superimposed layer).
- Contact or via layers (not shown) between wiring layers connect each layer to the layer above and/or below.
- the wiring in the BEOL layers 124 is a suitable metal separated by a suitable dielectric, typically oxide (SiO 2 ).
- a suitable dielectric typically oxide (SiO 2 ).
- clear paths 130 are reserved through the wiring layers for TSV formation, and vias are formed by a deep oxide etch followed by a deep silicon etch.
- the exploded cross sectional example of area 4 in FIG. 3 shown in FIGS. 4A-B shows an example of the two-step TSV etch to form TSV in a clear path 130 through the wafer 120 .
- a simple mask pattern (not shown) is formed on the wafer surface 126 , e.g., using a typical photolithographic mask.
- through holes 132 are formed to define the HMO 134 in the BEOL layers.
- a plasma etch etches the BEOL (oxide) layers using a Nitrogen trifluoride (NF 3 ) as a primary etchant.
- the Nitrogen trifluoride etches slightly more dielectric from the center than at the periphery of the via through holes 132 .
- the photolithographic via mask may be removed from the surface 126 .
- through holes 132 patterned through the BEOL layers have concave or cup-shaped bottoms 136 .
- HMO etching continues to, and at least partially into, the silicon wafer 138 preferably 0.5 microns (0.5 ⁇ m) into the silicon 138 .
- the resulting cup-shaped through holes 132 are deepest at the center bottom, with through holes 132 depth decreasing radially outward toward the TSV sidewalls.
- the shallowest areas of each cup shaped through hole is towards the periphery and rounded at the edges.
- the subsequently completed through-hole bottoms are silicon and etch uniformly, i.e., without any dielectric material at the center which may act as a mask and create misformed TSVs.
- step 110 the underlying silicon wafer 138 is etched through the HMO 134 using a typical etchant to complete TSV through-holes.
- a typical etchant to complete TSV through-holes.
- a Bosch deep reactive ion etching (DRIE) is used to etch the silicon which exhibits a well-known effect of sidewall rippling, or so-called “scalloping.”
- DRIE deep reactive ion etching
- the HMO breakthrough forms a sidewall 140 discontinuity or “stair-step” 142 at the HMO to Bosch etch transition due to the concave or cup-shaped bottom resulting from the HMO etch chemistry. It should be noted that above the “stair-step” 142 TSV sidewalls 140 form relatively smooth, and below exhibit Bosch scalloping.
- FIG. 5 shows an example of a metal TSV 144 formed in step 112 .
- a typical is formed by lining the TSV through hole with a suitable metal liner material to prevent chemical interaction between the TSV metal and the various chip layers through which the TSV passes.
- the liner is followed by depositing metal on the wafer and planarizing the metal to the chip surface.
- the TSV metal is copper (Cu).
- TSVs formed according to the preferred embodiments form more uniformly, across chip and across wafer.
- a preferred HMO has vias with a cup-shaped or concave structure that ends, in part or in whole, within the Si substrate.
- all HMO material is completely removed from via through holes prior to silicon etch for clean, complete vias.
- TSV pistoning is reduced and/or eliminated for clean, well formed vias across chip and across wafer.
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Abstract
Description
- Field of the Invention
- The present invention is related to manufacturing Integrated Circuit (IC) chips, and more particularly, to forming through silicon vias (TSV) in IC chips.
- Background Description
- Through silicon vias (TSV) are used for a number of Integrated Circuit (IC) chip applications. Typically, TSVs are formed by etching vias through the chip and filling the vias with metal after chip circuits and wiring are nearly complete. TSV etching requires etching vias completely through a stack of back end of line (BEOL) layers to the silicon (Si) chip surface, sometimes considered or called a hard mask open (HMO), followed by a silicon specific reactive ion etch (RIE) to etch into and through the Si substrate.
- If the HMO via pattern is insufficiently opened, then a dielectric film residue remains at the bottom of the vias. This dielectric film residue acts as an etch mask at the bottom of the vias, inhibiting complete Si removal. In particular, the dielectric film residual can compromise TSV integrity causing mis-formed TSVs, e.g., during a TSV copper fill step. Mis-formed and/or shallow TSVs can be mis-shapen and lead to what is known as TSV “pistoning” when copper is annealed to form the TSVs. In particular, pistoning occurs when the metal (e.g., Cu) filled into a misformed and/or improperly filled TSVs (e.g., containing voids) shifts due to subsequent thermal processing, which often pushes upward, fracturing overlying films. Also, etching typically is not uniform across a chip or wafer. For example, the HMO via pattern may open completely towards the center of a chip, with varying levels of residue remaining in the vias around the periphery. In some cases across the chip etch depth variability may be as much as one micron (˜2%) from center-to-edge. These mis-formed TSVs and TSV variability has degraded chip yield significantly.
- One approach to eliminating residue extends the HMO into the silicon, e.g., etching longer. In this approach, opening the HMO may consume significant additional resist to guarantee fully etching into the Si for edge TSVs that normally under etch. This additional resist consumption can prevent further processing, i.e., Si RIE, that may be necessary to make long extensions into the silicon. Complete removal of the resist carries the risk of etching through top field dielectric layers and copper, wires and/or vias, which would have detrimental effects on the etch chamber.
- Thus, there is a need for well-formed TSVs, and more particularly, for forming a clean HMO via pattern without residual dielectric material remaining on silicon at the via bottom in the open vias.
- In an aspect of embodiments of the invention Integrated Circuit (IC) chip fabrication yield is improved;
- In another aspect of embodiments of the invention through silicon via (TSV) defects are minimized in IC chips;
- In yet another aspect of embodiments of the invention IC chip TSV pistoning is minimized;
- In yet another aspect of embodiments of the invention IC chip TSV are uniformly produced to minimize TSV defects for improved IC chip yield.
- Embodiments of the invention relate to a method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of the IC chip identifies TSV locations. Etching the IC chip TSV pattern opens a cup shaped through hole through the stack to the silicon substrate at each TSV pattern location. The etched stack forms a TSV hard mask open (HMO) for the silicon substrate. Via through holes etched through the silicon substrate masked by the HMO are filled with conductor connecting IC circuits, e.g., to signal lines on the bottom of the chip.
- The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
-
FIG. 1 shows an example of the cross section through an integrated circuit (IC) chip during through silicon via (TSV) formation, after hard mask open (HMO) definition using a prior definition step; -
FIG. 2 shows an example of a preferred method of forming through silicon vias (TSV) in integrated circuit (IC) chips according to preferred embodiments of the invention; -
FIG. 3 shows a simple example of a silicon wafer with circuits on a circuit layer connected in MOL and BEOL layers; -
FIGS. 4A-B show an example of the two-step TSV etch to form TSV in a clear path through the wafer in an enlarged cross sectional example ofarea 4 inFIG. 2 ; -
FIG. 5 shows an example of a TSV formed through the wafer. - Turning now to the drawings and, more particularly,
FIG. 1 shows an example of the cross section through an integrated circuit (IC)chip 50 during through silicon via (TSV) 52 formation, after hard mask open (HMO) 54 definition using a prior definition step. As is apparent from this example, although etching has removed all of the dielectric at the HMO viaperiphery 56 and extended intosilicon 58, an unwanted dielectric cap orblister 60 remains in the center of the HMO via. When the underlying silicon is etched and filled with metal, e.g., copper (Cu), theHMO blisters 60 tend to cause TSV through holes to misform due to incomplete etching at the bottoms of the BEOL stack during HMO. The misformed through holes can lead to Cu voiding in thesilicon 58, which may cause pistoning after high temperature copper anneal, which causes film delamination. These, TSVs defects all reduce chip manufacturing yield. -
FIG. 2 shows an example of apreferred method 100 of forming through silicon vias (TSV) in integrated circuit (IC) chips according to preferred embodiments of the invention. Fabrication begins instep 102 with providing a typical silicon wafer. Instep 104 chip circuits are defined on the silicon wafer. Instep 106 chip processing continues through normal middle of the line (MOL) and back end of the line (BEOL) steps. After BEOL, a TSVs are formed in a two-step TSV etch, a preferred dielectric etch (hard mask open) 108 through all BEOL layers, followed by silicon Boschetch 110. Resulting through vias may exhibit a stair-step profile with a step at the HMO-silicon transition. - Then, in
step 112, the metal TSVs are formed. It should be noted that although described herein for through hole vias, the present invention has application to forming so-called “blind” vias, where connection to the via end is made after formation. Once metal TSVs are complete, chip manufacturing continues 114 normally, e.g., forming a final metal layer above the TSV layer connecting the TSVs to chip circuits there beneath, passivating and dicing the completed chips. -
FIG. 3 shows a simple example of asilicon wafer 120 provided instep 102 ofFIG. 2 with acircuit layer 122 with circuits formed instep 104 and after MOL andBEOL layers 124 instep 106. TSVs are to be formed at multiple locations, e.g., at 130, between theupper surface 126 to land onbottom metal 128, e.g., off-chip signal pads. Wiring in theBEOL layers 124 may be oriented orthogonally to each other, e.g., oriented in the layer x-direction on one layer and the layer y-direction next layer (i.e., above or superimposed layer). Contact or via layers (not shown) between wiring layers connect each layer to the layer above and/or below. Typically, the wiring in theBEOL layers 124 is a suitable metal separated by a suitable dielectric, typically oxide (SiO2). Thus,clear paths 130 are reserved through the wiring layers for TSV formation, and vias are formed by a deep oxide etch followed by a deep silicon etch. - The exploded cross sectional example of
area 4 inFIG. 3 shown inFIGS. 4A-B shows an example of the two-step TSV etch to form TSV in aclear path 130 through thewafer 120. Preferably, a simple mask pattern (not shown) is formed on thewafer surface 126, e.g., using a typical photolithographic mask. Instep 108 throughholes 132 are formed to define theHMO 134 in the BEOL layers. Preferably, a plasma etch etches the BEOL (oxide) layers using a Nitrogen trifluoride (NF3) as a primary etchant. The Nitrogen trifluoride etches slightly more dielectric from the center than at the periphery of the via throughholes 132. Optionally, at this point the photolithographic via mask may be removed from thesurface 126. - Thus, via through
holes 132 patterned through the BEOL layers have concave or cup-shapedbottoms 136. HMO etching continues to, and at least partially into, thesilicon wafer 138 preferably 0.5 microns (0.5 μm) into thesilicon 138. Preferably, the resulting cup-shaped throughholes 132 are deepest at the center bottom, with throughholes 132 depth decreasing radially outward toward the TSV sidewalls. Moreover, the shallowest areas of each cup shaped through hole is towards the periphery and rounded at the edges. Because the cup-shapedbottoms 136 extend below theHMO 134BEOL layers 124, the subsequently completed through-hole bottoms are silicon and etch uniformly, i.e., without any dielectric material at the center which may act as a mask and create misformed TSVs. - In
step 110 theunderlying silicon wafer 138 is etched through theHMO 134 using a typical etchant to complete TSV through-holes. Preferably, a Bosch deep reactive ion etching (DRIE) is used to etch the silicon which exhibits a well-known effect of sidewall rippling, or so-called “scalloping.” The HMO breakthrough forms asidewall 140 discontinuity or “stair-step” 142 at the HMO to Bosch etch transition due to the concave or cup-shaped bottom resulting from the HMO etch chemistry. It should be noted that above the “stair-step” 142 TSV sidewalls 140 form relatively smooth, and below exhibit Bosch scalloping. -
FIG. 5 shows an example of a metal TSV 144 formed instep 112. A typical is formed by lining the TSV through hole with a suitable metal liner material to prevent chemical interaction between the TSV metal and the various chip layers through which the TSV passes. The liner is followed by depositing metal on the wafer and planarizing the metal to the chip surface. Preferably, the TSV metal is copper (Cu). - Advantageously, TSVs formed according to the preferred embodiments form more uniformly, across chip and across wafer. A preferred HMO has vias with a cup-shaped or concave structure that ends, in part or in whole, within the Si substrate. Thus, all HMO material is completely removed from via through holes prior to silicon etch for clean, complete vias. TSV pistoning is reduced and/or eliminated for clean, well formed vias across chip and across wafer.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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US7973413B2 (en) | 2007-08-24 | 2011-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate via for semiconductor device |
US8252682B2 (en) * | 2010-02-12 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for thinning a wafer |
US8970043B2 (en) * | 2011-02-01 | 2015-03-03 | Maxim Integrated Products, Inc. | Bonded stacked wafers and methods of electroplating bonded stacked wafers |
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