US20160378590A1 - Controller controlling semiconductor memory device and operating method thereof - Google Patents
Controller controlling semiconductor memory device and operating method thereof Download PDFInfo
- Publication number
- US20160378590A1 US20160378590A1 US14/754,014 US201514754014A US2016378590A1 US 20160378590 A1 US20160378590 A1 US 20160378590A1 US 201514754014 A US201514754014 A US 201514754014A US 2016378590 A1 US2016378590 A1 US 2016378590A1
- Authority
- US
- United States
- Prior art keywords
- read
- command
- commands
- memory device
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1016—Error in accessing a memory location, i.e. addressing error
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
Definitions
- Various exemplary embodiments relate generally to an electronic device and, more particularly, to a controller controlling a semiconductor memory device and an operating method thereof.
- Semiconductor memory devices are made of semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (Inp). Semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices.
- Volatile memory devices lose stored data when powered off. Examples of volatile memory devices include Static RAM (SRAM), Dynamic RAM (DRAM) and Synchronous DRAM (SDRAM). Non-volatile memory devices retain stored data regardless of power on/off conditions. Examples of non-volatile memory include Read Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM) flash memory, Phase-change Random Access Memory (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM) and Ferroelectric RAM (FRAM). Flash memories are classified into NOR-type memories and NAND-type memories.
- ROM Read Only Memory
- MROM Mask ROM
- PROM Programmable ROM
- EPROM Erasable Programmable ROM
- EEPROM Electrically Erasable and Programmable ROM
- Flash memories are classified into NOR-type memories and NAND-type memories.
- a semiconductor memory device controller may generate commands at the request of a host and perform the generated commands.
- the controller may include a command queue to store commands.
- the command queue may be defined in a memory unit such as a RAM. Commands stored in the command queue may be sequentially output to the semiconductor memory device.
- An embodiment is directed to a controller having an improved operating time and an operating method thereof.
- An operating method for controlling a semiconductor memory device may include storing a plurality of read commands in a command queue managed on first-in first-out basis; providing one of the plurality of read commands to the semiconductor memory device; determining pass or fail of the provided read command based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting the remaining read commands in the command queue when the provided read command passes.
- the semiconductor memory device may include a plurality of pages, and the plurality of read commands may be commands for identifying data stored in one of the plurality of pages.
- the determining may include performing ECC decoding on the read data, and the provided read command may pass when the ECC decoding passes.
- the operating method may further include repeating the providing and determining with the remaining read commands when the provided read command fails.
- the operating method may further include generating a plurality of parameter setting commands to change a setting value of the semiconductor memory device, the plurality of parameter setting commands being stored in the command queue, along with the plurality of read commands; and providing one of the plurality of parameter setting commands to the semiconductor memory device.
- the aborting may include aborting remaining parameter setting commands in the command queue when the provided read command passes.
- the setting value may correspond to a voltage applied to a word of the semiconductor memory device line during a read operation of the semiconductor memory device.
- the command queue may include memory space from a head address to a tail address, and the plurality of read commands may be stored in memory space from a start address to an end address between the head and tail addresses.
- the aborting may include generating a shadow pointer pointing an address corresponding to first one of the remaining read commands when the provided read command passes; and erasing the remaining read commands pointed by the shadow pointer while moving the shadow pointer from a current address to a next address until the shadow pointer points to the end address.
- the aborting may include sequentially dropping the remaining read commands between the start address and the end address.
- the aborting may erase the remaining read commands stored in memory space between a start address and an end address in the command queue.
- the determining may determine whether the provided read command fails when ECC decoding fails on one or more code words included in the read data.
- the ECC decoding may be performed on one or more code words, on which the ECC decoding fails in the read data previously provided from the semiconductor memory device in response to previously provided read command.
- a controller controlling a semiconductor memory device may include a command queue managed on first-in first-out basis; a command generation unit suitable for storing a plurality of read commands in the command queue; a memory control unit suitable for: providing one of the plurality of read commands to the semiconductor memory device; and determining pass or fail of the provided read command based on read data, which is provided from the semiconductor memory device in response to the provided read command; and a command management unit suitable for aborting remaining read commands when the provided read command passes.
- the semiconductor memory device may include a plurality of pages, and the plurality of read commands may be for identifying data stored in one of the plurality of pages.
- the memory control unit may include a data buffer suitable for storing the read data provided from the semiconductor memory device in response to the provided read command; an error correction block suitable for performing ECC decoding on the read data in units of single code words; a decoding status table suitable for storing pass or fail information of the ECC decoding on each of code words included in the read data; and a multiplexing block suitable for providing the read data in single code word units from the data buffer to the error correction block; and a memory controller suitable for: controlling the multiplexing block to provide the error correction block with one or more code words, on which the ECC decoding fails in the read data previously provided from the semiconductor memory device in response to previously provided read command, by referring to the decoding status table; and updating the fail information stored in the decoding status table according to result of the ECC decoding.
- the memory control unit may determine failures in the provided read command when ECC decoding fails on one or more code words included in the read data.
- An operating method for controlling a semiconductor memory device including a plurality of pages may include storing a plurality of commands for identifying data of a selected page in a command queue managed on first-in first-out basis; providing one of the plurality of commands to the semiconductor device; repeating the providing with remaining read commands when the provided read command fails; and aborting remaining read commands when the provided read command passes.
- FIG. 1 is a block diagram illustrating a memory system according to an embodiment
- FIG. 2 is a block diagram illustrating a semiconductor memory device shown in FIG. 1 ;
- FIG. 3 is a block diagram illustrating a memory cell array shown in FIG. 2 ;
- FIG. 4 is a block diagram illustrating a controller shown in FIG. 1 according to an embodiment
- FIG. 5 is a flowchart illustrating an operating method of a controller according to an embodiment
- FIG. 6 is a conceptual diagram illustrating a command queue
- FIG. 7 is a flowchart illustrating an embodiment of step S 150 shown in FIG. 5 ;
- FIG. 8 is a conceptual diagram illustrating an embodiment shown in FIG. 7 ;
- FIG. 9 is a flowchart illustrating another embodiment of step S 150 shown in FIG. 5 ;
- FIG. 10 is a conceptual diagram of the embodiment shown in FIG. 9 ;
- FIG. 11 is a block diagram illustrating a controller shown in FIG. 1 according to another embodiment
- FIG. 12 is a conceptual diagram illustrating first and second command queues shown in FIG. 11 ;
- FIG. 13 is a diagram illustrating a memory control unit shown in FIGS. 4 and 11 ;
- FIG. 14 is a conceptual diagram illustrating code words included in read data
- FIG. 15 is a conceptual diagram illustrating a decoding status table shown in FIG. 13 ;
- FIG. 16 is a block diagram illustrating an embodiment of a controller shown in FIGS. 4 and 11 ;
- FIG. 17 is a block diagram illustrating an application example of a memory system shown in FIG. 1 .
- FIG. 1 is a block diagram illustrating a memory system 50 according to an embodiment.
- the memory system 50 may include a semiconductor memory device 100 and a controller 200 .
- the semiconductor memory device 100 may be controlled by the controller 200 .
- the semiconductor memory device 100 may include a memory cell array 110 and a peripheral circuit 120 driving the memory cell array 110 .
- the memory cell array 110 may include a plurality of non-volatile memory cells.
- the peripheral circuit 120 may be controlled by the controller 200 . Under the control of the controller 200 , the peripheral circuit 120 may program data into the memory cell array 110 , read the data from the memory cell array 110 , and erase the data from the memory cell array 110 .
- a read operation and a program operation of the semiconductor memory device 100 may be performed in units of pages.
- An erase operation of the semiconductor memory device 100 may be performed in units of memory blocks.
- the peripheral circuit 120 may receive a command indicating a program operation, a physical address and write data from the controller 200 .
- a single memory block and a single page included therein may be specified by the physical address.
- the peripheral circuit 120 may program the write data into the corresponding page.
- the peripheral circuit 120 may receive a command (hereinafter, read command) indicating the read operation and a physical address from the controller 200 .
- a command hereinafter, read command
- a single memory block and a single page included therein may be specified by the physical address.
- the peripheral circuit 120 may read data from the corresponding page and output the read data (hereinafter, read data) to the controller 200 .
- the peripheral circuit 120 may receive a command indicating the erase operation and a physical address from the controller 200 .
- the physical address may specify a single memory block.
- the peripheral circuit 120 may erase data of the memory block corresponding to the physical address.
- the semiconductor memory device 100 may be a flash memory device.
- the controller 200 may control the general operation of the semiconductor memory device 100 .
- the controller 200 may access the semiconductor memory device 100 at the request of a host.
- the controller 1200 may control a read operation, a program operation, an erase operation, and/or a background operation of the semiconductor memory device 100 .
- the controller 200 may provide an interface between the semiconductor memory device 100 and the host.
- the controller 200 may drive firmware for controlling the semiconductor memory device 100 .
- the controller 200 may provide a read command to the semiconductor memory device 100 in order to identify data of a page corresponding to the read request.
- the controller 200 may convert a logical block address included in the read request into a physical block address.
- the controller 200 may function as a flash translation layer (FTL).
- FTL flash translation layer
- the controller 200 may provide the generated physical address, along with the read command, to the semiconductor memory device 100 .
- the semiconductor memory device 100 may transfer the read data to the controller 200 .
- the controller 200 may determine whether an error is included in the read data.
- the controller 200 may decode the read data according to an error correction code.
- error correction codes such as Bose, Chaudhri, Hocquenghem (BCH) codes, Hamming codes, Reed Solomon codes, low density parity check (LDPC) codes, may be used.
- BCH Hocquenghem
- Reed Solomon codes LDPC low density parity check
- LDPC low density parity check
- Decoding success may mean that the corresponding read command passes, and decoding failure may mean that the corresponding read command fails.
- the controller 200 may output the error-corrected read data to the host.
- the controller 200 may re-transfer the read command to the semiconductor memory device 100 .
- FIG. 2 is a block diagram illustrating the semiconductor memory device 100 described with reference to FIG. 1 .
- FIG. 3 is a block diagram illustrating the memory cell array 110 shown in FIG. 2 .
- the semiconductor memory device 100 may include the memory cell array 110 and the peripheral circuit 120 .
- the memory cell array 110 may include a plurality of memory cells.
- the plurality of memory cells may be coupled to an address decoder 121 through row lines RL and coupled to a read and write circuit 123 through bit lines BL.
- the memory cell array 110 may include a plurality of memory blocks BLK 1 to BLKz.
- the first to z th memory blocks BLK 1 to BLKz may be coupled in common to first to m th bit lines BL 1 to BLm.
- the first to m th bit lines BL 1 to BLm may form the bit lines BL shown in FIG. 2 .
- Each of the memory blocks BLK 1 to BLKz may form an erase unit.
- FIG. 3 elements included in one (BLK 1 ) of the memory blocks BLK 1 to BLKz are illustrated and elements included in the remaining memory blocks BLK 2 to BLKz are omitted for clarity.
- Each of the remaining memory blocks BLK 2 to BLKz may be configured in substantially the same manner as the first memory block BLK 1 .
- the memory block BLK 1 may include a plurality of cell strings CS 1 to CSm.
- the first to m th cell strings CS 1 to CSm may be coupled to the first to m th bit lines BL 1 to BLm, respectively.
- Each of the cell strings CS 1 to CSm may include a drain selection transistor DST, a plurality of memory cells MC 1 to MCn coupled in series, and a source selection transistor SST.
- the drain selection transistor DST may be coupled to a drain selection line DSL 1 .
- the first to n th memory cells MC 1 to MCn may be coupled to first to n th word lines WL 1 to WLn, respectively.
- the source selection transistor SST may be coupled to a source selection line SSL 1 .
- a drain side of the drain selection transistor DST may be coupled to a corresponding bit line.
- a source side of the source selection transistor SST may be coupled to a reference voltage node.
- a source side of the source selection transistor SST may be coupled to a common source line (not illustrated). The common source line may be biased to a reference voltage.
- Memory cells coupled to a single word line of the first to m th cell strings CS 1 to CSm may form a single page pg. Therefore, the memory block BLK 1 may include a plurality of pages.
- the drain selection line DSL 1 , the first to n th word lines WL 1 to WLn and the source selection line SSL 1 may be included in the row lines RL shown in FIG. 2 .
- the drain selection line DSL 1 , the first to n th word lines WL 1 to WLn and the source selection line SSL 1 may be controlled by the address decoder 121 .
- the first to m th bit lines BL 1 to BLm may be controlled by the read and write circuit 123 .
- the peripheral circuit 120 may include the address decoder 121 , a voltage generator 122 , the read and write circuit 123 , an input/output buffer 124 and a control logic 125 .
- the address decoder 121 may be coupled to the memory cell array 110 through the row lines RL.
- the address decoder 121 may be controlled by the control logic 125 .
- the address decoder 121 may receive a physical address PA through the control logic 125 .
- the read operation of the semiconductor memory device 100 may be performed in units of pages (see reference character pg in FIG. 3 ).
- the physical address PA received during the read operation may include a block address and a row address.
- the address decoder 121 may decode the block address of the received physical address PA.
- the address decoder 121 may select one of the memory blocks BLK 1 to BLKz according to the decoded block address.
- the address decoder 121 may decode the row address of the received physical address PA and select one word line in a selected memory block. Thus, a single page may be selected.
- the address decoder 121 may apply a read voltage from the voltage generator 122 to the selected word line and apply a pass voltage from the voltage generator 122 to unselected word lines.
- the voltage generator 122 may be controlled by the control logic 125 .
- the voltage generator 122 may generate an internal power voltage by using an external power voltage provided to the semiconductor memory device 100 .
- the voltage generator 122 may generate the internal power voltage by regulating the external power voltage.
- the internal power voltage may be provided to the address decoder 121 , the read and write circuit 123 , the input/output buffer 124 and the control logic 125 and used as an operation voltage of the semiconductor memory device 100 .
- the voltage generator 122 may generate a plurality of voltages by using at least one of the external power voltage and the internal power voltage.
- the voltage generator 122 may include a plurality of pumping capacitors receiving the internal power voltage and generate a plurality of voltages by selectively activating the plurality of pumping capacitors under the control of the control logic 125 .
- the voltage generator 122 may generate a read voltage and a pass voltage having a higher voltage level than the read voltage during the read operation. The generated voltages may be provided to the address decoder 121 .
- the read and write circuit 123 may be coupled to the memory cell array 110 through the bit lines BL.
- the read and write circuit 123 may be controlled by the control logic 125 .
- the read and write circuit 123 may read and store read data DATA from the page of the selected word line of the memory cell array 110 during the read operation.
- the read data DATA may be transferred to the input/output buffer 124 through data lines DL.
- the input/output buffer 124 may be coupled to the read and write circuit 123 through the data lines DL.
- the input/output buffer 124 may be controlled by the control logic 125 .
- the input/output buffer 124 may externally output the read data DATA transferred from the read and write circuit 123 through the data lines DL.
- the control logic 125 may control the general operation of the semiconductor memory device 100 .
- the control logic 125 may receive a command CMD and the physical address PA.
- the command CMD may be a read command.
- the command CMD may indicate the program operation.
- the command CMD may indicate the erase operation.
- the control logic 125 may control the address decoder 121 , the voltage generator 122 , the read and write circuit 123 and the input/output buffer 124 in response to the received command CMD.
- a parameter setting command to change a setting value of the semiconductor memory device 100 may be received as the command CMD.
- the parameter setting command may include information to change the read voltage.
- the control logic 125 may control the voltage generator 122 to change the read voltage in response to the parameter setting command.
- the parameter setting command may include information to change the pass voltage.
- a threshold voltage distribution of memory cells included in each page may be shifted for various reasons. It is widely known that data of a selected word line is identified as different read data by controlling a read voltage. In other words, by applying an inappropriate read voltage, many error bits may be included in read data. By controlling the read voltage, the error bits included in the read data may be reduced.
- the controller 200 shown in FIG. 1 , may control the read voltage by providing the parameter setting command to the semiconductor memory device 100 , and receive read data of the corresponding page again by transferring the read command again.
- FIG. 4 is a block diagram illustrating the controller 200 described with reference to FIG. 1 according to an embodiment.
- the controller 200 may include a memory unit 210 , a command generation unit 220 , a memory control unit 230 , and a command management unit 240 .
- the memory unit 210 may be coupled to the command generation unit 220 , the memory control unit 230 , and the command management unit 240 .
- the memory unit 210 may provide a storage space in the controller 200 .
- a command queue CQ and a status information queue SQ may be defined. Both the command queue CQ and the status information queue SQ may be managed using a first-in first-out basis.
- Each of the command queue CQ and the status information queue SQ may include a head address HA and a tail address TA.
- the command generation unit 220 may be coupled to the memory unit 210 and the command management unit 240 .
- the command generation unit 220 may be controlled by the command management unit 240 .
- the command generation unit 220 may generate a command corresponding to the request under the control of the command management unit 240 .
- the command generation unit 220 may function as the flash translation layer (FTL).
- the command generation unit 220 may transform a logical block address included in the request from the host into a physical block address.
- the command generation unit 220 may store the generated physical address in connection with the corresponding command in the memory unit 210 .
- the physical address stored in the memory unit 210 may be transferred to the semiconductor memory device 100 , along with the corresponding command, by the memory control unit 230 .
- the command generation unit 220 may generate a plurality of commands for identifying data of a page (hereinafter, selected page) corresponding to the read request, and store the generated commands in the command queue CQ defined in the memory unit 210 .
- the command generation unit 220 may repeat generating of the read command and the parameter setting command, and input the generated read commands and parameter setting commands in the command queue CQ.
- the command generation unit 220 may generate a plurality of commands for identifying data of the selected page in response to the read request.
- the generated commands may be sequentially provided to the semiconductor memory device 100 .
- the command generation unit 220 may firstly generate a single read command in response to the read request.
- the read command and the corresponding physical address may be provided to the semiconductor memory device 100 .
- Read data may be received from the semiconductor memory device 100 .
- the command generation unit 220 may generate a plurality of commands for identifying the data of the selected page under the control of the command management unit 240 .
- the memory control unit 230 may be coupled to the memory unit 210 and the command management unit 240 .
- the memory control unit 230 may include an ECC block 235 .
- the memory control unit 230 may be controlled by the command management unit 240 .
- the memory control unit 230 may output a command from the command queue CQ under the control of the command management unit 240 , and provide the output command to the semiconductor memory device 100 .
- the semiconductor memory device 100 may receive the read command RCMD.
- the semiconductor memory device 100 may provide read data to the controller 200 in response to the read command RCMD.
- the read data may include data bits stored in a single page.
- the ECC block 235 of the memory control unit 230 may decode the read data through an error correction code to correct an error in the read data.
- the memory control unit 230 may store status information indicating that the read command RCMD passes in the status information queue SQ defined in the memory unit 210 .
- the memory control unit 230 may store status information indicating that the read command RCMD fails in the status information queue SQ.
- the semiconductor memory device 100 may change an internal setting value.
- the next read command RCMD may be output from the command queue CQ on a first-in first-out basis.
- the memory control unit 230 may provide the next read command RCMD to the semiconductor memory device 100 .
- the semiconductor memory device 100 may provide second read data to the controller 200 in response to the next read command RCMD.
- the second read data may be temporarily stored in the memory control unit 230 or the memory unit 210 .
- the ECC block 235 of the memory control unit 230 may decode the second read data through the error correction code. According to a decoding result, the memory control unit 230 may store second status information in the status information queue SQ.
- the controller 200 may sequentially provide the read commands and the parameter setting commands stored in the command queue CQ to the semiconductor memory device 100 , receive the corresponding read data, and decode the received read data.
- Information indicating whether the read data is successfully decoded or whether the corresponding read command passes or fails may be stored as status information in the status information queue SQ.
- the command management unit 240 may control the memory unit 210 , the command generation unit 220 and the memory control unit 230 .
- the command management unit 240 may control the command generation unit 220 to generate a plurality of commands in response to the read request from the host.
- the command management unit 240 may control the memory control unit 230 to transfer the command stored in the command queue CQ to the semiconductor memory device 100 .
- the command management unit 240 may manage the command queue CQ with reference to the status information stored in the status information queue SQ.
- a start address and an end address of the command queue CQ may indicate locations of the plurality of commands for identifying the data of the selected page in the command queue CQ.
- the start address and the end address may be defined between the head address HA and the tail address TA of the command queue CQ.
- the command generation unit 220 may provide the start address and the end address to the command management unit 240 .
- the command management unit 240 may identify the start address and the end address.
- the command management unit 240 may output the error-corrected read data from the memory control unit 230 to the host. According to an embodiment, when one of the plurality of read commands passes, the command management unit 240 may abort the remaining read commands and the remaining parameter setting commands remaining in the command queue CQ, or the read commands and the parameter setting commands following the passed read command on a first-in first-out basis.
- the command management unit 240 may determine whether the next read command RCMD passes. The command management unit 240 may determine whether the next read command RCMD passes on the basis of the next status information output from the status information queue SQ. As a result of the determination, the command management unit 240 may abort the remaining read commands and the remaining parameter setting commands remaining in the command queue CQ. For example, when the next read command RCMD passes, the read commands and the parameter setting commands following the next read command RCMD on the first-in first-out basis may be aborted.
- the command generation unit 220 generates a single read command to identify data of a selected page, and generates other commands, e.g., a parameter setting command and another read command, according to whether the read command fails.
- the command generation unit 220 generates a parameter setting command and a next read command to identify the data of the selected page again.
- the command generation unit 220 needs to stop the operation that is currently being performed.
- the command management unit 240 may transfer an interrupt signal to the command generation unit 220 , and the command generation unit 220 may stop the currently performed operation in response to the interrupt signal. Therefore, operating time of the command generation unit 220 and the controller 200 may be increased.
- the command generation unit 220 may search another command, e.g., the program command, in the command queue CQ. Subsequently, the command generation unit 220 may abort the searched command, or add another command for identifying the data of the selected page to an address previous to the address of the searched command. Therefore, operating time of the command generation unit 220 and the controller 200 may be increased.
- the command generation unit 220 may generate a plurality of commands for identifying the data of the selected page and store the generated commands in the command queue CQ.
- the command generation unit 220 may perform other operations. Therefore, operating time of the command generation unit 220 and the controller 200 may be improved.
- FIG. 5 is a flowchart illustrating an operating method of the controller 200 according to an embodiment.
- a plurality of read commands and a plurality of parameter setting commands may be generated.
- the read commands and the parameter setting commands may be for identifying the data of a selected page.
- the command generation unit 220 may generate the read commands and the parameter setting commands for identifying the data of the selected page under the control of the command management unit 240 .
- the generated commands may be stored in the command queue CQ.
- step S 130 while the read commands and the parameter setting commands are sequentially provided to the semiconductor memory device 100 , it may be determined whether each of the read commands passes.
- the memory control unit 230 may receive read data corresponding to the read command RCMD from the semiconductor memory device 100 .
- the memory control unit 230 may decode the read data and store information on whether the read data is successfully decoded as first status information in the status information queue SQ.
- the semiconductor memory device 100 may change an internal setting value.
- the memory control unit 230 may receive read data corresponding to the next read command RCMD from the semiconductor memory device 100 .
- the memory control unit 230 may decode the corresponding read data and store information on whether the corresponding read data is successfully decoded as second status information in the status information queue SQ.
- the first and second status information may be stored in the status information queue SQ on a first-in first-out basis.
- the command management unit 240 may monitor the status information queue SQ.
- the command management unit 240 may check the status information queue SQ and determine whether each read command passes.
- the memory control unit 230 which transfers the read commands and the parameter setting commands to the semiconductor memory device 100 and stores the status information in the status information queue SQ, and the command management unit 240 which checks the status information queue SQ and determines whether each command passes may perform these operations in parallel.
- step S 150 when one of the read commands passes, step S 150 may be performed.
- all of the read commands fail (“NO” at step S 140 ) it may mean that all of the commands generated at step S 110 are provided to the semiconductor memory device 100 and the identifying of the data of the selected page fails despite all of the read commands and parameter setting commands.
- step S 150 the remaining read commands and parameter setting commands in the command queue CQ may be aborted, or the read commands and the parameter setting commands following the passed read command on first-in first-out basis may be aborted.
- FIG. 6 is a conceptual diagram illustrating the command queue CQ.
- the command queue CQ may store commands between the head address HA and the tail address TA.
- the head address HA may indicate the location of the first command CMD 1 in the command queue CQ.
- the last command CMDq of the command queue CQ may be specified by the tail address TA.
- the command queue CQ may be managed on first-in first-out basis.
- the commands of the head address HA may be firstly input to the command queue CQ and output to the semiconductor memory device 100 .
- the commands of the tail address TA may be lastly input to the command queue CQ and output to the semiconductor memory device 100 .
- the commands CMD 1 to CMDp, RCMD 1 to RCMDx, PST 1 to PSTy, and CMDp+1 to CMDq generated by the command generation unit 220 may be stored in the command queue CQ in order of input to the command queue CQ.
- the commands stored in the command queue CQ may have their own addresses of the command queue CQ.
- the command generation unit 220 may generate first to x th read commands RCMD 1 to RCMDx and first to y th parameter setting commands PST 1 to PSTy for identifying the data of the selected page.
- the generated read commands RCMD 1 to RCMDx and parameter setting commands PST 1 to PSTy may be stored in the command queue CQ in order of input to the command queue CQ.
- the read commands RCMD 1 to RCMDx and the parameter setting commands PST 1 to PSTy may be sequentially stored between the start address SA of the command queue CQ and the end address EA of the command queue CQ.
- the command generation unit 220 may notify the command management unit 240 of the start address SA of the command queue CQ and the end address EA of the command queue CQ.
- the command management unit 240 may recognize that the commands for identifying the data of the selected page are located between the start address SA of the command queue CQ and the end address EA of the command queue CQ.
- FIG. 6 illustrates the read commands and the parameter setting commands alternately arranged in the command queue CQ.
- the first read command RCMD 1 , the first parameter setting command PST 1 , the second read command RCMD 2 , the second parameter setting command PST 2 . . . the y th parameter setting command PSTy, and the x th read command RCMDx may be sequentially arranged in the command queue CQ.
- the command generation unit 220 may arrange different numbers and orders of read commands and parameter setting commands in the command queue CQ.
- the read commands and the parameter setting commands may be arranged in the command queue CQ according to an implementation method of the command generation unit 220 and an implementation method of the ECC block 235 .
- the command generation unit 220 may generate other commands CMDp+1 to CMDq.
- the generated p+1 th to q th commands CMDp+1 to CMDq may be stored in the command queue CQ in a sequential manner from the end address EA.
- the first to p th commands CMD 1 to CMDp and the p+1 th to q th commands CMDp+1 to CMDq may not be the commands for identifying the data of the selected page. Under this condition, the commands CMD 1 to CMDq may not be limited. For example, each of the commands CMD 1 to CMDq may be one of commands for program operations, erase operations, and other read operations in response to another read request.
- All of the commands stored in the command queue CQ may be output on a first-in first-out basis.
- the memory control unit 230 may sequentially increase an operation pointer OP from the head address HA and output a command pointed by the operation pointer OP.
- the commands RCMD 1 to RCMDx and PST 1 to PSTy for identifying the data of the selected page may be output.
- FIG. 6 illustrates the operation pointer OP pointing to the first read command RCMD 1 .
- the first read command RCMD 1 may be output.
- the semiconductor memory device 100 may transfer the first read data corresponding to the first read command RCMD 1 to the controller 200 .
- the first parameter setting command PST 1 may be output.
- the semiconductor memory device 100 may change an internal setting value in response to the first parameter setting command PST 1 .
- the second read command RCMD 2 may be output.
- the semiconductor memory device 100 may transfer the second read data corresponding to the second read command RCMD 2 to the controller 200 .
- the command management unit 240 may abort the remaining commands, among the commands RCMD 1 to RCMDx and PST 1 to PSTy between the start address SA and the end address EA.
- the remaining commands RCMD 3 to RCMDx and PST 2 to PSTy following the first read command RCMD 1 between the start address SA and the end address EA may be aborted.
- FIG. 7 is a flowchart illustrating an embodiment of step S 150 described with reference to FIG. 5 .
- the command management unit 240 may define a shadow pointer SP between the start address SA and the end address EA when it is detected that one of the read commands in the command queue CQ passes.
- the command management unit 240 may inquire with the memory control unit 230 the location of the operation pointer OP, and define the operation pointer OP as the shadow pointer SP.
- the command queue CQ stores the remaining read commands and the remaining parameter setting commands between the address indicated by the shadow pointer SP and the end address EA. That is, the read commands and the parameter setting commands following the passed read command on first-in first-out basis may be stored between the address indicated by the shadow pointer SP and the end address EA in the command queue CQ.
- the command management unit 240 may erase a command of the address indicated by the shadow pointer SP.
- the command management unit 240 may move the shadow pointer SP to the next address in the command queue CQ.
- the command management unit 240 may abort the command of the end address EA and stop the cancellation of the remaining read commands and the remaining parameter setting commands.
- steps S 320 to S 340 may be repeated. In other words, steps S 320 to S 340 may be repeated until the shadow pointer SP indicates the end address EA.
- step S 330 may be performed before step S 320 .
- FIG. 8 is a conceptual diagram of an embodiment shown in FIG. 7 .
- the first to p th commands CMD 1 to CMDp may be output first.
- the memory control unit 230 may output the command pointed to by the operation pointer OP while sequentially moving the operation pointer OP to the next address from the head address HA.
- FIG. 8 illustrates the output commands with hatched lines.
- the memory control unit 230 may output the first read command RCMD 1 , the first parameter setting command PST 1 and the second read command RCMD 2 while moving the operation pointer OP to the next address.
- the shadow pointer SP may be defined between the start address SA and the end address EA when it is detected that one of the read commands in the command queue CQ passes.
- the command management unit 240 may inquire with the memory control unit 230 the location of the operation pointer OP, and define the shadow pointer SP so that the shadow pointer SP may point to the address of the operation pointer OP.
- FIG. 8 illustrates the operation pointer OP pointing to the address of the second read command RCMD 2 . Subsequently, the command management unit 240 may repeat erasing of the command of the address indicated by the shadow pointer SP and move the shadow pointer SP to the next address until the shadow pointer SP indicates the end address EA.
- the command management unit 240 may control the memory unit 210 to erase the commands stored at the address indicated by the shadow pointer SP. Therefore, the remaining read commands RCMD 3 to RCMDx and the remaining parameter setting commands PST 2 to PSTy in the command queue CQ may be aborted.
- the remaining command may not be output from the command queue CQ, and the remaining read commands and the remaining parameter setting commands may be aborted. Therefore, the remaining commands may be aborted more promptly.
- FIG. 9 is a flowchart illustrating another embodiment of step S 150 described with reference to FIG. 5 .
- the command management unit 240 may sequentially output from the command queue CQ the remaining commands following the passed read command on first-in first-out basis between the start address SA and the end address EA. Since the command queue CQ is operated on a first-in first-out basis, the output commands may be erased from the command queue CQ.
- the command management unit 240 may drop the output commands.
- FIG. 10 is a conceptual diagram of an embodiment shown in FIG. 9 .
- the first to p th commands CMD 1 to CMDp may be output.
- FIG. 10 illustrates the output commands as hatched lines.
- the operation pointer OP may reach the start address SA.
- the memory control unit 230 may output the first read command RCMD 1 , the first parameter setting command PST 1 and the second read command RCMD 2 while moving the operation pointer OP from the start address SA to the next address.
- the command management unit 240 may inquire with the memory control unit 230 to determine the location of the operation pointer OP, and sequentially output the remaining commands following the passed first or second read command RCMD 1 or RCMD 2 on first-in first-out basis between the start address SA and the end address EA while moving the operation pointer OP to the next address in the command queue CQ.
- FIG. 10 exemplarily illustrates the operation pointer OP pointing to the second read command RCMD 2 .
- the commands of the address indicated by the operation pointer OP may be sequentially output by the command management unit 240 .
- the output commands which follow the passed read command on the first-in first-out basis and are indicated by the operation pointer OP, may be dropped.
- the command management unit 240 may drop the sequentially output read commands. In other words, the sequentially output read command following the passed read command on the first-in first-out basis may be ignored. Thus, the remaining read commands and the remaining parameter setting commands in the command queue CQ may be aborted.
- the remaining commands may also be output from the command queue CQ without the cancellation process in the command queue CQ as described with reference to FIGS. 7 and 8 .
- the design of the command management unit 240 may be simplified.
- FIG. 11 is a block diagram illustrating the controller 200 shown in FIG. 1 according to another embodiment.
- FIG. 12 is a conceptual diagram of first and second command queues CQ 1 and CQ 2 shown in FIG. 11 .
- the controller 300 may include a memory unit 310 , the command generation unit 220 , the memory control unit 230 , and the command management unit 240 .
- the memory unit 310 may include the first command queue CQ 1 , the second command queue CQ 2 and the status information queue SQ.
- the first command queue CQ 1 may include a first head address HA 1 and a first tail address TA 1 .
- the second command queue CQ 2 may include a second head address HA 2 and a second address TA 2 .
- the memory unit 310 may store the plurality of commands RCMD 1 to RCMDx and PST 1 to PSTy for identifying the data of the selected page in the first command queue CQ 1 .
- the command generation unit 220 may store other commands CMD 1 to CMDq in the second command queue CQ 2 .
- the command generation unit 220 may store a command corresponding to a request from the host in the second command queue CQ 2 .
- the commands CMD 1 to CMDq stored in the second command queue CQ 2 may be sequentially output from the second head address HA 2 and provided to the semiconductor memory device 100 .
- the p th command CMDp may correspond to the command corresponding to the read request from the host.
- the p th command CMDp and a physical address indicating the selected page may be provided to the semiconductor memory device 100 .
- the semiconductor memory device 100 may transfer the corresponding read data to the controller 300 .
- the memory control unit 230 may decode the read data and store information on whether the read data is successfully decoded in the status information queue SQ.
- the command management unit 240 may control the command generation unit 220 to generate the commands RCMD 1 to RCMDx and PST 1 to PSTy for identifying the data of the selected page, and input the generated commands RCMD 1 to RCMDx and PST 1 to PSTy to the separate command queue CQ 1 .
- the operation pointer OP may be locked to the current address in the second command queue CQ 2 , and the commands RCMD 1 to RCMDx and PST 1 to PSTy in the first command queue CQ 1 may be output on a first-in first-out basis.
- the commands RCMD 1 to RCMDx and PST 1 to PSTy for identifying the data of the selected page may be stored in the first command queue CQ 1 .
- the remaining read commands and the remaining parameter setting commands following the passed read command on the first-in first-out basis may be erased from the first command queue CQ 1 for the cancellation.
- the first command queue CQ 1 may be initialized for the cancellation. Since the commands RCMD 1 to RCMDx and PST 1 to PSTy for identifying the data of the selected page are stored in the first command queue CQ 1 , the remaining commands may be aborted without managing the start address SA and the end address EA described with reference to FIG. 6 . Therefore, the design of the command management unit 240 may be simplified.
- FIG. 13 is a view illustrating the memory control unit 230 described with reference to FIGS. 4 and 11 .
- FIG. 14 is a conceptual diagram illustrating code words CW 1 to CW 4 included in read data.
- FIG. 15 is a conceptual diagram illustrating a decoding status table DT shown in FIG. 13 .
- the memory control unit 230 may include a memory controller 431 , a data buffer 432 , the ECC block 235 and a multiplexing block MUX.
- the memory controller 431 may control the data buffer 432 , the ECC block 235 and the multiplexing block MUX.
- the memory controller 431 may output the read command RCMD from the command queue CQ in response to the command management unit 240 , and provide the output read command RCMD to the semiconductor memory device 100 .
- the read data from the semiconductor memory device 100 may be stored in the data buffer 432 .
- the memory controller 431 may control the multiplexing block MUX to transfer part or all of the code words in the read data stored in the data buffer 432 to the ECC block 235 .
- the memory controller 431 may refer to the decoding status table DT.
- the read data transferred from the semiconductor memory device 100 may include data bits stored in a single page.
- the data bits may be divided into a plurality of code words.
- the read data may include the first to fourth code words CW 1 to CW 4 .
- the ECC block 235 may perform a decoding operation in units of code words.
- the ECC block 235 may be controlled by the memory controller 431 .
- the ECC block 235 may receive one or more code words through the multiplexing block MUX and decode each one of the code words according to an error correction code.
- the memory control unit 230 receives read data corresponding to the read commands RCMD 1 to RCMDx
- the ECC block 235 may receive the code words in the read data.
- the ECC block 235 may feedback information on whether the received code word is successfully decoded to the memory controller 431 .
- the ECC block 235 may temporarily store the error-corrected code word in the memory unit 210 .
- the memory controller 431 may store the decoding status table DT.
- the decoding status table DT may include information on whether the decoding of each of the code words passes or fails.
- the decoding status table DT of the memory controller 431 may include information whether each of the first to fourth code words CW 1 to CW 4 is successfully decoded.
- the memory controller 431 may receive the information on whether each code word succeeds from the ECC block 235 and update the decoding status table DT based on the received information. For example, as the semiconductor memory device 100 performs the read operations in response to more read commands and parameter setting commands, more of the first to fourth code words CW 1 to CW 4 may be successfully decoded.
- FIG. 15 illustrates the decoding status table DT including the information indicating whether the decoding of the first and second code words CW 1 and CW 2 passes and whether the decoding of the third and fourth code words CW 3 and CW 4 fails.
- the memory controller 431 may update information corresponding to the third code word CW 3 from fail to pass in the decoding status table DT.
- the memory controller 431 may store the status information indicating that the corresponding read command fails in the status information queue SQ.
- the memory controller 431 may store the status information indicating that the corresponding read command passes in the status information queue SQ.
- the memory controller 431 may control the multiplexing block MUX to transfer only the decoding-failed one of the code words CW 1 to CW 4 from the data buffer 432 to the ECC block 235 by referring to the decoding status table DT. Therefore, the ECC block 235 may not repeat decoding of all of the read data. Therefore, the amount of time needed to decode the read data may be improved.
- FIG. 13 illustrates the decoding status table DT included in the memory control unit 230 .
- the decoding status table DT may be stored in the memory unit 210 .
- FIG. 16 is a block diagram illustrating an embodiment 1200 of the controller 200 and 300 described with reference to FIGS. 4 and 11 .
- the controller 1200 may include a memory unit 1210 , a processing unit 1220 , a host interface 1230 , a memory interface 1240 and an error correction block 1250 .
- the processing unit 1220 may control the general operation of the controller 1200 .
- the memory unit 1210 may be used as operation memory of the processing unit 1220 , a cache memory between the semiconductor memory device 100 , shown in FIGS. 4 and 11 , and the host, and/or a buffer memory between the semiconductor memory device 100 and the host.
- the processing unit 1220 and the memory unit 1210 may function as the command generation unit 220 and the command management unit 240 shown in FIGS. 4 and 11 .
- the processing unit 1220 may load a program command, a data file, and a data structure in the memory unit 1210 , and perform the functions of the command generation unit 220 and the command management unit 240 by executing the loaded data.
- the memory unit 1210 may be used as the memory units 210 and 310 shown in FIGS. 4 and 11 .
- FIG. 16 illustrates providing one memory unit 1210 . However, two or more memory units may be provided.
- the host interface 1230 may include a protocol for exchanging data between the host and the controller 1200 .
- the controller 1200 may communicate with the host through one or more protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a private protocol, etc.
- USB universal serial bus
- MMC multimedia card
- PCI peripheral component interconnection
- PCI-E PCI-express
- ATA advanced technology attachment
- serial-ATA protocol serial-ATA protocol
- parallel-ATA a serial-ATA protocol
- SCSI small computer small interface
- ESDI enhanced small disk interface
- IDE integrated drive electronics
- the memory interface 1240 may interface with the semiconductor memory device 100 .
- the error correction block 1250 may decode the read data received from the semiconductor memory device 100 by using an error correction code.
- the memory interface 1240 and the error correction block 1250 may perform the function of the memory control unit 230 shown in FIGS. 4 and 11 .
- FIG. 17 is a block diagram illustrating an application example ( 2000 ) of the memory system 50 shown in FIG. 1 .
- the memory system 2000 may include a semiconductor memory device 2100 and a controller 2200 .
- the semiconductor memory device 2100 may include a plurality of semiconductor data chips.
- the plurality of semiconductor data chips may be divided into a plurality of groups.
- the plurality of groups may communicate with the controller 2200 through first to k th channels CH 1 to CHk, respectively.
- Each of the semiconductor data chips may be configured and operate in substantially the same manner as the semiconductor memory device 100 described above with reference to FIGS. 1 to 3 .
- Each of the groups may communicate with the controller 2200 through a single common channel.
- the controller 2200 may be configured in substantially the same manner as the controller 1200 described above with reference to FIG. 16 , and configured to control the plurality of data chips of the semiconductor memory device 2100 through the plurality of channels CH 1 to CHk.
- FIG. 17 illustrates the plurality of semiconductor data chips coupled to a single channel.
- the memory system 2000 may be modified so that a single semiconductor data chip may be coupled to a single channel.
- a command generation unit may generate commands for identifying data of a selected page and store the generated commands in a command queue. When a read command read from the command queue passes, commands remaining in the command queue among the corresponding commands may be aborted.
- the command generation unit may perform other operations. Therefore, the operating time of the command generation unit and a controller may be improved.
- a controller having an improved operating time and an operating method thereof are provided.
Abstract
Description
- Field of Invention
- Various exemplary embodiments relate generally to an electronic device and, more particularly, to a controller controlling a semiconductor memory device and an operating method thereof.
- Description of Related Art
- Semiconductor memory devices are made of semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (Inp). Semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices.
- Volatile memory devices lose stored data when powered off. Examples of volatile memory devices include Static RAM (SRAM), Dynamic RAM (DRAM) and Synchronous DRAM (SDRAM). Non-volatile memory devices retain stored data regardless of power on/off conditions. Examples of non-volatile memory include Read Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM) flash memory, Phase-change Random Access Memory (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM) and Ferroelectric RAM (FRAM). Flash memories are classified into NOR-type memories and NAND-type memories.
- A semiconductor memory device controller may generate commands at the request of a host and perform the generated commands. The controller may include a command queue to store commands. The command queue may be defined in a memory unit such as a RAM. Commands stored in the command queue may be sequentially output to the semiconductor memory device.
- An embodiment is directed to a controller having an improved operating time and an operating method thereof.
- An operating method for controlling a semiconductor memory device according to an embodiment may include storing a plurality of read commands in a command queue managed on first-in first-out basis; providing one of the plurality of read commands to the semiconductor memory device; determining pass or fail of the provided read command based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting the remaining read commands in the command queue when the provided read command passes.
- The semiconductor memory device may include a plurality of pages, and the plurality of read commands may be commands for identifying data stored in one of the plurality of pages.
- The determining may include performing ECC decoding on the read data, and the provided read command may pass when the ECC decoding passes.
- The operating method may further include repeating the providing and determining with the remaining read commands when the provided read command fails.
- The operating method may further include generating a plurality of parameter setting commands to change a setting value of the semiconductor memory device, the plurality of parameter setting commands being stored in the command queue, along with the plurality of read commands; and providing one of the plurality of parameter setting commands to the semiconductor memory device.
- The aborting may include aborting remaining parameter setting commands in the command queue when the provided read command passes.
- The setting value may correspond to a voltage applied to a word of the semiconductor memory device line during a read operation of the semiconductor memory device.
- The command queue may include memory space from a head address to a tail address, and the plurality of read commands may be stored in memory space from a start address to an end address between the head and tail addresses.
- The aborting may include generating a shadow pointer pointing an address corresponding to first one of the remaining read commands when the provided read command passes; and erasing the remaining read commands pointed by the shadow pointer while moving the shadow pointer from a current address to a next address until the shadow pointer points to the end address.
- The aborting may include sequentially dropping the remaining read commands between the start address and the end address.
- The aborting may erase the remaining read commands stored in memory space between a start address and an end address in the command queue.
- The determining may determine whether the provided read command fails when ECC decoding fails on one or more code words included in the read data.
- The ECC decoding may be performed on one or more code words, on which the ECC decoding fails in the read data previously provided from the semiconductor memory device in response to previously provided read command.
- A controller controlling a semiconductor memory device according to another embodiment may include a command queue managed on first-in first-out basis; a command generation unit suitable for storing a plurality of read commands in the command queue; a memory control unit suitable for: providing one of the plurality of read commands to the semiconductor memory device; and determining pass or fail of the provided read command based on read data, which is provided from the semiconductor memory device in response to the provided read command; and a command management unit suitable for aborting remaining read commands when the provided read command passes.
- The semiconductor memory device may include a plurality of pages, and the plurality of read commands may be for identifying data stored in one of the plurality of pages.
- The memory control unit may include a data buffer suitable for storing the read data provided from the semiconductor memory device in response to the provided read command; an error correction block suitable for performing ECC decoding on the read data in units of single code words; a decoding status table suitable for storing pass or fail information of the ECC decoding on each of code words included in the read data; and a multiplexing block suitable for providing the read data in single code word units from the data buffer to the error correction block; and a memory controller suitable for: controlling the multiplexing block to provide the error correction block with one or more code words, on which the ECC decoding fails in the read data previously provided from the semiconductor memory device in response to previously provided read command, by referring to the decoding status table; and updating the fail information stored in the decoding status table according to result of the ECC decoding.
- The memory control unit may determine failures in the provided read command when ECC decoding fails on one or more code words included in the read data.
- An operating method for controlling a semiconductor memory device including a plurality of pages according to an embodiment may include storing a plurality of commands for identifying data of a selected page in a command queue managed on first-in first-out basis; providing one of the plurality of commands to the semiconductor device; repeating the providing with remaining read commands when the provided read command fails; and aborting remaining read commands when the provided read command passes.
-
FIG. 1 is a block diagram illustrating a memory system according to an embodiment; -
FIG. 2 is a block diagram illustrating a semiconductor memory device shown inFIG. 1 ; -
FIG. 3 is a block diagram illustrating a memory cell array shown inFIG. 2 ; -
FIG. 4 is a block diagram illustrating a controller shown inFIG. 1 according to an embodiment; -
FIG. 5 is a flowchart illustrating an operating method of a controller according to an embodiment; -
FIG. 6 is a conceptual diagram illustrating a command queue; -
FIG. 7 is a flowchart illustrating an embodiment of step S150 shown inFIG. 5 ; -
FIG. 8 is a conceptual diagram illustrating an embodiment shown inFIG. 7 ; -
FIG. 9 is a flowchart illustrating another embodiment of step S150 shown inFIG. 5 ; -
FIG. 10 is a conceptual diagram of the embodiment shown inFIG. 9 ; -
FIG. 11 is a block diagram illustrating a controller shown inFIG. 1 according to another embodiment; -
FIG. 12 is a conceptual diagram illustrating first and second command queues shown inFIG. 11 ; -
FIG. 13 is a diagram illustrating a memory control unit shown inFIGS. 4 and 11 ; -
FIG. 14 is a conceptual diagram illustrating code words included in read data; -
FIG. 15 is a conceptual diagram illustrating a decoding status table shown inFIG. 13 ; -
FIG. 16 is a block diagram illustrating an embodiment of a controller shown inFIGS. 4 and 11 ; and -
FIG. 17 is a block diagram illustrating an application example of a memory system shown inFIG. 1 . - Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. The figures are provided to allow those with ordinary skill in the art to understand the scope of the embodiments of the invention. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth. Rather, these embodiments are provided so that this disclosure will be thorough and complete. In addition, the embodiments are provided to fully convey the scope of the invention to those skilled in the art.
- Throughout the disclosure, reference numerals correspond directly to the like numbered parts in the various figures and embodiments of the present invention. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form, and vice versa, as long as it is not specified.
-
FIG. 1 is a block diagram illustrating amemory system 50 according to an embodiment. - Referring to
FIG. 1 , thememory system 50 may include asemiconductor memory device 100 and acontroller 200. - The
semiconductor memory device 100 may be controlled by thecontroller 200. Thesemiconductor memory device 100 may include amemory cell array 110 and aperipheral circuit 120 driving thememory cell array 110. Thememory cell array 110 may include a plurality of non-volatile memory cells. - The
peripheral circuit 120 may be controlled by thecontroller 200. Under the control of thecontroller 200, theperipheral circuit 120 may program data into thememory cell array 110, read the data from thememory cell array 110, and erase the data from thememory cell array 110. - According to an embodiment, a read operation and a program operation of the
semiconductor memory device 100 may be performed in units of pages. An erase operation of thesemiconductor memory device 100 may be performed in units of memory blocks. - During a program operation, the
peripheral circuit 120 may receive a command indicating a program operation, a physical address and write data from thecontroller 200. A single memory block and a single page included therein may be specified by the physical address. Theperipheral circuit 120 may program the write data into the corresponding page. - During a read operation, the
peripheral circuit 120 may receive a command (hereinafter, read command) indicating the read operation and a physical address from thecontroller 200. A single memory block and a single page included therein may be specified by the physical address. Theperipheral circuit 120 may read data from the corresponding page and output the read data (hereinafter, read data) to thecontroller 200. - During an erase operation, the
peripheral circuit 120 may receive a command indicating the erase operation and a physical address from thecontroller 200. The physical address may specify a single memory block. Theperipheral circuit 120 may erase data of the memory block corresponding to the physical address. - According to an embodiment, the
semiconductor memory device 100 may be a flash memory device. - The
controller 200 may control the general operation of thesemiconductor memory device 100. Thecontroller 200 may access thesemiconductor memory device 100 at the request of a host. For example, thecontroller 1200 may control a read operation, a program operation, an erase operation, and/or a background operation of thesemiconductor memory device 100. Thecontroller 200 may provide an interface between thesemiconductor memory device 100 and the host. Thecontroller 200 may drive firmware for controlling thesemiconductor memory device 100. - When the host transfers a read request, the
controller 200 may provide a read command to thesemiconductor memory device 100 in order to identify data of a page corresponding to the read request. Thecontroller 200 may convert a logical block address included in the read request into a physical block address. According to an embodiment, thecontroller 200 may function as a flash translation layer (FTL). Thecontroller 200 may provide the generated physical address, along with the read command, to thesemiconductor memory device 100. - In response to each read command, the
semiconductor memory device 100 may transfer the read data to thecontroller 200. Thecontroller 200 may determine whether an error is included in the read data. For example, thecontroller 200 may decode the read data according to an error correction code. Various types of error correction codes, such as Bose, Chaudhri, Hocquenghem (BCH) codes, Hamming codes, Reed Solomon codes, low density parity check (LDPC) codes, may be used. For example, when the read data includes more error bits than a predetermined number, the decoding may fail. When the read data includes error bits equal to or less than the predetermined number, the decoding may succeed. - Decoding success may mean that the corresponding read command passes, and decoding failure may mean that the corresponding read command fails. When decoding succeeds, the
controller 200 may output the error-corrected read data to the host. When the decoding fails, thecontroller 200 may re-transfer the read command to thesemiconductor memory device 100. -
FIG. 2 is a block diagram illustrating thesemiconductor memory device 100 described with reference toFIG. 1 .FIG. 3 is a block diagram illustrating thememory cell array 110 shown inFIG. 2 . - Referring to
FIG. 2 , thesemiconductor memory device 100 may include thememory cell array 110 and theperipheral circuit 120. - The
memory cell array 110 may include a plurality of memory cells. The plurality of memory cells may be coupled to anaddress decoder 121 through row lines RL and coupled to a read and writecircuit 123 through bit lines BL. - Referring to
FIG. 3 , thememory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The first to zth memory blocks BLK1 to BLKz may be coupled in common to first to mth bit lines BL1 to BLm. The first to mth bit lines BL1 to BLm may form the bit lines BL shown inFIG. 2 . Each of the memory blocks BLK1 to BLKz may form an erase unit. - In
FIG. 3 , elements included in one (BLK1) of the memory blocks BLK1 to BLKz are illustrated and elements included in the remaining memory blocks BLK2 to BLKz are omitted for clarity. Each of the remaining memory blocks BLK2 to BLKz may be configured in substantially the same manner as the first memory block BLK1. - The memory block BLK1 may include a plurality of cell strings CS1 to CSm. The first to mth cell strings CS1 to CSm may be coupled to the first to mth bit lines BL1 to BLm, respectively.
- Each of the cell strings CS1 to CSm may include a drain selection transistor DST, a plurality of memory cells MC1 to MCn coupled in series, and a source selection transistor SST. The drain selection transistor DST may be coupled to a drain selection line DSL1. The first to nth memory cells MC1 to MCn may be coupled to first to nth word lines WL1 to WLn, respectively. The source selection transistor SST may be coupled to a source selection line SSL1. A drain side of the drain selection transistor DST may be coupled to a corresponding bit line. A source side of the source selection transistor SST may be coupled to a reference voltage node. According to an embodiment, a source side of the source selection transistor SST may be coupled to a common source line (not illustrated). The common source line may be biased to a reference voltage.
- Memory cells coupled to a single word line of the first to mth cell strings CS1 to CSm may form a single page pg. Therefore, the memory block BLK1 may include a plurality of pages.
- The drain selection line DSL1, the first to nth word lines WL1 to WLn and the source selection line SSL1 may be included in the row lines RL shown in
FIG. 2 . The drain selection line DSL1, the first to nth word lines WL1 to WLn and the source selection line SSL1 may be controlled by theaddress decoder 121. The first to mth bit lines BL1 to BLm may be controlled by the read and writecircuit 123. - Referring again to
FIG. 2 , theperipheral circuit 120 may include theaddress decoder 121, avoltage generator 122, the read and writecircuit 123, an input/output buffer 124 and acontrol logic 125. - The
address decoder 121 may be coupled to thememory cell array 110 through the row lines RL. Theaddress decoder 121 may be controlled by thecontrol logic 125. Theaddress decoder 121 may receive a physical address PA through thecontrol logic 125. - The read operation of the
semiconductor memory device 100 may be performed in units of pages (see reference character pg inFIG. 3 ). The physical address PA received during the read operation may include a block address and a row address. - The
address decoder 121 may decode the block address of the received physical address PA. Theaddress decoder 121 may select one of the memory blocks BLK1 to BLKz according to the decoded block address. - The
address decoder 121 may decode the row address of the received physical address PA and select one word line in a selected memory block. Thus, a single page may be selected. Theaddress decoder 121 may apply a read voltage from thevoltage generator 122 to the selected word line and apply a pass voltage from thevoltage generator 122 to unselected word lines. - The
voltage generator 122 may be controlled by thecontrol logic 125. Thevoltage generator 122 may generate an internal power voltage by using an external power voltage provided to thesemiconductor memory device 100. For example, thevoltage generator 122 may generate the internal power voltage by regulating the external power voltage. The internal power voltage may be provided to theaddress decoder 121, the read and writecircuit 123, the input/output buffer 124 and thecontrol logic 125 and used as an operation voltage of thesemiconductor memory device 100. - The
voltage generator 122 may generate a plurality of voltages by using at least one of the external power voltage and the internal power voltage. According to an embodiment, thevoltage generator 122 may include a plurality of pumping capacitors receiving the internal power voltage and generate a plurality of voltages by selectively activating the plurality of pumping capacitors under the control of thecontrol logic 125. For example, thevoltage generator 122 may generate a read voltage and a pass voltage having a higher voltage level than the read voltage during the read operation. The generated voltages may be provided to theaddress decoder 121. - The read and write
circuit 123 may be coupled to thememory cell array 110 through the bit lines BL. The read and writecircuit 123 may be controlled by thecontrol logic 125. - The read and write
circuit 123 may read and store read data DATA from the page of the selected word line of thememory cell array 110 during the read operation. The read data DATA may be transferred to the input/output buffer 124 through data lines DL. - The input/
output buffer 124 may be coupled to the read and writecircuit 123 through the data lines DL. The input/output buffer 124 may be controlled by thecontrol logic 125. The input/output buffer 124 may externally output the read data DATA transferred from the read and writecircuit 123 through the data lines DL. - The
control logic 125 may control the general operation of thesemiconductor memory device 100. Thecontrol logic 125 may receive a command CMD and the physical address PA. During a read operation, the command CMD may be a read command. During a program operation, the command CMD may indicate the program operation. During an erase operation, the command CMD may indicate the erase operation. Thecontrol logic 125 may control theaddress decoder 121, thevoltage generator 122, the read and writecircuit 123 and the input/output buffer 124 in response to the received command CMD. - A parameter setting command to change a setting value of the
semiconductor memory device 100 may be received as the command CMD. For example, the parameter setting command may include information to change the read voltage. Thecontrol logic 125 may control thevoltage generator 122 to change the read voltage in response to the parameter setting command. For example, the parameter setting command may include information to change the pass voltage. - A threshold voltage distribution of memory cells included in each page may be shifted for various reasons. It is widely known that data of a selected word line is identified as different read data by controlling a read voltage. In other words, by applying an inappropriate read voltage, many error bits may be included in read data. By controlling the read voltage, the error bits included in the read data may be reduced. When a read command fails since read data obtained by performing the read command includes many error bits, the
controller 200, shown inFIG. 1 , may control the read voltage by providing the parameter setting command to thesemiconductor memory device 100, and receive read data of the corresponding page again by transferring the read command again. -
FIG. 4 is a block diagram illustrating thecontroller 200 described with reference toFIG. 1 according to an embodiment. - Referring to
FIG. 4 , thecontroller 200 may include amemory unit 210, acommand generation unit 220, amemory control unit 230, and acommand management unit 240. - The
memory unit 210 may be coupled to thecommand generation unit 220, thememory control unit 230, and thecommand management unit 240. Thememory unit 210 may provide a storage space in thecontroller 200. In thememory unit 210, a command queue CQ and a status information queue SQ may be defined. Both the command queue CQ and the status information queue SQ may be managed using a first-in first-out basis. Each of the command queue CQ and the status information queue SQ may include a head address HA and a tail address TA. - The
command generation unit 220 may be coupled to thememory unit 210 and thecommand management unit 240. Thecommand generation unit 220 may be controlled by thecommand management unit 240. In response to a request from the host, thecommand generation unit 220 may generate a command corresponding to the request under the control of thecommand management unit 240. - According to an embodiment, the
command generation unit 220 may function as the flash translation layer (FTL). Thecommand generation unit 220 may transform a logical block address included in the request from the host into a physical block address. When the corresponding command is stored in the command queue CQ, thecommand generation unit 220 may store the generated physical address in connection with the corresponding command in thememory unit 210. The physical address stored in thememory unit 210 may be transferred to thesemiconductor memory device 100, along with the corresponding command, by thememory control unit 230. - According to an embodiment, the
command generation unit 220 may generate a plurality of commands for identifying data of a page (hereinafter, selected page) corresponding to the read request, and store the generated commands in the command queue CQ defined in thememory unit 210. According to an embodiment, thecommand generation unit 220 may repeat generating of the read command and the parameter setting command, and input the generated read commands and parameter setting commands in the command queue CQ. - According to an embodiment, the
command generation unit 220 may generate a plurality of commands for identifying data of the selected page in response to the read request. The generated commands may be sequentially provided to thesemiconductor memory device 100. - According to an embodiment, the
command generation unit 220 may firstly generate a single read command in response to the read request. The read command and the corresponding physical address may be provided to thesemiconductor memory device 100. Read data may be received from thesemiconductor memory device 100. When decoding of the read data fails, thecommand generation unit 220 may generate a plurality of commands for identifying the data of the selected page under the control of thecommand management unit 240. - The
memory control unit 230 may be coupled to thememory unit 210 and thecommand management unit 240. Thememory control unit 230 may include anECC block 235. Thememory control unit 230 may be controlled by thecommand management unit 240. - The
memory control unit 230 may output a command from the command queue CQ under the control of thecommand management unit 240, and provide the output command to thesemiconductor memory device 100. - When a read command RCMD is output from the command queue CQ, the
semiconductor memory device 100 may receive the read command RCMD. Thesemiconductor memory device 100 may provide read data to thecontroller 200 in response to the read command RCMD. The read data may include data bits stored in a single page. TheECC block 235 of thememory control unit 230 may decode the read data through an error correction code to correct an error in the read data. When the decoding succeeds or the read command RCMD passes, thememory control unit 230 may store status information indicating that the read command RCMD passes in the status information queue SQ defined in thememory unit 210. When the decoding fails or the read command RCMD fails, thememory control unit 230 may store status information indicating that the read command RCMD fails in the status information queue SQ. - After the read command RCMD is output, when a parameter setting command PST is output from the command queue CQ, the
semiconductor memory device 100 may change an internal setting value. - The next read command RCMD may be output from the command queue CQ on a first-in first-out basis. The
memory control unit 230 may provide the next read command RCMD to thesemiconductor memory device 100. Thesemiconductor memory device 100 may provide second read data to thecontroller 200 in response to the next read command RCMD. According to an embodiment, the second read data may be temporarily stored in thememory control unit 230 or thememory unit 210. TheECC block 235 of thememory control unit 230 may decode the second read data through the error correction code. According to a decoding result, thememory control unit 230 may store second status information in the status information queue SQ. - By the above-described manner, the
controller 200 may sequentially provide the read commands and the parameter setting commands stored in the command queue CQ to thesemiconductor memory device 100, receive the corresponding read data, and decode the received read data. Information indicating whether the read data is successfully decoded or whether the corresponding read command passes or fails may be stored as status information in the status information queue SQ. - The
command management unit 240 may control thememory unit 210, thecommand generation unit 220 and thememory control unit 230. Thecommand management unit 240 may control thecommand generation unit 220 to generate a plurality of commands in response to the read request from the host. Thecommand management unit 240 may control thememory control unit 230 to transfer the command stored in the command queue CQ to thesemiconductor memory device 100. - The
command management unit 240 may manage the command queue CQ with reference to the status information stored in the status information queue SQ. A start address and an end address of the command queue CQ may indicate locations of the plurality of commands for identifying the data of the selected page in the command queue CQ. The start address and the end address may be defined between the head address HA and the tail address TA of the command queue CQ. - The
command generation unit 220 may provide the start address and the end address to thecommand management unit 240. Thecommand management unit 240 may identify the start address and the end address. - When the status information output from the status information queue SQ indicates that the read command RCMD passes, the
command management unit 240 may output the error-corrected read data from thememory control unit 230 to the host. According to an embodiment, when one of the plurality of read commands passes, thecommand management unit 240 may abort the remaining read commands and the remaining parameter setting commands remaining in the command queue CQ, or the read commands and the parameter setting commands following the passed read command on a first-in first-out basis. - When the status information output from the status information queue SQ indicates that the read command RCMD fails, the
command management unit 240 may determine whether the next read command RCMD passes. Thecommand management unit 240 may determine whether the next read command RCMD passes on the basis of the next status information output from the status information queue SQ. As a result of the determination, thecommand management unit 240 may abort the remaining read commands and the remaining parameter setting commands remaining in the command queue CQ. For example, when the next read command RCMD passes, the read commands and the parameter setting commands following the next read command RCMD on the first-in first-out basis may be aborted. - Unlike the present invention, it is assumed that the
command generation unit 220 generates a single read command to identify data of a selected page, and generates other commands, e.g., a parameter setting command and another read command, according to whether the read command fails. When the corresponding read command fails, thecommand generation unit 220 generates a parameter setting command and a next read command to identify the data of the selected page again. Thus, thecommand generation unit 220 needs to stop the operation that is currently being performed. For example, thecommand management unit 240 may transfer an interrupt signal to thecommand generation unit 220, and thecommand generation unit 220 may stop the currently performed operation in response to the interrupt signal. Therefore, operating time of thecommand generation unit 220 and thecontroller 200 may be increased. When another command, e.g., a program command, is already input to the command queue CQ, thecommand generation unit 220 may search another command, e.g., the program command, in the command queue CQ. Subsequently, thecommand generation unit 220 may abort the searched command, or add another command for identifying the data of the selected page to an address previous to the address of the searched command. Therefore, operating time of thecommand generation unit 220 and thecontroller 200 may be increased. - According to an embodiment of the present invention, the
command generation unit 220 may generate a plurality of commands for identifying the data of the selected page and store the generated commands in the command queue CQ. When one of the read commands output from the command queue CQ passes, the remaining commands in the command queue CQ may be aborted or the commands that follow the passed read command on the first-in first-out basis may be aborted. In parallel with the cancellation, thecommand generation unit 220 may perform other operations. Therefore, operating time of thecommand generation unit 220 and thecontroller 200 may be improved. -
FIG. 5 is a flowchart illustrating an operating method of thecontroller 200 according to an embodiment. - Referring to
FIGS. 4 and 5 , at step S110, a plurality of read commands and a plurality of parameter setting commands may be generated. The read commands and the parameter setting commands may be for identifying the data of a selected page. When decoding of a first read data fails, thecommand generation unit 220 may generate the read commands and the parameter setting commands for identifying the data of the selected page under the control of thecommand management unit 240. At step S120, the generated commands may be stored in the command queue CQ. - At step S130, while the read commands and the parameter setting commands are sequentially provided to the
semiconductor memory device 100, it may be determined whether each of the read commands passes. - When the read command RCMD is provided to the
semiconductor memory device 100, thememory control unit 230 may receive read data corresponding to the read command RCMD from thesemiconductor memory device 100. Thememory control unit 230 may decode the read data and store information on whether the read data is successfully decoded as first status information in the status information queue SQ. When the parameter setting command is provided to thesemiconductor memory device 100, thesemiconductor memory device 100 may change an internal setting value. When the next read command RCMD is provided to thesemiconductor memory device 100, thememory control unit 230 may receive read data corresponding to the next read command RCMD from thesemiconductor memory device 100. Thememory control unit 230 may decode the corresponding read data and store information on whether the corresponding read data is successfully decoded as second status information in the status information queue SQ. The first and second status information may be stored in the status information queue SQ on a first-in first-out basis. - The
command management unit 240 may monitor the status information queue SQ. Thecommand management unit 240 may check the status information queue SQ and determine whether each read command passes. - The
memory control unit 230 which transfers the read commands and the parameter setting commands to thesemiconductor memory device 100 and stores the status information in the status information queue SQ, and thecommand management unit 240 which checks the status information queue SQ and determines whether each command passes may perform these operations in parallel. - At step S140, when one of the read commands passes, step S150 may be performed. When all of the read commands fail (“NO” at step S140), it may mean that all of the commands generated at step S110 are provided to the
semiconductor memory device 100 and the identifying of the data of the selected page fails despite all of the read commands and parameter setting commands. - At step S150, the remaining read commands and parameter setting commands in the command queue CQ may be aborted, or the read commands and the parameter setting commands following the passed read command on first-in first-out basis may be aborted.
-
FIG. 6 is a conceptual diagram illustrating the command queue CQ. - Referring to
FIG. 6 , the command queue CQ may store commands between the head address HA and the tail address TA. The head address HA may indicate the location of the first command CMD1 in the command queue CQ. The last command CMDq of the command queue CQ may be specified by the tail address TA. The command queue CQ may be managed on first-in first-out basis. The commands of the head address HA may be firstly input to the command queue CQ and output to thesemiconductor memory device 100. The commands of the tail address TA may be lastly input to the command queue CQ and output to thesemiconductor memory device 100. - The commands CMD1 to CMDp, RCMD1 to RCMDx, PST1 to PSTy, and CMDp+1 to CMDq generated by the
command generation unit 220 may be stored in the command queue CQ in order of input to the command queue CQ. The commands stored in the command queue CQ may have their own addresses of the command queue CQ. - For example, when first to pth commands CMD1 to CMDp are sequentially stored in the command queue CQ, the
command generation unit 220 may generate first to xth read commands RCMD1 to RCMDx and first to yth parameter setting commands PST1 to PSTy for identifying the data of the selected page. The generated read commands RCMD1 to RCMDx and parameter setting commands PST1 to PSTy may be stored in the command queue CQ in order of input to the command queue CQ. The read commands RCMD1 to RCMDx and the parameter setting commands PST1 to PSTy may be sequentially stored between the start address SA of the command queue CQ and the end address EA of the command queue CQ. Thecommand generation unit 220 may notify thecommand management unit 240 of the start address SA of the command queue CQ and the end address EA of the command queue CQ. Thus, thecommand management unit 240 may recognize that the commands for identifying the data of the selected page are located between the start address SA of the command queue CQ and the end address EA of the command queue CQ. -
FIG. 6 illustrates the read commands and the parameter setting commands alternately arranged in the command queue CQ. InFIG. 6 , the first read command RCMD1, the first parameter setting command PST1, the second read command RCMD2, the second parameter setting command PST2 . . . the yth parameter setting command PSTy, and the xth read command RCMDx may be sequentially arranged in the command queue CQ. However, this is only an example. For another example, thecommand generation unit 220 may arrange different numbers and orders of read commands and parameter setting commands in the command queue CQ. In other words, the read commands and the parameter setting commands may be arranged in the command queue CQ according to an implementation method of thecommand generation unit 220 and an implementation method of theECC block 235. - After the read commands RCMD1 to RCMDx and the parameter setting commands PST1 to PSTy are stored in the command queue CQ, the
command generation unit 220 may generate other commands CMDp+1 to CMDq. The generated p+1th to qth commands CMDp+1 to CMDq may be stored in the command queue CQ in a sequential manner from the end address EA. - The first to pth commands CMD1 to CMDp and the p+1th to qth commands CMDp+1 to CMDq may not be the commands for identifying the data of the selected page. Under this condition, the commands CMD1 to CMDq may not be limited. For example, each of the commands CMD1 to CMDq may be one of commands for program operations, erase operations, and other read operations in response to another read request.
- All of the commands stored in the command queue CQ may be output on a first-in first-out basis. For example, the
memory control unit 230 may sequentially increase an operation pointer OP from the head address HA and output a command pointed by the operation pointer OP. After the first to pth commands CMD1 to CMDp are output, the commands RCMD1 to RCMDx and PST1 to PSTy for identifying the data of the selected page may be output. -
FIG. 6 illustrates the operation pointer OP pointing to the first read command RCMD1. The first read command RCMD1 may be output. When the first read command RCMD1 is provided to thesemiconductor memory device 100, thesemiconductor memory device 100 may transfer the first read data corresponding to the first read command RCMD1 to thecontroller 200. - The first parameter setting command PST1 may be output. The
semiconductor memory device 100 may change an internal setting value in response to the first parameter setting command PST1. Subsequently, the second read command RCMD2 may be output. When the second read command RCMD2 is provided to thesemiconductor memory device 100, thesemiconductor memory device 100 may transfer the second read data corresponding to the second read command RCMD2 to thecontroller 200. - It may be determined whether the first read command RCMD1 passes according to the first read data. The first read data may be decoded. The status information may be stored in the status information queue SQ indicating whether the first read data is successfully decoded. It may be determined whether the first read command RCMD1 passes based on the status information. When the first read command RCMD1 passes, the
command management unit 240 may abort the remaining commands, among the commands RCMD1 to RCMDx and PST1 to PSTy between the start address SA and the end address EA. For example, when the second read command RCMD2 is output and it is detected that the first read command RCMD1 passes, the remaining commands RCMD3 to RCMDx and PST2 to PSTy following the first read command RCMD1 between the start address SA and the end address EA may be aborted. -
FIG. 7 is a flowchart illustrating an embodiment of step S150 described with reference toFIG. 5 . - Referring to
FIGS. 4, 6 and 7 , at step S310, thecommand management unit 240 may define a shadow pointer SP between the start address SA and the end address EA when it is detected that one of the read commands in the command queue CQ passes. For example, thecommand management unit 240 may inquire with thememory control unit 230 the location of the operation pointer OP, and define the operation pointer OP as the shadow pointer SP. This means that the command queue CQ stores the remaining read commands and the remaining parameter setting commands between the address indicated by the shadow pointer SP and the end address EA. That is, the read commands and the parameter setting commands following the passed read command on first-in first-out basis may be stored between the address indicated by the shadow pointer SP and the end address EA in the command queue CQ. - At step S320, the
command management unit 240 may erase a command of the address indicated by the shadow pointer SP. At step S330, thecommand management unit 240 may move the shadow pointer SP to the next address in the command queue CQ. At step S340, when the shadow pointer SP indicates the end address EA, thecommand management unit 240 may abort the command of the end address EA and stop the cancellation of the remaining read commands and the remaining parameter setting commands. When the shadow pointer SP has not indicated the end address EA yet, steps S320 to S340 may be repeated. In other words, steps S320 to S340 may be repeated until the shadow pointer SP indicates the end address EA. According to another embodiment, step S330 may be performed before step S320. -
FIG. 8 is a conceptual diagram of an embodiment shown inFIG. 7 . - Referring to
FIG. 8 , the first to pth commands CMD1 to CMDp may be output first. Thememory control unit 230 may output the command pointed to by the operation pointer OP while sequentially moving the operation pointer OP to the next address from the head address HA.FIG. 8 illustrates the output commands with hatched lines. - The
memory control unit 230 may output the first read command RCMD1, the first parameter setting command PST1 and the second read command RCMD2 while moving the operation pointer OP to the next address. - The shadow pointer SP may be defined between the start address SA and the end address EA when it is detected that one of the read commands in the command queue CQ passes. The
command management unit 240 may inquire with thememory control unit 230 the location of the operation pointer OP, and define the shadow pointer SP so that the shadow pointer SP may point to the address of the operation pointer OP.FIG. 8 illustrates the operation pointer OP pointing to the address of the second read command RCMD2. Subsequently, thecommand management unit 240 may repeat erasing of the command of the address indicated by the shadow pointer SP and move the shadow pointer SP to the next address until the shadow pointer SP indicates the end address EA. Thecommand management unit 240 may control thememory unit 210 to erase the commands stored at the address indicated by the shadow pointer SP. Therefore, the remaining read commands RCMD3 to RCMDx and the remaining parameter setting commands PST2 to PSTy in the command queue CQ may be aborted. - According to an embodiment, the remaining command may not be output from the command queue CQ, and the remaining read commands and the remaining parameter setting commands may be aborted. Therefore, the remaining commands may be aborted more promptly.
-
FIG. 9 is a flowchart illustrating another embodiment of step S150 described with reference toFIG. 5 . - Referring to
FIGS. 4, 6 and 7 , at step S410, when it is detected that one of the read commands in the command queue CQ passes, thecommand management unit 240 may sequentially output from the command queue CQ the remaining commands following the passed read command on first-in first-out basis between the start address SA and the end address EA. Since the command queue CQ is operated on a first-in first-out basis, the output commands may be erased from the command queue CQ. - At step S420, the
command management unit 240 may drop the output commands. -
FIG. 10 is a conceptual diagram of an embodiment shown inFIG. 9 . - Referring to
FIG. 10 , the first to pth commands CMD1 to CMDp may be output.FIG. 10 illustrates the output commands as hatched lines. The operation pointer OP may reach the start address SA. - Subsequently, the
memory control unit 230 may output the first read command RCMD1, the first parameter setting command PST1 and the second read command RCMD2 while moving the operation pointer OP from the start address SA to the next address. - For example, when the first read command RCMD1 or the second read command RCMD2 passes, the
command management unit 240 may inquire with thememory control unit 230 to determine the location of the operation pointer OP, and sequentially output the remaining commands following the passed first or second read command RCMD1 or RCMD2 on first-in first-out basis between the start address SA and the end address EA while moving the operation pointer OP to the next address in the command queue CQ.FIG. 10 exemplarily illustrates the operation pointer OP pointing to the second read command RCMD2. The commands of the address indicated by the operation pointer OP may be sequentially output by thecommand management unit 240. Subsequently, the output commands, which follow the passed read command on the first-in first-out basis and are indicated by the operation pointer OP, may be dropped. Thecommand management unit 240 may drop the sequentially output read commands. In other words, the sequentially output read command following the passed read command on the first-in first-out basis may be ignored. Thus, the remaining read commands and the remaining parameter setting commands in the command queue CQ may be aborted. - According to an embodiment, even when the remaining read commands and the remaining parameter setting commands following the passed read command on the first-in first-out basis are aborted, the remaining commands may also be output from the command queue CQ without the cancellation process in the command queue CQ as described with reference to
FIGS. 7 and 8 . Thus, the design of thecommand management unit 240 may be simplified. -
FIG. 11 is a block diagram illustrating thecontroller 200 shown inFIG. 1 according to another embodiment.FIG. 12 is a conceptual diagram of first and second command queues CQ1 and CQ2 shown inFIG. 11 . - Referring to
FIGS. 11 and 12 , thecontroller 300 may include amemory unit 310, thecommand generation unit 220, thememory control unit 230, and thecommand management unit 240. - The
memory unit 310 may include the first command queue CQ1, the second command queue CQ2 and the status information queue SQ. The first command queue CQ1 may include a first head address HA1 and a first tail address TA1. The second command queue CQ2 may include a second head address HA2 and a second address TA2. Thememory unit 310 may store the plurality of commands RCMD1 to RCMDx and PST1 to PSTy for identifying the data of the selected page in the first command queue CQ1. Thecommand generation unit 220 may store other commands CMD1 to CMDq in the second command queue CQ2. - The
command generation unit 220 may store a command corresponding to a request from the host in the second command queue CQ2. The commands CMD1 to CMDq stored in the second command queue CQ2 may be sequentially output from the second head address HA2 and provided to thesemiconductor memory device 100. - For example, when the operation pointer OP indicates the pth command CMDp, the pth command CMDp may correspond to the command corresponding to the read request from the host. The pth command CMDp and a physical address indicating the selected page may be provided to the
semiconductor memory device 100. Thesemiconductor memory device 100 may transfer the corresponding read data to thecontroller 300. Thememory control unit 230 may decode the read data and store information on whether the read data is successfully decoded in the status information queue SQ. When the pth command CMDp is determined to fail as a result of checking the status information queue SQ, thecommand management unit 240 may control thecommand generation unit 220 to generate the commands RCMD1 to RCMDx and PST1 to PSTy for identifying the data of the selected page, and input the generated commands RCMD1 to RCMDx and PST1 to PSTy to the separate command queue CQ1. - Then, the operation pointer OP may be locked to the current address in the second command queue CQ2, and the commands RCMD1 to RCMDx and PST1 to PSTy in the first command queue CQ1 may be output on a first-in first-out basis.
- According to this embodiment, the commands RCMD1 to RCMDx and PST1 to PSTy for identifying the data of the selected page may be stored in the first command queue CQ1. When one of the read commands output from the first command queue CQ1 passes, the remaining read commands and the remaining parameter setting commands following the passed read command on the first-in first-out basis may be erased from the first command queue CQ1 for the cancellation. The first command queue CQ1 may be initialized for the cancellation. Since the commands RCMD1 to RCMDx and PST1 to PSTy for identifying the data of the selected page are stored in the first command queue CQ1, the remaining commands may be aborted without managing the start address SA and the end address EA described with reference to
FIG. 6 . Therefore, the design of thecommand management unit 240 may be simplified. -
FIG. 13 is a view illustrating thememory control unit 230 described with reference toFIGS. 4 and 11 .FIG. 14 is a conceptual diagram illustrating code words CW1 to CW4 included in read data.FIG. 15 is a conceptual diagram illustrating a decoding status table DT shown inFIG. 13 . - Referring to
FIG. 13 , thememory control unit 230 may include amemory controller 431, a data buffer 432, theECC block 235 and a multiplexing block MUX. - The
memory controller 431 may control the data buffer 432, theECC block 235 and the multiplexing block MUX. Thememory controller 431 may output the read command RCMD from the command queue CQ in response to thecommand management unit 240, and provide the output read command RCMD to thesemiconductor memory device 100. The read data from thesemiconductor memory device 100 may be stored in the data buffer 432. Thememory controller 431 may control the multiplexing block MUX to transfer part or all of the code words in the read data stored in the data buffer 432 to theECC block 235. Thememory controller 431 may refer to the decoding status table DT. - The read data transferred from the
semiconductor memory device 100 may include data bits stored in a single page. The data bits may be divided into a plurality of code words. For example, as shown inFIG. 14 , the read data may include the first to fourth code words CW1 to CW4. - The
ECC block 235 may perform a decoding operation in units of code words. TheECC block 235 may be controlled by thememory controller 431. TheECC block 235 may receive one or more code words through the multiplexing block MUX and decode each one of the code words according to an error correction code. Whenever thememory control unit 230 receives read data corresponding to the read commands RCMD1 to RCMDx, the ECC block 235 may receive the code words in the read data. In addition, the ECC block 235 may feedback information on whether the received code word is successfully decoded to thememory controller 431. According to an embodiment, the ECC block 235 may temporarily store the error-corrected code word in thememory unit 210. - According to an embodiment, the
memory controller 431 may store the decoding status table DT. The decoding status table DT may include information on whether the decoding of each of the code words passes or fails. As show inFIG. 15 , the decoding status table DT of thememory controller 431 may include information whether each of the first to fourth code words CW1 to CW4 is successfully decoded. Thememory controller 431 may receive the information on whether each code word succeeds from theECC block 235 and update the decoding status table DT based on the received information. For example, as thesemiconductor memory device 100 performs the read operations in response to more read commands and parameter setting commands, more of the first to fourth code words CW1 to CW4 may be successfully decoded. -
FIG. 15 illustrates the decoding status table DT including the information indicating whether the decoding of the first and second code words CW1 and CW2 passes and whether the decoding of the third and fourth code words CW3 and CW4 fails. For example, when the ECC block 235 successfully decodes the third code word CW3, thememory controller 431 may update information corresponding to the third code word CW3 from fail to pass in the decoding status table DT. When theECC block 235 fails in decoding one or more of the first to fourth code words CW1 to CW4, thememory controller 431 may store the status information indicating that the corresponding read command fails in the status information queue SQ. Whenever the ECC block 235 successfully decodes each of the first to fourth code words CW1 to CW4, thememory controller 431 may store the status information indicating that the corresponding read command passes in the status information queue SQ. - According to an embodiment, the
memory controller 431 may control the multiplexing block MUX to transfer only the decoding-failed one of the code words CW1 to CW4 from the data buffer 432 to the ECC block 235 by referring to the decoding status table DT. Therefore, the ECC block 235 may not repeat decoding of all of the read data. Therefore, the amount of time needed to decode the read data may be improved. -
FIG. 13 illustrates the decoding status table DT included in thememory control unit 230. However, this is only an example. In another example, the decoding status table DT may be stored in thememory unit 210. -
FIG. 16 is a block diagram illustrating anembodiment 1200 of thecontroller FIGS. 4 and 11 . - Referring to
FIG. 16 , thecontroller 1200 may include amemory unit 1210, aprocessing unit 1220, ahost interface 1230, amemory interface 1240 and anerror correction block 1250. - The
processing unit 1220 may control the general operation of thecontroller 1200. Thememory unit 1210 may be used as operation memory of theprocessing unit 1220, a cache memory between thesemiconductor memory device 100, shown inFIGS. 4 and 11 , and the host, and/or a buffer memory between thesemiconductor memory device 100 and the host. Theprocessing unit 1220 and thememory unit 1210 may function as thecommand generation unit 220 and thecommand management unit 240 shown inFIGS. 4 and 11 . For example, theprocessing unit 1220 may load a program command, a data file, and a data structure in thememory unit 1210, and perform the functions of thecommand generation unit 220 and thecommand management unit 240 by executing the loaded data. - Additionally, the
memory unit 1210 may be used as thememory units FIGS. 4 and 11 .FIG. 16 illustrates providing onememory unit 1210. However, two or more memory units may be provided. - The
host interface 1230 may include a protocol for exchanging data between the host and thecontroller 1200. For example, thecontroller 1200 may communicate with the host through one or more protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a private protocol, etc. - The
memory interface 1240 may interface with thesemiconductor memory device 100. Theerror correction block 1250 may decode the read data received from thesemiconductor memory device 100 by using an error correction code. Thememory interface 1240 and theerror correction block 1250 may perform the function of thememory control unit 230 shown inFIGS. 4 and 11 . -
FIG. 17 is a block diagram illustrating an application example (2000) of thememory system 50 shown inFIG. 1 . - Referring to
FIG. 17 , thememory system 2000 may include asemiconductor memory device 2100 and acontroller 2200. Thesemiconductor memory device 2100 may include a plurality of semiconductor data chips. The plurality of semiconductor data chips may be divided into a plurality of groups. - In
FIG. 17 , the plurality of groups may communicate with thecontroller 2200 through first to kth channels CH1 to CHk, respectively. Each of the semiconductor data chips may be configured and operate in substantially the same manner as thesemiconductor memory device 100 described above with reference toFIGS. 1 to 3 . - Each of the groups may communicate with the
controller 2200 through a single common channel. Thecontroller 2200 may be configured in substantially the same manner as thecontroller 1200 described above with reference toFIG. 16 , and configured to control the plurality of data chips of thesemiconductor memory device 2100 through the plurality of channels CH1 to CHk. -
FIG. 17 illustrates the plurality of semiconductor data chips coupled to a single channel. However, thememory system 2000 may be modified so that a single semiconductor data chip may be coupled to a single channel. - According to an embodiment, a command generation unit may generate commands for identifying data of a selected page and store the generated commands in a command queue. When a read command read from the command queue passes, commands remaining in the command queue among the corresponding commands may be aborted. The command generation unit may perform other operations. Therefore, the operating time of the command generation unit and a controller may be improved.
- According to an embodiment, a controller having an improved operating time and an operating method thereof are provided.
- It will be apparent to those skilled in the art that various modifications can be made to the above-described exemplary embodiments of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover all such modifications provided they come within the scope of the appended claims and their equivalents.
Claims (20)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/754,014 US9542269B1 (en) | 2015-06-29 | 2015-06-29 | Controller controlling semiconductor memory device and operating method thereof |
TW104122790A TWI666649B (en) | 2015-06-29 | 2015-07-14 | Controller controlling semiconductor memory device and operating method thereof |
KR1020150106669A KR102281946B1 (en) | 2015-06-29 | 2015-07-28 | Controller controlling semiconductor memory device and operating method thereof |
CN201610086289.2A CN106297865B (en) | 2015-06-29 | 2016-02-15 | Controller for controlling semiconductor memory device and method of operating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/754,014 US9542269B1 (en) | 2015-06-29 | 2015-06-29 | Controller controlling semiconductor memory device and operating method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
US20160378590A1 true US20160378590A1 (en) | 2016-12-29 |
US9542269B1 US9542269B1 (en) | 2017-01-10 |
Family
ID=57605289
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/754,014 Active 2035-09-02 US9542269B1 (en) | 2015-06-29 | 2015-06-29 | Controller controlling semiconductor memory device and operating method thereof |
Country Status (4)
Country | Link |
---|---|
US (1) | US9542269B1 (en) |
KR (1) | KR102281946B1 (en) |
CN (1) | CN106297865B (en) |
TW (1) | TWI666649B (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170060477A1 (en) * | 2015-08-28 | 2017-03-02 | Kabushiki Kaisha Toshiba | Memory device that updates parameters transmitted to a host based on operational settings |
US20180130534A1 (en) * | 2016-11-04 | 2018-05-10 | Winbond Electronics Corp. | Semiconductor memory device and reading method thereof |
US20190138455A1 (en) * | 2017-11-08 | 2019-05-09 | SK Hynix Inc. | Memory controller and method of operating the same |
CN109918315A (en) * | 2017-12-12 | 2019-06-21 | 爱思开海力士有限公司 | The operating method of storage system and storage system |
US20190235954A1 (en) * | 2018-01-31 | 2019-08-01 | SK Hynix Inc. | Memory controller and method of operating the same |
US10635350B2 (en) | 2018-01-23 | 2020-04-28 | Western Digital Technologies, Inc. | Task tail abort for queued storage tasks |
CN111341370A (en) * | 2018-12-19 | 2020-06-26 | 爱思开海力士有限公司 | Semiconductor memory device, controller, memory device and operating method thereof |
CN112017700A (en) * | 2019-05-30 | 2020-12-01 | 美光科技公司 | Dynamic power management network for memory devices |
US11687450B2 (en) * | 2020-05-19 | 2023-06-27 | SK Hynix Inc. | Storage device for translating address and operating method thereof |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI648620B (en) * | 2017-08-07 | 2019-01-21 | 慧榮科技股份有限公司 | Memory device and operation instruction error processing method |
KR102516547B1 (en) * | 2018-03-08 | 2023-04-03 | 에스케이하이닉스 주식회사 | Memory controller and memory system having the same |
KR102524916B1 (en) * | 2018-03-13 | 2023-04-26 | 에스케이하이닉스 주식회사 | Storage device and operating method thereof |
KR102620262B1 (en) * | 2019-06-04 | 2024-01-03 | 에스케이하이닉스 주식회사 | Semiconductor memory device, operating methods thereof and memory system |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6976204B1 (en) * | 2001-06-15 | 2005-12-13 | Advanced Micro Devices, Inc. | Circuit and method for correcting erroneous data in memory for pipelined reads |
JP4564390B2 (en) * | 2005-03-31 | 2010-10-20 | 東芝ストレージデバイス株式会社 | Information processing device |
KR100865830B1 (en) * | 2007-02-22 | 2008-10-28 | 주식회사 하이닉스반도체 | Method of reading a memory device |
TWI428918B (en) * | 2009-09-29 | 2014-03-01 | Silicon Motion Inc | Memory device and data access method for a memory device |
KR101082756B1 (en) * | 2010-07-09 | 2011-11-10 | 주식회사 하이닉스반도체 | Method for operating semiconductor memory device |
WO2012050934A2 (en) * | 2010-09-28 | 2012-04-19 | Fusion-Io, Inc. | Apparatus, system, and method for a direct interface between a memory controller and non-volatile memory using a command protocol |
KR101639853B1 (en) | 2011-05-20 | 2016-07-14 | 소프트 머신즈, 인크. | Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines |
JP5547148B2 (en) | 2011-09-13 | 2014-07-09 | 株式会社東芝 | Memory device |
US8667368B2 (en) * | 2012-05-04 | 2014-03-04 | Winbond Electronics Corporation | Method and apparatus for reading NAND flash memory |
KR101932920B1 (en) * | 2012-09-14 | 2019-03-18 | 삼성전자 주식회사 | Host for controlling non-volatile memory crad, system including the same and operating method there-of |
JP2014140111A (en) * | 2013-01-21 | 2014-07-31 | Sony Corp | Controller, information processing system, method of controlling controller, and program |
US9256384B2 (en) | 2013-02-04 | 2016-02-09 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method and system for reducing write latency in a data storage system by using a command-push model |
KR102143517B1 (en) * | 2013-02-26 | 2020-08-12 | 삼성전자 주식회사 | Semiconductor Memory Device including error correction circuit and Operating Method thereof |
KR20140146275A (en) * | 2013-06-14 | 2014-12-26 | 삼성전자주식회사 | Operating method for memory controller controlling nonvolatile memory device and nonvolatile memroy system |
TWI534829B (en) * | 2013-08-12 | 2016-05-21 | 華邦電子股份有限公司 | Serial nand flash memory |
-
2015
- 2015-06-29 US US14/754,014 patent/US9542269B1/en active Active
- 2015-07-14 TW TW104122790A patent/TWI666649B/en active
- 2015-07-28 KR KR1020150106669A patent/KR102281946B1/en active IP Right Grant
-
2016
- 2016-02-15 CN CN201610086289.2A patent/CN106297865B/en active Active
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170060477A1 (en) * | 2015-08-28 | 2017-03-02 | Kabushiki Kaisha Toshiba | Memory device that updates parameters transmitted to a host based on operational settings |
US10289482B2 (en) * | 2015-08-28 | 2019-05-14 | Toshiba Memory Corporation | Memory device that updates parameters transmitted to a host based on operational settings |
KR102040868B1 (en) | 2016-11-04 | 2019-11-05 | 윈본드 일렉트로닉스 코포레이션 | Semiconductor memory device and method of reading thereof |
US20180130534A1 (en) * | 2016-11-04 | 2018-05-10 | Winbond Electronics Corp. | Semiconductor memory device and reading method thereof |
KR20180050218A (en) * | 2016-11-04 | 2018-05-14 | 윈본드 일렉트로닉스 코포레이션 | Semiconductor memory device and method of reading thereof |
US10176873B2 (en) * | 2016-11-04 | 2019-01-08 | Winbond Electronics Corp. | Semiconductor memory device and reading method thereof |
US20190138455A1 (en) * | 2017-11-08 | 2019-05-09 | SK Hynix Inc. | Memory controller and method of operating the same |
CN109918315A (en) * | 2017-12-12 | 2019-06-21 | 爱思开海力士有限公司 | The operating method of storage system and storage system |
US10635350B2 (en) | 2018-01-23 | 2020-04-28 | Western Digital Technologies, Inc. | Task tail abort for queued storage tasks |
US20190235954A1 (en) * | 2018-01-31 | 2019-08-01 | SK Hynix Inc. | Memory controller and method of operating the same |
US10795762B2 (en) * | 2018-01-31 | 2020-10-06 | SK Hynix Inc. | Memory controller and method of operating the same |
CN111341370A (en) * | 2018-12-19 | 2020-06-26 | 爱思开海力士有限公司 | Semiconductor memory device, controller, memory device and operating method thereof |
CN112017700A (en) * | 2019-05-30 | 2020-12-01 | 美光科技公司 | Dynamic power management network for memory devices |
US20200379546A1 (en) * | 2019-05-30 | 2020-12-03 | Micron Technology, Inc. | Dynamic power management network for memory devices |
US11029746B2 (en) * | 2019-05-30 | 2021-06-08 | Micron Technology, Inc. | Dynamic power management network for memory devices |
US11687450B2 (en) * | 2020-05-19 | 2023-06-27 | SK Hynix Inc. | Storage device for translating address and operating method thereof |
Also Published As
Publication number | Publication date |
---|---|
US9542269B1 (en) | 2017-01-10 |
TW201701283A (en) | 2017-01-01 |
TWI666649B (en) | 2019-07-21 |
KR20170002256A (en) | 2017-01-06 |
CN106297865A (en) | 2017-01-04 |
KR102281946B1 (en) | 2021-07-27 |
CN106297865B (en) | 2020-09-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9542269B1 (en) | Controller controlling semiconductor memory device and operating method thereof | |
KR102615659B1 (en) | Memory system and operating method thereof | |
US11204846B2 (en) | Memory system and method for operating the same | |
US9564189B2 (en) | Memory system including semiconductor memory device and program method thereof | |
KR102461738B1 (en) | Semiconductor memory device and operating method thereof | |
KR20180118329A (en) | Memory system, data processing system and operating method thereof | |
KR102564774B1 (en) | Apparatus for diagnosing memory system or data processing system and operating method of memory system or data processing system based on diagnosis | |
KR102565888B1 (en) | Semiconductor memory device and operating method thereof | |
KR102643658B1 (en) | Semiconductor memory device and operating method thereof | |
KR102603243B1 (en) | Semiconductor memory device and operating method thereof | |
CN106653083B (en) | Semiconductor memory device and method of operating the same | |
CN109697995B (en) | Semiconductor memory device and method of operating the same | |
US20200057580A1 (en) | Semiconductor memory device and operating method thereof | |
KR102429456B1 (en) | Semiconductor memory device and operating method thereof | |
US10776273B2 (en) | Memory system having multiple cache pages and operating method thereof | |
US10170176B2 (en) | Apparatus and methods for generating reference voltages for input buffers of a memory device | |
US10019199B2 (en) | Controller coupled to semiconductor memory device and operating method thereof | |
US20160172039A1 (en) | Semiconductor memory device and method of operating the same | |
US8982635B2 (en) | Semiconductor memory device and writing method thereof | |
US9905304B2 (en) | Memory system and program operation method based on program speed information | |
US20210223987A1 (en) | Controller with smart scheduling and method of operating the controller | |
US11782646B2 (en) | Memory device and memory system having the memory device | |
US11556281B2 (en) | Semiconductor memory device and controller | |
KR102665270B1 (en) | Semiconductor memory device and operating method thereof | |
CN111933204A (en) | Semiconductor memory device and method of operating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SK HYNIX INC., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROH, YOUNG DONG;PARK, SE CHUN;REEL/FRAME:036035/0019 Effective date: 20150616 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |