US20160365300A1 - Coolant Distribution Structure For Monolithic Microwave Integrated Circuits (MMICs) - Google Patents
Coolant Distribution Structure For Monolithic Microwave Integrated Circuits (MMICs) Download PDFInfo
- Publication number
- US20160365300A1 US20160365300A1 US14/734,372 US201514734372A US2016365300A1 US 20160365300 A1 US20160365300 A1 US 20160365300A1 US 201514734372 A US201514734372 A US 201514734372A US 2016365300 A1 US2016365300 A1 US 2016365300A1
- Authority
- US
- United States
- Prior art keywords
- coolant
- layer
- slots
- input
- output port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002826 coolant Substances 0.000 title claims abstract description 221
- 238000009826 distribution Methods 0.000 title claims abstract description 85
- 230000005540 biological transmission Effects 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 37
- 229910003460 diamond Inorganic materials 0.000 claims description 18
- 239000010432 diamond Substances 0.000 claims description 18
- 239000012530 fluid Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 5
- 230000002401 inhibitory effect Effects 0.000 claims description 2
- 239000007787 solid Substances 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims 1
- 238000001816 cooling Methods 0.000 abstract description 13
- 235000012431 wafers Nutrition 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000005192 partition Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000012809 cooling fluid Substances 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 239000003643 water by type Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6644—Packaging aspects of high-frequency amplifiers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6683—High-frequency adaptations for monolithic microwave integrated circuit [MMIC]
Definitions
- This disclosure relates generally to semiconductor cooling structures and more particularly to coolant distribution structures for enabling coolant to flow in very close proximity to active semiconductor devices, such as Field Effect Transistors (FETs), of monolithic microwave integrated circuits (MMICs).
- FETs Field Effect Transistors
- MMICs monolithic microwave integrated circuits
- coolant structures are used to provide coolant in MMICs.
- One such structure is described in U.S. Pat. No. 7,548,424, inventors Altman, et al. issued Jun. 16, 2009 entitled, “Distributed transmit/receive integrated microwave module chip level cooling system”assigned to the same assignee as the present patent application.
- While such coolant structure provides coolant for MMIC chips in many applications, as power handling requirements increase there are applications requiring even higher coolant capacity and efficiencies. More particularly, in many MMIC chips having very high density active semiconductor devices it is highly desirable to provide liquid coolant flow in close proximity to the active devices. This introduces challenges from a hardware design and fabrication standpoint and introduces complexity from an electrical standpoint which a cooling structure must overcome.
- a coolant distribution structure for an MMIC having: an input/output port having at least one input port for receiving a coolant for transmission to coolant channels in the MMIC and at least one output port for exiting the coolant after such coolant has cooled active devices in the MMIC; a coolant pass-through layer to receive the coolant from the at least one input port and having structure to enable flow through the coolant channels by inhibiting such received coolant from passing directly to the output port; a distribution layer for receiving coolant passing from the coolant pass-through layer and distributing such received coolant to the cooling channels to absorb heat generated by the active devices and then directing the heated coolant back to the at least one output port of the input/output port layer.
- a coolant distribution structure for a monolithic integrated circuit (MMIC), the MMIC having a substrate with an active device layer on the top surface of the substrate and a plurality of coolant channels formed on a bottom surface of the substrate.
- the coolant distribution structure includes: an input/output port layer having at least one input port for receiving a coolant for transmission to the plurality of coolant channels and an output port for exiting the coolant after such coolant has cooled active devices in the active device layer; a coolant pass-through layer disposed on the input/output port layer to receive the coolant from the input port and having a input transmission structure portion configured to inhibit such received coolant from passing directly to the output port of the input/output port layer prior to such received coolant being transmitted to the plurality of cooling channels; and a coolant distribution layer mounted to the bottom surface of the substrate fir receiving coolant passing from pass-through layer, the coolant distribution layer distributing such received coolant to the plurality of cooling channels to absorb heat generated by the active devices, and then re-
- the pass-through layer and the coolant distribution layer are configured to have a coolant transmission structure that allows intake of cold coolant from the input/output port layer in only the input port and exhaust of heated coolant back to the output port layer to prevent short circuiting (that is, a direct flow) of cold and heated coolant streams.
- the input/output port layer has a pair of spaced input ports and wherein the output port is disposed between the pair of input ports.
- the coolant passthrough layer has formed therein: two sets of a plurality of parallel slots, each one of the sets being disposed over a corresponding one of the pair of input ports, the slots in the two sets being aligned one with the other to provide the input transmission structure portion; and a third set of parallel slots disposed over the output port, the slots in the third set being offset laterally from the slots in said two sets to provide the output transmission structure portion.
- the slots in said two sets of parallel slots are disposed in a pair of rows and the slots in the second set of slots are disposed in a row parallel to said pair of rows.
- the slots in the said third. set of parallel slots disposed over the output port are disposed in a row parallel to the pair of rows of slots disposed over the input ports.
- the slots in the said third row of slots are offset laterally from and disposed centrally between the rows of slots disposed over the input ports.
- the slots in said two sets and in the third set are elongated along a direction perpendicular to the rows.
- the input and the output ports in the input/output port layer are elongated a width of the MMIC and span the rows of slots in the distribution layer and the pass through layer.
- the coolant distribution layer has formed therein a plurality of parallel slots, one set of the parallel slots being supply slots and another set of the parallel slots being return slots, the set of supply slots being in aligned with the slots in the pair of a first plurality of parallel slots in the pass-through layer and the set of return slots being in aligned with the slots in the second set of slots in the pass-through layer.
- the slots in the coolant distribution layer are parallel to the slots in the coolant pass-through layer.
- the slots in the distribution layer and the pass-through layer are configured transverse to the input and the output ports of the input/output port layer such that the direction of coolant flow in the slots in the distribution layer is perpendicular to the long dimension of the input port and the output port of the input/output port layer.
- the coolant channels in the MMIC are blind-etched into the MMIC from the back side to form an integrated heat sink with the un-etched portion of the MMIC.
- the coolant channels have a width span of a few tens of microns and a depth of more than 250 ⁇ m in high conductivity diamond to be characterized as high aspect ratio diamond micro-channels.
- the coolant channels in the substrate are elongated along a direction perpendicular to the slots in the distribution layer.
- sections of the coolant channels are separated one from another by partitions to provide the channels with discontinuities along the lengths of the channels.
- the partitions are disposed under the active devices.
- FIG. 1 is an isometric view of an monolithic integrated circuit (MMIC) chip having active devices therein cooled by a coolant distribution structure, partially cut away, and mounted to a back-side the MMIC according to the disclosure;
- MMIC monolithic integrated circuit
- FIG. 1A is an exploded view, of an input/output layer, a coolant pass-through layer, a coolant distribution layer, and an MMIC chip of FIG. 1 , having a substrate with an active layer on the upper surface of the substrate thereof and having formed in the back side thereof micro-channels according to the disclosure;
- FIG. 1B is an enlarged, plan view a portion of an end of one slot in one of the layers of the coolant distribution structure of FIG. 1 , such enlarged portion being partially circled by an arrow in FIG. 1A ;
- FIG. 2 is a plan view of the coolant distribution structure of FIG. 1 viewed from the bottom of an input/output port layer and exposed portions of a coolant distribution layer of the structure according to the disclosure;
- FIGS. 2A-2D are cross-sectional views of the coolant distribution structure of FIG. 1 taken along lines 2 A- 2 A- 2 D- 2 D, respectively in FIG. 2 according to the disclosure, including a coolant distribution layer and an MMIC chip formed thereon according to the disclosure;
- FIG. 3 is a plan view of the coolant distribution layer of the coolant distribution structure of FIG. 1 with the substrate thereon, the substrate having micro-channels in a back surface thereof,
- FIG. 3A is a cross sectional view taken along one of the micro-channels along line 3 A- 3 A of FIG. 3 according to the disclosure.
- FIG. 4 is a plan view of the top surface of the substrate of the coolant distribution structure of FIG. 2 , shown in relationship with an isometric view of the coolant distribution structure with the underling MMIC chip of FIG. 1 according to the disclosure; an enlarged plan view of the coolant distribution layer, substrate and active layer of the coolant distribution structure of FIG. 1 being shown in FIG. 4A and an enlarged isometric view of the coolant distribution layer, substrate and active layer of the coolant distribution structure of FIG. 1 being shown in FIG. 4B .
- a coolant distribution structure 10 having: a manifold 11 for mounting to the hack side of a MMIC, here a MMIC chip 20 .
- the manifold 11 is a silicon manifold having: a bottom, silicon input/output port layer 12 ( FIG. 1A ), a middle, silicon coolant pass-through layer 14 , and a upper silicon coolant distribution layer 16 , here, for example, fabricated from two SiO 2 bonded silicon (Si) wafers 15 A 15 B.
- the input/output port layer 12 and the coolant pass-through layer 14 may be formed from two separate silicon wafers, here, in this embodiment, the input/output port layer 12 and the coolant pass-through layer 14 are formed using the same wafer 15 A; it being noted that for purposes of illustration, the input/output port layer 12 and the coolant pass-through layer 14 , although here formed from a single wafer 15 A, are shown exploded in FIG. 1A . More particularly, the wafer 15 A is processed first from one side using photolithographic-etching techniques to form, in about one half the thickness of the wafer, the input/output layer 12 and is next processed from the other side to form in the remaining thickness of the wafer 15 A, the coolant pass-through layer 14 .
- the wafer 15 B is processed from only one side using photolithographic-etching techniques to form the coolant distribution layer 16 .
- the two waters 15 A and 15 B are coated with silicon oxide, polished and then bonded together using plasma activated oxide bonding.
- FIGS. 2A-2D and 3A indicate, for illustration, the input/output port layer 12 and the coolant pass-through layer 14 as two separate silicon members.
- the MMIC chip 20 includes a diamond substrate 30 having formed on an upper surface thereof, here for example by MOCVD, an active device layer 32 , here for example, GaN. More particularly the substrate 30 of a monolithic integrated circuit (MMIC) chip 20 ( FIG. 1A ) is fabricated from high conductivity Chemically Vapor Deposited (CVD) diamond gown to a thickness of here, for example, 300 ⁇ m, having the back side 18 thereof polished to ⁇ 1 ⁇ m Ra. The CVD grown diamond substrate 30 is dry-etched, using for example, a Reactive Ion Etch (RIE) to form a plurality of blind, coolant micro-channels 26 , here for example, with an aspect ratio of approximately 10:1.
- RIE Reactive Ion Etch
- the MMIC chip 20 coolant micro-channels 26 ( FIG. 2A ), here etched out of a solid diamond blank, with blind micro-channel terminations on the substrate 30 ; thus, the micro-channels 26 and substrate 30 are integrated with one another being part of the same diamond blank.
- the active device layer 32 ( FIG. 1 ), here for example, a 0.5 to 2 ⁇ m thick layer of Gallium Nitride (GaN), here, for example, using a metalorganic chemical vapor deposition (MOCVD) process.
- a hermetic seal is formed between the MMIC chip 20 and the Si manifold 11 comprising of layers 12 , 14 and 16 ( FIG. 1A ) on the backside surface 18 ( FIG. 1A ) of the chip 20 using for example, a bonding technique described in U.S. Pat. No. 8,978,892, issued Mar. 24, 2015, entitled “Method for creating a selective solder seal interface for an integrated circuit cooling system”, inventors Davis et al., assigned to the same assignee as the present patent application.
- the backside surface 18 is polished to ⁇ 1 ⁇ m Ra prior to bonding.
- the micro-channels 26 have an aspect ratio of greater than 10:1.
- the micro-channels 26 have a width of 25 ⁇ m, are separated one from another 25 ⁇ m, have a depth >250 ⁇ m with the diamond substrate 30 having a thickness of 300 ⁇ m.
- the upper surface 33 ( FIGS. 1 and 1A )—the active device layer 32 of the MMIC chip 20 has firmed thereon, a microwave, two-stage amplifier circuit 36 .
- the circuit 36 is fed RF signals received, on an input co-planar waveguide (CPW) transmission line 38 ; it being noted that while CPW has a strip conductor disposed between a pair of coplanar ground plane conductors (not shown), here, for convenience in illustration, only the strip conductor portion of the CPW is shown.
- CPW co-planar waveguide
- the received RF signals are fed to the first amplification stage 40 , here a pair of Field Effect Transistors FETs 40 , through a passive input matching network (IMN), here also, for example, CPW transmission line network (here again only the strip conductor portion of the CPW being shown).
- INN passive input matching network
- the first stage amplified signals are then fed to a second amplification stage 42 , here also a pair of FETs 42 , through a passive interstage matching network (ISMN), here also, for example, CPW transmission network.
- ISMN passive interstage matching network
- the second stage amplified signals are then passed to output CPW transmission line 44 through a passive matching network (OMN), here also, for example, CPW transmission network.
- OPN passive matching network
- the manifold 11 of the coolant distribution structure 10 receives coolant from a cooling fluid amply, not shown, through, here for example, a pair of input ports 24 a, 24 b of the input/output port layer 12 ( FIG. 1A ) and directs the received coolant to channels 26 , herein referred to as micro-channels 26 ( FIGS. 2A and 2B ) formed in the back-side of the MMIC chip 20 after such coolant passes through coolant pass-through layer 14 and coolant distribution layer 16 ( FIGS. 2, 2A and 2B ); the coolant then Absorbs heat generated by active devices, here Field Effect Transistors (FETs), here, for example, HEMTs, formed in the top surface of MMIC chip 20 ( FIG.
- FETs Field Effect Transistors
- coolant manifold 11 feeds coolant to the coolant channels 26 in the chip 20 to provide coolant flow in close proximity to the active the FETS 40 , 42 .
- the coolant channels 26 have a blind end on the substrate 30 which enables electrical isolation between the active transistors FETs 40 , 42 and the fluid by way of the un-etched portion of substrate 30 thickness.
- the coolant channels 26 that are part of the chip 20 form an integrated heat sink with the chip 20 .
- the cooling channels 26 are micro-channels with very small effective fluid flow diameter to enable very high heat transfer rates to the fluid. These micro-channels 26 are configured in a parallel arrangement which ensures smaller heat gain by the fluid per flow path, thereby keeping the fluid and the chip 20 cool.
- channels 26 also enables distribution of flow over larger area of flow and shorter flow paths, which helps reduce the constriction to flow, thereby reducing pressure drop and energy requirements to drive the flow in the desired manner.
- the micro-channels 26 in the chip 20 do not extend continuously along the entire dimension of the chip 20 in the direction of the flow. Instead, the micro-channels 26 are separated along its length by partitions 50 formed in the hack side of the substrate 30 , FIG. 1A . That is, the channels 26 are partitioned (broken) in regions in the vicinity of FETS 40 , 42 such that there is no cooling fluid directly underneath the FETs 40 , 42 .
- This partitioned structure enables the heat to first “impinge” on the substrate 30 , here diamond, partitions which spreads the heat, thereby reducing the heat density that the cooling fluid is required to alleviate.
- This strategy reduces the operating temperature of the active devices by means providing cooler fluid zones local to the heated device.
- the blind ending of the micro-channels 26 in the chip 20 is such that the cooling fluid is separated from the electrically active devices (the FETs 40 , 42 ) by means of a diamond substrate 30 .
- the substrate thickness, or the separation, between the fluid and active devices, is 50 ⁇ m for a 2-6 GHz MMIC in one embodiment.
- the Si manifold 11 and the diamond chip 20 are adhered together to form one complete fluid routing and cooling structure by means of a thin hermetic bonding interface, for example, a 6 ⁇ m layer of metallic solder that is selectively deposited on the adhering surfaces of the diamond chip 20 and the Si manifold 11 .
- the manifold 11 layers; the input/output layer 12 , the pass-through layer 14 and the coolant distribution layer 16 are adhered to each other with SiO 2 , thereby forming a multi-layered Si manifold structure 11 .
- the fluid routing and diamond cooling structure 10 configured this way is tailored to the RF device geometry to enable precise, uniform and targeted distribution of coolant on the heated chip substrate surface.
- cooling channels are micro-channels configured in a massively parallel manifold arrangement to minimize pressure drop and maximize convective heat transfer performance.
- the micro-channels 26 are of similar width to enable creation using dry etching techniques.
- Partitions 50 ( FIG. 1A ) between micro-channels 26 are strategically located in proximity to the HEMT 20 being cooled to maximize conjugate (convection/conduction) heat transfer performance.
- the micro-channels 26 are separated from the active GaN surface by a minimum distance to ensure minimal interaction between electrical fields and the coolant (e.g., 50 ⁇ m for a 2-6 GHz MMIC). Bonding layers form a thin hermetic interface between the diamond micro-channels 26 and a Si manifold 11 fluid distribution structure. The bonding layers are selectively deposited solder. The Si manifold 11 design that is tailored to the RF device geometry to enable precise, uniform and targeted distribution of coolant to the diamond micro-channels, while keeping the coolant supply pressure drop and power.
- the coolant distribution structure 10 includes: the input/output port layer 12 having the pair of input ports 24 a, 24 b for receiving the coolant for transmission to the plurality of micro-coolant channels 26 and the output port 28 , disposed between the pair of input ports 24 a, 24 b, for exiting the coolant after such coolant has cooled active devices, FETs 40 , 42 in the active device layer 32 .
- the coolant pass-through layer 14 disposed, and bonded to, the input/output port layer 12 receives the coolant from the pair of input port 24 a, 24 b.
- the coolant pass-through layer 14 ( FIGS. 1A, 2A and 2B ) has three sections, 46 a, 46 b, and 46 c: sections 46 a and 46 c each have a plurality of, here for example, seven spaced supply slots 48 S.
- Section 46 b is disposed between sections 46 a and 46 c and includes a plurality of, here for example, eight return slots 48 R.
- the slots 48 S are disposed in rows disposed above the input ports 24 a and 24 b.
- the slots 48 R are disposed in a row disposed above the output port 28 . It is noted that the input ports 24 a, 24 b and the output port 28 are elongated along the X-direction ( FIG.
- slots 48 S, 48 R are elongated along a direction along the Y-direction which is perpendicular to the elongated direction of the input ports 24 a, 24 b and the output port 28 . It is also noted that while the supply slots 48 S in sections 46 a and 46 c are aligned along the X-direction, the return slots 48 R are offset, along the X- and Y-directions, from the supply slots 48 S.
- each one of the supply slots 48 S in sections 46 a faces (when looking along the Y-direction) a corresponding one of the supply slots 48 S in section 46 c
- each one of the return slots 48 R faces (when looking along the Y-direction) a region between a pair of the supply slots 48 S.
- the coolant distribution layer 16 ( FIG. 1A ) is integral with the coolant pass-through layer 14 and includes a plurality of parallel, channels S and R; S being a supply channels and R being a return channels.
- the channels S and R are elongated along the Y-direction.
- there are seven supply channels S and eight return channels R The supply channels S are disposed over the supply slots 48 S and the return channels are disposed over the return slots 48 R.
- the micro-channels 26 are elongated along the X-direction; a direction perpendicular to the elongated direction of the supply and return channels S and R.
- the three sections, 46 a, 46 b, and 46 c of the coolant pass-through layer 16 provide an input transmission structure portion configured to inhibit received coolant from passing directly to the output port 28 of the input/output port layer 12 prior to such received coolant being transmitted to the plurality of cooling micro-channels 26 and enabling such heat absorbed coolant to pass directly to the output port 28 of the input/output port layer 12 without mixing with cooler fluid in the input ports 24 a and 24 b, as shown, in FIGS. 2A through 2D .
- end of the input and output ports 24 a, 24 b of the input/output port layer 12 as well as the ends of the sots 48 R and 48 S of the coolant pass-through layer 14 and the slots S and R in the coolant distribution layer 16 are rounded rather than being square as shown in FIG. 1B for an exemplary one of the slots, here one of the slots 48 R to reduce stress around the corners of the slots.
- FIGS. 3, 3A, and 4 the relationship between coolant flow, the supply channels S and the return channels R in the coolant distribution layer 16 and, micro-channels 26 , substrate 30 and the active layer 32 and the FETs 40 , 42 is shown.
- partitions 50 FIG. 1A and FIG. 4
- the coolant channels 26 are separated one from another by partitions 50 to provide the channels 26 with discontinuities along the lengths of the channels 26 .
- This partitioning provides locally reduced fluid temperature, which, in turn provides lower FET temperature by maximizing conjugate conduction/convection heat transfer.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
- This invention was made with government support under Contract No. FA8650-14-C-7469 awarded by the Department of the Air Force. The government has certain rights in this invention.
- This disclosure relates generally to semiconductor cooling structures and more particularly to coolant distribution structures for enabling coolant to flow in very close proximity to active semiconductor devices, such as Field Effect Transistors (FETs), of monolithic microwave integrated circuits (MMICs).
- As is known in the art, coolant structures are used to provide coolant in MMICs. One such structure is described in U.S. Pat. No. 7,548,424, inventors Altman, et al. issued Jun. 16, 2009 entitled, “Distributed transmit/receive integrated microwave module chip level cooling system”assigned to the same assignee as the present patent application. While such coolant structure provides coolant for MMIC chips in many applications, as power handling requirements increase there are applications requiring even higher coolant capacity and efficiencies. More particularly, in many MMIC chips having very high density active semiconductor devices it is highly desirable to provide liquid coolant flow in close proximity to the active devices. This introduces challenges from a hardware design and fabrication standpoint and introduces complexity from an electrical standpoint which a cooling structure must overcome.
- In accordance with the present disclosure, a coolant distribution structure for an MMIC is provided having: an input/output port having at least one input port for receiving a coolant for transmission to coolant channels in the MMIC and at least one output port for exiting the coolant after such coolant has cooled active devices in the MMIC; a coolant pass-through layer to receive the coolant from the at least one input port and having structure to enable flow through the coolant channels by inhibiting such received coolant from passing directly to the output port; a distribution layer for receiving coolant passing from the coolant pass-through layer and distributing such received coolant to the cooling channels to absorb heat generated by the active devices and then directing the heated coolant back to the at least one output port of the input/output port layer.
- In one embodiment, a coolant distribution structure is provided for a monolithic integrated circuit (MMIC), the MMIC having a substrate with an active device layer on the top surface of the substrate and a plurality of coolant channels formed on a bottom surface of the substrate. The coolant distribution structure includes: an input/output port layer having at least one input port for receiving a coolant for transmission to the plurality of coolant channels and an output port for exiting the coolant after such coolant has cooled active devices in the active device layer; a coolant pass-through layer disposed on the input/output port layer to receive the coolant from the input port and having a input transmission structure portion configured to inhibit such received coolant from passing directly to the output port of the input/output port layer prior to such received coolant being transmitted to the plurality of cooling channels; and a coolant distribution layer mounted to the bottom surface of the substrate fir receiving coolant passing from pass-through layer, the coolant distribution layer distributing such received coolant to the plurality of cooling channels to absorb heat generated by the active devices, and then re-directing heated coolant back to the output port of the input/output layer via the pass-through layer. The pass-through layer and the coolant distribution layer are configured to have a coolant transmission structure that allows intake of cold coolant from the input/output port layer in only the input port and exhaust of heated coolant back to the output port layer to prevent short circuiting (that is, a direct flow) of cold and heated coolant streams.
- In one embodiment, the input/output port layer has a pair of spaced input ports and wherein the output port is disposed between the pair of input ports.
- In one embodiment, the coolant passthrough layer has formed therein: two sets of a plurality of parallel slots, each one of the sets being disposed over a corresponding one of the pair of input ports, the slots in the two sets being aligned one with the other to provide the input transmission structure portion; and a third set of parallel slots disposed over the output port, the slots in the third set being offset laterally from the slots in said two sets to provide the output transmission structure portion.
- In one embodiment, the slots in said two sets of parallel slots are disposed in a pair of rows and the slots in the second set of slots are disposed in a row parallel to said pair of rows.
- In one embodiment, the slots in the said third. set of parallel slots disposed over the output port are disposed in a row parallel to the pair of rows of slots disposed over the input ports.
- In the embodiment, the slots in the said third row of slots are offset laterally from and disposed centrally between the rows of slots disposed over the input ports.
- In one embodiment, the slots in said two sets and in the third set are elongated along a direction perpendicular to the rows.
- In one embodiment, the input and the output ports in the input/output port layer are elongated a width of the MMIC and span the rows of slots in the distribution layer and the pass through layer.
- In one embodiment, the coolant distribution layer has formed therein a plurality of parallel slots, one set of the parallel slots being supply slots and another set of the parallel slots being return slots, the set of supply slots being in aligned with the slots in the pair of a first plurality of parallel slots in the pass-through layer and the set of return slots being in aligned with the slots in the second set of slots in the pass-through layer.
- In one embodiment, the slots in the coolant distribution layer are parallel to the slots in the coolant pass-through layer.
- In one embodiment, the slots in the distribution layer and the pass-through layer are configured transverse to the input and the output ports of the input/output port layer such that the direction of coolant flow in the slots in the distribution layer is perpendicular to the long dimension of the input port and the output port of the input/output port layer.
- In one embodiment, the coolant channels in the MMIC are blind-etched into the MMIC from the back side to form an integrated heat sink with the un-etched portion of the MMIC.
- In one embodiment, the coolant channels have a width span of a few tens of microns and a depth of more than 250 μm in high conductivity diamond to be characterized as high aspect ratio diamond micro-channels.
- In one embodiment, the coolant channels in the substrate are elongated along a direction perpendicular to the slots in the distribution layer.
- In one embodiment, sections of the coolant channels are separated one from another by partitions to provide the channels with discontinuities along the lengths of the channels.
- In one embodiment the partitions are disposed under the active devices.
- The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
-
FIG. 1 is an isometric view of an monolithic integrated circuit (MMIC) chip having active devices therein cooled by a coolant distribution structure, partially cut away, and mounted to a back-side the MMIC according to the disclosure; -
FIG. 1A is an exploded view, of an input/output layer, a coolant pass-through layer, a coolant distribution layer, and an MMIC chip ofFIG. 1 , having a substrate with an active layer on the upper surface of the substrate thereof and having formed in the back side thereof micro-channels according to the disclosure; -
FIG. 1B is an enlarged, plan view a portion of an end of one slot in one of the layers of the coolant distribution structure ofFIG. 1 , such enlarged portion being partially circled by an arrow inFIG. 1A ; -
FIG. 2 is a plan view of the coolant distribution structure ofFIG. 1 viewed from the bottom of an input/output port layer and exposed portions of a coolant distribution layer of the structure according to the disclosure; -
FIGS. 2A-2D are cross-sectional views of the coolant distribution structure ofFIG. 1 taken along lines 2A-2A-2D-2D, respectively inFIG. 2 according to the disclosure, including a coolant distribution layer and an MMIC chip formed thereon according to the disclosure; -
FIG. 3 is a plan view of the coolant distribution layer of the coolant distribution structure ofFIG. 1 with the substrate thereon, the substrate having micro-channels in a back surface thereof, -
FIG. 3A is a cross sectional view taken along one of the micro-channels alongline 3A-3A ofFIG. 3 according to the disclosure; and -
FIG. 4 is a plan view of the top surface of the substrate of the coolant distribution structure ofFIG. 2 , shown in relationship with an isometric view of the coolant distribution structure with the underling MMIC chip ofFIG. 1 according to the disclosure; an enlarged plan view of the coolant distribution layer, substrate and active layer of the coolant distribution structure ofFIG. 1 being shown inFIG. 4A and an enlarged isometric view of the coolant distribution layer, substrate and active layer of the coolant distribution structure ofFIG. 1 being shown inFIG. 4B . - Like reference symbols in the various drawings indicate like elements.
- Referring now to
FIGS. 1 and 1A , acoolant distribution structure 10 is shown having: amanifold 11 for mounting to the hack side of a MMIC, here aMMIC chip 20. Here themanifold 11 is a silicon manifold having: a bottom, silicon input/output port layer 12 (FIG. 1A ), a middle, silicon coolant pass-throughlayer 14, and a upper siliconcoolant distribution layer 16, here, for example, fabricated from two SiO2 bonded silicon (Si) wafers 15A 15B. It is noted that that while the input/output port layer 12 and the coolant pass-throughlayer 14 may be formed from two separate silicon wafers, here, in this embodiment, the input/output port layer 12 and the coolant pass-throughlayer 14 are formed using the same wafer 15A; it being noted that for purposes of illustration, the input/output port layer 12 and the coolant pass-throughlayer 14, although here formed from a single wafer 15A, are shown exploded inFIG. 1A . More particularly, the wafer 15A is processed first from one side using photolithographic-etching techniques to form, in about one half the thickness of the wafer, the input/output layer 12 and is next processed from the other side to form in the remaining thickness of the wafer 15A, the coolant pass-throughlayer 14. The wafer 15B is processed from only one side using photolithographic-etching techniques to form thecoolant distribution layer 16. After processing the two wafers 15A and 15B as described, the two waters 15A and 15B are coated with silicon oxide, polished and then bonded together using plasma activated oxide bonding. It should be noted that the cross sectional views ofFIGS. 2A-2D and 3A indicate, for illustration, the input/output port layer 12 and the coolant pass-throughlayer 14 as two separate silicon members. - The MMIC
chip 20 includes adiamond substrate 30 having formed on an upper surface thereof, here for example by MOCVD, anactive device layer 32, here for example, GaN. More particularly thesubstrate 30 of a monolithic integrated circuit (MMIC) chip 20 (FIG. 1A ) is fabricated from high conductivity Chemically Vapor Deposited (CVD) diamond gown to a thickness of here, for example, 300 μm, having theback side 18 thereof polished to <1 μm Ra. The CVDgrown diamond substrate 30 is dry-etched, using for example, a Reactive Ion Etch (RIE) to form a plurality of blind, coolant micro-channels 26, here for example, with an aspect ratio of approximately 10:1. - More particularly, the
MMIC chip 20 coolant micro-channels 26 (FIG. 2A ), here etched out of a solid diamond blank, with blind micro-channel terminations on thesubstrate 30; thus, the micro-channels 26 andsubstrate 30 are integrated with one another being part of the same diamond blank. - The active device layer 32 (
FIG. 1 ), here for example, a 0.5 to 2 μm thick layer of Gallium Nitride (GaN), here, for example, using a metalorganic chemical vapor deposition (MOCVD) process. A hermetic seal, not shown, is formed between theMMIC chip 20 and theSi manifold 11 comprising oflayers FIG. 1A ) on the backside surface 18 (FIG. 1A ) of thechip 20 using for example, a bonding technique described in U.S. Pat. No. 8,978,892, issued Mar. 24, 2015, entitled “Method for creating a selective solder seal interface for an integrated circuit cooling system”, inventors Davis et al., assigned to the same assignee as the present patent application. As noted above, thebackside surface 18 is polished to <1 μm Ra prior to bonding. The micro-channels 26 have an aspect ratio of greater than 10:1. Here, for example, the micro-channels 26 have a width of 25 μm, are separated one from another 25 μm, have a depth >250 μm with thediamond substrate 30 having a thickness of 300 μm. - Still more particularly, the upper surface 33 (
FIGS. 1 and 1A )—theactive device layer 32 of theMMIC chip 20 has firmed thereon, a microwave, two-stage amplifier circuit 36. Thecircuit 36 is fed RF signals received, on an input co-planar waveguide (CPW)transmission line 38; it being noted that while CPW has a strip conductor disposed between a pair of coplanar ground plane conductors (not shown), here, for convenience in illustration, only the strip conductor portion of the CPW is shown. The received RF signals are fed to thefirst amplification stage 40, here a pair of FieldEffect Transistors FETs 40, through a passive input matching network (IMN), here also, for example, CPW transmission line network (here again only the strip conductor portion of the CPW being shown). The first stage amplified signals are then fed to asecond amplification stage 42, here also a pair ofFETs 42, through a passive interstage matching network (ISMN), here also, for example, CPW transmission network. The second stage amplified signals are then passed to outputCPW transmission line 44 through a passive matching network (OMN), here also, for example, CPW transmission network. - The
manifold 11 of thecoolant distribution structure 10 receives coolant from a cooling fluid amply, not shown, through, here for example, a pair ofinput ports FIG. 1A ) and directs the received coolant tochannels 26, herein referred to as micro-channels 26 (FIGS. 2A and 2B ) formed in the back-side of theMMIC chip 20 after such coolant passes through coolant pass-throughlayer 14 and coolant distribution layer 16 (FIGS. 2, 2A and 2B ); the coolant then Absorbs heat generated by active devices, here Field Effect Transistors (FETs), here, for example, HEMTs, formed in the top surface of MMIC chip 20 (FIG. 1 ) and is then directed by thecoolant distribution structure 10 back to an exhaust, not shown, through anoutput port 28 of the input/output port layer 12 through thecoolant distribution layer 16, coolant pass-throughlayer 14, as shown inFIGS. 2A, 2B, 2C and 2D . - Thus,
coolant manifold 11 feeds coolant to thecoolant channels 26 in thechip 20 to provide coolant flow in close proximity to the active theFETS coolant channels 26, as noted above, have a blind end on thesubstrate 30 which enables electrical isolation between theactive transistors FETs substrate 30 thickness. Thus, thecoolant channels 26 that are part of thechip 20 form an integrated heat sink with thechip 20. The coolingchannels 26 are micro-channels with very small effective fluid flow diameter to enable very high heat transfer rates to the fluid. These micro-channels 26 are configured in a parallel arrangement which ensures smaller heat gain by the fluid per flow path, thereby keeping the fluid and thechip 20 cool. Parallelization ofchannels 26 also enables distribution of flow over larger area of flow and shorter flow paths, which helps reduce the constriction to flow, thereby reducing pressure drop and energy requirements to drive the flow in the desired manner. The micro-channels 26 in thechip 20 do not extend continuously along the entire dimension of thechip 20 in the direction of the flow. Instead, the micro-channels 26 are separated along its length bypartitions 50 formed in the hack side of thesubstrate 30,FIG. 1A . That is, thechannels 26 are partitioned (broken) in regions in the vicinity ofFETS FETs substrate 30, here diamond, partitions which spreads the heat, thereby reducing the heat density that the cooling fluid is required to alleviate. This strategy reduces the operating temperature of the active devices by means providing cooler fluid zones local to the heated device. The blind ending of the micro-channels 26 in thechip 20 is such that the cooling fluid is separated from the electrically active devices (theFETs 40, 42) by means of adiamond substrate 30. The substrate thickness, or the separation, between the fluid and active devices, is 50 μm for a 2-6 GHz MMIC in one embodiment. TheSi manifold 11 and thediamond chip 20 are adhered together to form one complete fluid routing and cooling structure by means of a thin hermetic bonding interface, for example, a 6 μm layer of metallic solder that is selectively deposited on the adhering surfaces of thediamond chip 20 and theSi manifold 11. The manifold 11 layers; the input/output layer 12, the pass-throughlayer 14 and thecoolant distribution layer 16 are adhered to each other with SiO2, thereby forming a multi-layeredSi manifold structure 11. The fluid routing anddiamond cooling structure 10 configured this way is tailored to the RF device geometry to enable precise, uniform and targeted distribution of coolant on the heated chip substrate surface. - With such structure, cooling channels are micro-channels configured in a massively parallel manifold arrangement to minimize pressure drop and maximize convective heat transfer performance. The micro-channels 26 are of similar width to enable creation using dry etching techniques. Partitions 50 (
FIG. 1A ) betweenmicro-channels 26 are strategically located in proximity to theHEMT 20 being cooled to maximize conjugate (convection/conduction) heat transfer performance. - The micro-channels 26 are separated from the active GaN surface by a minimum distance to ensure minimal interaction between electrical fields and the coolant (e.g., 50 μm for a 2-6 GHz MMIC). Bonding layers form a thin hermetic interface between the diamond micro-channels 26 and a
Si manifold 11 fluid distribution structure. The bonding layers are selectively deposited solder. TheSi manifold 11 design that is tailored to the RF device geometry to enable precise, uniform and targeted distribution of coolant to the diamond micro-channels, while keeping the coolant supply pressure drop and power. - Referring now again, to
FIGS. 2, 2A and 2B , thecoolant distribution structure 10 includes: the input/output port layer 12 having the pair ofinput ports micro-coolant channels 26 and theoutput port 28, disposed between the pair ofinput ports FETs active device layer 32. The coolant pass-throughlayer 14 disposed, and bonded to, the input/output port layer 12 receives the coolant from the pair ofinput port - The coolant pass-through layer 14 (
FIGS. 1A, 2A and 2B ) has three sections, 46 a, 46 b, and 46 c:sections 46 a and 46 c each have a plurality of, here for example, seven spaced supply slots 48S. Section 46 b is disposed betweensections 46 a and 46 c and includes a plurality of, here for example, eightreturn slots 48R. The slots 48S are disposed in rows disposed above theinput ports slots 48R are disposed in a row disposed above theoutput port 28. It is noted that theinput ports output port 28 are elongated along the X-direction (FIG. 1A ), parallel to the direction of the rows ofslots 48S, 48R in the three sections, 46 a, 46 b, and 46 c which are aligned also along the X-direction. It is also noted that theslots 48S, 48R are elongated along a direction along the Y-direction which is perpendicular to the elongated direction of theinput ports output port 28. It is also noted that while the supply slots 48S insections 46 a and 46 c are aligned along the X-direction, thereturn slots 48R are offset, along the X- and Y-directions, from the supply slots 48S. That is, while each one of the supply slots 48S in sections 46 a faces (when looking along the Y-direction) a corresponding one of the supply slots 48S insection 46 c, each one of thereturn slots 48R faces (when looking along the Y-direction) a region between a pair of the supply slots 48S. - The coolant distribution layer 16 (
FIG. 1A ) is integral with the coolant pass-throughlayer 14 and includes a plurality of parallel, channels S and R; S being a supply channels and R being a return channels. The channels S and R are elongated along the Y-direction. Here, there are seven supply channels S and eight return channels R, The supply channels S are disposed over the supply slots 48S and the return channels are disposed over thereturn slots 48R. It is also not that the micro-channels 26 are elongated along the X-direction; a direction perpendicular to the elongated direction of the supply and return channels S and R. - With such an arrangement, the three sections, 46 a, 46 b, and 46 c of the coolant pass-through
layer 16 provide an input transmission structure portion configured to inhibit received coolant from passing directly to theoutput port 28 of the input/output port layer 12 prior to such received coolant being transmitted to the plurality of cooling micro-channels 26 and enabling such heat absorbed coolant to pass directly to theoutput port 28 of the input/output port layer 12 without mixing with cooler fluid in theinput ports FIGS. 2A through 2D . - It should be noted that the end of the input and
output ports output port layer 12, as well as the ends of thesots 48R and 48S of the coolant pass-throughlayer 14 and the slots S and R in thecoolant distribution layer 16 are rounded rather than being square as shown inFIG. 1B for an exemplary one of the slots, here one of theslots 48R to reduce stress around the corners of the slots. - Referring now to
FIGS. 3, 3A, and 4 , the relationship between coolant flow, the supply channels S and the return channels R in thecoolant distribution layer 16 and, micro-channels 26,substrate 30 and theactive layer 32 and theFETs FIG. 1A andFIG. 4 ) are located between all micro-channels 26 in proximity to theFETs coolant channels 26 are separated one from another bypartitions 50 to provide thechannels 26 with discontinuities along the lengths of thechannels 26. This partitioning provides locally reduced fluid temperature, which, in turn provides lower FET temperature by maximizing conjugate conduction/convection heat transfer. - A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, other MMIC circuits may be used with the coolant distribution structure. Further, the number of supply slots and return slots and their relative configuration may differ from one MMIC to another MMIC. Likewise, the number of micro channels may differ from one MMIC to another MMIC. Accordingly, other embodiments are within the scope of the following claims.
Claims (18)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/734,372 US9502330B1 (en) | 2015-06-09 | 2015-06-09 | Coolant distribution structure for monolithic microwave integrated circuits (MMICs) |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/734,372 US9502330B1 (en) | 2015-06-09 | 2015-06-09 | Coolant distribution structure for monolithic microwave integrated circuits (MMICs) |
Publications (2)
Publication Number | Publication Date |
---|---|
US9502330B1 US9502330B1 (en) | 2016-11-22 |
US20160365300A1 true US20160365300A1 (en) | 2016-12-15 |
Family
ID=57287760
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/734,372 Active US9502330B1 (en) | 2015-06-09 | 2015-06-09 | Coolant distribution structure for monolithic microwave integrated circuits (MMICs) |
Country Status (1)
Country | Link |
---|---|
US (1) | US9502330B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10020243B2 (en) | 2016-03-08 | 2018-07-10 | Toyota Motor Engineering & Manufacturing North America, Inc. | Power electronics assemblies having a wide bandgap semiconductor device and an integrated fluid channel system |
US10121729B2 (en) * | 2016-07-25 | 2018-11-06 | Toyota Motor Engineering & Manufacturing North America, Inc. | Power electronics assemblies having a semiconductor device with metallized embedded cooling channels |
JP2019208732A (en) * | 2018-06-01 | 2019-12-12 | キヤノンメディカルシステムズ株式会社 | Inverter device, gradient magnetic field power supply and magnetic resonance imaging device |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10401099B2 (en) | 2016-10-05 | 2019-09-03 | Raytheon Company | Transparent heat exchanger |
US11193722B2 (en) | 2018-05-01 | 2021-12-07 | Dana Canada Corporation | Heat exchanger with multi-zone heat transfer surface |
EP3564992B1 (en) * | 2018-05-02 | 2021-07-07 | EKWB d.o.o. | Fluid-based cooling device for cooling at least two distinct first heat-generating elements of a heat source assembly |
US11177192B2 (en) * | 2018-09-27 | 2021-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device including heat dissipation structure and fabricating method of the same |
US11791312B2 (en) * | 2018-12-04 | 2023-10-17 | Qorvo Us, Inc. | MMICs with backside interconnects for fanout-style packaging |
US11521914B2 (en) * | 2018-12-27 | 2022-12-06 | Intel Corporation | Microelectronic assemblies having a cooling channel |
US11626340B2 (en) | 2019-12-12 | 2023-04-11 | Qorvo Us, Inc. | Integrated circuit (IC) package with embedded heat spreader in a redistribution layer (RDL) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7548424B2 (en) * | 2007-03-12 | 2009-06-16 | Raytheon Company | Distributed transmit/receive integrated microwave module chip level cooling system |
JP6093186B2 (en) * | 2013-01-11 | 2017-03-08 | 本田技研工業株式会社 | Semiconductor module cooler |
US8987892B2 (en) | 2013-05-10 | 2015-03-24 | Raytheon Company | Method for creating a selective solder seal interface for an integrated circuit cooling system |
-
2015
- 2015-06-09 US US14/734,372 patent/US9502330B1/en active Active
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10020243B2 (en) | 2016-03-08 | 2018-07-10 | Toyota Motor Engineering & Manufacturing North America, Inc. | Power electronics assemblies having a wide bandgap semiconductor device and an integrated fluid channel system |
US10032694B2 (en) | 2016-03-08 | 2018-07-24 | Toyota Motor Engineering & Manufacturing North America, Inc | Power electronics assemblies having a semiconductor cooling chip and an integrated fluid channel system |
US10224265B2 (en) | 2016-03-08 | 2019-03-05 | North America, Inc. | Power electronics assemblies having a semiconductor cooling chip and an integrated fluid channel system |
US10121729B2 (en) * | 2016-07-25 | 2018-11-06 | Toyota Motor Engineering & Manufacturing North America, Inc. | Power electronics assemblies having a semiconductor device with metallized embedded cooling channels |
JP2019208732A (en) * | 2018-06-01 | 2019-12-12 | キヤノンメディカルシステムズ株式会社 | Inverter device, gradient magnetic field power supply and magnetic resonance imaging device |
JP7062524B2 (en) | 2018-06-01 | 2022-05-06 | キヤノンメディカルシステムズ株式会社 | Inverter device, gradient magnetic field power supply, and magnetic resonance imaging device |
Also Published As
Publication number | Publication date |
---|---|
US9502330B1 (en) | 2016-11-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9502330B1 (en) | Coolant distribution structure for monolithic microwave integrated circuits (MMICs) | |
US10566265B2 (en) | Electronic assemblies having a cooling chip layer with impingement channels and through substrate vias | |
US11121060B2 (en) | Electronics assemblies and cooling structures having metalized exterior surface | |
US9484284B1 (en) | Microfluidic impingement jet cooled embedded diamond GaN HEMT | |
US7353859B2 (en) | Heat sink with microchannel cooling for power devices | |
US8482919B2 (en) | Power electronics card assemblies, power electronics modules, and power electronics devices | |
US6388317B1 (en) | Solid-state chip cooling by use of microchannel coolant flow | |
US5998240A (en) | Method of extracting heat from a semiconductor body and forming microchannels therein | |
US10192814B2 (en) | Electronic assemblies having a cooling chip layer with fluid channels and through substrate vias | |
EP2228821B1 (en) | Methods for Making Millichannel Substrate | |
US10224265B2 (en) | Power electronics assemblies having a semiconductor cooling chip and an integrated fluid channel system | |
US8929071B2 (en) | Low cost manufacturing of micro-channel heatsink | |
US9721909B1 (en) | Hybrid microwave integrated circuit | |
US8766433B2 (en) | Electronic chip having channels through which a heat transport coolant can flow, electronic components and communication arm incorporating said chip | |
EP1287559A1 (en) | Power transistors for radio frequencies | |
US7414316B2 (en) | Methods and apparatus for thermal isolation in vertically-integrated semiconductor devices | |
US6545543B2 (en) | Small aspect ratio MMIC power amplifier layout | |
US7391067B1 (en) | Hybrid microwave integrated circuit | |
US20230380106A1 (en) | Systems for cooler devices and cooling manifolds | |
US9735088B2 (en) | Systems and methods for thermal control of integrated circuits | |
TW202109795A (en) | Heterogeneous multi-layer mmic assembly |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RAYTHEON COMPANY, MASSACHUSETTS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GUPTA, ANURAG;ALTMAN, DAVID H.;MILNE, JASON G.;REEL/FRAME:035871/0843 Effective date: 20150608 |
|
AS | Assignment |
Owner name: RAYTHEON COMPANY, MASSACHUSETTS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KOONTZ, CHRISTOPHER R.;REEL/FRAME:037430/0219 Effective date: 20160107 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |