US20160359332A1 - Power converter circuit with ac output and at least one transformer - Google Patents
Power converter circuit with ac output and at least one transformer Download PDFInfo
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- US20160359332A1 US20160359332A1 US15/243,656 US201615243656A US2016359332A1 US 20160359332 A1 US20160359332 A1 US 20160359332A1 US 201615243656 A US201615243656 A US 201615243656A US 2016359332 A1 US2016359332 A1 US 2016359332A1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
-
- H02J3/383—
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
- H02J3/381—Dispersed generators
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/4807—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode having a high frequency intermediate AC stage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2300/00—Systems for supplying or distributing electric power characterised by decentralized, dispersed, or local generation
- H02J2300/20—The dispersed energy generation being of renewable origin
- H02J2300/22—The renewable source being solar energy
- H02J2300/24—The renewable source being solar energy of photovoltaic origin
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2300/00—Systems for supplying or distributing electric power characterised by decentralized, dispersed, or local generation
- H02J2300/20—The dispersed energy generation being of renewable origin
- H02J2300/22—The renewable source being solar energy
- H02J2300/24—The renewable source being solar energy of photovoltaic origin
- H02J2300/26—The renewable source being solar energy of photovoltaic origin involving maximum power point tracking control for photovoltaic sources
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
- H02J3/388—Islanding, i.e. disconnection of local power supply from the network
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/0077—Plural converter units whose outputs are connected in series
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/56—Power conversion systems, e.g. maximum power point trackers
Definitions
- DC/AC converters are connected in series, where each of these converters receives a DC supply voltage from a PV module.
- a central control unit is employed to synchronize the individual DC/AC converters in a multi-level switching pattern. This system requires constant synchronized control of all individual units.
- a second embodiment relates to a method that includes generating at least one synchronization signal by a synchronization circuit, outputting an output current by at least one series circuit comprising a plurality of converter units, wherein at least one of the converter units comprises a transformer, and generating an output current by at least one of the plurality of converter units such that at least one of a frequency and a phase of the generated output current is dependent on the synchronization signal.
- FIG. 6 illustrates an embodiment of the DC/AC converter of FIG. 5 in detail
- FIG. 7 which includes FIGS. 7A to 7C , illustrates different embodiments of switches that may be used in the DC/AC converter of FIG. 6 ;
- FIG. 9 illustrates a first branch of the control circuit of FIG. 8 in detail
- FIG. 15 illustrates a further embodiment of the control circuit of one DC/AC converter
- FIG. 16 illustrates an embodiment of the DC/DC converter implemented with two interleaved boost converter stages
- FIG. 18 illustrates a second embodiment of a control circuit for the DC/DC converter of FIG. 16 ;
- FIG. 21 illustrates a first embodiment of a controller implemented in the DC/AC converter unit of FIG. 19 ;
- FIG. 23 illustrates an embodiment of a power converter circuit having a plurality of converter units organized in two series circuits being connected in parallel;
- FIG. 27 illustrates a first embodiment of a signal generator in the converter unit of FIG. 26 ;
- FIG. 28 illustrates timing diagrams of signals occurring in the signal generator of FIG. 27 ;
- FIG. 35 illustrates a further embodiment of a power converter circuit
- FIG. 38 illustrates an embodiment of a power converter circuit including an unfolding circuit connected between a series circuit with converter units and output terminals;
- FIG. 1 illustrates a first embodiment of a power converter circuit (power inverter circuit) 4 for converting a plurality of n (at least two) DC input voltages V 3 1 , V 3 2 , V 3 n into one AC output voltage v 1 .
- the power converter circuit includes a plurality of n (at least two) converter units 2 1 , 2 2 , 2 n , with n ⁇ 2.
- Each power converter unit 2 1 , 2 2 , 2 n further includes an output capacitance C 1 , C 2 , C n connected between the individual output terminals 23 1 , 24 1 , 23 2 , 24 2 , 23 n , 24 n and provides an output current i 1 1 , i 1 2 , i 1 n .
- the output current of one converter unit 2 1 , 2 2 , 2 n is the current received at a circuit node common to the output capacitance C 1 , C 2 , C n and one of the output terminals.
- the output current of the converter unit 2 1 is the current flowing into the circuit node at which the output capacitor C 1 is connected to the first output terminal 23 1 .
- the DC power sources 3 implemented as PV arrays are only schematically illustrated in FIG. 1 . These PV arrays each include at least one solar cell. Some exemplary embodiments of PV arrays including at least one solar cell are illustrated in FIGS. 2A to 2C .
- FIG. 2A illustrates a first embodiment. In this embodiment, the PV array 3 includes only one solar cell 31 .
- one PV array 3 includes a string of m solar cells 31 , 3 m wherein m>1, connected in series.
- p strings of solar cells are connected in parallel, wherein p>1.
- Each of the switches 42 1 , 42 2 , 42 3 , 42 4 receives a control signal S 42 1 , S 42 2 , S 42 3 , S 42 4 at its control terminal.
- These control signals S 42 1 -S 42 4 are provided by a drive circuit 45 dependent on the reference signals S REF received from the controller 5 .
- the drive signal S 42 1 -S 42 4 are pulse-width modulated (PWM) drive signals configured to switch the corresponding switch 42 1 - 42 4 on and off. It should be noted that a switching frequency of the PWM signals S 42 1 -S 42 4 is significantly higher than a frequency of the alternating reference signal S REF .
- An integrating circuit receives the output signal from the linear filter, integrates the output signal of the linear filter 514 and provides the frequency and phase signal (the phase angle signal) S ⁇ t , from which the VCO (see 52 in FIG. 8 ) generates the reference signal S i1-REF . Integrating the output signal of the linear filter in the time domain corresponds to a multiplication with 1/s in the frequency domain.
- the DC/DC converter 6 can be implemented like a conventional DC/DC converter.
- a first embodiment of a DC/DC converter 6 that can be used in the converter unit 2 is illustrated in FIG. 12 .
- the DC/DC converter 6 illustrated in FIG. 12 is implemented as a boost converter.
- This type of converter includes a series circuit with an inductive storage element 64 , such as a choke, and a switch 65 between the input terminals of the DC/DC converter 6 , where the input terminals of the DC/DC converter 6 correspond to the input terminals 21 , 22 of the converter unit 2 .
- FIG. 13 A first embodiment of the PWM control circuit 67 is illustrated in FIG. 13 . Like in FIG. 8 (which illustrates an embodiment of the controller 5 ) in FIG. 11 functional blocks of the controller 67 are illustrated. These functional blocks can be implemented as analog circuits, as digital circuits or can be implemented using hardware and software.
- the control circuit 67 calculates an error signal S ERR from the input voltage signal S v3 and the reference signal S REF-V3 .
- the error signal S ERR is calculated by either subtracting the input voltage signal V 3 from the reference signal S REF-V3 (as illustrated) or by subtracting the reference signal S REF-V3 from the input voltage signal S v3 .
- the error signal S ERR is provided by a subtraction element 671 that receives the input voltage signal S v3 and the reference signal S REF-V3 .
- a PWM driver 673 receives the duty cycle signal S DC and a clock signal CLK and generates the drive signal S 65 as a PWM signal having a switching frequency as defined by the clock signal CLK and a duty cycle as defined by the duty cycle signal S DC .
- This driver 673 can be a conventional PWM driver that is configured to generate a PWM drive signal based on a clock signal and a duty cycle information. Such drivers are commonly known, so that no further information are required in this regard.
- the boost converter according to FIG. 12 does not only provide a load to the DC source 3 in order to operate the DC source 3 in its maximum power point.
- This boost converter also generates an output voltage V 6 received by the DC/AC converter 4 (see FIG. 11 ) that is higher than the input voltage V 3 .
- the boost converter is implemented such that the output voltage V 6 is higher than a peak voltage of the output voltage v 2 of the DC/AC converter, but lower than a voltage blocking capability of the switches (see 42 1 - 42 4 in FIG. 6 ) implemented in the DC/AC converter.
- the DC/DC converter 6 may also be implemented as a buck converter.
- This buck converter includes a series circuit with an inductive storage element 64 , such as a choke, and a switch 65 between the first input terminal 21 and the first output terminal 61 .
- a freewheeling element 66 such as a diode, is connected between the second output terminal 62 and a circuit node common to the inductive storage element 64 and the switch 65 .
- a capacitive storage element 63 such as a capacitor, is connected between the input terminals 21 , 22 .
- the subtraction element 56 generates a further error signal based on a difference between the input voltage signal S v6 and the reference signal S V6-REF .
- the filter 55 receives the further error signal and generates an amplitude signal S AMPL representing an amplitude of the reference signal S REF from the further error signal.
- the filter may have a P-characteristic, an I-characteristic, a PI-characteristic, or a PID-characteristic.
- the amplitude signal S AMPL and the output signal of the VCO 52 are received by the multiplier 57 that provides the output current reference signal S i1-REF .
- each converter stage includes a rectifier element 66 1 , 66 2 such as a diode, connected between a circuit node common to the corresponding inductive storage element 64 1 , 64 2 and the corresponding switch 65 1 , 65 2 and the first output terminal 61 of the DC/DC converter 6 .
- the second output terminal 62 of the DC/DC converter 6 is connected to the second input terminal 22 .
- the control circuit (controller) 67 of the DC/DC converter 6 generates two PWM drive signals S 65 1 , S 65 2 , namely a first drive signal S 65 1 for the switch 65 1 of the first converter stage 60 1 , and a second drive signal S 65 2 for the switch 65 2 of the second converter stage 60 2 .
- the first and second boost converter stages 60 1 , 60 2 are operated interleaved, which means that there is a time offset between the switching cycles of the first switch 65 1 and the switching cycles of the second switch 65 2 .
- FIG. 19 illustrates a further embodiment of a converter unit 2 with a DC/AC converter 4 .
- the converter unit 2 may further include a DC/DC converter 6 (see FIG. 9 ) connected between the input terminals 21 , 22 and the DC/AC converter.
- a DC/DC converter 6 see FIG. 9
- the DC/DC converter 4 receives the input voltage V 3 of the converter unit 2 or the output voltage of the DC/DC converter 4 (not illustrated in FIG. 19 ) as an input voltage.
- the DC/AC converter 4 receives the input voltage V 3 .
- the controller 5 for generating the reference signal S REF according to FIG. 19 may correspond to the controllers illustrated in FIGS. 8 and 15 with the difference that the oscillating signal provided at the output of the oscillator 53 is rectified.
- An embodiment of the controller 5 according to FIG. 19 is illustrated in FIG. 21 .
- This controller 5 corresponds to the controller according to FIG. 8 with the difference that the output signal of the filter 53 is received by a rectifier 58 that generates a rectified version of the oscillating output signal of the oscillator 53 .
- this is equivalent to forming the absolute value of the oscillating output signal of the oscillator 53 .
- the reference signal S REF is available at the output of the rectifier 58 .
- the controller receives the output current signal S i1 representing the output current i 1 and the synchronization signal S v1 for generating the reference signal S REF .
- this is only an example. It would also be possible to generate the reference signal S REF based on signals representing the output voltage v 80 and the output current i 80 of the buck converter 80 . In this case, the reference signal is generated such that output current i 80 and the output voltage v 80 of the buck converter 80 have a given phase difference.
- the operating principle of a power converter circuit 1 including DC/AC converters as illustrated in FIG. 19 will now be explained with reference to FIGS. 1 and 19 .
- the explanation will be based on the assumption that the voltage of the power grid 100 is a sinusoidal voltage so that an output current i 1 with a sinusoidal waveform is desired. Further, it is assumed that the input powers of the individual DC/AC converters is zero, while the power grid voltage v N is applied to the input terminals 11 , 12 and the bridge circuits 85 in the individual converter units are in operation.
- the smoothing capacitors 89 of the buck converters are connected in series between the output terminals 11 , 12 . When the individual capacitors 89 have the same size, the voltage across each of these capacitors 89 is 1/n times the power grid voltage v N .
- the synchronization circuit 10 can be implemented as a voltage measurement circuit that measures the external AC voltage v 1 and that generates the at least one synchronization signal S v1 such that the synchronization signal is a continuous signal representing the external AC voltage v 1 and, therefore, having the same frequency and phase as the external AC voltage v 1 .
- FIG. 24 illustrates a further embodiment of the synchronization circuit 10 .
- phase shift between the output currents i 1 of the individual converter units 2 and the external AC voltage v 1 can be adjusted through the phase-shift signal SPS, so that there is no need to individually provide phase shift signals (S 100 in FIGS. 15, 21 and 22 ) to the individual converter units 2 .
- phase shift signals S 100 in FIGS. 15, 21 and 22
- standard power line communication circuits can be used for the communication between the synchronization circuit 10 and the individual converter units 2 since the output current Because i OUT of the converter circuit is an AC current.
- the power line of the converter circuit 1 which is the line carrying the output current i OUT and connecting the outputs of the individual converter units 2 is used for the communication.
- a first power line communication interface (not shown) coupled to the power line receives the synchronization signal S V1 and forwards the synchronization signal S v1 suitably modulated via the power line to the individual converter units 2 .
- Each converter unit includes a corresponding power line communication interface coupled to the power line and configured to receive and demodulate the modulated synchronization signal S v1 .
- the synchronization signal S v1 is a pulse signal including a sequence of signal pulses and the individual converter 2 units are configured to generate a continuous signal having a frequency and a phase from the pulse signal.
- the pulsed synchronization signal S v1 is only transmitted for a short time when a frequency and/or phase of the pulsed signal changes. This means, only a short sequence with some cycles of the pulsed signal S v1 is transmitted, while after the transmission of the sequence the pulsed signal is interrupted for a time period significantly longer than one cycle period. This interruption may be several seconds or several minutes.
- a clock generator receives the pulsed signal S v1 . The clock generator is configured to measure the frequency of the pulsed signal S v1 and to generate a clock signal provided to the integrator with a frequency corresponding to the measured frequency of the pulsed signal S v1 .
- the clock generator is, in particular configured to store the frequency information and to generate the clock signal even in those time periods when the pulsed signal S v1 has been switched off and updates the frequency each time a new sequence of the pulsed signal S v1 is transmitted. Equivalently, the calculation unit stores the calculated value C until a new sequence of the pulsed signal S v1 is transmitted that allows the calculation unit 201 to re-calculate the constant value.
- the synchronization signal S v1 is an AC signal that is only transmitted for a certain time period, such as, for example, for a duration corresponding to only several periods of the AC signal.
- the signal generator 20 is configured to evaluate a frequency and a phase information of the synchronization signal S v1 and is configured to generate the continuous synchronization signal S v1 based on this frequency and time information.
- the synchronization signal S v1 may be transmitted only once at the beginning of the operation of the power converter circuit 1 to the individual converter units, or may be transmitted periodically during the operation of the power converter circuit 1 .
- the power converter is, e.g., in the standby mode, when the supply voltages (V 3 1 -V 3 n in FIG. 1 ) provided by the DC power sources are too low for generating the output currents it
- the individual DC power sources 3 1 - 3 n are implemented as PV modules, this may occur at night.
- the power converter circuit 1 switches from the normal mode 901 to the standby mode 902 when a shut-down condition is met, and changes from the standby mode 902 to the normal mode when a start-up condition is met.
- the process of switching the power converter circuit 1 from the normal mode to the standby mode will be referred to as shut down and a sequence of operations involved in this process will be referred to as shut-down sequence in the following.
- the process of switching the power converter circuit 1 from the standby mode to the normal mode will be referred to as start-up and a sequence of operations involved in this process will be referred to as start-up sequence in the following.
- the power converter circuit 1 may include an operation mode controller that defines the operation mode of the power converter circuit 1 .
- the operation mode controller 50 controls the overall operation of the power converter circuit 1 .
- FIG. 31 illustrates a block diagram of a power converter circuit 1 that includes an operation mode controller 50 .
- the operation mode controller 50 can be implemented as a microprocessor, an ASIC, a digital signal processor, a state machine, or the like.
- the operation mode controller 50 is configured to detect the output voltage v OUT .
- the output voltage v OUT is the sum of the output voltages v 2 of the individual converter units 2 , where this output voltage v OUT increases after sunrise when the solar power received by the PV modules increases.
- the operation mode controller 50 controls the synchronization circuit 10 to generate the synchronization signal S v1 with the normal waveform has the connection circuit 70 connect the series circuit 2 1 - 2 n to the output terminals 11 , 12 .
- the synchronization signal S v1 in a normal mode can be a continuous AC signal, a periodic pulse signal, or an AC signal for a limited time duration.
- start-up sequence C which includes features from both, the start-up sequences A and B
- the operation mode controller 50 leaves the series circuit 2 1 - 2 n disconnected from the output terminals 11 , 12 in the standby mode.
- the converter units 2 are configured to pass through the input voltage V 3 to the output terminals 23 , 24 in the standby mode.
- switching of the power converter circuit 1 from the standby mode to the normal mode is initiated by the sunrise signal.
- switching from the standby mode to the normal mode includes changing the waveform of the synchronization signal S v1 from the standby waveform to the normal waveform.
- the individual converter units 2 automatically shut down, so that no shut-down information has to be transmitted from the operation mode controller 50 to the individual converter units 2 .
- a decrease of the output current to zero is detected by the operation mode controller 50 which may then cause the synchronization circuit 10 to generate a standby waveform of the synchronization signal S v1 .
- a first type of grid error that may occur is “islanding.”
- the power grid has a high input impedance at the input terminals 7 , 12 .
- This error can be detected by having the series circuit with the converter units 2 generate a constant output current i OUT or an AC output current i OUT with a frequency that is different from the frequency of the external AC voltage v 1 .
- the frequency of the output current i OUT (which is zero, when the output current i OUT is constant) can be adjusted through the synchronization signal S v1 .
- the synchronization circuit 10 in the fault-ride-through mode continuous to generate a continuous synchronization signal based on the frequency and phase information of the synchronization signal generated before in the normal mode, i.e., before an interruption of the external AC voltage v 1 has been detected.
- the operation mode controller may be configured to restart the power converter circuit after a given time period, such as, e.g., one minute, two minutes, etc.
- the first stage 210 is connected to the input terminals 21 , 22 that are configured to receive the supply voltage V 3 from a DC power source 3 (not shown in FIG. 37 ).
- the switches 211 - 214 of the two half-bridges can be switched on and off independently of each other by a drive circuit 230 that generates drive signals S 211 , S 212 , S 213 , S 214 received by the individual switches 211 - 214 .
- the operating principle of the first stage 210 is explained further below.
- the converter unit 2 further includes a second stage 220 coupled between the inductive storage elements 215 , 216 of the first stage and the output terminals 23 , 24 of the converter unit 3 .
- the second stage 220 that will also be referred to as boost stage in the following, includes a first switch 221 connected between the first inductive storage element 215 and the first output terminal 23 of the converter stage 2 , and a second switch 222 connected between the second output terminal 24 and a circuit node common to the first inductive storage element 215 and the first switch 221 .
- the second inductive storage element 216 is connected to the second output terminal 24 .
- each converter unit 2 provides an AC current i 1 .
- each converter unit 2 specifically the DC/AC converter 4 in each converter unit 2 , includes an H4 bridge with two half-bridges (see, for example, the H4 bridge with the first half-bridge 42 1 , 42 2 and the second half-bridge 42 3, 42 4 in FIG. 6 ).
- This output current i 1 has a frequency and a phase that is defined by the synchronization signal S v1′′ so that the output current i 1 of one converter unit has the waveform of a rectified sinusoidal signal.
- an overall output current i OUT-REC of the converter unit series circuit has the waveform of the output currents i 1 of the individual converter units 2 .
- the unfolding circuit 330 may include a bridge circuit with two half-bridges similar to the bridge circuit 85 explained with reference to FIG. 19 .
- reference character 23 1 denotes the first output terminal of the first converter unit 21 (not shown in FIG. 40 )
- reference character 23 2 denotes the second output terminal of the n-th converter unit 2 n (not shown in FIG. 40 ).
- These terminals will be referred to as first and second terminals, respectively, of the converter unit series circuit.
- the unfolding circuit transforms the series circuit output current i OUT-REC into the AC output current I OUT .
- the unfolding circuit 300 may include a first and a second half-bridge each including a first switch 301 , 303 and a second switch 302 , 304 .
- the two half-bridges are connected between output terminals 23 1 , 24 n of the converter unit series circuit.
- An output terminal of the first half-bridge 301 , 302 is connected to the first output terminal 11
- an output terminal of the second half-bridge 303 , 304 is connected to the second output terminal 12 .
- the individual converter units 2 only need to be capable of providing an output current i 1 with one polarity and not an output current that periodically changes between a positive and a negative polarity. This allows to simplify the topology of the DC/AC converter 4 in each of the converter units 2 .
- the term “DC/AC converter” is used in connection with the converters 4 explained before that generate an alternating output current from a direct input current and a direct input voltage, respectively.
- the term “DC/AC converter” is also used in connection with converters that generate an output current with a periodically varying amplitude and with only one polarity, such as an output current having the waveform of a rectified sinusoidal signal.
- a duty cycle of a PWM drive signal S 412 received by the first switch 412 may vary dependent on the boost voltage or, more specifically, dependent on an error between the boost voltage V 414 and a desired set-voltage.
- the second switch 413 acts as a freewheeling element that takes over the current through the inductive storage element 411 and charges the capacitive storage element 414 each time the first switch 412 is switched off.
- the third switch 423 is permanently on and the fourth switch 424 is permanently off.
- the first switch 421 is driven in a PWM fashion such that the output current i 1 has a waveform as defined by the reference signal S REF received by the drive circuit 426 .
- the second switch 422 acts as a freewheeling element in those time period in which the first switch 421 is switched off.
- the second switch 422 is replaced by a freewheeling element, such as a diode.
- the input terminals 21 , 22 of the individual converter units 2 where the DC power sources 3 are connected to are not galvanically isolated from the output terminals 11 , 12 where the output current hour is available.
- a galvanic isolation may be desirable.
- a power grid that receives the output current hour is a middle voltage grid supplying a voltage v 1 with an amplitude of between about 10 kV and about 20 kV, while the individual DC power sources 3 output supply voltages of several by or several 100V.
- a galvanic isolation between the inputs 21 , 22 and the output 11 , 12 is may be required.
- the rectifier circuit 622 includes the DC link capacitor 60 and is configured to generate the DC link voltage V 60 from a voltage V 69 S across the primary winding.
- the DC/DC converter 6 can be configured to control at least one of the input voltage V 3 and the DC link voltage V 60 .
- the switching circuit 621 receives the input voltage reference signal S REF-V3 , explained before.
- An MPP tracker (not shown in FIG. 44 ) may output the input voltage reference signal S REF-V3 .
- the switching circuit 621 can be configured to control the input voltage by suitably adjusting a duty cycle of the PWM voltage V 69 P applied to the primary winding 69 P .
- a boost stage 623 (illustrated in dashed lines in FIG. 46 ) is connected between the input 21 , 22 and the switching circuit 621 .
- the boost stage 623 is configured to output a boost voltage V 623 that is higher than the input voltage V 3 and that is received by the switching circuit 621 .
- the boost stage 623 may include a conventional boost converter topology.
- the boost stage 623 may receive the input voltage reference signal S REF-V3 and may be configured to control the input voltage V 3 .
- rectifier elements represented by a diode symbol can be implemented as diodes.
- rectifier elements as synchronous rectifiers (SR) including a switching element, such as a MOSFET.
- FIG. 48 illustrates a further embodiment of a DC/DC converter 6 .
- the DC/DC converter 6 of FIG. 48 includes a phase-shift zero-voltage switching (ZVS) full bridge topology.
- the switching circuit 621 includes two half bridges each including a high-side switch 605 1 , 606 1 and a low-side switch 605 2 , 606 2 connected between the input terminals 21 , 22 for receiving the input voltage V 3 .
- a series circuit with an inductive storage element 610 and the primary winding 69 P of the transformer 69 is connected between output terminals of the two half bridges.
- the transformer 69 includes a secondary winding with a center tap resulting in two secondary winding sections 69 S1 , 69 S2 .
- the rectifier circuit 622 includes a series circuit with an inductive storage element 611 and the DC link capacitor 6 o.
- the first secondary winding section 69 S1 is coupled to this series circuit 611 , 60 , via a first rectifier element 607
- the second first secondary winding section 69 S2 is coupled to the series circuit 611 , 60 via a second rectifier element 609 .
- a third rectifier element 612 is connected in parallel with the series circuit with the inductive storage element 611 and the DC link capacitor 60 . More precisely, inductive storage element 611 is connected to the first secondary winding section 69 S1 via the first rectifier element 607 and to the second secondary winding section 69 S2 via the second rectifier element 609 .
- a center tap of the secondary winding 69 S1 , 69 S2 is connected to the circuit node of the DC link capacitor 60 that faces away from inductive storage element 611 . This circuit node corresponds to the second output terminal 62 .
- a timing of switching on and switching off the individual switches 605 1 , 605 2 , 606 1 , 606 2 of the two half-bridges is such that at least some of the switches are switched on and/or switched off when the voltage across the respective switch is zero. This is known as zero voltage switching (ZVS).
- ZVS zero voltage switching
- FIG. 50 illustrates a DC/DC converter 6 according to a further embodiment that includes an LLC resonant topology.
- the switching circuit 621 of the DC/DC converter 6 includes a half-bridge with a high-side switch 805 1 and a low-side switch 805 2 connected between the input terminals 21 , 22 for receiving the DC input voltage V 3 .
- the switching circuit 621 further includes a series LLC circuit with a capacitive storage element 806 , an inductive storage element 807 , and the primary winding 69 P of the transformer 69 .
- This series LLC circuit is connected in parallel with the low-side switch 805 2 .
- a further inductive storage element 808 is connected in parallel with the primary winding 69 P .
- the transformer 69 includes a center tap resulting in two secondary winding sections, namely a first secondary winding section 69 S1 and a second secondary winding section 69 S2 coupled to the primary winding 69 P and each having the same winding sense as the primary winding 69 P .
- the first secondary winding section 69 S1 is coupled to the first output terminal 61 through a first rectifier element 809
- the second secondary winding section 69 S2 is coupled to the first output terminal 61 through a second rectifier element 810 .
- a circuit node common to the first and second secondary winding sections 69 S1 , 69 S2 is coupled to the second output terminal 62 .
- the DC link capacitor 60 is connected between the output terminals 61 , 62 .
- the DC link voltage V 6 is available between the output terminals 61 , 62 .
- reference characters S 805 1 , S 805 2 denote drive signals received by the switches 805 1 , 805 2 of the half-bridge. These drive signals S 805 1 , S 805 2 are generated by a drive circuit 812 in accordance with the input voltage signal S v3 and the reference signal S REF-V3 such that the level of the input voltage V 3 corresponds to a level represented by the reference signal S REF-V3 .
- FIG. 52 illustrates yet a further embodiment of a power converter circuit 1 .
- This power converter circuit 1 includes a DC/DC stage with a plurality of DC/DC converters that share one transformer 69 .
- the transformer 69 includes m primary windings 69 P1 - 60 Pm and n secondary windings 69 S1 - 60 Sn that are inductively coupled.
- Each of the primary windings 69 P1 - 60 Pm is coupled to a switching circuit 621 1 - 621 m , wherein each of the switching circuits 621 1 - 621 m is connected to an input with input terminals 21 1 , 21 m , 22 1 , 22 m .
- FIG. 53 illustrates a further embodiment of a power converter circuit 1 including a plurality of converter units 2 having their outputs 23 , 24 connected in series between output terminals 11 , 12 of the power converter circuit 1 .
- the individual converter units 2 can be implemented as explained with reference to FIGS. 5 to 36 herein before and each include a DC/AC converter 4 .
- a DC/DC converter 6 is connected between the input 21 , 22 of the individual converter unit 2 and the corresponding DC/AC converter.
- each of the DC/AC converters 4 outputs an AC current i 1 in accordance with the synchronization signal S V1 .
- the frequency of the AC currents is, e.g., 50 Hz or 60 Hz and is defined by the synchronization signal S V1 .
Abstract
A power converter circuit includes a synchronization circuit that is configured to generate at least one synchronization signal. A series circuit includes a number of converter units configured to output an output current. At least one of the converter units includes a transformer and is configured to generate an output current such that a frequency or a phase of the generated output current is dependent on the synchronization signal.
Description
- This application is a continuation of U.S. Non-Provisional application Ser. No. 13/736,796, filed on Jan. 8, 2013, which application is hereby incorporated herein by reference in its entirety.
- Embodiments of the present invention relate to a power converter circuit, a power supply system with a power converter circuit, and a method for operating a power converter circuit.
- With an increasing interest in sustainable energy production there is a focus on using photovoltaic modules for producing electric power. Photovoltaic (PV) modules include a plurality of photovoltaic (PV) cells, that are also known as solar cells. Since the output voltage of one cell is relatively low, a PV module usually includes a string with a plurality of series connected solar cells, such as between 50 to 100 cells connected in series, or even several such strings connected in parallel.
- A PV module provides a DC supply voltage, while power grids, such as national power grids, have an AC supply voltage. In order to supply the energy provided by a PV module to the power grid it is, therefore, necessary to convert the DC voltage of the PV module into an AC voltage that is consistent with the AC supply voltage of the power grid.
- A first approach for converting the PV module DC voltage into a power grid AC voltage includes connecting several PV modules in series so as to obtain a DC voltage that is higher than the peak voltage of the power grid AC voltage, and converting the DC voltage into the AC voltage using a DC/AC converter. The amplitude of the DC voltage is typically between 200V and 1000V. High DC voltages, however, are critical in terms of the occurrence of electric arcs.
- According to a second approach, a plurality of DC/AC converters are provided, where each of these converters is connected to a PV module. The individual converters have their AC voltage outputs connected in parallel and each of these converters generates an AC voltage that is consistent with the power grid AC supply voltage from the DC voltage provided by the string of solar cells. The DC voltage provided by one PV module usually has an amplitude in the range of between 20V and 100V, depending on the number of cells that are connected in series within one module and depending on the technology used to implement the solar cells, while the peak voltage of the power grid AC voltage is about 155V or 325V, depending on the country. However, due to the large difference between input and output voltages these converters have a disadvantage in terms of efficiency.
- According to a further approach, several DC/AC converters are connected in series, where each of these converters receives a DC supply voltage from a PV module. In this system a central control unit is employed to synchronize the individual DC/AC converters in a multi-level switching pattern. This system requires constant synchronized control of all individual units.
- There is, therefore, a need for a power converter circuit that is capable of efficiently transforming relatively low DC supply voltages into a AC supply voltage that is consistent with a power grid voltage.
- A first embodiment relates to a power converter circuit. The power converter circuit includes a synchronization circuit configured to generate at least one synchronization signal, and at least one series circuit including a plurality of converter units configured to output an output current. At least one of the plurality of converter units includes a transformer and is configured to generate an output current such that at least one of a frequency and a phase of the generated output current is dependent on the synchronization signal.
- A second embodiment relates to a method that includes generating at least one synchronization signal by a synchronization circuit, outputting an output current by at least one series circuit comprising a plurality of converter units, wherein at least one of the converter units comprises a transformer, and generating an output current by at least one of the plurality of converter units such that at least one of a frequency and a phase of the generated output current is dependent on the synchronization signal.
- A third embodiment relates to a power converter circuit. The power converter circuit includes means for generating at least one synchronization signal, means for outputting an overall output current, and means for outputting an output current such that at least one of a frequency and a phase of the generated output current is dependent on the synchronization signal. The means for outputting the output current include a transformer.
- Examples will now be explained with reference to the drawings. The drawings serve to illustrate the basic principle, so that only aspects necessary for understanding the basic principle are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like signals and circuit components.
-
FIG. 1 schematically illustrates a power converter circuit including a plurality of DC/AC converter units connected in series and a voltage measurement circuit; -
FIG. 2 , which includesFIGS. 2A-2C , illustrates different embodiments of photovoltaic arrays, each including at least one solar cell; -
FIG. 3 schematically illustrates a power converter circuit including a plurality of DC/AC converter units connected in series and a voltage measurement circuit including a plurality of measurement units connected in series; -
FIG. 4 , which includesFIGS. 4A-4D , illustrates different embodiments of measurement units; -
FIG. 5 shows a block diagram illustrating a first embodiment of one DC/AC converter unit, including a DC/AC converter and a control circuit; -
FIG. 6 illustrates an embodiment of the DC/AC converter ofFIG. 5 in detail; -
FIG. 7 , which includesFIGS. 7A to 7C , illustrates different embodiments of switches that may be used in the DC/AC converter ofFIG. 6 ; -
FIG. 8 illustrates a first embodiment of the control circuit of one DC/AC converter unit; -
FIG. 9 illustrates a first branch of the control circuit ofFIG. 8 in detail; -
FIG. 10 illustrates a second embodiment of the control circuit of one DC/AC converter unit; -
FIG. 11 shows a block diagram illustrating a second embodiment of one converter unit, including a DC/DC converter, a maximum power point tracker, a DC/AC converter, and a control circuit; -
FIG. 12 illustrates an embodiment of the DC/DC converter implemented as a boost converter; -
FIG. 13 schematically illustrates a control circuit of the DC/DC converter ofFIG. 12 ; -
FIG. 14 illustrates an embodiment of the DC/DC converter implemented as a buck converter; -
FIG. 15 illustrates a further embodiment of the control circuit of one DC/AC converter; -
FIG. 16 illustrates an embodiment of the DC/DC converter implemented with two interleaved boost converter stages; -
FIG. 17 illustrates a first embodiment of a control circuit for the DC/DC converter ofFIG. 16 ; -
FIG. 18 illustrates a second embodiment of a control circuit for the DC/DC converter ofFIG. 16 ; -
FIG. 19 shows a block diagram illustrating a further embodiment of one DC/AC converter unit including a buck converter and an unfolding bridge; -
FIG. 20 shows timing diagrams illustrating the operating principle of the DC/AC converter unit ofFIG. 19 ; -
FIG. 21 illustrates a first embodiment of a controller implemented in the DC/AC converter unit ofFIG. 19 ; -
FIG. 22 illustrates a second embodiment of a controller implemented in the DC/AC converter unit ofFIG. 19 ; -
FIG. 23 illustrates an embodiment of a power converter circuit having a plurality of converter units organized in two series circuits being connected in parallel; -
FIG. 24 illustrates a further embodiment of the synchronization circuit; -
FIG. 25 illustrates an embodiment of a transmission circuit in the synchronization circuit ofFIG. 24 ; -
FIG. 26 illustrates a further embodiment of one converter unit; -
FIG. 27 illustrates a first embodiment of a signal generator in the converter unit ofFIG. 26 ; -
FIG. 28 illustrates timing diagrams of signals occurring in the signal generator ofFIG. 27 ; -
FIG. 29 illustrates a first embodiment of a signal generator in the converter unit ofFIG. 26 ; -
FIG. 30 schematically illustrates two possible operation modes of the power converter circuit; -
FIG. 31 illustrates an embodiment of a power converter circuit including an operation mode controller; -
FIG. 32 illustrates an embodiment of a converter unit including an operation mode unit; -
FIG. 33 illustrates a first embodiment of a transfer from a first operation mode to a second operation mode; -
FIG. 34 illustrates a second embodiment of a transfer from a first operation mode to a second operation mode; -
FIG. 35 illustrates a further embodiment of a power converter circuit; -
FIG. 36 illustrates an embodiment of a converter unit implemented in the power converter circuit ofFIG. 35 ; -
FIG. 37 illustrates a further embodiment of a converter unit; -
FIG. 38 illustrates an embodiment of a power converter circuit including an unfolding circuit connected between a series circuit with converter units and output terminals; -
FIG. 39 shows timing diagrams illustrating the operating principle of the power converter circuit ofFIG. 38 ; -
FIG. 40 illustrates an embodiment of the unfolding circuit; -
FIG. 41 illustrates a first embodiment of a converter unit in the power converter circuit ofFIG. 38 ; -
FIG. 42 illustrates a second embodiment of a converter unit in the power converter circuit ofFIG. 38 ; -
FIG. 43 illustrates a third embodiment of a converter unit in the power converter circuit ofFIG. 38 ; -
FIG. 44 illustrates a first embodiment of a power converter circuit including at least one transformer; -
FIG. 45 illustrates a second embodiment of a power converter circuit including at least one transformer; -
FIG. 46 schematically illustrates one embodiment of a DC/DC converter including a transformer; -
FIG. 47 illustrates an embodiment of a DC/DC converter having a two-transistor forward (TIT) topology; -
FIG. 48 illustrates an embodiment of a DC/DC converter having a phase-shift (PS) zero-voltage-switching (ZVS) converter topology; -
FIG. 49 illustrates an embodiment of a DC/DC converter having a flyback converter topology; -
FIG. 50 illustrates an embodiment of a DC/DC converter having an LLC converter topology; -
FIG. 51 illustrates one embodiment of a DC/AC converter including a transformer; -
FIG. 52 illustrates one embodiment of a power converter circuit with a plurality of DC/DC converter that share one transformer; and -
FIG. 53 illustrates yet another embodiment of a power converter circuit with a plurality of DC/DC converter that share one transformer. - In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing” etc., is used with reference to the orientation of the figures being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
- In the following, embodiments of the present invention will be explained in a specific context, namely in the context of converting electrical power or electrical voltages provided by a plurality of photovoltaic arrays into an alternating voltage, specifically an alternating power grid supply voltage. The alternating voltage and the alternating power grid voltage will also be referred to as AC voltage and AC power grid voltage, respectively, in the following. However, this is only an example, embodiments of the invention may be employed in a wide range of applications in which a conversion of direct voltages into an AC voltage is required. In the following, direct voltages will also be referred to as DC voltages. Any type of DC power source may be used instead of an photovoltaic array, such as a fuel cell. It is even possible, to employ DC power source of different types, such as photovoltaic arrays and fuel cells, in one application.
-
FIG. 1 illustrates a first embodiment of a power converter circuit (power inverter circuit) 4 for converting a plurality of n (at least two) DC input voltages V3 1, V3 2, V3 n into one AC output voltage v1. It should be noted in this connection that throughout the drawings DC voltages and DC currents will be denoted using capital letters “V” and “I,” while AC voltages and AC currents will be denoted using lowercase letters “v” and “i.” The power converter circuit includes a plurality of n (at least two)converter units input terminals DC power source FIG. 1 , besides thepower converter circuit 1 with theconverter units DC power sources DC power sources power converter circuit 1 form an AC power supply system or an AC current supply system. TheDC power sources FIG. 1 . However employing PV modules as DC power sources is only an example. Any other type of DC power source, such as a power source including fuel cells, may be used as well. It is even possible to employ different types of DC power sources in one power supply system. - Each of the
converter units output terminals converter units output terminals power converter circuit 1. For this, afirst converter unit 21 has afirst output terminal 23 1 coupled to afirst output terminal 11 of thepower converter circuit 1 and alast converter unit 2 n in the cascade has asecond output terminal 24 n coupled to asecond output terminal 12 of thepower converter circuit 1. Further, each of the first output terminals (other than output terminal 23 1) are connected to one second output terminal (other than output terminal 24 n ) of another converter unit. - The
output terminals power converter circuit 1 are configured to receive a voltage v1. For example, theoutput terminals FIG. 1 , the power grid is represented by avoltage source 100 and a load Z connected in parallel with thepower source 100. Thevoltage source 100 of the power grid represents a plurality of AC voltage sources in the power grid, and load Z represents a plurality of loads connected to the power sources in the power grid. The power grid defines the AC voltage v1 between the output terminal. Since this voltage v1 is defined by an external source, such as the power grid, this voltage will be referred to as external AC voltage v1 in the following. - Each of the
converter units output terminals converter units converter units -
- Each
power converter unit individual output terminals converter unit first converter unit 21, the output current of theconverter unit 2 1 is the current flowing into the circuit node at which the output capacitor C1 is connected to thefirst output terminal 23 1. The current flowing from thefirst output terminal 23 1 of thefirst converter unit 2 1will be referred to as converter circuit output current iOUT. This current corresponds to the current flowing between the individual converter units 2 1-2 n. The output capacitances C1, C2, Cn are part of theindividual converter units - In the steady state, the AC output currents i1 1, i1 2, i1 n or, more precisely, the rms values of the AC output currents i1 1, i1 2, i1 n, correspond to the power converter circuit output current iOUT or the rms value of the output current iOUT, respectively, so that there is very little to no rms current into the output capacitors C1-Cn. However, there can be situations in which the output currents i1 1, i1 2, i1 n of the
individual converter units - The
power converter circuit 1 further includes asynchronization circuit 10 connected between theoutput terminals power converter circuit 1. Thesynchronization circuit 10 is configured to provide at least one synchronization signal Sv1. According to one embodiment, the synchronization signal is an AC signal having a phase and a frequency that are dependent on the phase and the frequency, respectively, of the external AC voltage v1. - The
individual converter units FIG. 1 , theindividual converter units converter units FIG. 3 herein below. The at least one synchronization signal Sv1 can be transmitted to theindividual converter units FIG. 1 , a signal transmission bus can be provided through which the at least one synchronization signal Sv1 is transmitted to theindividual converter units FIG. 1 ), there is a dedicated transmission path between thevoltage synchronization circuit 10 and each of theconverter units synchronization circuit 10 to theindividual converter units - The
individual converter units converter unit converter unit - In
FIG. 1 , same features of theDC voltage sources DC voltage sources converter units first converter unit 2 1, “2” for thesecond converter unit 2 2 and “n” for the n-th converter unit 2 n. In the following, when explanations equivalently apply to each of theDC sources converter units reference character 2, for example, represents an arbitrary one of the converter units,reference character 23 represents a first output terminal of an arbitrary one of the converter units, reference character i1 denotes the output current of anarbitrary converter unit 2, reference character denotes the output capacitance C of anarbitrary converter unit 2, and so on. - The power converter of
FIG. 1 includes n=3converter units 2. However, having n=3 converter units is only an example. Any number ofn converter units 2, wherein n>1, can be connected in series to form the power converter circuit i. - Besides the internal control loops of the
converter units 2 thepower converter circuit 1 does not require an outer control loop connected to theindividual converter units 2 and/or additional communication paths between theindividual converter units 2, when thepower converter circuit 1 is in the steady state. When thepower converter circuit 1 is in the steady state the system can be defined by equation (1) and one further equation for each of the converter units 2: -
v2RMS i1RMS =V3·I3 (2), - where v2 rms denotes the RMS (route mean square) value of the output voltage v2 of one
converter units 2, i1 RMS is denotes the RMS value of the output current i1 of one converter unit, V3 denotes the input voltage and I3 denotes the input current of theconverter unit 2. It should be noted that (very low) losses may occur in eachconverter unit 2. For the sake of simplicity, these losses are not considered in equation (2). In the steady state, the RMS values of the individual output currents i1 RMS are equal and correspond to the rms value of the power converter circuit output current iOUT-RMS, that is: -
i1RMS =i1OUT-RMS (3). - Since equations (2) and (3) is valid for each of the individual converter units, there are n equations, each of these equations describing the relationship between the input power and the average output power of each of the
converter units 2, where the input power Pin is given as -
Pin=V3·I3 (4), - and the output power Pout is given as
-
Pout=v RMS ·i1RMS (5). - The input power Pin of each of the
individual converter units 2 and the input voltage V3 and the input current I3, respectively, are external parameters given by the individualDC power sources 3. The external AC voltage v1 between theoutput terminals - Thus, there are n+1 variables in the
power converter circuit 1, namely the n output voltages v2 of theindividual converter units 2 and the (equal) output currents i1. However, referring to equations (1) and (2) the system is defined by n+1 equations, so that each of the n+1 variables is determined when the system is in its steady state. Besides having each of theconverters 2 generate its AC output current i1 such that there is a given phase difference (such as zero) between the AC output current i1 and the external AC voltage no additional control or regulation mechanism is required. When the output currents i1 of theindividual converter units 2 are in phase with the external AC voltage v1 the real output power of each converter unit equals the apparent output power, so that the reactive output power is zero. Theindividual converter units 2 control their output currents i1 dependent on the phase information as represented by the at least one synchronization signal Sv1 and control their output current such that the input power received at theinput terminals output terminals - The
DC power sources 3 implemented as PV arrays are only schematically illustrated inFIG. 1 . These PV arrays each include at least one solar cell. Some exemplary embodiments of PV arrays including at least one solar cell are illustrated inFIGS. 2A to 2C .FIG. 2A illustrates a first embodiment. In this embodiment, thePV array 3 includes only onesolar cell 31. Referring to a further embodiment illustrated inFIG. 2B , onePV array 3 includes a string of msolar cells FIG. 2C , p strings of solar cells are connected in parallel, wherein p>1. Each of the strings includes msolar cells FIGS. 2A to 2C are only exemplary. Many other solar cell arrangements may be used as well as aDC source 3. -
FIG. 3 illustrates an embodiment of a power converter circuit that includes asynchronization circuit 10 implemented as a voltage measurement circuit with a plurality ofmeasurement units individual measurement units output terminals FIG. 1 ) are not illustrated inFIG. 3 . The plurality ofmeasurement units measurement units converter unit input terminals converter unit measurement unit - In the embodiment illustrated in
FIG. 3 , the number ofmeasurement units converter units measurement unit converter unit - The
individual measurement units FIGS. 4A to 4D below. InFIGS. 4A to 4D ,reference character 10 1 denotes an arbitrary one of themeasurement units FIG. 3 . - Referring to
FIG. 4A , onemeasurement unit 10 i may include aresistor 101 connected between the terminals of themeasurement unit 10 i that serve to connect the individual measurement units (10 1-10 n inFIG. 3 ) in series and that serve to couple the individual measurement units to the converter units (2 1-2 n inFIG. 3 ). According to one embodiment, the resistances of theresistors 101 in theindividual measurement units 10 i are equal or at least approximately equal. In this case, the absolute values of the measurement voltages provided by theindividual measurement units 10 i are equal. In ameasurement circuit 10 that includesmeasurement units 10 i implemented with aresistor 101, the individual measurement voltages v1 i are proportional to the output voltage v1. - In a
measurement circuit 10 withmeasurement units 10 i including resistors, theindividual measurement units 10 i form a resistive voltage divider. Referring to a further embodiment illustrated inFIG. 4B , theindividual measurement units 10 i each include acapacitor 102 instead of a resistor. In this case, theindividual measurement units 10 i form a capacitive voltage divider between theoutput terminals - Referring to
FIG. 4C , that illustrates a further embodiment, eachmeasurement unit 10 i can be implemented with a parallel circuit including aresistor 101 and acapacitor 102. - Referring to
FIG. 4D , that illustrates yet another embodiment of onemeasurement unit 10 i, each measurement unit or at least some of the measurement units can be implemented with a voltage divider having afirst voltage divider 101 and a secondvoltage divider element 102. These voltage divider elements are implemented as resistors in the embodiment according toFIG. 4D . However, thesevoltage divider elements measurement unit 10 i, but is the voltage across the firstvoltage divider element 101, so that the measurement voltage v1 i is a fraction of the voltage across themeasurement unit 10 i. - It should be noted that implementing the
synchronization circuit 10 as a voltage measurement circuit that generates the synchronization signal Sv1 to be in phase with the external AC voltage v1 is only an example. Examples of other synchronization circuits are explained herein further below. -
FIG. 5 illustrates a first embodiment of aconverter unit 2 for converting the DC input voltage provided by one DC source (not shown inFIG. 3 ) into an AC output voltage v2. Theconverter unit 2 includes a DC/AC converter 4 connected between theinput terminals output terminals AC converter 4 further receives a reference signal SREF, which may be an alternating signal having a frequency and a phase. The DC/AC converter 4 is configured to generate the AC output current i1 dependent on the reference signal SREF such that a frequency and a phase of the output current i1 correspond to a frequency and a phase, respectively, of the synchronization signal Sv1. The DC/AC converter 4 can be implemented like a conventional DC/AC converter that is configured to generate an output current in phase with an alternating reference signal. Such DC/AC converters are commonly known. - It should be noted that each of the DC/
AC converter units - The reference signal SREF is generated by a
control circuit 5 dependent on the synchronization signal Sv1 and an output current signal Si1. The synchronization signal Sv1 is either the synchronization signal Sv1 explained with reference toFIG. 1 , one of the measurement voltages v1 i explained with reference toFIG. 3 , or a scaled version or a fraction thereof. The output current signal represents the output current i1, i.e., the output current signal Si1 is dependent on the output current i1. According to one embodiment, the output current signal Si1 is a scaled version of the output current i1. The output current signal Si1 can be generated in a conventional manner from the output current i1 using a current measurement circuit (not illustrated). The output current signal Si1 is generated for each of the converter units (2 1-2 n) individually by detecting the respective output current of each converter unit. Referring toFIG. 5 , the output current i1 of the illustratedconverter unit 2 is the current received at the circuit node common to thefirst output terminal 23 and the output capacitance C. - The
control circuit 5, which will also be referred to as controller in the following, generates the reference signal SREF dependent on the synchronization signal Sv1 and the output current signal Si1 such that the output current, when generated in correspondence with the reference signal SREF, is in phase with the external AC voltage v1 or has a given phase shift relative to the external AC voltage v1. It should be noted that, since the external AC voltage v1 and the output current i1 are alternating signals, the synchronization signal Sv1 and the output current signal Si1 are also alternating signals. In theconverter unit 2, the DC/AC converter 4 and thecontroller 5 are part of a control loop that controls the output current i1 to be in phase with the external AC voltage v1 or to have a given phase shift relative thereto. - Although a conventional DC/AC converter may be used in the
converter unit 2 as the DC/AC converter 4 connected between theinput terminals output terminals AC converter 4 will be explained in detail with reference toFIG. 6 , in order to ease understanding of embodiments of the invention. - The DC/
AC converter 4 illustrated inFIG. 6 is a full-bridge (H4) converter with two half-bridge circuits each connected between theinput terminals input terminals first switch 42 1 and asecond switch 42 2 form the first half-bridge, and athird switch 42 3 and afourth switch 42 4 form the second half-bridge. Each of the half-bridges includes an output, where an output of the first half-bridge is formed by a circuit node common to the load paths of the first andsecond switch fourth switches first output terminal 23 of theconverter unit 2 via a firstinductive element 44 1, such as a choke. The output terminal of the second half-bridge is coupled to thesecond output terminal 24 of theconverter unit 2 via a secondinductive element 44 2, such as a choke. According to a further embodiment (not illustrated) only one of the first and secondinductive elements converter 4 further includes aninput capacitance 41, such as a capacitance, connected between theinput terminals output terminals - Each of the
switches drive circuit 45 dependent on the reference signals SREF received from thecontroller 5. The drive signal S42 1-S42 4 are pulse-width modulated (PWM) drive signals configured to switch the corresponding switch 42 1-42 4 on and off. It should be noted that a switching frequency of the PWM signals S42 1-S42 4 is significantly higher than a frequency of the alternating reference signal SREF. The reference signal SREF may be a sinusoidal signal with a frequency of 50 Hz or 60 Hz, depending on the country in which the power grid is implemented, while the switching frequency of the individual switches 42 1-42 4 may be in the range of several kHz up to several 10 kHz, or even up to several 100 kHz. Thedrive circuit 45 is configured to individually adjust the duty cycle of each of the drive signals S42 1-S42 4 between 0 and 1 in order to have the waveform of the output current i1 follow the waveform of the reference signal SREF. When the duty cycle of one drive signal is o, the corresponding switch is permanently switched off, and when the duty cycle of one drive signal is 1, the corresponding switch is permanently switched on. The duty cycle of a drive signal is the relationship between the time period for which the drive signal switches the corresponding switch and the duration of one switching cycle. The duration of one switching cycle is the reciprocal of the switching frequency. - Referring to what has been explained before, the output current i1 is an AC current with a positive half-cycle in which the output current is positive, and with a negative half-cycle in which the output current i1 is negative. The time behavior of the output current i1 is dependent on the reference signal SREF which also has positive and negative half-cycles.
- Two possible operating principles of the
converter 4 will briefly be explained. First, it is assumed that a positive half-cycle of the output current i1 is to be generated. According to a first operating principle, which is known as bipolar switching or 2-level switching, the first andfourth switches third switches fourth switches input capacitance 41 and the output voltage v2, where the output voltage v2 is defined by the power grid voltage vN. The switches 42 1-42 4 each include a freewheeling element, such as a diode, that is also illustrated inFIG. 4 . The freewheeling elements of the second andthird switches fourth switches fourth switches switches fourth switches third switches fourth switches fourth switches switches - According to a second operating principle, which is known as phase chopping or 3-level switching, the
first switch 42 1 is permanently switched on during the positive half cycle of the output voltage v2, the second andthird switches fourth switch 42 4 is switched on and off in a clocked fashion. During an on-phase of the first andfourth switches input capacitance 41 and the output voltage v2, where the output voltage v2 is defined by the power grid voltage vN. During an off-phase of the fourth switch 42 4 a freewheeling path is offered by the freewheeling element ofswitch 42 3 and the switched-onfirst switch 42 1 thus enabling a zero volt state across the output chokes. In this method, the amplitude of the output current i1 can be adjusted through the duty cycle of the switching operation of thefourth switch fourth switches second switch 42 2 is permanently switched on, and thethird switch 42 3 is switched on and off in a clocked fashion. - In order to control an instantaneous amplitude of the output current i1 during the positive half-cycle, the
drive circuit 45 varies the duty cycle of the at least one switch that is switched on and off in a clocked fashion. The duty cycle of the at least one clocked switch and the duty cycle of its drive signal, respectively, is increased in order to increase the amplitude of the output current i1 and is decreased in order to decrease the amplitude of the output current i1. This duty cycle is dependent on the instantaneous amplitude of the reference signal SREF. - The switches 42 1-42 4 may be implemented as conventional electronic switches. Referring to
FIG. 7A , which illustrates a first embodiment for implementing the switches, the switches may be implemented as MOSFETs, specifically as n-type MOSFETs.Electronic switch 42 inFIG. 7A represents an arbitrary one of the switches 42 1-42 4. A MOSFET, such as the n-type MOSFET illustrated inFIG. 7A has an integrated diode that is also illustrated inFIG. 7A . This diode is known as body diode and may act as a freewheeling element. A drain-source path, which is a path between a drain terminal and a source terminal, forms a load path of a MOSFET, and a gate terminal forms a control terminal. - Referring to
FIG. 7B , the switches 42 1-42 4 could also be implemented as IGBTs, where additionally a diode may be connected between a collector and an emitter terminal of the IGBT. This diode acts as a freewheeling element. In an IGBT, the load path runs between the emitter and the collector terminal, and the gate terminal forms a control terminal. - According to a further embodiment, two of the four switches, such as the first and
third transistors - According to yet another embodiment, illustrated in
FIG. 7C , the switches 42 1-42 4 can be implemented as GaN-HEMTs (Gallium-Nitride High Electron Mobility Transistors). Unlike a conventional (silicon or silicon carbide) MOSFET a GaN-HEMT does not include an integrated body diode. In a GaN-HEMT, a current conduction in a reverse direction (corresponding to the forward direction of a body diode in a conventional MOSFET) can be obtained through a substrate biased turn-on. When implementing the switches in GaN technology, all switches of one converter unit can be implemented on a common semiconductor substrate. -
FIG. 8 schematically illustrates an embodiment of thecontroller 5 that generates the reference signal SREF dependent on the synchronization signal Sv1 and the output current signal Si1.FIG. 8 shows a block diagram of thecontroller 5 in order to illustrate its operating principle. It should be noted that the block diagram illustrated inFIG. 8 merely serves to illustrate the functionality of thecontroller 5 rather than its implementation. The individual function blocks, that will be explained in further detail below, may be implemented using a conventional technology that is suitable to implement a controller. Specifically, the function blocks of thecontroller 5 may be implemented as analog circuits, digital circuits, or may be implemented using hardware and software, such as a microcontroller on which a specific software is running in order to implement the functionality of thecontroller 5. - Referring to
FIG. 8 , thecontroller 5 includes a phase locked loop (PLL) 51 that provides a frequency and phase signal Sωt representing the frequency and the phase of the synchronization signal Sv1. Specifically, Sωt represents an instantaneous phase angle of the (sinusoidal) synchronization signal received at the input of thecontrol circuit 5. Thus, signal Sωt will also be referred to as phase angle signal in the following. ThePLL 51 receives the synchronization signal Sv1. The frequency and phase signal Sωt provided by thePLL 51 is received by a signal generator, such as a VCO, that generates a sinusoidal signal Si1-REF being in phase with the synchronization signal Sv1 and forming a reference signal for the output current i1 of theconverter unit 2. - Referring to
FIG. 8 , the controller further receives the output current signal Si1 and calculates an error signal by subtracting the output current signal Si1 from the output current reference signal Si1-REF. The subtraction operation is performed by a subtractor receiving the output current measurement signal Si1-REF and the output current signal Si1 at input terminals and providing the error signal at an output terminal. The error signal, which is also a sinusoidal signal is filtered in afilter 53 connected downstream thesubtractor 54. The reference signal SREF is a filtered version of the error signal available at the output of thefilter 53. The filter is, e.g., a proportional (P) filter. - Optionally, a phase signal Sφ is added to the output signal of the
PLL 51 before generating the sinusoidal reference signal Si1-REF. In this embodiment the reference signal Si1-REF and, therefore, the output current i1, has a phase relative to the synchronization signal Sv1, with the phase shift being defined by the phase signal S100 . -
FIG. 9 illustrates an embodiment of thePLL 51 ofFIG. 6 . This PLL includes a phase detector with acalculation unit 511 that calculates the sine or the cosine of the phase angle signal S107 t, andmultiplier 512 that receives the output signal from thecalculation unit 511 and the synchronization signal Sv1. An error signal SERROR is available at the output of themultiplier 512. The error signal SERROR is received by a linear filter (LF) 514, such as, e.g., a linear proportional-integral (PI) filter. In the steady state, an output signal Sω of the linear filter represents the frequency of the synchronization signal Sv1. An integrating circuit (a filter with an integrating (I) characteristic) receives the output signal from the linear filter, integrates the output signal of thelinear filter 514 and provides the frequency and phase signal (the phase angle signal) Sωt, from which the VCO (see 52 inFIG. 8 ) generates the reference signal Si1-REF. Integrating the output signal of the linear filter in the time domain corresponds to a multiplication with 1/s in the frequency domain. -
FIG. 10 illustrates a further embodiment of the of thecontroller 5. In this embodiment, asecond PLL 51′ receives the output current signal Si1 and calculates a further frequency and phase signal representing frequency and phase of the output current signal Si1. The further frequency and phase signal is subtracted from the frequency and phase signal Sωt representing frequency and phase of the synchronization signal Sv1 (and, optionally, the phase shift Sφ) using asubtractor 54, so as to provide an error signal. The error signal is filtered using afilter 53 and asignal generator 52, such as a VCO, receives the error signal and generates a sinusoidal reference signal with frequency and phase defined by the filtered error signal. In this embodiment, thefilter 53 can be implemented as a P-filter or as a PI-filter. -
FIG. 11 illustrates a further embodiment of oneconverter unit 2. This converter unit besides the DC/AC converter 4 and thecontroller 5 includes a DC/DC converter 6 connected between theinput terminals AC converter 4. The DC/AC converter 4 may be implemented, as explained with reference toFIGS. 6 to 10 , with the difference that the DC/AC converter 4 ofFIG. 11 receives a DC input voltage V6 from the DC/DC converter 6 instead of the input voltage V3 of theconverter unit 2. Acapacitor 60 connected between theterminals DC converter 6 or aninput capacitor 4 of the DC/AC converter 4, or both. Thiscapacitor 60 can be referred to as DC link capacitor. - The DC/
DC converter 6 is configured to adjust the input voltage V3 or the input current I3 to a voltage or current value, respectively, that is dependent on a reference signal SREF-V3 received by the DC/DC converter 6. For explanation purposes it is assumed that the DC/DC converter 6 adjusts the input voltage V3 dependent on the reference signal SREF-V3. Adjusting the input voltage V3 of theconverter unit 2 may help to operate theDC power source 3 connected to theinput terminals - A solar cell and, therefore, a PV module including several solar cells, acts like a power generator providing a DC output voltage and a DC output current when it is exposed to sunlight. For a given light power received by the PV array there is a range of output currents and a range of corresponding output voltages at which the PV array can be operated. However, there is only one output current and one corresponding output voltage at which the electric power provided by the PV array has its maximum. The output current and the output voltage at which the output power assumes its maximum define the maximum power point (MPP). The MPP varies dependent on the light power received by the array and dependent on the temperature.
- Referring to
FIG. 11 , theconverter unit 2 further includes a maximum power point tracker (MPPT) 7 that is configured to provide the reference signal SREF-V3 such that DC/DC converter 6 adjusts the input voltage such that theDC source 3 is operated in its MPP. TheMPPT 7 receives an input current signal SI3 that represents the input current I3 provided by the DC source 3 (illustrated in dashed lines inFIG. 9 ), and an input voltage signal Sv3 that represents the input voltage V3 provided by theDC source 3. From the input current signal SI3 and the input voltage signal Sv3 theMPPT 7 calculates the instantaneous input power provided by theDC source 3. The input voltage signal Sv3 can be obtained from the input voltage V3 in a conventional manner by, for example, using a voltage measurement circuit. Equivalently, the input current signal SI3 can be obtained from the input current I3 in a conventional manner using, for example, a current measurement circuit. Those voltage measurement circuits and current measurement circuits are commonly known and are not illustrated inFIG. 11 . - The basic operating principle of the
MPPT 7 in order to find the MPP is to vary the reference signal SREF-V3 within a given signal range and to determine the input power provided by theDC source 3 for each of the input voltages V3 defined by the different reference signals SREF-v3. TheMPPT 7 is further configured to detect the input voltage V3 for which the maximum input power has been obtained, and to finally set the reference signal SREF-v3 to that value for which the maximum input power has been detected. - Since the solar energy received by the
PV array 3 may vary theMPPT 7 is further configured to check whether theDC source 3 is still operated in its maximum power point either regularly or when there is an indication that the maximum power point might have changed. An indication that the maximum power point might have changed is, for example, when the input current I3 represented by the input current signal SI3 changes without the reference signal SREF-v3 having changed. The regular check or the event-driven check of theMPPT 7 whether theDC source 3 is still operated in its maximum power point, may include the same algorithm that has been explained before for detecting the maximum power point for the first time. Conventional algorithms for detecting the maximum power point that can be implemented in theMPPT 7 include, for example, a “hill climbing algorithm” or a “perturb-and-observe algorithm.” - The DC/
DC converter 6 can be implemented like a conventional DC/DC converter. A first embodiment of a DC/DC converter 6 that can be used in theconverter unit 2 is illustrated inFIG. 12 . The DC/DC converter 6 illustrated inFIG. 12 is implemented as a boost converter. This type of converter includes a series circuit with aninductive storage element 64, such as a choke, and aswitch 65 between the input terminals of the DC/DC converter 6, where the input terminals of the DC/DC converter 6 correspond to theinput terminals converter unit 2. Further, arectifier element 66, such as a diode, is connected between a circuit node common to theinductive storage element 64 and theswitch 65 and afirst output terminal 61 of the DC/DC converter 6. Asecond output terminal 62 of the DC/DC converter 6 is connected to thesecond input terminal 22. An output voltage V6 of the DC/DC converter is available between theoutput terminals FIG. 12 , the DC/DC converter 6 may further include a firstcapacitive storage element 63, such as a capacitor, between theinput terminals capacitive storage element 68, such as a capacitor, between theoutput terminals capacitive storage element 68 acts as an energy storage that is necessary when generating the AC output current i1. from the DC voltage V6 available at the output of the DC/DC converter 6. - The
switch 65 can be implemented as a conventional electronic switch, such as a MOSFET or an IGBT. Further, the rectifyingelement 66 could be implemented as a synchronous rectifier, which is a rectifier implemented using an electronic switch, such as a MOSFET or an IGBT. According to a further embodiment, theswitch 65 is implemented as GaN-HEMT. - The DC/
DC converter 6 further includes a control circuit (controller) 67 for generating a drive signal S65 for theswitch 65. This drive signal S65 is a pulse-width modulated (PWM) drive signal. ThePWM controller 67 is configured to adjust the duty cycle of this drive signal S65 such that the input voltage V3 corresponds to the desired input voltage as represented by the reference signal SREF-V3. For this, thecontrol circuit 67 receives the reference signal SREF-V3 and the input voltage signal Sv3 that represents the input voltage V3. - A first embodiment of the
PWM control circuit 67 is illustrated inFIG. 13 . Like inFIG. 8 (which illustrates an embodiment of the controller 5) inFIG. 11 functional blocks of thecontroller 67 are illustrated. These functional blocks can be implemented as analog circuits, as digital circuits or can be implemented using hardware and software. Referring toFIG. 13 , thecontrol circuit 67 calculates an error signal SERR from the input voltage signal Sv3 and the reference signal SREF-V3. The error signal SERR is calculated by either subtracting the input voltage signal V3 from the reference signal SREF-V3 (as illustrated) or by subtracting the reference signal SREF-V3 from the input voltage signal Sv3. The error signal SERR is provided by asubtraction element 671 that receives the input voltage signal Sv3 and the reference signal SREF-V3. - The error signal SERR is received by a
filter 672 that generates a duty cycle signal SDC from the error signal SERR. The duty cycle signal SDC represents the duty cycle of the drive signal S65 provided by thecontrol circuit 67. Thefilter 672 can be a conventional filter for generating a duty cycle signal SDC from an error signal SERR in a PWM controller of a DC/DC converter, such as a P-filter, a PI-filter, or a PID-filter. - A
PWM driver 673 receives the duty cycle signal SDC and a clock signal CLK and generates the drive signal S65 as a PWM signal having a switching frequency as defined by the clock signal CLK and a duty cycle as defined by the duty cycle signal SDC. Thisdriver 673 can be a conventional PWM driver that is configured to generate a PWM drive signal based on a clock signal and a duty cycle information. Such drivers are commonly known, so that no further information are required in this regard. - The basic control principle of the
controller 67 ofFIG. 12 will briefly be explained. Assume that the input voltage V3 has been adjusted to a given value represented by the reference signal SREF-V3 and that the reference signal SREF-V3 changes, so that the input voltage V3 has to be re-adjusted. For explanation purposes it is assumed that the input voltage V3 is to be increased as defined by the reference signal SREF-v3. In this case thecontrol circuit 67 reduces the duty cycle of the drive signal S65. Reducing the duty cycle of the drive signal S65 results in a decreasing (average) input current I3, where decreasing the input current I3, at a given power provided by theDC source 3 results in an increasing input voltage V3. Equivalently, the duty cycle is increased when the input voltage V3 is to be decreased. An increase in the duty cycle results in an increase of the input current I3. - The boost converter according to
FIG. 12 does not only provide a load to theDC source 3 in order to operate theDC source 3 in its maximum power point. This boost converter also generates an output voltage V6 received by the DC/AC converter 4 (seeFIG. 11 ) that is higher than the input voltage V3. Further, the boost converter is implemented such that the output voltage V6 is higher than a peak voltage of the output voltage v2 of the DC/AC converter, but lower than a voltage blocking capability of the switches (see 42 1-42 4 inFIG. 6 ) implemented in the DC/AC converter. - Referring to
FIG. 14 , the DC/DC converter 6 may also be implemented as a buck converter. This buck converter includes a series circuit with aninductive storage element 64, such as a choke, and aswitch 65 between thefirst input terminal 21 and thefirst output terminal 61. Afreewheeling element 66, such as a diode, is connected between thesecond output terminal 62 and a circuit node common to theinductive storage element 64 and theswitch 65. Acapacitive storage element 63, such as a capacitor, is connected between theinput terminals - Like in the boost converter of
FIG. 12 , theswitch 65 in the buck converter ofFIG. 14 can be implemented as a conventional electronic switch, such as a MOSFET or an IGBT, or could be implemented as a GaN-HEMT. Further, the freewheelingelement 66 could be implemented as a synchronous rectifier. - Like in the boost converter according to
FIG. 12 , theswitch 65 in the buck converter according toFIG. 14 is driven by a PWM drive signal S65 provided by acontrol circuit 67. Thecontrol circuit 67 may be implemented as illustrated inFIG. 13 . The operating principle of thecontrol circuit 67 in the buck converter ofFIG. 14 is the same as in the boost converter ofFIG. 12 , i.e., the duty cycle of the drive signal S65 is increased when the input voltage V3 is to be decreased, and the duty cycle is decreased, when the input voltage V3 is to be increased. - It should be noted that implementing the DC/
DC converter 6 as a boost converter (seeFIG. 12 ) or as a buck converter (seeFIG. 14 ) is only an example. The DC/DC converter 6 could also be implemented as a buck-boost converter, a boost-buck-converter, a flyback converter, and so on. Whether a boost converter or a buck converter is used as a DC/DC converter for tracking the maximum power point of theDC source 3 and for providing the input voltage V6 to the DC/AC converter 4, influences the number ofconverter units 2 to be connected in series in order for the sum of the output voltages v2 of theconverter units 2 to correspond to the external AC voltage v1. This will be explained by the way of an example in the following. - Assume that there is an external AC voltage v1 with 240VRMS is desired. The peak voltage (maximum amplitude) of this voltage v1 is 338V (240V sqrt(2), where sqrt is the square root). Further assume that the
DC sources 3 are PV arrays each providing an output voltage between 24V and 28V when exposed to sunlight. The DC/AC converter 4 has a buck characteristic, which means that the peak value of the output voltage v2 (seeFIG. 4 ) is less than the received DC input voltage V3 or V6, respectively. Thus, when buck converters are employed as DC/DC converters 6 in theconverter units 2 or when no DC/DC converters are used, at least 15converter units 2 with PV panels connected thereto need to be connected in series. This is based on the assumption that each PV array generates a minimum voltage of V3=24V and that a peak voltage of the external AC voltage v1 is 338V. The number of 15 is obtained by simply dividing 338V through 24V (338V/24V=14,08) and rounding the result to the next higher integer. - When, however, a boost converter is used as the DC/
DC converter 6 that, for example, generates an output voltage V6=60V from the input voltage V3 (which is between 24V and 28V) the number ofconverter units 2 to be connected in series may be reduced to about 6. - In the DC/AC converter illustrated in
FIG. 11 , the output voltage V6 of the DC/DC converter may vary dependent on the input power received at theinput terminals DC source 3 and dependent on the output current i1 or, more exactly, dependent on the average of the output current i1. According to a further embodiment illustrated inFIG. 15 , thecontrol circuit 5 is further configured to control the input voltage of the DC/AC converter 4 and the output voltage of the DC/DC converter 6, respectively. For this, thecontrol circuit 5 receives an input voltage signal Sv6 that represents the input voltage V6. Thecontrol circuit 5 is configured to adjust the input voltage V6 by varying the duty cycle of those switches in the DC/AC converter 4 that are driven in a clocked fashion. The input voltage can be increased by generally decreasing the duty cycle and can be decreased by generally increasing the duty cycle. For this, thecontrol circuit 5 includes a further control loop, where this control loop is slower than the control loop that causes the output current i1 to follow the reference signal SREF. This control loop is, for example configured to cause variations of the duty cycle at a frequency of between 1 Hz and 10 Hz. - The
control circuit 5 ofFIG. 15 is based on the control circuit illustrated inFIG. 8 and additionally includes a further control loop that serves to adjust the amplitude of the output current reference signal Si1-REF dependent on the input voltage signal Sv6. Instead of the control loop illustrated inFIG. 8 , the control circuit according toFIG. 15 could also be implemented based on the control circuit ofFIG. 10 . Referring toFIG. 15 , the control loop includes: afurther subtraction element 56, afilter 55, and amultiplier 57. Thesubtraction element 56 receives the input voltage signal Sv6 and a reference signal SV6-REF that represents a set value of the input voltage V6. Thesubtraction element 56 generates a further error signal based on a difference between the input voltage signal Sv6 and the reference signal SV6-REF. Thefilter 55 receives the further error signal and generates an amplitude signal SAMPL representing an amplitude of the reference signal SREF from the further error signal. The filter may have a P-characteristic, an I-characteristic, a PI-characteristic, or a PID-characteristic. The amplitude signal SAMPL and the output signal of theVCO 52 are received by themultiplier 57 that provides the output current reference signal Si1-REF. The output current reference signal Si1-REF has an amplitude that is dependent on the input voltage V6 and that serves to control the input voltage V6 of the DC/AC converter (4 inFIG. 11 ), and a frequency and phase of the output current i1. The frequency and the phase of the reference signal SREF are dependent on the at least one synchronization signal Sv1 and the output current signal Si1 and serve to adjust frequency and phase of the output current i1 such that there is a given phase difference between the output current and the output voltage. - The input voltage reference signal SV6-REF may have a fixed value that is, selected such that the input voltage V6 is sufficiently below the voltage blocking capability of switches employed in the DC/AC converter. However, it is also possible to vary the input voltage reference signal SV6-REF dependent on the output current, specifically on the rms value of the output current i1. According to one embodiment, the input voltage reference signal Sv6-REF decreases when the output current i1 increases, and the input voltage reference signal SV6-REF increases when the output current decreases. According to one embodiment, the input voltage reference signal SV6-REF has a first signal value when the output current i1 is below a given threshold value, and has a lower second signal value when the output current i1 is above a given threshold value.
- The control circuit illustrated in
FIG. 15 could also be implemented in a converter as illustrated inFIG. 6 in which the DC/DC converter is omitted. In this case, the input voltage to be controlled is the output voltage V3 of the PV module, so that the voltage signal SV6 inFIG. 15 is replaced by the voltage signal Sv3 representing the output voltage of theDC source 3, and the input voltage reference signal SV6-REF is replaced by the reference signal Sv3-REF defining a desired output voltage of theDC source 3. The input voltage reference signal SV3-REF may in this case be provided by an MPPT in order to operate the DC source (PV module) 3 in its MPP. -
FIG. 16 illustrates a further embodiment of DC/DC converter 6 that can be implemented in a DC/AC converter unit 2 of FIG. it The DC/DC converter ofFIG. 16 is implemented as a boost converter with twoconverter stages converter stages input terminals output terminals converter units FIG. 12 and includes a series circuit with aninductive storage element switch DC converter 6, where the input terminals of the DC/DC converter 6 correspond to theinput terminals converter unit 2. Further, each converter stage includes arectifier element inductive storage element corresponding switch first output terminal 61 of the DC/DC converter 6. Thesecond output terminal 62 of the DC/DC converter 6 is connected to thesecond input terminal 22. - The two
converter stages capacitive storage element 63 between theinput terminals capacitive storage element 68 between theoutput terminals DC converter 6 is available across the secondcapacitive storage element 68. - Referring to
FIG. 16 , the control circuit (controller) 67 of the DC/DC converter 6 generates two PWM drive signals S65 1, S65 2, namely a first drive signal S65 1 for theswitch 65 1 of thefirst converter stage 60 1, and a second drive signal S65 2 for theswitch 65 2 of thesecond converter stage 60 2. According to one embodiment, the first and second boost converter stages 60 1, 60 2 are operated interleaved, which means that there is a time offset between the switching cycles of thefirst switch 65 1 and the switching cycles of thesecond switch 65 2. Providing twoconverter stages DC converter 6. Of course, more than two boost converter stages 60 1, 60 2 can be connected in parallel. - Referring to
FIG. 16 , eachboost converter stage FIG. 17 illustrates a first embodiment of thecontroller 67 configured to generate PWM drive signals S65 1, S65 2 for eachconverter stage - Referring to
FIG. 17 thecontrol circuit 67 is based on thecontrol circuit 67 ofFIG. 13 and includes thesubtraction element 671 receiving the input voltage signal Sv3 and the input voltage reference signal SREF-V3 and thefilter 672 for providing the duty cycle signal SDC. Thecontroller 67 ofFIG. 17 further includes afirst PWM driver 673 1 receiving a first duty cycle signal SDC1 that is dependent on the duty cycle signal SDC provided by thefilter 672 and receiving a first clock signal CLK1, and asecond PWM driver 6731 receiving a second duty-cycle signal SDC2 that is dependent on the duty cycle signal SDC provided by thefilter 672 and receiving a second clock signal CLK2. According to one embodiment, the first and second clock signals CLK1, CLK2 have the same frequency. However, there is a phase shift between the first and second clock signal CLL1, CLK2, so that there is a phase shift between the first PWM drive signal S65 1 provided by thefirst PWM driver 673 1 and the second PWM drive signal S65 2 provided by thesecond PWM driver 673 2. - If the first and second converter stages 60 1, 60 2 would perfectly match so that there would be no risk of unbalanced output currents I6 1, I6 2, the duty cycle signal SDC could be used as the first duty cycle signal SDC1 and as the second duty cycle signal SDC2. However, due to an inevitable mismatch of the components in the converter stages 60 1, 60 2 the output currents I6 1, I6 2 can be unbalanced when the first and second drive signal S65 1, S65 2 would be generated with exactly the same duty cycle.
- In order to compensate for such unbalances of the first and second output currents I6 1, I6 2, the
controller 67 ofFIG. 17 includes an additional control loop, that can be referred to as current balancing loop or power balancing loop. This control loop receives a first output current signal SI61 representing the first output current I6 1 of thefirst converter stage 60 1, and a second output current signal SI62 representing the output current I6 2 of thesecond converter stage 60 2. These output current signals SI61, SI62 can be generated using conventional current measurement units. The output current signals SI61,m SI62 are received by asubtraction unit 675 that generates a further error signal SERR2. The further error signal SERR2 is representative of a difference between the first and second output currents I6 1, I6 2. Further error signal SERR2 is received by afilter 676 that generates a filtered error signal. Thefilter 676 may have a P-characteristic, a I-characteristic, or a PI-characteristic. - A
further subtraction unit 674 1 subtracts the filtered error signal from the duty cycle signal SDC to generate the first duty cycle signal SDC1, and anadder 674 2 adds the filtered error signal to the duty cycle signal DC to generate the second duty cycle signal SDC2. - The operating principle of the
controller 67 ofFIG. 17 is as follows. When the first and second output currents I6 1, I6 2 are identical, the further error signal SERR2 is zero. In this case, the first duty cycle signal SDC1 corresponds to the second duty cycle signal SDC2. When, for example, the first output current I6 1 is larger than the second output current I6 2, the further error SERR2 and the filtered error signal have a positive value. In this case, the duty cycle signal SDC1 (obtained by subtracting the filtered error signal from the duty cycle signal SDC) becomes smaller than the second duty cycle signal SDC2 (obtained by adding the filtered error signal to the duty cycle signal SDC). Thus, the duty cycle of the first drive signal S65 1 becomes smaller than the duty cycle of the second drive signal S65 2 in order to reduce the first output current I6 1 and to increase the second output current I6 2, so as to balance these output currents I6 1, I6 2. -
FIG. 18 illustrates a further embodiment of thecontrol circuit 67 that is configured to balance the output currents I6 1, I6 2. Thecontrol circuit 67 ofFIG. 18 is based on thecontrol circuit 67 ofFIG. 17 . In thecontrol circuit 67 ofFIG. 18 , thesubtraction unit 674 1 that generates the first duty cycle signal SDC1 does not receive the duty cycle signal SDC but receives a filtered version of a difference between the duty cycle signal SDC and the first output current signal SI61. Asubtraction unit 677 1 calculates the difference and a filter 678 1, filters the difference. The filter may have a P-characteristic, an I-characteristic or PI-characteristic. Equivalently, theadder 674 2 that provides the second duty cycle signal SDC2 does not receive the duty cycle signal SDC but receives a filtered difference between the duty cycle signal SDC and the second input current signal SI62. Asubtraction unit 677 2 calculates the difference between the duty cycle signal SDC and the second output current signal SI62, and a filter 678 2 filters the difference. The output signals of the filter 678 1, 678 2 are received by thesubtraction unit 674 1 and theadder 674 2, respectively. - While in the embodiment illustrated in
FIG. 17 a single control loop is employed to regulate the input voltage V3, a dual control loop structure is employed in the embodiment according toFIG. 18 . -
FIG. 19 illustrates a further embodiment of aconverter unit 2 with a DC/AC converter 4. Theconverter unit 2 may further include a DC/DC converter 6 (seeFIG. 9 ) connected between theinput terminals FIG. 13 . Dependent on whether or not theconverter unit 2 includes a DC/DC converter the DC/AC converter 4 receives the input voltage V3 of theconverter unit 2 or the output voltage of the DC/DC converter 4 (not illustrated inFIG. 19 ) as an input voltage. Just for explanation purposes it is assumed that the DC/AC converter 4 receives the input voltage V3. - The DC/AC converter of
FIG. 19 includes abuck converter 80 that receives the input voltage V3 as an input voltage. Thebuck converter 80 is configured to generate an output current i80 which is a rectified version of the output current i1 of the DC/AC converter 4. Assume, for example that a desired waveform of the output current i1 is a sinusoidal waveform. In this case, the output current i80 provided by theconverter 80 has the waveform of a rectified sinusoidal curve or the waveform of the absolute value of a sinusoidal curve, respectively. This is schematically illustrated inFIG. 20 , in which exemplary timing diagrams of a sinusoidal output current i1 and the corresponding output current i80 of theconverter 80 are illustrated. - The output current i1 of the DC/
AC converter 4 is produced from the output current i80 of thebuck converter 80 using abridge circuit 85 with two half-bridges, where each of these half-bridges is connected betweenoutput terminals buck converter 80. Thisbridge circuit 85 can be referred to as unfolding bridge. A first half-bridge includes a first and asecond switch output terminals third switch 85 3 and afourth switch 85 4 connected in series between theoutput terminals second switches first output terminal 23. An output terminal of the second half-bridge, which is a circuit node common to the third andfourth switch second output terminal 24 of theconverter unit 2. Optionally, anEMI filter 88 with two inductances, such as chokes, is coupled between the output terminals of the half-bridges and theoutput terminals converter unit 2. The output capacitance C of theconverter unit 2 that is connected between the output terminals can be part of theEMI filter 88. - Referring to
FIG. 19 , the output current i80 of thebuck converter 80 has a frequency which is twice the frequency of the output current i1. A switching frequency of the switches 85 1-85 4 of thebridge circuit 85 corresponds to the frequency of the output current i1. During a positive half-cycle of the output current i1 the first andfourth switch third switches bridge circuit 85 are driven by drive signals S85 1-S85 4 generated by adrive circuit 88. Timing diagrams of these drive signals S85 1-S85 4 are also illustrated inFIG. 20 . InFIG. 20 , a high signal level of these timing diagrams represents an on-level of the corresponding drive signal S85 1-S85 4. An on-level of the drive signal is a signal level at which the corresponding switch is switched on. The drive signals S85 1-S85 4 may, for example, be generated dependent on the output voltage v80 of thebuck converter 80, where, according to one embodiment, drivecircuit 88 changes the switching state of the switches each time the output voltage v80 has decreased to 0. “Changing the switching state” means either switching the first and thefourth switches 85, 854 on and the other two switches off, or means switching the second and thethird switch - The
buck converter 8 may have a conventional buck converter topology and may include aswitch 83 connected in series with aninductive storage element 84, where the series circuit is connected between thefirst input terminal 21 of theconverter unit 2 or thefirst output terminal 61 of a DC/DC converter (not shown), and thefirst output terminal 81 of thebuck converter 80, respectively. Arectifier element 86 is connected between the second output terminal 82 (corresponding to the second input terminal 22) of the buck converter and a circuit node common to theswitch 83 and theinductive storage element 84. Theswitch 83 can be implemented as a conventional electronic switch, such as a MOSFET or an IGBT, or as a GaN-HEMT. Therectifier element 86 can be implemented as a diode or as a synchronous rectifier. Further, acapacitive storage element 85, such as a capacitor, is connected between the input terminals of thebuck converter 80, and anoptional smoothing capacitor 89 is connected between theoutput terminals - The
switch 83 of thebuck converter 80 is driven by a PWM drive signal S83 generated by a control circuit orcontroller 87. Thecontroller 87 of thebuck converter 80 receives the reference signal SREF from thecontroller 5 of theconverter unit 2. Thecontroller 87 of thebuck converter 80 is configured to generate its output current i80 in correspondence with the reference signal SREF. This reference signal SREF according toFIG. 19 , unlike the reference signal SREF ofFIG. 11 , does not have the waveform of the output current i1, but has the waveform of the rectified output current i1. This reference signal SREF is also generated from the synchronization signal Sv1 and the output current signal Si1. - The
controller 5 for generating the reference signal SREF according toFIG. 19 may correspond to the controllers illustrated inFIGS. 8 and 15 with the difference that the oscillating signal provided at the output of theoscillator 53 is rectified. An embodiment of thecontroller 5 according toFIG. 19 is illustrated inFIG. 21 . Thiscontroller 5 corresponds to the controller according toFIG. 8 with the difference that the output signal of thefilter 53 is received by arectifier 58 that generates a rectified version of the oscillating output signal of theoscillator 53. Mathematically this is equivalent to forming the absolute value of the oscillating output signal of theoscillator 53. The reference signal SREF is available at the output of therectifier 58. -
FIG. 22 illustrates a further embodiment of acontroller 5 that can implemented in the DC/AC converter 4 ofFIG. 19 . Thecontroller 5 ofFIG. 22 is based on thecontroller 5 ofFIG. 15 with the difference that the amplitude signal SREF is generated from the input voltage signal Sv3 voltage signal Sv3 that represents the input voltage V3 provided by theDC source 3, and from the input voltage reference signal SREF-V3. The input voltage reference signal SREF-V3 can be generated by an MPPT, such as anMPPT 7 explained with reference toFIG. 11 . - The control loops illustrated in
FIGS. 15, 21 and 22 could, of course, be amended to be based on the control loop structure ofFIG. 10 instead ofFIG. 8 . - Referring to
FIG. 19 , thecontroller 87 of thebuck converters 80 can be implemented like a conventional controller for providing a PWM drive signal in a buck converter. Thecontroller 86 receives the reference signal SREF and an output current signal Si80, where the output current signal Si80 represents the output current vi80 of thebuck converter 80. Thecontroller 86 is configured to vary the duty cycle of the drive signal S83 such that the output current i80 of thebuck converter 80 is in correspondence with the reference signal SREF. The functionality of thiscontroller 86 corresponds to the functionality of thecontroller 67 illustrated inFIG. 13 . In the embodiment illustrated inFIG. 19 the controller receives the output current signal Si1 representing the output current i1 and the synchronization signal Sv1 for generating the reference signal SREF. However, this is only an example. It would also be possible to generate the reference signal SREF based on signals representing the output voltage v80 and the output current i80 of thebuck converter 80. In this case, the reference signal is generated such that output current i80 and the output voltage v80 of thebuck converter 80 have a given phase difference. - The operating principle of a
power converter circuit 1 including DC/AC converters as illustrated inFIG. 19 will now be explained with reference toFIGS. 1 and 19 . The explanation will be based on the assumption that the voltage of thepower grid 100 is a sinusoidal voltage so that an output current i1 with a sinusoidal waveform is desired. Further, it is assumed that the input powers of the individual DC/AC converters is zero, while the power grid voltage vN is applied to theinput terminals bridge circuits 85 in the individual converter units are in operation. In this case, the smoothingcapacitors 89 of the buck converters are connected in series between theoutput terminals individual capacitors 89 have the same size, the voltage across each of thesecapacitors 89 is 1/n times the power grid voltage vN. - Assume now that the DC/AC converters receives an input power from the
PV modules 3 connected thereto. The DC/AC converters then adjust their common output current i1 to be in phase with the external voltage v1 (the power grid voltage). The amplitude of the output current i1 is, in particular, controlled through the input voltage V3, where the current is increased when the voltage V3 increases, and the current is decreased when the voltage V3 decreases. - When the output current i1 provided by one DC/AC converter decreases, a current that corresponds to a difference between the output current i1 and the common current i1 OUT is provided by the output capacitor C which causes the voltage v2 across the output capacitor C to decrease until the input power provided to the DC/AC converter corresponds to its output power. A decrease of the voltage v2 across the
output capacitor 89 of one DC/AC converter 4 or oneconverter unit 2 causes an increase of the voltages across the output capacitors of the other converter units. This process proceeds until theconverter unit 2 has settled in stable operation point at a lower output current i1. If theother converter units 2 at first continue to run at the same duty cycle, the increase of the voltages across their output capacitors leads to a reduction of their output currents i1 (and hence to a reduction of the common output current) in order to keep their output powers equal their input powers. When the output current i1 provided by one DC/AC converter increases so as to be higher than the common current i1 OUT, the corresponding output capacitor C is charged which results in an increase of the voltage across the output capacitor C of the one converter and a decrease of the voltage across the output capacitors of the other converters. - It became obvious from the explanation provided before that besides the control loops in the
individual converter units 2 no additional control loop is required in order to control the output voltages of theindividual converter units 2. Thepower converter circuit 1 with theconverter units 2 is “self-organizing.” Referring toFIG. 1 , assume that, for example, in the steady state the input power provided by thefirst DC source 3 1 to thefirst converter unit 2 1 would drop, for example because the corresponding PV array is shaded. The output voltage v2 1 of thecorresponding converter unit 2 would then drop, while the output voltages of theother converter units first converter unit 2 1 decreases, the common output current i1 OUT at first remains unchanged, while the output current i1 1 of thefirst converter unit 2 1 decreases. The decrease of the output current i1 1 and the unchanged common output current i1 OUT1 causes a discharging of the output capacitor C1 of thefirst converter unit 2 1 so that the output voltage v2 1 decreases. A decrease of the output voltage of the first converter unit, however, causes an increase of the output voltages of the other converters, which now decrease their output currents in order to keep their output powers equal their input powers. The transition processes finishes when a “new” common output current iOUT our has settled in to which the individual output currents i1 correspond. This is a self-organizing and self-stabilizing process that does not require and additional control loop besides the control loops in theindividual converter units 2 disclosed before. -
FIG. 23 illustrates a further embodiment of a power converter circuit. In this power converter circuit twoseries circuits output terminals series circuits series circuit 1 of converter units 2 1-2 n explained before. The converter units of the two groups (the two series circuits) are coupled to thesame synchronization circuit 10 that can be implemented in accordance with one of the embodiments explained before. Of course, more than two series circuits each with a plurality of converter units can be connected in parallel. - Referring to the explanation herein before, the
synchronization circuit 10 can be implemented as a voltage measurement circuit that measures the external AC voltage v1 and that generates the at least one synchronization signal Sv1 such that the synchronization signal is a continuous signal representing the external AC voltage v1 and, therefore, having the same frequency and phase as the external AC voltage v1.FIG. 24 illustrates a further embodiment of thesynchronization circuit 10. - In the embodiment illustrated in
FIG. 24 , thesynchronization circuit 10 receives the external AC voltage v1 available at theoutput terminals synchronization circuit 10 receives a phase-shift signal SPS that defines a desired phase shift between the synchronization signal Sv1 and the external AC voltage v1. In the embodiment illustrated inFIG. 24 , thesynchronization circuit 10 includes a phase-shift circuit 110 that provides an output voltage v1′. The output voltage v1′ of the phase-shift circuit 110 has a phase shift relative to the external AC voltage v1, with the phase shift being defined by the phase-shift signal SPS.A transmission circuit 120 receives the output voltage v1′ of the phase-shift circuit 110 and generates the at least one synchronization signal Sv1 transmitted to the individual converter units 2 (not illustrated inFIG. 24 ). - Referring to
FIG. 25 , thetransmission circuit 120 may be implemented as a voltage divider having a plurality ofvoltage divider elements transmission circuit 120 is similar to the voltage divider illustrated inFIG. 3 . The individual voltage divider elements 120 1-120 n of thevoltage divider 120 can be implemented like thevoltage divider elements 10 i explained with reference toFIGS. 4A to 4C and 5 . Referring toFIG. 25 , each of the voltage divider elements 120 1-120 n provides a voltage v1 1′, v1 2′, v1 n′, with each of these voltages representing one synchronization signal received by one converter unit 2 (not illustrated inFIG. 25 ) in the same way as the individual converter units 2 1-2 n ofFIG. 3 receive the individual voltages v1 1, v1 2, v1 n. - When employing a
synchronization circuit 10 as illustrated inFIG. 24 , a phase shift between the output currents i1 of theindividual converter units 2 and the external AC voltage v1 can be adjusted through the phase-shift signal SPS, so that there is no need to individually provide phase shift signals (S100 inFIGS. 15, 21 and 22 ) to theindividual converter units 2. However, it is of course possible to additionally provide phase shift signals to theindividual converter units 2. - Transmitting the at least one synchronization signal Sv1 to the individual converter units through a voltage divider, as illustrated in
FIG. 25 , is only one possible embodiment. According to further embodiments, the at least one synchronization signal Sv1 is transmitted to theindividual converter units 2 via a signal bus, a radio path, or via a power line using power line communication. Of course, corresponding receiver circuits are employed in theconverter units 2 in this case. - Referring to power line communication, standard power line communication circuits can be used for the communication between the
synchronization circuit 10 and theindividual converter units 2 since the output current Because iOUT of the converter circuit is an AC current. In this case, the power line of theconverter circuit 1, which is the line carrying the output current iOUT and connecting the outputs of theindividual converter units 2 is used for the communication. A first power line communication interface (not shown) coupled to the power line receives the synchronization signal SV1 and forwards the synchronization signal Sv1 suitably modulated via the power line to theindividual converter units 2. Each converter unit includes a corresponding power line communication interface coupled to the power line and configured to receive and demodulate the modulated synchronization signal Sv1. - According to a further embodiment, that is illustrated in dashed lines in
FIG. 24 , the synchronization circuit does not only receive a phase-shift signal SPS but additionally to the phase shift signal SPS or instead of the phase shift signal SPS receives a control signal SCTRL through which other parameters of the synchronization signal SV1, such as the frequency and/or the amplitude of the synchronization signal SV1 can be adjusted. In this embodiment, the synchronization signal SV1 can be generated independent of the external AC voltage v1, which may be helpful in some operation scenarios explained below. - Referring to the explanation herein before, the synchronization signal Sv1 received by each
converter unit 2 can be a continuous signal that is continuously transmitted from thesynchronization circuit 10 to theconverter units 2. Each of theconverter units 2 continuously generates its corresponding output current i1 in accordance with the synchronization signal Sv1, which means with a frequency and a phase defined by the synchronization signal Sv1. - According to a further embodiment, the synchronization signal Sv1 is a pulse signal including a sequence of signal pulses and the
individual converter 2 units are configured to generate a continuous signal having a frequency and a phase from the pulse signal. -
FIG. 26 illustrates an embodiment of aconverter unit 2 that is configured to receive a pulse signal as a synchronization signal Sv1. The converter unit ofFIG. 26 corresponds to the converter units ofFIGS. 5 and 11 and additionally includes asignal generator 20 that receives the pulsed synchronization signal Sv1 and that is configured to generate a continuous sinusoidal synchronization signal Sv1′ from the pulsed signal Sv1. In this embodiment, the continuous synchronization signal Sv1′ provided at the output of thesignal generator 20 is received by thecontrol circuit 5 and is processed in thecontrol circuit 5 in the same way as a continuous sinusoidal synchronization signal Sv1 explained herein before. - According to one embodiment, the pulsed synchronization signal Sv1 is a periodic signal having signal pulses that are equally distant, and
signal generator 20 is configured to generate a sinusoidal signal Sv1′ from the pulsed signal Sv1. According to one embodiment, thesignal generator 20 generates the sinusoidal synchronization signal Sv1′ such that a zero crossing of the sinusoidal signal Sv1′ occurs each time a signal pulse of the pulsed synchronization signal Sv1 occurs. In this embodiment, the mutual distance of the signal pulses defines the frequency of the continuous synchronization signal Sv1′ generated by thesignal generator 20 and the absolute position of the individual signal pulses on the time scale defines the phase of the continuous synchronization signal. An embodiment of a signal generating 20 configured to receive a pulsed synchronization signal Sv1 and configured to generate a continuous sinusoidal synchronization signal Sv1′ with a frequency and a phase as defined by the pulsed synchronization signal Sv1 is illustrated inFIG. 27 . Timing diagrams of signals occurring in this signal generator are illustrated inFIG. 28 . - Referring to
FIG. 27 , the signal generator includes anintegrator 202 receiving the pulsed synchronization signal Sv1 as a clock signal. A timing diagram of an embodiment of the pulsed synchronization signal Sv1 is illustrated inFIG. 28 . The integrator is configured to integrate a constant signal C received at a second input beginning with each signal pulse of the pulsed synchronization signal Sv1′. An output signal of theintegrator 202 is a ramp signal SRAMP with a frequency corresponding to the frequency of the pulsed synchronization signal Sv1′. The constant signal is provided by acalculation unit 201 that receives pulsed signal Sv1 and calculates the constant signal C to be proportional to the frequency of the pulsed synchronization signal Sv1′ or to be inversely proportional to a time period T (seeFIG. 28 ) of the pulsed signal Sv1 ′. In the steady state, the slope of the individual ramps of the ramp signal SRAMP is dependent on the frequency (and decreases when the frequency is reduced) and the amplitudes of the individual ramps are equal. According to one embodiment, thecalculation unit 201 calculates the constant value C in each cycle of the pulsed signal Sv1′ and provides the calculated value to the integrator in the next cycle. Thus, a frequency change of the synchronization becomes effective in the generation of the ramp signal SRAMP with a delay of one cycle of the pulsed signal. - Referring to
FIG. 27 , atrigonometric function generator 203 receives the ramp signal SRAMP and generates the continuous synchronization signal Sv1′ by calculating the sine or the cosine of instantaneous values of the ramp signal SRAMP. The resulting continuous synchronization signal Sv1′ is illustrated inFIG. 28 . In the embodiment illustrated inFIGS. 27 and 28 the continuous synchronization signal Sv1′ has a zero crossing from negative to positive signal values each time a signal pulse of the pulsed synchronization signal occurs. - Of course, the signal generator of
FIG. 27 could easily be modified to generate the continuous synchronization signal Sv1′ such that with each pulse of the pulsed signal Sv1 a zero crossing from positive to negative signal values occurs. - According to one embodiment, the pulsed synchronization signal Sv1 is only transmitted for a short time when a frequency and/or phase of the pulsed signal changes. This means, only a short sequence with some cycles of the pulsed signal Sv1 is transmitted, while after the transmission of the sequence the pulsed signal is interrupted for a time period significantly longer than one cycle period. This interruption may be several seconds or several minutes. In this embodiment, a clock generator receives the pulsed signal Sv1. The clock generator is configured to measure the frequency of the pulsed signal Sv1 and to generate a clock signal provided to the integrator with a frequency corresponding to the measured frequency of the pulsed signal Sv1. The clock generator is, in particular configured to store the frequency information and to generate the clock signal even in those time periods when the pulsed signal Sv1 has been switched off and updates the frequency each time a new sequence of the pulsed signal Sv1 is transmitted. Equivalently, the calculation unit stores the calculated value C until a new sequence of the pulsed signal Sv1 is transmitted that allows the
calculation unit 201 to re-calculate the constant value. - According to a further embodiment, the synchronization signal Sv1 is an AC signal that is only transmitted for a certain time period, such as, for example, for a duration corresponding to only several periods of the AC signal. In this embodiment, the
signal generator 20 is configured to evaluate a frequency and a phase information of the synchronization signal Sv1 and is configured to generate the continuous synchronization signal Sv1 based on this frequency and time information. In this embodiment, the synchronization signal Sv1 may be transmitted only once at the beginning of the operation of thepower converter circuit 1 to the individual converter units, or may be transmitted periodically during the operation of thepower converter circuit 1. - An embodiment of a
signal generator 20 that is configured to generate a continuous (sinusoidal) synchronization signal Sv1′ from a synchronization signal Sv1 that is available for only several periods is illustrated inFIG. 29 . The signal generator ofFIG. 29 is based on the signal generator ofFIG. 27 and additionally includes azero crossing detector 205 receiving the synchronization signal Sv1 and configured to generate a pulse signal. The pulse signal generated by the zero crossing detector includes a signal pulse each time a positive or a negative zero crossing is detected. The pulse signal provided by the zerocrossing detector 205 is then processed by theclock generator 204, thecalculation unit 201, theintegrator 202, and thetrigonometric function generator 203 as explained with reference toFIGS. 27 and 28 . In this embodiment, the continuous synchronization signal Sv1′ is synchronized to the synchronization signal Sv1 during that time period when the synchronization signal Sv1 is available and, after the synchronization signal has been switched off, continues to generate the continuous synchronization signal Sv1′ based on the frequency and phase information stored in theclock generator 204 and thecalculation unit 201. - According to a further embodiment, the synchronization signal Sv1 transmitted to the individual converter units corresponds to the frequency and phase signal Sωt explained with reference to
FIGS. 15, 21 and 22 . In this embodiment, thesignal generator 20 can be omitted and thecontrol circuit 5 can be simplified by omitting thePLL 51. - In each of the individual cases where different signal waveforms of the synchronization signal Sv1 have been discussed, the synchronization signal Sv1 can be generated by the
synchronization circuit 10 connected betweenoutput terminals - So far, the operation of the power converter circuit in a normal operation mode has been explained. In the normal operation mode, each of the
individual converter units 2 is configured to generate its output current i1 such that the output current i1 has a frequency and the phase as defined by the synchronization signal Sv1 received by theconverter unit 2. Besides the normal operation mode, other operation modes of thepower converter circuit 1 can be utilized as well. - According to one embodiment, that is schematically illustrated in
FIG. 30 , thepower converter circuit 1 is either operated in thenormal mode 901 or in astandby mode 902. In thestandby mode 902 theindividual converter units 2 are deactived so that the output currents i1 of theindividual converter units 2 are zero, but may again be activated. - For example, the power converter is, e.g., in the standby mode, when the supply voltages (V3 1-V3 n in
FIG. 1 ) provided by the DC power sources are too low for generating the output currents it When the individual DC power sources 3 1-3 n are implemented as PV modules, this may occur at night. - The
power converter circuit 1 switches from thenormal mode 901 to thestandby mode 902 when a shut-down condition is met, and changes from thestandby mode 902 to the normal mode when a start-up condition is met. The process of switching thepower converter circuit 1 from the normal mode to the standby mode will be referred to as shut down and a sequence of operations involved in this process will be referred to as shut-down sequence in the following. The process of switching thepower converter circuit 1 from the standby mode to the normal mode will be referred to as start-up and a sequence of operations involved in this process will be referred to as start-up sequence in the following. - The
power converter circuit 1 may include an operation mode controller that defines the operation mode of thepower converter circuit 1. With other words, theoperation mode controller 50 controls the overall operation of thepower converter circuit 1.FIG. 31 illustrates a block diagram of apower converter circuit 1 that includes anoperation mode controller 50. Theoperation mode controller 50 can be implemented as a microprocessor, an ASIC, a digital signal processor, a state machine, or the like. - In the embodiment illustrated in
FIG. 31 , theoperation mode controller 50 receives at least one operation parameter of thepower converter circuit 1 from ameasurement unit 600, is configured to control aconnection circuit 70 connected between the series circuit with the individual converter units 2 1-2 n and theoutput terminals synchronization unit 10. Themeasurement circuit 600 is configured to measure at least one of the output current iOUT of the series circuit with the converter units 2 1-2 n, and a voltage vOUT across the series circuit 2 1-2 n. As schematically illustrated inFIG. 31 , themeasurement circuit 600 may include acurrent measurement circuit 600 for measuring the output current iOUT, and avoltage measurement circuit 602 for measuring the output voltage vOUT. The output voltage vOUT across the series circuit corresponds to the external AC voltage v1 when the series circuit is connected to theoutput terminals connection circuit 70 that is configured to either connect the series circuit 2 1-2 n to theoutput terminals output terminals first switch 701 connected between the series circuit 2 1-2 n and thefirst output terminal 11 and asecond switch 702 connected between the series circuit 2 1-2 n and thesecond output terminal 12. Theseswitches FIG. 31 , theconnection circuit 70 may include an optionalthird switch 703 connected in parallel with the series circuit 2 1-2 n. Thisswitch 703 may be closed when an output voltage of the series circuit with theindividual converter units 2 is above a given voltage threshold, in order to limit the output voltage. Optionally, a resistor or another type of current limiting element is connected in series with thisswitch 703. - In
FIG. 31 , signal S600 provided by themeasurement circuit 600 to theoperation mode controller 50 represents the at least one operation parameter measured by themeasurement circuit 600. This measurement signal S600 includes information on at least one of the output current iOUT and the output voltage your. Signal S70 inFIG. 31 schematically illustrates a control signal generated by theoperation mode controller 50 and received by theconnection circuit 70. Dependent on the control signal S70, theconnection circuit 70 connects the series circuit to theoutput terminals output terminals - Referring to
FIG. 31 , theoperation mode controller 50 further controls thesynchronization circuit 10 that generates the synchronization signal Sv1. InFIG. 31 , only the control signal SCTRL is drawn to be received by thesynchronization circuit 10. The control signal SCTRL defines the signal parameters of the synchronization signal Sv1, such as frequency, phase and amplitude. As controlled by the control signal SCTRL the synchronization signal Sv1 can dependent on the external AC voltage v1 also received by thesynchronization circuit 10, such as have a given phase shift (zero or other than zero) relative to the external AC voltage, or the synchronization signal Sv1 can be independent of the external AC voltage v1. Referring to the explanation below, there may be operating scenarios (such as fault ride through) where it is necessary to generate the synchronization signal Sv1 independent of the external AC voltage v1. - In the power converter circuit of
FIG. 31 , the synchronization signal Sv1 is not only used in the normal mode to provide a synchronization information to theindividual converter units 2 for generating the output currents i1, but is also used in the standby mode for signaling theindividual converter units 2 that a change from the standby mode to the normal mode is desired. In thispower converter circuit 1, theoperation mode controller 50 has thesynchronization circuit 10 generate the synchronization signal Sv1 with a standby waveform in the standby mode. The standby waveform is a waveform that is different from the signal waveform of the synchronization signal Sv1 in the normal mode. According to one embodiment, the standby waveform is a waveform with a constant signal value, such as zero. -
FIG. 32 illustrates an embodiment of aconverter unit 2 that is configured to evaluate the operation mode information included in the synchronization signal Sv1 and that can be operated in a normal mode or a standby mode. The overallpower converter circuit 1 is in the normal mode when each of theconverter units 2 is in the normal mode and is in the standby mode when each of the converter units is in thestandby mode 2. Theconverter unit 2 shown inFIG. 32 is based on the converter units ofFIGS. 5, 11 and 26 , where the DC/DC converter 6 and itscontrol circuit 7, and thesignal generator 20 are optional. Theconverter unit 2 includes anoperation mode unit 30 that receives the synchronization signal Sv1 and that is configured to evaluate the synchronization signal Sv1. Theoperation mode unit 30 is, in particular, configured to detect a change of the synchronization signal Sv1 from the standby waveform to the normal waveform, the latter being the usual waveform in the normal mode. Referring to the explanation above, the normal waveform can be a continuous AC waveform, a pulsed signal waveform, or an AC waveform with only periods. - The
operation mode unit 30 is further configured to control the DC/AC converter 4, in particular to activate the DC/AC converter 4 in the normal mode and to deactivate the DC/AC converter in the standby mode. When theconverter unit 2 further includes the DC/DC converter 6, theoperation mode unit 30 further controls the operation (activates or deactivates) of the DC/DC converter 6. When the DC/AC converter 4 and the optional DC/DC converter 6 is activated, the operating principle of theconverter unit 2 corresponds to the operating principle explained before, which means theconverter unit 2 provides an output current i1 in accordance with the synchronizations signal Sv1. When the DC/AC converter 4 and the optional DC/DC converter 6 are deactivated, the switches (seeFIGS. 6 and 19 ) in the DC/AC converter 4 and the DC/DC converter are either switched off, or some of the switches are permanently switched on. This is explained in greater detail below. - In the standby mode, the
operation mode controller 50 either disconnects the series circuit 2 1-2 n from theoutput terminals output terminals - Embodiments of start-up sequences for switching from the standby mode to the normal mode are explained below. For explanation purposes it is assumed that the individual DC power sources are PV modules. In this case, a start-up sequences is required at least once a day, namely in the morning after sunrise.
- A first embodiment of a start-up sequence (start-up sequence A) is illustrated in
FIG. 33 . In this embodiment, theindividual converter units 2 in thestandby mode 902 are configured to pass the input voltage V3 from theinput terminals output terminals operation mode controller 50 is configured to have theconnection circuit 70 disconnect the series circuit 2 1-2 n from theoutput terminals - The input voltage V3 can be connected through the
converter unit 2 to theoutput terminals AC converter 4 and the optional DC/DC converter 6 in a specific configuration. When, for example, the DC/AC converter 4 is implemented with a H4-bridge as illustrated inFIG. 6 , the input voltage V3 can be connected through to theoutput terminals first switch 42 1 and thefourth switch 42 4. When the optional DC/DC converter 6 is a boost converter, as illustrated inFIG. 12 , theswitch 65 is permanently switched off, and when the optional DC/DC converter 6 is a buck converter, as illustrated inFIG. 14 , theswitch 65 is permanently switched on. The switching states of the switches in the DC/AC converter 4 and the DC/DC converter 6 in the standby mode is governed by theoperation mode unit 30. - When, for example, the DC/AC converter is implemented with a buck converter and an unfolding bridge as illustrated in
FIG. 19 , the input voltage V3 can be connected through to theoutput terminals first switch 85 1 and thefourth switch 85 4 in the unfoldingbridge 85 and by switching on theswitch 83 in thebuck converter 80. - After sunrise, the input voltage V3 at the
input terminals operation mode controller 50 is configured to detect the output voltage vOUT. The output voltage vOUT is the sum of the output voltages v2 of theindividual converter units 2, where this output voltage vOUT increases after sunrise when the solar power received by the PV modules increases. When the output voltage vOUT reaches a given threshold voltage vOUT-TH, theoperation mode controller 50 controls thesynchronization circuit 10 to generate the synchronization signal Sv1 with the normal waveform has theconnection circuit 70 connect the series circuit 2 1-2 n to theoutput terminals - The
operation mode unit 30 detects the change of the synchronization signal Sv1 from the standby level to the normal level. Theoperation mode unit 30 then activates the DC/AC converter 4 and the optional DC/DC converter 6 to operate as explained with reference toFIGS. 1 to 23 before. According to one embodiment, the DC/AC converter 4 and the optional DC/DC converter 6 are activated at the time of a zero crossing of the synchronization signal Sv1, so as to ramp up the output current i1. - According to one embodiment, not only frequency and phase of the output current i1, but also the amplitude of the output current i1 is controlled during the start-up phase so as to, e.g., continuously increase the output current in the start-up phase. The output current i1 of each
converter 2 can be controlled by controlling the input power of theconverter 2. Controlling the input power is possible in each converter topology in which the input voltage V3 is controlled, that is in each topology where the input voltage V3 is adjusted dependent on an input voltage reference signal SV3-REF. In the normal mode, the input voltage reference signal SV3-REF may be generated by an MPP tracker (see,circuit block 7 inFIGS. 11 and 32 ) that serves to operatePV modules 3 providing the input voltage V3 in an optimum operation point. In order to control the input voltage V3 and, therefore, in order to control the output current i1 during start-up, the operationmode control circuit 30 can be configured to provide the input voltage reference signal SREF-V3 during start-up or can be configured to control theMPP tracker 7 during start-up. This is schematically illustrated in dotted lines inFIG. 32 . During the start-up phase, thePV modules 3 are not necessarily operated in their MPP. According to one embodiment, the operationmode control circuit 30 increases the input voltage reference signal SREF-V3 stepwise in two, three or more steps, so as to stepwise increase the amplitude of the AC output current i1 of theindividual converter units 2. - When in the
converter unit 2 ofFIG. 32 , the DC/AC converter 4 includes abuck converter 80 and an H4-bridge 85, as illustrated inFIG. 19 , thebuck converter 80 can be configured to control the input voltage V3. The DC/DC converter 6 may be omitted in this case. An embodiment of acontrol circuit 5 that is configured to control the input voltage V3 in the DC/AC converter 4 ofFIG. 19 is illustrated inFIG. 22 . While in the normal mode, the input voltage reference signal SV3-REF is provided by an MPP tracker (not illustrated inFIGS. 19 and 22 ), the input voltage reference signal SV3-REF may be provided by theoperation mode unit 30 during the start-up phase in order to control the output current i1 during the start-up phase. - Switching on the switches in the DC/
AC converter 4 and the optional DC/DC converter 6 in the standby mode requires a power supply. Referring toFIG. 32 , eachconverter unit 2 includes apower supply unit 40 that provides for the power supply of the individual components in theconverter unit 2. Thepower supply unit 40 is either connected to theinput terminals output terminals DC converter 6 and the DC/AC converter 4, to the DC link capacitor. - When the
power supply unit 40 is connected to theinput terminals AC converter 4 and the DC/DC converter 6 is, of course, only provided when an input voltage V3 other than zero is provided by the DC power source. Thus, after sunrise, the input voltage V3 first powers thepower supply unit 40, which powers the components in thepower converter unit 2, which then passes the input voltage V3 through to theoutput terminals operation mode controller 50, which then has theconverter unit 2 change to the normal mode by having thesynchronization circuit 10 change the synchronization signal Sv1 from the standby waveform to the normal waveform. Before solar power is provided to the PV modules, i.e., when the input voltage V3 is zero, each of the switches in theconverter unit 2 is switched off and the converter unit cannot be activated. This operation mode can be referred to as shut-off mode. - A second embodiment of a start-up sequence (start-up sequence B) is illustrated in
FIG. 34 . In this embodiment, theoperation mode controller 50 leaves the series circuit 2 1-2 n connected to theoutput terminals power converter circuit 1 is in the standby mode. Theindividual converter units 2 are deactivated, so that the output current iOUT is zero and the output voltage vOUT corresponds to the external AC voltage v1. The external AC voltage v1 charges the input capacitor of the DC/AC converter 4, which is the DC link capacitor when a DC/DC converter 6 and a DC/AC converter 4 are employed. The charging of the input capacitor of the DC/AC converter 4 is explained for the DC/AC converter topologies ofFIGS. 6 and 19 below. Referring toFIG. 6 , the switches of the H4-bridge each have a freewheeling element 42 1-42 4. Via these freewheeling elements the input capacitor 41 (or theDC link capacitor 600 ofFIG. 11 ) is charged to the peak value of the AC voltage v2 between theoutput terminals FIG. 32 ) controls the switches of a DC/AC converter 4 implemented with a H4-bridge to be switched off. - When the DC/
AC converter 4 is implemented with an unfoldingbridge 85 as illustrated inFIG. 19 , theDC link capacitor 89 is charged through freewheeling elements (not illustrated inFIG. 19 ) of the individual switched 85 1-85 4 to the peak value of the AC input voltage v2. - In this embodiment, the
power supply unit 40 is connected to the input capacitor of the DC/AC converter 4 or to the DC link capacitor which permanently provides for a power supply of theconverter unit 2. - While in the start-up sequence A the power converter automatically enters the normal mode when sufficiently high input voltages V3 are provided, an additional trigger signal is required in the start-up sequence B informing the
operation mode controller 50 that thepower converter circuit 1 may switch from the standby mode to the normal operation mode. According to one embodiment, the trigger signal is a signal indicating the sunrise and, therefore the time when enough solar power is expected to be received by the individual PV modules in order to successfully switch from the standby mode to the normal mode. This trigger signal can be provided from an external source to theoperation mode controller 50 or can be calculated in theoperation mode controller 50 dependent on the specific date, the geographical position of the PV modules and a table that includes the time of sunrise at the geographical position at different dates. This signal triggering a switching from the standby mode to the normal mode will be referred to as trigger signal or sunrise signal in the following. - According to a further embodiment (start-up sequence C), which includes features from both, the start-up sequences A and B, the
operation mode controller 50 leaves the series circuit 2 1-2 n disconnected from theoutput terminals converter units 2 are configured to pass through the input voltage V3 to theoutput terminals power converter circuit 1 from the standby mode to the normal mode is initiated by the sunrise signal. Again, switching from the standby mode to the normal mode includes changing the waveform of the synchronization signal Sv1 from the standby waveform to the normal waveform. - There may be several reasons for the
power converter circuit 1 to switch from the normal mode to the standby mode. According to one embodiment, theoperation mode controller 50 is also configured to cause thepower converter circuit 1 to switch from the normal mode to the standby mode when theoperation mode controller 50 detects the occurrence of a shut-down condition. A shut-down information can be transmitted from theoperation mode controller 50 to theindividual converter units 2 in different ways. When a shut-down information is received by theindividual converter units 2, the converter units are deactivated and enter the standby mode. - As explained above in connection with start-up sequence I, the
operation mode controller 50 can be configured to only start-up thepower converter circuit 1 when the output voltage vOUT our in the standby mode is higher than a given reference voltage. There may be several reasons why the output voltage vOUT is too low. First, the solar power received by the PV modules can be too low. Second, there are notenough converter units 2 connected in series. - According to a first embodiment, the synchronization signal Sv1 is used to transmit a shut-down information from the
operation mode controller 50 to theindividual converter units 2. Independent of the waveform of the synchronization signal Sv1 in the normal mode, theoperation mode controller 50 simply controls thesynchronization circuit 10 to generate a standby waveform of the synchronization signal Sv1. Theoperation mode units 30 in theindividual converter 2 are configured to detect the standby waveform and to deactivate the corresponding converter unit upon detection of the standby waveform. In the standby mode, the output currents i1 of theindividual converter units 2 become zero. - According to a further embodiment, the
operation mode controller 50 has theconnection circuit 70 to disconnect the series circuit from theoutput terminals converter units 2 are still in the normal mode, the output current provided by eachconverter unit 2 causes the output voltages v2 of theindividual converter units 2 to increase, so that the overall output voltage your increases. In this embodiment, theconverter units 2, are configured to detect their output voltage v2 and are configured to enter the standby mode when the output voltage increases to an overvoltage threshold. According to one embodiment, theoperation mode unit 30 of eachconverter unit 2 monitors the output voltage v2 and compares the output voltage with the overvoltage threshold and shuts down theconverter unit 2 when the output voltage v2 reaches the overvoltage threshold. According to one embodiment, the overvoltage threshold is chosen to be dependent on the voltage blocking capability of the semiconductor switches employed in the DC/AC converter 4 of eachconverter unit 2. - In this embodiment, there is no direct transmission of information from the
operation mode controller 50 to theindividual converter units 2. Instead, the switching information is provided by allowing the output voltages v2 of theindividual converter units 2 to increase to the overvoltage threshold. - Also in those cases in which the synchronization signal is used to transmit the switching information, so that there is no intended overvoltage in the
individual converter units 2, an overvoltage of the output voltages of oneconverter unit 2 may occur, e.g., when disconnecting the series circuit 2 1-2 n from the power grid. Thus, an overvoltage protection may be implemented in theindividual converter units 2 in each case. - Some embodiments of shut-down conditions (errors) that can be detected by the operation mode controller are explained below. Dependent on the type of error, the
operation mode controller 50 may try to restart thepower converter circuit 1 after a certain time, or may keep the power converter circuit shut down. - According to one embodiment, the power converter circuit switches from the normal mode to the standby mode, when the output current falls below a given current threshold. This transfer is initiated by the
operation mode controller 50 that compares the output current iOUT based on information received from themeasurement unit 600 with the current threshold. The current threshold is, for example, chosen from a range of between 0.2 A and 0.5 A. - Another type of error may occur when the solar power received by each of the
converter units 2 is low. In this case, the output current iOUT of the series circuit with theindividual converter units 2 may have a non-sinusoidal waveform such that the waveform of the output current iOUT follows the waveform of the external AC voltage v1 when the instantaneous value of the output voltage v1 is low, and that the output current iOUT is kept on a constant value or even decreases at higher instantaneous values of the output current. This type of error can be detected by theoperation mode controller 50 by comparing the waveform of the output voltage vOUT or the external AC voltage v1, respectively, and the output current iOUT. When this type of error is detected by theoperation mode controller 50, theoperation mode controller 50 initiates one of the shut-down sequences explained above in order to switch thepower converter circuit 1 into the standby mode. - According to a further embodiment, the
operation mode controller 50 is configured to measure a phase difference between a phase of the external AC voltage v1 and the output current iOUT. When this phase difference is larger than a desired phase difference, namely the phase difference given by the synchronization signal Sv1 v1 and/or the phase difference as defined by the phase signals Sφ, two different courses of action initiated by theoperation mode controller 50 are possible. When, for example, the phase difference between the output voltage iOUT and the external AC voltage v1 is below a first phase difference threshold, the phase difference of the synchronization signal Sv1 relative to the external AC voltage v1 can be changed in order to readjust the phase difference between the output current iOUT and the external AC voltage v1. When, however, the phase difference is above the phase-difference threshold, theoperation mode controller 50 may shut down thepower converter circuit 1 using one of the shut-down sequences explained before. - Similar to having the power converter start-up using a trigger signal at sunrise, a corresponding trigger signal can be used to shut-down the power converter circuit at sunset.
- When, for example, the solar power received by some of the PV modules is much lower than the solar power received by other modules, the output voltage of the
converter units 2 connected to the PV modules receiving a low solar power decreases, while the output voltage of theother converter units 2 increases. This mechanism has been explained in detail herein before. When there are several PV modules that receive a significantly lower solar power than other modules, the external AC voltage v1 applied to theoutput terminals other converter units 2. Theconverter units 2 having an overvoltage may shut down, which results in an overvoltage at the outputs ofother converter units 2, which are then shut down. This proceeds, until each of theconverter units 2 is shut down. When theconverter units 2 are shut down, the output current becomes zero. In this case, theindividual converter units 2 automatically shut down, so that no shut-down information has to be transmitted from theoperation mode controller 50 to theindividual converter units 2. A decrease of the output current to zero is detected by theoperation mode controller 50 which may then cause thesynchronization circuit 10 to generate a standby waveform of the synchronization signal Sv1. - The
operation mode controller 50 may not only be configured to monitor the operation of thepower converter circuit 1, but may also be configured to monitor the power grid, specifically the external AC voltage v1, in order to shut down thepower converter circuit 1 when an error is detected. - A first type of grid error that may occur is “islanding.” In this case, the power grid has a high input impedance at the
input terminals converter units 2 generate a constant output current iOUT or an AC output current iOUT with a frequency that is different from the frequency of the external AC voltage v1. As explained hereinbefore, the frequency of the output current iOUT (which is zero, when the output current iOUT is constant) can be adjusted through the synchronization signal Sv1. - In order to test for the occurrence of an islanding error, the
operation mode controller 50 can be configured to have thesynchronization circuit 10 generate the synchronization signal with a frequency other than the frequency of the external AC voltage v1. In a test mode in which theoperation mode controller 50 changes the output current iOUT as explained before, theoperation mode controller 50 compares the waveform of the output current iOUT with the waveform of the external voltage v1 available at theoutput terminals output terminals 11, 12). In this case, the operation mode controller shuts down thepower converter circuit 1. - According to one embodiment, the
operation mode controller 50 is configured to monitor the external AC voltage v1 and is configured to shut down thepower converter circuit 1 when the external AC voltage v1 is switched off or interrupted. - According to one embodiment, the
operation mode controller 50 does not shut down thepower converter circuit 1 immediately when the external AC voltage v1 is interrupted, but has the series circuit generate an AC output current iOUT for a specified time period, such as, for example, several milliseconds (ms). Theoperation mode controller 1 shuts down thepower converter circuit 1 when the external AC voltage v1 has not recovered after this specified time period. The operation mode in which an AC output current iOUT is provided although the external AC voltage v1 has been interrupted, is out phase, lower than usual, distorted, short-circuited, etc., is referred to as “fault ride through.” - In the fault-ride-through mode, the synchronization information in accordance to which the
individual converter units 2 generate their output currents i1 can be provided in different ways. An embodiment, in which the synchronization information is only transmitted at the beginning of the normal mode and in which a continuous synchronization signal is generated (in the signal generator 20) in theindividual converter units 2, no additional synchronization information needs to be provided in the fault-ride-through mode. When, however, theindividual converter units 2 require a continuous synchronization signal, and when the synchronization signal in the normal mode is generated from the external AC voltage v1, thesynchronization circuit 10 in the fault-ride-through mode continuous to generate a continuous synchronization signal based on the frequency and phase information of the synchronization signal generated before in the normal mode, i.e., before an interruption of the external AC voltage v1 has been detected. - The
power converter circuit 1 may even be used to stabilize the voltage on the power grid. - Referring to the explanation provided before, in the normal mode, the output current iOUT generated by the series circuit of the
individual converter units 2 has a frequency and a phase as defined by the synchronization signal Sv1. The frequency and the phase of the synchronization signal Sv1 can be adjusted by theoperation mode controller 50. In the normal mode, the synchronization signal Sv1 is usually generated such that the frequency information included in the synchronization signal Sv1 corresponds to the frequency of the external AC voltage v1 and the phase information corresponds to the phase of the external AC voltage v1. In this case, the output current iOUT is in phase with the external AC voltage v1. - However, there may be situations in which it is desired to have a phase difference between the output current iOUT and the external AC voltage v1, in order to provide reactive power to the power grid so as to stabilize the voltage on the power grid. This phase difference can easily be adjusted by suitably adjusting the phase information included in the synchronization signal Sv1. According to one embodiment, the
operation mode controller 50 receives an external signal from a utility provider, where this external signal includes a desired phase difference between the output current iOUT and the external voltage v1. The external signal can be provided to the operation mode controller via conventional communication channels, such as radio channels, power lines, or the internet. - According to a further embodiment, the
operation mode controller 50 measures the output power provided by thepower converter circuit 1 to the power grid and adjusts the phase difference between the output current iOUT and the external AC voltage v1 dependent on the output power. According to one embodiment, the phase difference increases, so as to increase the reactive power provided to the net, when the output power provided by thepower converter circuit 1 increases. - According to a further embodiment, the
operation mode controller 50 is configured to detect the frequency of the external AC voltage and is configured to reduce the output power of thepower converter circuit 1 when the frequency reaches a frequency threshold such as 50.2 Hz or 60.3 Hz that is above a set value, such as 50 Hz or 60 Hz. The frequency of a grid voltage may increase when there is more power input to the grid than there is power consumed by consumers connected to the grid. - The output power of the
power converter circuit 1 can be controlled by controlling the input voltages V3 of theindividual converter units 2. This has been explained in connection with “start-up sequence A” before. The information that a reduction of the output power of theindividual converter units 2 is required, may be transmitted from theoperation mode controller 50 to theindividual converter units 2 through the same channel through which the synchronization signal Sv1 is transmitted. - Referring to the explanation above, there may be operation scenarios when the
power converter circuit 1 is shut down after an error has occurred. After thepower converter circuit 1 has been shut down the power converter circuit can be restarted using one of the start-up sequences explained herein before. In the following, “to restart” thepower converter circuit 1 means to employ one of the start-up sequences to again start thepower converter circuit 1. - When, e.g., the
power converter circuit 1 has been shut down due to an error of the power grid, theoperation mode controller 50 can be configured to check the external AC voltage v1 and can be configured to restart thepower converter circuit 1 after the grid voltage v1 has returned to normal. Theoperation mode controller 50 may be configured to check the grid voltage in regular time intervals, such as every minute, every five minutes, etc. - When, e.g., the power converter circuit i has been shut down due to an under-voltage condition, due to automatic shutdown, or due to a phase difference, the operation mode controller may be configured to restart the power converter circuit after a given time period, such as, e.g., one minute, two minutes, etc.
- Of course, the occurrence of an error may also be detected during start-up so that it is even possible to shut down the power converter circuit i before the normal operation mode has been reached.
- Referring to explanation before, the output current i1 of the
individual converter units 2 may be increased in accordance with a given time profile during the start-up phase. This current profile may be fixed current profile. According to a further embodiment, the profile of the output current i1 during start-up is limited dependent on the shut-down history, which means dependent on whether the power converter circuit i has been shut down due to an error. According to one embodiment the output current is increased slower (in accordance with a shallower current profile) when thepower converter circuit 1 has been shut down due to an under-voltage condition, due to automatic shutdown, or due to a phase difference. When the restart fails because an error has occurred during the start-up phase, an even shallower current profile may be applied after the next restart. A “shallower current profile” is a profile in which the current increases slower. - In the embodiments explained before, the synchronization signal Sv1 is provided by the
synchronization circuit 10, where thesynchronization circuit 10 is configured to generate the synchronization signal Sv1, dependent on the external AC voltage v1, e.g., in the normal mode, or independent of the external AC voltage, e.g., when an error has occurred. - According to a further embodiment illustrated in
FIG. 35 , thesynchronization circuit 10 includessynchronization units synchronization unit converter unit corresponding converter unit converter unit individual synchronization units - An embodiment of a
converter unit 2 that can be used in the power converter circuit i ofFIG. 35 is illustrated inFIG. 36 . Theconverter unit 2 ofFIG. 36 is based on theconverter unit 2 explained in detail with reference toFIG. 32 . In theconverter unit 2 ofFIG. 36 , the synchronization signal Sv1 is a voltage measurement signal received by measuring the output voltage v2 of theconverter unit 2. The operating principle of theconverter unit 2 ofFIG. 36 is explained below. - For explanation purposes it is assumed, that the power converter circuit i is in the standby mode. In the standby mode, the power converter circuit i is connected to the
output terminals 11, 12 (seeFIG. 35 ) so that the external AC voltage v1 is applied to the series circuit with theindividual converter units 2. In the standby mode, when the output power of the power converter circuit i is zero, the output capacitances (C in theconverter unit 2 ofFIG. 36 ) of theindividual converter units 2 act as a capacitive voltage divider so that the voltages v2 at the outputs of theindividual converter units 2 are in phase with the external AC voltage v1. The start-up sequence employed to start up theindividual converter units 2 corresponds to start-up sequence B explained before, with the following differences. - At the beginning of the start-up sequence or before the beginning of the start-up sequence, the synchronization signal Sv1 is provided to the
signal generator 20 for a short time period, such as for several periods of the synchronization signal Sv1 which at this time is a sinusoidal signal that is in phase with the external Ac voltage v1. Thesignal generator 20 synchronizes to the synchronization signal Sv1 and then autonomously generates the continuous synchronization signal Sv1′ in the start-up phase and in the normal mode after the start-up phase. Thesignal generator 20 can be implemented as explained with reference toFIG. 29 before. - Referring to
FIG. 36 , theoperation mode unit 30 may control the time period when the synchronization signal Sv1 is provided to thesignal generator 20. This is schematically illustrated by having aswitch 301 connected between the synchronization unit (not shown inFIG. 36 ) and thesignal generator 20, with the switch being controlled by the operation mode unit. However, this serves to illustrate the operating rather than the implementation. Of course, many different means may be employed to provide the synchronization signal Sv1 that is dependent on the output voltage v2 to the signal generator for a given time period before or at the beginning of the start-up sequence. - In this converter circuit i, after the converter circuit i has entered the normal mode, the
operation mode controller 50 may be configured to detect a phase difference between the output current i1 and the external AC voltage and to shut down the converter circuit i when the phase difference exceeds a given threshold. The converter circuit i may be shut down as explained before in the section TRANSMISSION OF SHUT-DOWN INFORMATION II. The restart mechanism may correspond to one of the restart mechanisms explained before. At a restart after the shutdown, the converter circuit i will again be synchronized to the external voltage v1 as explained above. - According to a further embodiment, the
operation mode controller 50 provides a phase shift signal, corresponding to the phase shift signal Sφ explained before, to controlcircuits 5 of theindividual converter units 2. In this embodiment, theoperation mode controller 50 is configured to adapt the phase shift signal Sφ when the phase difference between the output current iOUT and the external voltage v1 is above a first phase difference threshold and below a second phase difference threshold, in order to prevent a further a further increase of the phase difference. Further, theoperation mode controller 50 is configured to shut down the converter circuit in order to force a restart when a the phase difference is above the second phase difference threshold. -
FIG. 37 illustrates yet another of a topology of aconverter unit 2 for generating an AC output voltage v2 from a DC input voltage V3. Like the other converter units explained before, theoutputs converter unit 2 ofFIG. 37 can be connected in series with the output terminals of other corresponding converter units so as to form apower converter circuit 1 explained herein. InFIG. 37 , only the topology of oneconverter 2 unit is shown, control circuits (such ascontrol circuits 5 explained before) are not illustrated. - Referring to
FIG. 37 , theconverter unit 2 includes afirst stage 210 that is a combination of an unfolding bridge and a buck converter. Thefirst stage 210 includes two half-bridges each including afirst switch second switch first stage 210 further includes a first inductive storage element 215, and a secondinductive storage element 216. The first inductive storage element 215 is connected to the output of the first half-bridge, and the secondinductive storage element 216 is connected to the output of the second half-bridge, wherein the output of each half-bridge is formed by a circuit node that is common to the first and second switches that form the corresponding half-bridge. Thefirst stage 210 is connected to theinput terminals FIG. 37 ). The switches 211-214 of the two half-bridges can be switched on and off independently of each other by adrive circuit 230 that generates drive signals S211, S212, S213, S214 received by the individual switches 211-214. The operating principle of thefirst stage 210 is explained further below. - The
converter unit 2 further includes asecond stage 220 coupled between theinductive storage elements 215, 216 of the first stage and theoutput terminals converter unit 3. Thesecond stage 220, that will also be referred to as boost stage in the following, includes afirst switch 221 connected between the first inductive storage element 215 and thefirst output terminal 23 of theconverter stage 2, and asecond switch 222 connected between thesecond output terminal 24 and a circuit node common to the first inductive storage element 215 and thefirst switch 221. Further, the secondinductive storage element 216 is connected to thesecond output terminal 24. Theswitches drive circuit 230 that generates drive signals S221, S222 received by theindividual switches FIG. 37 each of the switches 211-214 and 221, 222 of the first andsecond stage FIG. 37 ) connected in parallel with a switching element. In thesecond stage 220, however, bidirectional blocking and conducting switches are required due to the bipolar nature of the input and output voltage. These bidirectional switches may include two MOSFETs arranged in a back-to-back configuration. Depending on the polarity of the voltage one of the two MOSFETs may be turned on permanently, so that the body diode of the other MOSFET can be used as a freewheeling element that conducts dependent on the polarity of a voltage across the individual switch without requiring a further control signal. - The
converter unit 2 is configured to generate the AC output current i1 at theoutput drive circuit 230. This reference signal SREF can be generated as explained before. - The operating principle of the
converter unit 2 is explained in the following. For explanation purposes it is assumed that the output current i1 to be generated is a sinusoidal current and that the output voltage v2 is a sinusoidal voltage with an amplitude that is higher than the DC input voltage V3. Generating one period of the sinusoidal output voltage v2 includes six phases, namely (A) a first phase in which the instantaneous value of the output voltage v2 is positive and smaller than the input voltage V3; (B) a second phase in which the instantaneous value of the output voltage v2 is positive and higher than the input voltage V3; (C) a third phase in which the instantaneous value of the output voltage v2 is positive and again smaller than the input voltage V3; (D) a fourth phase in which the instantaneous value of the output voltage v2 is negative and has a magnitude that is smaller than the input voltage V3; a fifth phase (E) in which the instantaneous value of the output voltage v2 is negative and has a magnitude that is higher than the input voltage V3; and a sixth phase (F) in which in which the instantaneous value of the output voltage v2 is negative and has again a magnitude that is smaller than the input voltage V3. - In the first phase (A), the output current i1 is controlled through the
first switch 211 of the first half-bridge that is driven in a PWM fashion by thedrive circuit 230. Thefirst switch 221 of thesecond stage 220 is switched on in this phase, while thesecond switch 222 of thesecond stage 220 is switched off. Thefirst switch 213 of the second half-bridge is permanently off in the first phase, and thesecond switch 214 of the second half-bridge is permanently on. Thesecond switch 212 of the first half-bridge acts as a freewheeling element in those time periods in which thefirst switch 211 is off. For this, the freewheeling diode takes over the freewheeling current. Theswitch 212 may be turned on parallel to the conducting body diode. - In the first phase (A), the
converter unit 2 acts as a buck converter. The amplitude of the output current i1 is controlled through the duty cycle of the first switch 111 in this phase. The amplitude of the output voltage is defined by the external voltage v1 (not shown inFIG. 37 ). - In the second phase (B), the
first switch 211 of the first half-bridge and thesecond switch 214 of the second half-bridge are on, while thesecond switch 212 of the first half-bridge and thefirst switch 213 of the second half-bridge are off. Thesecond switch 222 of thesecond stage 120 is driven in a PWM fashion, and thefirst switch 221 acts as a freewheeling element in those time periods when the second switch 122 is off. The amplitude of the output current i1 is controlled through the duty cycle of thesecond switch 222. In the second phase (B), theconverter unit 3 acts as a boost converter, wherein each time thesecond switch 222 of thesecond stage 220 is on energy is stored in the first inductive storage element 215. This energy is transferred to the output with theoutput terminals second switch 222 has been switched off. - The operating principle in the third phase (C), corresponds to the operating principle in the first phase (A).
- In the fourth phase (D), the output current i1 is controlled through the
first switch 213 of the second half-bridge that is driven in a PWM fashion. Thefirst switch 221 of the second stage is on, while thesecond switch 222 is off in this phase. Further, thefirst switch 211 of the first half-bridge is off in this phase, thesecond switch 212 of the first half-bridge is on, and thesecond switch 214 of the second half-bridge acts as a freewheeling element in those time periods in which thefirst switch 213 is off. In the fourth phase (D), theconverter unit 3 acts as a buck converter providing a negative output current i1. The amplitude of the output current i1 is controlled through the duty cycle of thefirst switch 213 of the second half-bridge. - In the fifth phase (E), the
first switch 213 of the second half-bridge and thesecond switch 212 of the first half-bridge are on, while thesecond switch 214 of the second half-bridge and thefirst switch 211 of the first half-bridge are off. Thesecond switch 222 of thesecond stage 120 is driven in a PWM fashion, and thefirst switch 221 acts as a freewheeling element in those time periods when thesecond switch 222 is off. The amplitude of the output current i1 is controlled through the duty cycle of thesecond switch 222. In the fifth phase (E), like in the second phase, theconverter unit 2 acts as a boost converter. - The operating principle in the sixth phase (F), corresponds to the operating principle in the fourth phase.
- The
drive circuit 230 may receive an input voltage signal Sv3 representing the input voltage V3 and an output voltage signal Sv2 representing the output voltage v2. Based on these signals, thedrive circuit 230 detects whether the output voltage v2 is positive or negative, and whether the instantaneous value of the output voltage v2 is higher or lower than the input voltage. Based on this detection, thedrive circuit 230 operates theconverter unit 2 in one of the buck mode and the boost mode. In each of these phases, the desired level of the output current i1 is defined by the voltage control signal SREF. This signal can be an alternating signal in order to generate an alternating output voltage current and can be generated, e.g., dependent on an output current signal Si1 and an synchronization signal Sv1 as explained before. In each case, a switching frequency of those switches that are operated in a PWM fashion is significantly higher than a frequency of the reference signal. The switching frequency can be several 10 kHz or several 100 kHz, while the reference signal can be several 10 Hz, such 50 Hz or 60 Hz. The frequency of the reference signal SREF may vary in order to be able to correctly control the frequency of the output current i1. - In each of the embodiments explained before in which the
power converter circuit 1 provides an AC output current to a load, eachconverter unit 2 provides an AC current i1. For this, eachconverter unit 2, specifically the DC/AC converter 4 in eachconverter unit 2, includes an H4 bridge with two half-bridges (see, for example, the H4 bridge with the first half-bridge bridge 42 3, 42 4 inFIG. 6 ). -
FIG. 38 illustrates an embodiment of apower converter circuit 1 in which the complexity of theindividual converter units 2 can be reduced. In this embodiment, theindividual converter units 2 receive a synchronization signal Sv1″ that is a rectified AC signal instead of an AC signal. Everything else that has been explained in connection with the synchronization signal Sv1 herein before applies to the synchronization signal Sv1″ accordingly. - Like the
converter units 2 explained before, theconverter units 2 ofFIG. 38 are configured to generate their output currents i1 with a frequency and phase as defined by the synchronization signal Sv1″. According to one embodiment, thesynchronization circuit 10 generates the synchronization signal Sv1″ dependent on an external voltage v1 applied to theoutput terminals synchronization circuit 10 may generate the synchronization signal Sv1″ such that the synchronization signal Sv1″ has a frequency and a phase that is dependent on a rectified of the external voltage v1. If, for example, the external voltage v1 has a sinusoidal waveform, then the synchronization signal Sv1″ has the waveform of a rectified sinusoidal signal. The synchronization signal Sv1″ may be in phase with the rectified external voltage v1″, or there may be a phase difference between the synchronization signal Sv1″ and the rectified external voltage v1″. -
FIG. 39 schematically shows timing diagrams of an external voltage v1 with a sinusoidal waveform, of the corresponding rectified voltage v1″, and of the synchronization signal Sv1″. In embodiment illustrated inFIG. 39 , the synchronization signal Sv1″ is in phase with the rectified external voltage v1″. However, this is only an example, it is also possible to have a phase difference between these signals Sv1″, v1″.FIG. 39 further illustrates a timing diagram of the output current i1 of one of theconverter units 2. This output current i1 has a frequency and a phase that is defined by the synchronization signal Sv1″ so that the output current i1 of one converter unit has the waveform of a rectified sinusoidal signal. In the steady state, an overall output current iOUT-REC of the converter unit series circuit has the waveform of the output currents i1 of theindividual converter units 2. - Referring to
FIG. 38 , an unfoldingcircuit 300 connected between the series circuit with the converter units and theoutput terminals 11, i2 receives the output current iOUT-REC provided by the converter unit series circuit and transforms (unfolds) this output current iOUT-REC having the waveform of a rectified AC signal (such as a rectified sinusoidal signal) into an output current iOUT having the waveform of an AC signal (such as a sinusoidal signal). The output current iOUT is output at theoutput terminals - Referring to
FIG. 40 , that shows one embodiment of the unfoldingcircuit 300, the unfolding circuit 330 may include a bridge circuit with two half-bridges similar to thebridge circuit 85 explained with reference toFIG. 19 . InFIG. 40 ,reference character 23 1 denotes the first output terminal of the first converter unit 21 (not shown inFIG. 40 ), andreference character 23 2 denotes the second output terminal of the n-th converter unit 2 n (not shown inFIG. 40 ). These terminals will be referred to as first and second terminals, respectively, of the converter unit series circuit. The unfolding circuit transforms the series circuit output current iOUT-REC into the AC output current IOUT. For this, the unfoldingbridge 300 alternatingly assumes a first switching state and a second switching state. In the first switching state, thefirst terminal 23 1 of the series circuit is connected to thefirst output terminal 11, and thesecond output terminal 24 n of the series circuit is connected to thesecond output terminal 12, and in the second switching state, thefirst terminal 23 1 of the series circuit is connected to thesecond output terminal 12, and thesecond output terminal 24 n of the series circuit is connected to thefirst output terminal 12. The unfolding bridge changes the switching state at the beginning of each period of the synchronization signal Sv1″. In the embodiment ofFIG. 38 , a new period of the synchronization signal begins each time the synchronization signal Sv1″ decreases to zero. - Referring to
FIG. 40 , the unfoldingcircuit 300 may include a first and a second half-bridge each including afirst switch second switch output terminals bridge first output terminal 11, and an output terminal of the second half-bridge second output terminal 12. In this unfolding circuit, thefirst switch 301 of the first half-bridge and thesecond switch 304 of the second half-bridge are switched on and theother switches second switch 302 of the first half-bridge and thefirst switch 303 of the second half-bridge are switched on and theother switches control circuit 310 receives the synchronization signal Sv1″ and controls the individual switches such that the unfoldingcircuit 300 dependent on the synchronization signal Sv1″ alternatingly assumes the first and second switching states, so as to generate an alternating output current iOUT from the rectified alternating output current iOUT-REC provided by the converter unit series circuit. - According to one embodiment, the
synchronization circuit 10 generates the synchronization signal Sv1″ dependent on the external voltage v1. In this case, thesynchronization circuit 10 may receive the external voltage v1 or may receive the rectified external voltage v1″ (as illustrated in dashed lines inFIG. 38 ). In this embodiment, thecontrol circuit 310 of the unfolding bridge may receive the external voltage v1 (or a signal representing the external voltage) instead of the synchronization signal Sv1″ in order to control the unfolding bridge. In this embodiment, thecontrol circuit 310 operates the unfoldingbridge 300 in the first switching state during positive half-cycles of the external voltage v1, and in the second switching state during negative half-cycles of the external voltage v1. - Referring to
FIG. 38 , the unfoldingbridge 300 not only converts the output current i1 OUT-REC of the series circuit into the output current hour of thepower converter circuit 1, but also converts (rectifies) the external voltage v1 and applies the rectified external voltage v1″ to the series circuit with the converter units 2 (and optionally to the synchronization circuit 10). - According to a further embodiment, the
synchronization circuit 10 generates the synchronization signal Sv1″ based on other information than the external voltage v1. This may become necessary in those cases in which the voltage v1 between theterminals power converter circuit 1 to also define the frequency of this voltage v1. For example, this may become necessary when the power converter circuit i operates in an island grid. - In the
power converter circuit 1 ofFIG. 38 , theindividual converter units 2 only need to be capable of providing an output current i1 with one polarity and not an output current that periodically changes between a positive and a negative polarity. This allows to simplify the topology of the DC/AC converter 4 in each of theconverter units 2. In the context of the present description the term “DC/AC converter” is used in connection with theconverters 4 explained before that generate an alternating output current from a direct input current and a direct input voltage, respectively. However, the term “DC/AC converter” is also used in connection with converters that generate an output current with a periodically varying amplitude and with only one polarity, such as an output current having the waveform of a rectified sinusoidal signal. - According to one embodiment, the DC/
AC converter 4 in each of the converter units is implemented with a buck converter, a boost-buck converter, or a buck-boost converter topology. One embodiment of aconverter unit 2 including a DC/AC converter 4 with abuck topology 4 is illustrated inFIG. 41 . Referring toFIG. 41 , the DC/AC converter 4 is coupled between the input with the first andsecond input terminals output terminals converter unit 2. Optionally, a DC/DC converter 6 is connected between theinput converter unit 2 and the DC/AC converter 4. This DC/DC converter 6 and thecorresponding control circuit 7 may correspond to one of the DC/DC converters 6 explained before. - The DC/
AC converter 4 ofFIG. 41 can be obtained from one of the DC/AC converters 4 with an H4-bridge explained before by omitting thethird switch 42 3 and theinductive storage element 44 2 and by replacing thefourth switch 42 4 by a short circuit. Referring toFIG. 41 , the buck converter includes a half-bridge with a high-side switch 401 and a low-side switch 402 connected in series. The half-bridge receives the input voltage V3 or the DC link voltage V6 (when theconverter unit 2 includes the DC/DC converter 6). Aninductive storage 403 element is coupled between an output of the half-bridge and theoutput converter unit 2. In the present embodiment, theinductive storage element 404 is connected between the output of the half-bridge first output terminal 23. - In the DC/
AC converter 4 ofFIG. 41 , the high-side switch 401 is driven in a PWM fashion by adrive circuit 404 such that the output current i1 has a waveform as defined by a reference signal SREF received by thedrive circuit 404. The reference signal SREF is generated by thecontrol circuit 5 dependent on the synchronization signal Sv1″ and an output current signal Si1 representing the output current i1. According to one embodiment, thecontrol circuit 5 generates the reference signal SREF such that the DC/AC converter generates the output current i1 to be in phase with the synchronization signal Sv1. - In the DC/
AC converter 4 ofFIG. 41 , the low-side switch 402 acts as a freewheeling element that takes over the current through theinductive storage element 403 when the high-side switch 401 is switched off. This low-side switch 402 may include a freewheeling diode (that is also illustrated inFIG. 41 ). According to one embodiment, the low-side switch 402 is replaced by a freewheeling diode. - The DC/
AC converter 4 can be implemented as a buck converter when the level of the output voltage v2 is always smaller than the level of the input voltage V3 and the DC link voltage V60, respectively. If the maximum level of the output voltage v2 of the DC/AC converter is higher than the level of the input voltage V3 and the DC link voltage V60, respectively, the DC/AC converter may be implemented with one of a boost-buck converter topology and a buck-boost converter topology. - One embodiment of a
converter unit 2 with a DC/AC converter 4 having a boost-buck converter topology is illustrated inFIG. 42 , and one embodiment of aconverter unit 2 with a DC/AC converter 4 having a buck-boost converter topology is illustrated inFIG. 43 . InFIGS. 42 and 43 an optional DC/DC converter 6 connected between theinput terminals AC converter 4 is not illustrated. When the converter units ofFIGS. 42 and 43 are implemented with a DC/DC converter 6, the DC/AC converter 4 receives the DC link voltage V6 instead of the input voltage V3. - Referring to
FIG. 42 , the DC/AC converter 4 includes a boost stage with a firstinductive storage element 411, first andsecond switches inductive storage element 411 and thefirst switch 412 receives the input voltage V3. A series circuit with thesecond switch 413 and the capacitive storage element 414 is connected in parallel with thefirst switch 412. The boost stage generates a boost voltage V414 across the capacitive storage element 414. - The boost stage operates like a conventional boost converter and may be configured to generate a constant boost voltage V414 at the capacitive storage element 414. In this case, a
first drive circuit 418 drives the first andsecond switches first drive circuit 418 may receive a boost voltage signal SV414 representing the boost voltage 414. Specifically, thefirst drive circuit 418 may drive thefirst switch 412 in a PWM fashion, wherein energy is stored in the firstinductive storage element 411 each time thefirst switch 412 is switched on. A duty cycle of a PWM drive signal S412 received by thefirst switch 412 may vary dependent on the boost voltage or, more specifically, dependent on an error between the boost voltage V414 and a desired set-voltage. Thesecond switch 413 acts as a freewheeling element that takes over the current through theinductive storage element 411 and charges the capacitive storage element 414 each time thefirst switch 412 is switched off. - Referring to
FIG. 42 , the DC/AC converter 4 further includes a buck stage with athird switch 415, asecond switch 416 and a secondinductive storage element 417. This buck stage has a topology corresponding to the topology of the DC/AC converter 4 ofFIG. 41 , wherein thethird switch 415 corresponds to the high-side switch 401 ofFIG. 41 , thefourth switch 416 corresponds to the low-side switch 402 ofFIG. 41 , and the secondinductive storage element 417 corresponds to theinductive storage element 403 ofFIG. 41 . - A
second drive circuit 419 that may correspond to thedrive circuit 404 explained with reference toFIG. 41 drives theswitches control circuit 5. - While in the DC/
AC converter 4 ofFIG. 42 , the boost stage and the buck stage are operated simultaneously, the DC/AC converter 4 with the buck-boost topology illustrated inFIG. 43 either operates as a boost converter (in a boost mode) or operates as a buck converter (in a buck mode). Referring toFIG. 43 , the DC/AC converter 4 includes a series circuit with afirst switch 421 and asecond switch 422 connected between theinput terminals third switch 423 and afourth switch 424 connected between the output terminals. Aninductive storage element 425 is connected between a first circuit node common to the first andsecond switches fourth switches converter unit 2 ofFIG. 37 by omitting the second half-bridge inductive storage element 216 and by connecting thesecond input 22 with thesecond output 24. - A
drive circuit 426 controls the individual switches such that the DC/AC converter 4 is either operated in a buck mode or in a boost mode. The operating principle of the DC/AC converter 4 ofFIG. 43 corresponds to the operating principle of theconverter unit 2 in the operation phases (A) to (C) wherein this converter unit operates in the buck mode in phases (A) and (C) and in the boost mode in phase (B). - When the DC/AC converter of
FIG. 43 is in the buck mode, thethird switch 423 is permanently on and thefourth switch 424 is permanently off. Further, thefirst switch 421 is driven in a PWM fashion such that the output current i1 has a waveform as defined by the reference signal SREF received by thedrive circuit 426. Thesecond switch 422 acts as a freewheeling element in those time period in which thefirst switch 421 is switched off. According to one embodiment, thesecond switch 422 is replaced by a freewheeling element, such as a diode. - In the boost mode, the
first switch 421 is permanently switched on and thesecond switch 422 is permanently switched off. In the boost mode, thecontrol circuit 426 operates thefourth switch 424 in a PWM fashion such that the output current i1 has a waveform as defined by the reference signal SREF. Thethird switch 423 acts as a freewheeling element. Optionally, thethird switch 423 is replaced by a diode. - Referring to
FIG. 43 , thedrive circuit 426 besides the reference signal SREF also receives an output voltage signal Sv2 representing an instantaneous value of the output voltage v2 and an input voltage signal Sv3 representing the input voltage. Thedrive circuit 426 is configured to operate the AC/DC converter 4 in the buck mode whenever the output voltage signal Sv2 and the input voltage signal Sv3 indicate that the input voltage v3 is higher than the instantaneous value of the output voltage v2. Otherwise, thedrive circuit 426 operates the DC/AC converter 4 in the boost mode. - In the embodiments of the
power converter 1 circuit explained before, theinput terminals individual converter units 2 where theDC power sources 3 are connected to are not galvanically isolated from theoutput terminals DC power sources 3 output supply voltages of several by or several 100V. In this case, a galvanic isolation between theinputs output - There are several different concepts to provide a galvanic isolation between the
inputs outputs FIGS. 44 and 45 below. -
FIG. 44 illustrates a first embodiment of apower converter circuit 1 including at least one transformer. In thispower converter circuit 1, the individual converter units 2 (reference character “2” denotes an arbitrary one of the converter units 2 1-2 n ofFIG. 44 ) each include a DC/DC converter 6 and a DC/AC converter 4 as explained with reference toFIG. 11 before. For the ease of illustration, control circuits of the DC/DC converters 6 and the DC/AC converters 4 are not illustrated inFIG. 44 . Each of the DC/DC converters 6 is connected between oneDC power source 3 and one DC/AC converter 4 and includes atransformer 69 that provides for a galvanic isolation between the DC power source and theoutput terminals DC converters 6 are explained below. - Although the individual DC/DC converters of
FIG. 44 are drawn to include one transformer each, it is also possible that two or more DC/DC converters 6 share one transformer. Each of the DC/DC converters 6 outputs a DC link voltage received by the corresponding DC/AC converter 4. - The individual DC/
AC converters 4 can be implemented, as explained before. Optionally, an unfoldingbridge 300 is connected between the series circuit with theconverter units 2 or the series circuit with the DC/AC converters 4, respectively, and theoutput terminals 11, 12 (as explained herein with reference toFIG. 38 ). The unfoldingbridge 300 can be omitted when theindividual converter units 2 each output an AC current i1, and the unfoldingbridge 300 is connected between the series circuit with theconverter units 2 and the output terminals when theindividual converter units 2 each output a rectified AC current i1. -
FIG. 45 illustrates a further embodiment of apower converter circuit 1 including at least one transformer. In thispower converter circuit 1, each of theindividual converter units 2 includes a DC/AC converter 4, wherein each DC/AC converter 4 includes onetransformer 69. Specific embodiments of the DC/AC converters 4 ofFIG. 45 are explained with reference to drawings below. - Referring to
FIG. 45 , the input of each DC/AC converter 4 is coupled to oneDC power source 3. Optionally, in eachconverter unit 2, a DC/DC converter 6 is connected between theDC power source 3 and the DC/AC converter 4. The individual DC/DC converters 6 that each output a DC link voltage V6 may be implemented as explained with reference toFIGS. 12 to 18 herein before. For the ease of illustration, control circuits of the DC/AC converters 4 and the optional DC/DC converters 6 are not illustrated inFIG. 45 . - The DC/
AC converters 4 can be implemented to either output an AC current i1 or to output a rectified AC current. In the first case, the series circuit with the DC/AC converters 4 can be connected to theoutput terminals FIG. 45 ) receives the rectified AC current and outputs and AC current to theoutput terminals AC converters 4 are explained with reference to drawings below. - Some exemplary embodiments of DC/
DC converters 6 that each include a transformer and that may be used in thepower converter circuit 1 explained with reference toFIG. 44 are explained with reference toFIGS. 46 to 50 in the following. -
FIG. 46 shows a basic topology of a DC/DC converter 6 with atransformer 69 having a primary winding 69 P and a secondary winding 69 S. The DC/DC converter 6 includes aswitching circuit 621 that receives the input voltage V3 and applies a pulse-width modulated voltage V69 P to the primary winding 69 P of thetransformer 69. Optionally, aninput capacitor 63 corresponding to theinput capacitor 63 explained before is connected between theinput terminals rectifier circuit 622 connected thereto. Therectifier circuit 622 includes theDC link capacitor 60 and is configured to generate the DC link voltage V60 from a voltage V69 S across the primary winding. The DC/DC converter 6 can be configured to control at least one of the input voltage V3 and the DC link voltage V60. Just for explanation purposes it is assumed that the DC/DC converter 6 is configured to control the input voltage V3. In this case, theswitching circuit 621 receives the input voltage reference signal SREF-V3, explained before. An MPP tracker (not shown inFIG. 44 ) may output the input voltage reference signal SREF-V3. Theswitching circuit 621 can be configured to control the input voltage by suitably adjusting a duty cycle of the PWM voltage V69 P applied to the primary winding 69 P. - Optionally, a boost stage 623 (illustrated in dashed lines in
FIG. 46 ) is connected between theinput switching circuit 621. Theboost stage 623 is configured to output a boost voltage V623 that is higher than the input voltage V3 and that is received by the switchingcircuit 621. Theboost stage 623 may include a conventional boost converter topology. In case aboost stage 623 is connected between theinput switching circuit 621, theboost stage 623 may receive the input voltage reference signal SREF-V3 and may be configured to control the input voltage V3. - Four more specific embodiments of DC/
DC converters 6 each having a basic topology as explained with reference toFIG. 46 are explained with reference toFIGS. 47 to 50 below. Each of these topologies may include an input capacitor explained with reference toFIG. 46 . However, such input capacitor is not illustrated inFIGS. 47 to 50 . Further, each of these topologies optionally includes a boost stage connected between theinput switching circuit 621. However, such boost stage is also not illustrated inFIGS. 47 to 50 . -
FIG. 47 illustrates a first embodiment of a DC/DC converter 6 with atransformer 69 including a primary winding 69 P and a secondary winding 69 S. The DC/DC converter 6 ofFIG. 47 has a topology known as two transistor forward (TTF) topology. The primary winding 69 P and the secondary winding 69 S have the same winding senses in this type of DC/DC converter 6. The primary winding 69 P is connected between afirst switch 506 1 and asecond switch 506 2 of theswitching circuit 621, with the series circuit with theswitches input terminals first switch 506 1 and the primary winding 69 P is coupled to thesecond input terminal 22 via a first rectifier element 507 1, such as a diode. Further, a circuit node common to the primary winding 69 P and thesecond switch 506 2 is coupled to thefirst input terminal 21 via a second rectifier element 507 2, such as a diode. - In the
rectifier circuit 622, a series circuit with athird rectifier element 504, aninductive storage element 508, and theDC link capacitor 60 is connected in parallel with the secondary winding 69 S. TheDC link capacitor 60 is connected between theoutput terminals fourth rectifier element 505 is connected in parallel with the series circuit withinductive storage element 508 and theDC link capacitor 60. - Referring to
FIG. 47 , adrive circuit 510 generates a drive signal S506 to the first andsecond switches drive circuit 510 is configured to adjust the duty cycle of the drive signal S506 such that a voltage level of the input voltage V3 corresponds to a voltage level represented by the reference signal SREF-v3. - The operating principle of the DC/
DC converter 6 ofFIG. 47 is as follows. Each time the first andsecond switches input terminals FIG. 47 when the input voltage V3 has a polarity as indicated inFIG. 47 . This voltage causes a current through thethird rectifier element 504, theinductive storage element 508 and theDC link capacitor 60. When theswitches first rectifier element 504 becomes zero and a current induced by theinductive storage element 508 flows through thesecond rectifier element 505. A temporary increase of the duty cycle of the drive signal S506 at a given input power provided by the DC power source V3 results in an increase of the input current I3 and a decrease of the input voltage V3, and a decrease of the duty cycle results in a decrease of the input current I3 and an increase of the input voltage V3. - In the DC/
DC converter 6 ofFIG. 47 , as well as in other DC/DC converters 6 explained above and below, rectifier elements represented by a diode symbol can be implemented as diodes. However, it is also possible to implement these rectifier elements as synchronous rectifiers (SR) including a switching element, such as a MOSFET. -
FIG. 48 illustrates a further embodiment of a DC/DC converter 6. The DC/DC converter 6 ofFIG. 48 includes a phase-shift zero-voltage switching (ZVS) full bridge topology. Referring toFIG. 48 , theswitching circuit 621 includes two half bridges each including a high-side switch side switch input terminals inductive storage element 610 and the primary winding 69 P of thetransformer 69 is connected between output terminals of the two half bridges. Thetransformer 69 includes a secondary winding with a center tap resulting in two secondary windingsections sections - The
rectifier circuit 622 includes a series circuit with aninductive storage element 611 and the DC link capacitor 6o. The first secondary windingsection 69 S1 is coupled to thisseries circuit first rectifier element 607, and the second first secondary windingsection 69 S2 is coupled to theseries circuit second rectifier element 609. Athird rectifier element 612 is connected in parallel with the series circuit with theinductive storage element 611 and theDC link capacitor 60. More precisely,inductive storage element 611 is connected to the first secondary windingsection 69 S1 via thefirst rectifier element 607 and to the second secondary windingsection 69 S2 via thesecond rectifier element 609. A center tap of the secondary winding 69 S1, 69 S2 is connected to the circuit node of theDC link capacitor 60 that faces away frominductive storage element 611. This circuit node corresponds to thesecond output terminal 62. - The
switches drive circuit 609 dependent on the input voltage reference signal SREF-V3 and the input voltage Sv3 such that the level of the input voltage V3 corresponds to the level represented by the reference signal SREF-V3. InFIG. 48 , reference characters S605 1, S605 2, S606 1, S606 2 denote drive signals provided by thedrive circuit 609 to theindividual switches individual switches side switch 605 1 of the first half-bridge and the low-side switch 606 2 of the second half-bridge are switched on. Thus, a current I69 P flows through the firstinductive storage element 610 and the primary winding 69 P. Voltages V69 S1, V69 S2 across the secondary windingsections FIG. 48 when the input voltage V3 has a polarity as indicated inFIG. 48 . The voltage V69 S1 across the first secondary windingsection 69 S1 causes a current 1607 through thefirst rectifier element 607, the secondinductive storage element 611 and the capacitive storage element 608, while thesecond rectifier element 609 blocks. - In a second phase, the
high side switch 605 1 of the first half-bridge is switched on and the high-side switch 606 1 of the second half-bridge is switched on. There may be a delay time between switching off the low-side switch 605 2 of the first half-bridge and switching on the high-side switch 606 1 of the second half-bridge. During this delay time, a freewheeling element (not illustrated) connected in parallel with the high-side switch 606 1 may take the current. Theswitches - In the second phase, the voltage across the primary winding 69 P and the voltages V69 S1, V69 S2 across the
secondary windings inductive storage element 611 continuous to flow, where thethird rectifier element 610 takes over the current through theinductive storage element 61 and the capacitive storage element 608. - In the third phase, the high-
side switch 606 1 of the second half-bridge and the low-side switch 605 2 of the first half-bridge are switched on. The voltages V69 S1, V69 S2 across the secondary windingsections FIG. 11 . In this case, a current flows through the second secondary windingsection 69 S2, thesecond rectifier element 609, theinductive storage element 611 and the capacitive storage element 608. - In the fourth phase, the low-
side switch 605 2 of the first half-bridge is switched off, and the half-side switch 605 1 of the first half-bridge is switched on. The voltage across the primary winding 69 P and the voltages across the secondary windingsections inductive storage element 611 and the capacitive storage element 608 continuous to flow, where thethird rectifier element 609 provides a current path for this current. - According to one embodiment, a timing of switching on and switching off the
individual switches - Like in the DC/
DC converters 6 explained before, the input voltage V3 can be controlled such that the level of the input voltage V3 corresponds to the level represented by the reference signal SREF-V3. In particular, the input voltage V3 can be regulated by adjusting the time durations of the first phase and the third phase, whereas an increase of these time durations (dependent on the input voltage signal Sv3 and the reference signal SREF-V3) results in an increase of the input current I3, so that at a given input power provided by the DC power source 3 (not shown inFIG. 48 ) the input voltage V3 decreases. Equivalently, the input voltage V3 increases when the time durations of the first and third phase increase. -
FIG. 49 illustrates a DC/DC converter 6 according to a further embodiment. The DC/DC converter 6 ofFIG. 49 is implemented as flyback converter. Referring toFIG. 49 , theswitching circuit 621 of the DC/DC converter 6 includes aswitching element 701 connected in series with the primary winding 69 P of thetransformer 69. The series circuit with the primary winding 69 P and theswitching element 701 is connected between theinput terminals rectifier circuit 622 that is connected to the secondary winding 69 S of thetransformer 69 includes a series circuit with arectifier element 703 and the DC link capacitor 6o. TheDC link capacitor 60 is connected between theoutput terminals DC converter 6. - Referring to
FIG. 49 , the DC/DC converter 6 further includes adrive circuit 702 that is operable to output a PWM drive signal S701 received by the switchingelement 701. - The basic operating principle of the DC/
DC converter 6 is as follows. Each time theswitching element 701 is switched on, energy is magnetically stored in the air gap of thetransformer 69. The primary winding 69 P and the secondary winding 22 S have opposite winding senses, so that a current through the secondary winding 69 S is zero when the switching element 711 is switched on. When the switching element 711 switches off, the energy stored in thetransformer 69 is transferred to the secondary winding 69 S and causes a current from the secondary winding 69 S via therectifier element 713 to theDC link capacitor 60 of therectifier circuit 622. Dependent on the specific type of thedrive circuit 712, at least one of the operation parameters of DC/DC converter 2 can be adjusted. This is explained in further detail herein below. - According to one embodiment, like in the DC/
DC converters 6 explained before, the input voltage V3 is controlled such that the level of the input voltage V3 corresponds to the level represented by the reference signal SREF-V3 received by thedrive circuit 712. The input voltage V3 can be regulated by adjusting the duty cycle of the PWM drive signal S711, whereas an increase of the duty cycle results in an increase of the input current I3, so that at a given input power provided by the DC power source 3 (not shown inFIG. 47 ) the input voltage V3 decreases. Equivalently, the input voltage V3 increases when the duty cycle increases. -
FIG. 50 illustrates a DC/DC converter 6 according to a further embodiment that includes an LLC resonant topology. Referring toFIG. 50 , theswitching circuit 621 of the DC/DC converter 6 includes a half-bridge with a high-side switch 805 1 and a low-side switch 805 2 connected between theinput terminals switching circuit 621 further includes a series LLC circuit with acapacitive storage element 806, aninductive storage element 807, and the primary winding 69 P of thetransformer 69. This series LLC circuit is connected in parallel with the low-side switch 805 2. A furtherinductive storage element 808 is connected in parallel with the primary winding 69 P. - The
transformer 69 includes a center tap resulting in two secondary winding sections, namely a first secondary windingsection 69 S1 and a second secondary windingsection 69 S2 coupled to the primary winding 69 P and each having the same winding sense as the primary winding 69 P. In therectifier circuit 622, the first secondary windingsection 69 S1 is coupled to thefirst output terminal 61 through afirst rectifier element 809, and the second secondary windingsection 69 S2 is coupled to thefirst output terminal 61 through asecond rectifier element 810. A circuit node common to the first and second secondary windingsections second output terminal 62. TheDC link capacitor 60 is connected between theoutput terminals output terminals - In
FIG. 50 , reference characters S805 1, S805 2 denote drive signals received by the switches 805 1, 805 2 of the half-bridge. These drive signals S805 1, S805 2 are generated by adrive circuit 812 in accordance with the input voltage signal Sv3 and the reference signal SREF-V3 such that the level of the input voltage V3 corresponds to a level represented by the reference signal SREF-V3. - The operating principle of the DC/DC converter of
FIG. 50 is as follows. Thedrive circuit 812 alternatingly switches the high-side switch 805 1 and the low-side switch 805 2 on and off. This causes an alternating current through the primary winding 69 P of thetransformer 69. This alternating current is transferred to the secondary side. When the alternating current through the primary winding 69 P has a first direction, a current on the secondary side flows through the first secondary windingsection 69 S1 and thefirst rectifier element 809 to theDC link capacitor 60 and theoutput terminals section 69 S2 and thesecond rectifier element 810 to theDC link capacitor 60 and theoutput terminals - The series LLC circuit has two resonance frequencies, namely a first resonance frequency, and a second resonance frequency lower than the first resonance frequency. In order to control the input power of the DC/DC converter 6 (and to thereby control the input voltage V3) the
drive circuit 812 operates the first and second switches 805 1, 805 2 with a frequency that is typically between the first and the second resonance frequency and close to the first resonance frequency, wherein through a variation of the switching frequency the quality factor of the LLC circuit can be varied. By varying the quality factor the input power and, therefore, the input voltage V3 of the DC/DC converter 6 can be adjusted. - Although a TTF topology, a phase-shift ZVS topology, a flyback topology, and a half-bridge LLC topology have been explained in detail, the implementation of the DC/
DC converters 6 is not restricted to these topologies. Other conventional DC/DC converter topologies including a transformer, such as a single transistor forward topology, a full-bridge LLC topology, or an active clamp forward topology may be used as well. These topologies are commonly known, so that no further explanations are required in this regard. Further, the individual DC/DC converters 6 could be implemented as interleaved DC/DC converters. An interleaved DC/DC converter includes at least two of the topologies explained herein below, wherein these topologies are connected in parallel so as to commonly receive the DC input voltage V3, wherein the individual topologies connected in parallel are activated in a timely interleaved fashion. - In the embodiment of
FIG. 44 , eachconverter unit 2 receives a DC voltage V3 from aDC power source 3. The level of the DC voltage V3 is dependent on the specific type of DC power source. According to one embodiment, the individualDC power sources 3 each include a string with several PV modules connected in series, so as to provide a voltage level of between several 10V and several 100V. In this case, thepower converter circuit 1 can be configured to be coupled to a mid-voltage grid supplying voltages of between 10 kV and 20 kV. - In case the individual DC/
AC converters 4 are configured to generate a rectified AC current i1, an unfoldingbridge 300 is connected between the series circuit with the DC/AC converters 4 and theoutput FIG. 44 . The topology of the unfoldingbridge 300 may correspond to the topology of the unfoldingbridge 300 ofFIG. 40 , wherein the individual switches 301-304 are selected such that they are capable to withstand the voltage between theoutput terminals - A
power converter circuit 1 configured to be coupled to a mid-voltage grid, may includeconverter units 2 with any of the topologies explained with reference toFIGS. 46 to 50 herein before. According to one specific embodiment, eachconverter unit 2 includes a DC/DC converter 2 with boost stage 623 (seeFIG. 46 ) and with a PS-ZVS converter explained with reference toFIG. 48 . A ratio between the input voltage V3 and the boost voltage V623 (seeFIG. 46 ) provided by theboost stage 623 is, e.g., between 1.2:1 and 10:1. Referring to the concept explained with reference toFIG. 45 , the DC/AC converters 4 in theindividual converter units 2 provide for a galvanic isolation between theinputs DC power sources 3 are connected thereto and theoutput AC converters 4 explained before can be replaced by a DC/AC converter 4 comprising a transformer. - For example, in the embodiment of
FIG. 19 , theconverter 80 with the buck converter topology could be replaced by aconverter 80 with a flyback converter topology including a transformer. A DC/AC converter 4 modified in this way is illustrated inFIG. 51 . In this embodiment, the DC/AC converter 4 is connected to theinput terminals FIG. 45 , it is also possible to connect a DC/DC converter 6 between theinput terminals AC converter 4. In this case, the DC/AC converter 4 receives the DC link voltage V6 (not shown inFIG. 51 ) instead of the input voltage V3. - The
converter 80 ofFIG. 51 includes a conventional flyback converter topology including a series circuit with a primary winding 84 P of a transformer and a switchingelement 83 coupled to theinput terminals rectifier element 86 andoptional output capacitor 89 is connected to a secondary winding 84 S of the transformer. The secondary winding 84 S is inductively coupled with the primary winding 84 P. - The operating principle of the
converter 80 ofFIG. 51 corresponds to the operating principle of theconverter 80 ofFIG. 19 . That is, theswitch 83 receives a PWM drive signal from thedrive circuit 87 such that a signal waveform of the output current i80 of theconverter 80 has a waveform as defined by the reference signal SREF received by thedrive circuit 87. Thecontrol circuit 5 generates the reference signal SREF dependent on the synchronization signal Sv1 and the output current signal Si1 such that there is a predefined phase difference between the output current and the synchronization signal Sv1. Theconverter 80 generates the output current i80 to have the waveform of a rectified alternating current. - The other features of the
converter unit 2 ofFIG. 51 correspond to theconverter unit 2 explained with reference toFIG. 19 . That is, an unfoldingbridge 85 receives the output current i80 from theconverter 80 and generates an alternating output current i1 from the rectified alternating current i80. - In a power converter circuit implemented with a plurality of
converter units 2 as illustrated inFIG. 51 , eachconverter unit 2 has an unfoldingbridge 85. However, in accordance with the embodiment explained with reference toFIG. 38 and as explained with reference toFIG. 45 , it is also possible to implement each of theindividual converter units 2 with theconverter 80 only and to provide only one unfolding bridge (300 inFIG. 38 ) for one series circuit with a plurality ofconverter units 2. This is equivalent to implementing the converter units 21-2 n each with a flyback converter corresponding to theflyback converter 80 ofFIG. 51 . - However, implementing the
converter 80 with a flyback converter topology is only an example. Thisconverter 80 could be implemented with another converter topology including a transformer, explained before. According to a further embodiment (not illustrated), the individual DC/AC converter 4 have a cycloinverter topology as disclosed in Trubitsyn, et al., “High-Efficiency Inverter for Photovoltaic Applications,” IEEE, Energy Conversion Congress and Exposition (ECCE), 2010, pages 2803-2810. -
FIG. 52 illustrates yet a further embodiment of apower converter circuit 1. Thispower converter circuit 1 includes a DC/DC stage with a plurality of DC/DC converters that share onetransformer 69. In the present embodiment, thetransformer 69 includes m primary windings 69 P1-60 Pm and n secondary windings 69 S1-60 Sn that are inductively coupled. Each of the primary windings 69 P1-60 Pm is coupled to a switching circuit 621 1-621 m, wherein each of the switching circuits 621 1-621 m is connected to an input withinput terminals circuits FIG. 50 , a rectifier circuit 622 1-622 n is connected to each of the secondary windings 69 S1-69 Sn. Each rectifier circuit 622 1-622 n is configured to generate a DC link voltage V6 1-V6 n from a voltage across the corresponding secondary winding 69 S1-69 Sn. Each of a plurality DC/AC converters 4 1-4 n, that have their outputs connected in series receives one of the DC link voltages V6 1-V6 n, wherein the individual DC/AC converters 4 1-4 n together output the output current i1. Optionally, an unfoldingbridge 300 is connected between the series circuit with the DC/AC converters 4 1-4 n and theoutput terminals - In the present embodiment, the number m of switching circuits 621 1-621 m and the number of rectifying circuits 622 1-622 n are not equal, wherein m<n. However, it is also possible to implement the
power converter circuit 2 with the same number of switching circuits 621 1-621 m and rectifying circuits 622 1-622 n (m=n), or with less rectifying circuits 622 1-622 n than switching circuits 621 1-621 m (m>n). - The individual DC/AC converters 4 1-4 n can be implemented with one of the DC/AC converter topologies explained herein before. The control scheme of the DC/
AC converters 4 may correspond to the control schemes explained before. - In the power converter arrangement of
FIG. 50 , each of the switching circuits 621 1-621 m forms a DC/DC converter with one of the rectifier circuit 622 1-622 n. The individual switching circuits 621 1-621 m and the corresponding rectifier circuits 622 1-622 n can be implemented with one of the topologies explained with reference toFIGS. 47 to 50 before, wherein the topology of the individual rectifier circuits 622 1-622 n is adapted to the topology of the switching circuits 621 1-621 m. That is, the switching circuits 621 1-621 m have a topology according to one DC/DC converter topology, explained before, and the rectifier circuit have a topology according to the same DC/DC converter topology. -
FIG. 53 illustrates a further embodiment of apower converter circuit 1 including a plurality ofconverter units 2 having theiroutputs output terminals power converter circuit 1. Theindividual converter units 2 can be implemented as explained with reference toFIGS. 5 to 36 herein before and each include a DC/AC converter 4. Optionally, a DC/DC converter 6 is connected between theinput individual converter unit 2 and the corresponding DC/AC converter. Referring to the explanation above, each of the DC/AC converters 4 outputs an AC current i1 in accordance with the synchronization signal SV1. The frequency of the AC currents is, e.g., 50 Hz or 60 Hz and is defined by the synchronization signal SV1. - In order to provide for a galvanic isolation between the
inputs individual converter units 2 and theoutput power converter circuit 1, eachconverter unit 2 additionally to the DC/AC converter 4 and the optional DC/DC converter 2 includes atransformer 69 with a primary winding coupled to the output of the corresponding DC/AC converter 4 with a secondary winding. The secondary windings of theindividual transformers 69 are connected in series between theoutput terminals power converter circuit 1. Thetransformers 69 are low frequency transformers that are capable to generate a secondary side current (that is a current through the secondary winding) that corresponds to a primary side current (that is a current through the primary winding) or that is proportional to the primary side current. In each case, the primary side current is the current output by the corresponding DC/AC converter. - Although an
operation mode controller 50, aconnection circuit 70 and ameasurement circuit 600 is only illustrated in thepower converter circuits 1 ofFIGS. 31 and 35 , anoperation mode controller 50, aconnection circuit 70 and ameasurement circuit 600 could be implemented in each of the otherpower converter circuits 1, explained herein, as well. - Each of the circuits explained before may be implemented as analog or digital circuit, or as a mixed circuit with analog and digital circuit means. Consequently, the signals explained before may be analog or digital signals. In case of the synchronization signal Sv1 or Sv1 ′, respectively, “continuous synchronization signal” means that the synchronization signal is available in each period of the AC output current i1 and has a waveform corresponding to the waveform of the corresponding output current i1.
- Although various exemplary embodiments of the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the spirit and scope of the invention. It will be obvious to those reasonably skilled in the art that other components performing the same functions may be suitably substituted. It should be mentioned that features explained with reference to a specific figure may be combined with features of other figures, even in those cases in which this has not explicitly been mentioned. Further, the methods of the invention may be achieved in either all software implementations, using the appropriate processor instructions, or in hybrid implementations that utilize a combination of hardware logic and software logic to achieve the same results. Such modifications to the inventive concept are intended to be covered by the appended claims.
- Spatially relative terms such as “under,” “below,” “lower,” “over,” “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first,” “second” and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
- As used herein, the terms “having,” “containing,” “including,” “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a,” “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
- With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
- It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Claims (21)
1. A power converter circuit, comprising:
a synchronization circuit configured to generate at least one synchronization signal; and
a series circuit comprising a plurality of converter units configured to output an output current;
wherein at least one of the plurality of converter units comprises a transformer and is configured to generate an output current such that a frequency or a phase of the generated output current is dependent on the synchronization signal.
2. The power converter circuit of claim 1 ,
wherein the power converter circuit is configured to receive an external voltage; and
wherein the synchronization circuit is configured to generate the synchronization signal based on a voltage level of the external voltage.
3. The power converter circuit of claim 2 , wherein the synchronization circuit is configured to generate the synchronization signal such that there is a phase difference between the external voltage and the synchronization signal.
4. The power converter circuit of claim 3 , wherein the phase difference is substantially equal to zero.
5. The power converter circuit of claim 1 , wherein the at least one of the plurality of converter units comprises:
a first converter configured to receive a direct voltage and to output a direct voltage; and
a second converter configured to receive the direct voltage output by the first converter and to generate the output current.
6. The power converter circuit of claim 5 , wherein the first converter comprises a topology selected from the group consisting of:
a flyback converter topology;
a two-transistor forward (TTF) converter topology;
a phase-shift zero-voltage switching (PS ZVS) converter topology; and
an LLC converter topology.
7. The power converter circuit of claim 1 , wherein the at least one of the plurality of converter units comprises a converter configured to receive a direct voltage and to output a rectified current based on the synchronization signal.
8. The power converter circuit of claim 7 , wherein the at least one of the plurality of converter units further comprises an unfolding bridge configured to receive the rectified current and to generate the output current.
9. The power converter circuit of claim 7 , further comprising an unfolding bridge coupled to the series circuit.
10. The power converter circuit of claim 7 , wherein the converter comprises a topology selected from the group consisting of:
a flyback converter topology;
a two-transistor forward (TTF) converter topology;
a phase-shift zero-voltage switching (PS ZVS) converter topology; and
an LLC converter topology.
11. The power converter circuit of claim 1 , wherein the plurality of converter units share one transformer.
12. A method, comprising:
generating a synchronization signal by a synchronization circuit;
outputting an output current by a series circuit that comprises a plurality of converter units, wherein at least one of the plurality of converter units comprises a transformer;
generating an output current by at least one of the plurality of converter units such that a frequency or a phase of the generated output current is dependent on the synchronization signal.
13. The method of claim 12 , further comprising receiving an external voltage, wherein the synchronization signal is generated based on a voltage level of the external voltage by the synchronization circuit.
14. The method of claim 13 , wherein the synchronization signal is generated such that there is a phase difference between the external voltage and the synchronization signal by the synchronization circuit.
15. The method of claim 14 , wherein the phase difference is substantially equal to zero.
16. The method of claim 12 , further comprising:
receiving a direct voltage by a first converter in one of the plurality converter units;
outputting a direct voltage by the first converter; and
receiving the direct voltage from the first converter by a second converter in one of the plurality of converter units and generating the output current by the second converter.
17. The method of claim 16 , wherein the first converter comprises a topology selected from the group consisting of:
a flyback converter topology;
a two-transistor forward (TTF) converter topology;
a phase-shift zero-voltage switching (PS ZVS) converter topology; and
an LLC converter topology.
18. The method of claim 12 , further comprising receiving a direct voltage and outputting a rectified current based on the synchronization signal by a converter in one of the plurality converter units.
19. The method of claim 18 , further comprising receiving the rectified current and generating the output current by an unfolding bridge.
20. The method of claim 19 , wherein the converter comprises a topology selected from the group consisting of:
a flyback converter topology;
a two-transistor forward (TTF) converter topology;
a phase-shift zero-voltage switching (PS ZVS) converter topology; and
an LLC converter topology.
21. The method of claim 12 , wherein the plurality of converter units share one transformer.
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US15/243,656 US20160359332A1 (en) | 2013-01-08 | 2016-08-22 | Power converter circuit with ac output and at least one transformer |
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US15/243,656 US20160359332A1 (en) | 2013-01-08 | 2016-08-22 | Power converter circuit with ac output and at least one transformer |
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US9263971B2 (en) | 2011-12-16 | 2016-02-16 | Empower Micro Systems Inc. | Distributed voltage source inverters |
US9143056B2 (en) | 2011-12-16 | 2015-09-22 | Empower Micro Systems, Inc. | Stacked voltage source inverter with separate DC sources |
US9099938B2 (en) | 2011-12-16 | 2015-08-04 | Empower Micro Systems | Bi-directional energy converter with multiple DC sources |
US9537677B2 (en) | 2012-01-16 | 2017-01-03 | Sensanna Incorporated | Individually identifiable surface acoustic wave sensors, tags and systems |
US9401663B2 (en) | 2012-12-21 | 2016-07-26 | Infineon Technologies Austria Ag | Power converter circuit with AC output |
US9484746B2 (en) | 2012-01-17 | 2016-11-01 | Infineon Technologies Austria Ag | Power converter circuit with AC output |
US9478989B2 (en) | 2012-01-17 | 2016-10-25 | Infineon Technologies Austria Ag | Power converter circuit with AC output |
US9461474B2 (en) | 2012-01-17 | 2016-10-04 | Infineon Technologies Austria Ag | Power converter circuit with AC output |
US20150008748A1 (en) | 2012-01-17 | 2015-01-08 | Infineon Technologies Austria Ag | Power Converter Circuit, Power Supply System and Method |
US9673732B2 (en) | 2012-01-24 | 2017-06-06 | Infineon Technologies Austria Ag | Power converter circuit |
-
2013
- 2013-01-08 US US13/736,796 patent/US9425622B2/en active Active
-
2016
- 2016-08-22 US US15/243,656 patent/US20160359332A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160172860A1 (en) * | 2014-12-15 | 2016-06-16 | Solantro Semiconductor Corp. | Power converter communications |
US10381836B2 (en) * | 2014-12-15 | 2019-08-13 | Solantro Semiconductor Corp. | Power converter communications |
Also Published As
Publication number | Publication date |
---|---|
US9425622B2 (en) | 2016-08-23 |
US20140191582A1 (en) | 2014-07-10 |
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