US20160315048A1 - Semiconductor electroplating system - Google Patents
Semiconductor electroplating system Download PDFInfo
- Publication number
- US20160315048A1 US20160315048A1 US15/138,167 US201615138167A US2016315048A1 US 20160315048 A1 US20160315048 A1 US 20160315048A1 US 201615138167 A US201615138167 A US 201615138167A US 2016315048 A1 US2016315048 A1 US 2016315048A1
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- US
- United States
- Prior art keywords
- conducting ring
- layer
- wafer
- electroplating system
- sidewall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000009713 electroplating Methods 0.000 title claims abstract description 40
- 238000002955 isolation Methods 0.000 claims abstract description 61
- 238000007747 plating Methods 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 description 177
- 239000000758 substrate Substances 0.000 description 30
- 230000004888 barrier function Effects 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000011017 operating method Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 230000001965 increasing effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
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- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
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- C25D17/005—Contacting devices
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- C25D7/00—Electroplating characterised by the article coated
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Definitions
- the present invention relates to a semiconductor electroplating system.
- a typical RF sensor includes a chip package and passive components.
- the passive components can be, for example, inductors.
- the chip package is used as an active component. Both the chip package and the inductors are disposed on a printed circuit board, and the inductors are placed outside the chip package.
- An aspect of the present invention is to provide a chip package.
- a chip package includes a chip, an isolation layer and a redistribution layer.
- the chip has a substrate, an electrical pad and a protection layer.
- the substrate has a first surface and an opposite second surface.
- the protection layer is located on the first surface, and the electrical pad is located in the protection layer.
- the substrate has a through hole, and the protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole.
- the isolation layer is located on the second surface, a sidewall of the through hole, and a sidewall of the concave hole.
- the redistribution layer includes a connection portion and a passive component portion.
- the connection portion is located on the isolation layer and in electrical contact with the electrical pad.
- the passive component portion is located on the isolation layer that is on the second surface, and an end of the passive component portion is connected to the connection portion that is on the second surface.
- Another aspect of the present invention is to provide a manufacturing method of a chip package.
- a manufacturing method of a chip package includes the following steps.
- the manufacturing method of a chip package includes the following steps.
- a temporary adhesive layer is used to attach a carrier to a wafer.
- the wafer has a substrate, an electrical pad and a protection layer.
- the substrate has a first surface and an opposite second surface.
- the protection layer is located on the first surface, and the electrical pad is located in the protection layer.
- the second surface of the substrate is etched to form a through hole in the substrate.
- the protection layer in the through hole is etched, such that a concave hole is formed in the protection layer, and the electrical pad is exposed through the concave hole and the through hole.
- An isolation layer is formed on the second surface, a sidewall of the through hole, and a sidewall of the concave hole.
- a redistribution layer is formed on the isolation layer and the electrical pad. The redistribution layer is patterned to simultaneously form a connection portion and a passive component portion in the redistribution layer.
- the connection portion is located on the isolation layer and in electrical contact with the electrical pad.
- the passive component portion is located on the isolation layer that is on the second surface, and an end of the passive component portion is connected to the connection portion that is on the second surface.
- the chip package since the redistribution layer of the chip package has a passive component portion, the chip package thereby has both the functions of an active component and of an passive component.
- the passive component portion can be used as the inductor of the chip package. While patterning the redistribution layer, both the passive component portion and the connection portion are formed simultaneously, such that the passive component portion is formed on the isolation layer that is on the second surface of the substrate. Hence, the required time for manufacturing the passive component portion may be saved.
- the chip package of the present invention may be used as a RF sensor which do not require a typical independent inductor but still has an inductor function.
- Another aspect of the invention is to provide a semiconductor electroplating system.
- a semiconductor electroplating system includes a conducting ring and at least one conductive device.
- the conducting ring is used for carrying a wafer.
- the conducting ring has at least two connecting points.
- the wafer has a first surface and an opposite second surface.
- An isolation layer is located on the second surface. Two ends of the conductive device are respectively connected to the two connecting points of the conducting ring.
- the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer.
- the conductive device is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.
- Another aspect of the invention is to provide a semiconductor electroplating system.
- a semiconductor electroplating system includes a conducting ring and at least one conductive piece.
- the conducting ring is used for carrying a wafer.
- the conducting ring has a ring-shaped track.
- the wafer has a first surface and an opposite second surface.
- the isolation layer is located on the second surface.
- Each of two ends of the conductive piece has a connecting point.
- Each of the connecting points is movably connected to the ring-shaped track of the conducting ring, and the conductive piece overlaps a portion of the conducting ring.
- FIG. 1 is a cross-sectional view of a chip package according to an embodiment of the present invention
- FIG. 2 is a schematic view of a layout of a redistribution layer of the chip package shown in FIG. 1 ;
- FIG. 3 is a flow chart of a manufacturing method of a chip package according to an embodiment of the present invention.
- FIG. 4 is a cross-sectional view of a wafer after being attached by a carrier according to an embodiment of the present invention
- FIG. 5 is a cross-sectional view of a substrate shown in FIG. 4 after being ground;
- FIG. 6 is a cross-sectional view of a through hole after being formed in the substrate shown in FIG. 5 ;
- FIG. 7 is a cross-sectional view of a concave hole after being formed in a protection layer shown in FIG. 6 ;
- FIG. 8 is a cross-sectional view of an isolation layer after being formed on a second surface, a sidewall of the through hole, and a sidewall of the concave hole shown in FIG. 7 ;
- FIG. 9 is a cross-sectional view of the redistribution layer after being formed on the isolation layer and the electrical pad shown in FIG. 8 ;
- FIG. 10 is a cross-sectional view of a conductive structure after being formed on the redistribution layer shown in FIG. 9 ;
- FIG. 11A is a cross-sectional view of a chip package according to another embodiment of the present invention.
- FIG. 11B is a schematic view of a layout of a redistribution layer of the chip package shown in FIG. 11A ;
- FIG. 12A is a cross-sectional view of a chip package according to further another embodiment of the present invention.
- FIG. 12B is a schematic view of a layout of a redistribution layer of the chip package in FIG. 12A ;
- FIG. 12C is another embodiment of FIG. 12B ;
- FIG. 13 is a cross-sectional view of a chip package according to further another embodiment of the present invention.
- FIG. 14 is a cross-sectional view of a chip package according to further another embodiment of the present invention.
- FIG. 15 is a flow chart of an operating method of a semiconductor electroplating system according to an embodiment of the present invention.
- FIG. 16 is a top view of a semiconductor electroplating system according to an embodiment of the present invention.
- FIG. 17 is a cross-sectional view of the semiconductor electroplating system taken along line 17 - 17 shown in FIG. 16 ;
- FIG. 18 is a cross-sectional view of a redistribution layer that is to be patterned after being formed on an isolation layer shown in FIG. 8 through the semiconductor electroplating system shown in FIG. 16 ;
- FIG. 19 is a top view of a semiconductor electroplating system according to an embodiment of the present invention.
- FIG. 20 is a flow chart of an operating method of a semiconductor electroplating system according to an embodiment of the present invention.
- FIG. 21 is a top view of a semiconductor electroplating system according to an embodiment of the present invention.
- FIG. 1 is a cross-sectional view of a chip package 100 according to an embodiment of the present invention.
- FIG. 2 is a schematic view of a layout of a redistribution layer 130 of the chip package 100 shown in FIG. 1 .
- the chip package 100 includes a chip 110 , an isolation layer 120 , and a redistribution layer (RDL) 130 .
- the chip 110 has a substrate 112 , an electrical pad 114 and a protection layer 116 .
- the substrate 112 has a first surface 111 and an opposite second surface 113 .
- the protection layer 116 is located on the first surface 111 .
- the electrical pad 114 is located in the protection layer 116 .
- the substrate 112 has a through hole 115
- the protection layer 116 has a concave hole 117 , such that the electrical pad 114 is exposed through the concave hole 117 and the through hole 115 .
- the isolation layer 120 is located on the second surface 113 , the sidewall of the through hole 115 , and the sidewall of the concave hole 117 .
- the redistribution layer 130 includes a connection portion 132 and a passive component portion 134 .
- the connection portion 132 is located on the isolation layer 120 and in electrical contact with the electrical pad 114 .
- the passive component portion 134 is located on the isolation layer 120 that is on the second surface 113 , and an end of the passive component portion 134 is connected to the connection portion 132 that is on the second surface 113 .
- the chip package 100 may be a RF sensor, but the present invention is not limited in this regard.
- the substrate 112 may be made of a material including silicon.
- the protection layer 116 may include inter-layer dielectric (ILD), inter-metal dielectric (IMD), and passivation layer.
- the redistribution layer 130 may be made of a material including aluminum or copper, and the physical vapor deposition (PVD) method or the electroplating method may be used to form the redistribution layer 130 that covers the isolation layer 120 and the electrical pad 114 , then a patterning process is used to simultaneously form the connection portion 132 and the passive component portion 134 in the redistribution layer 130 .
- the patterning process may include photolithography techniques, such as exposure, developing and etching.
- the chip package 100 Since the redistribution layer 130 of the chip package 100 has a passive component portion 134 , the chip package 100 thereby has both the function of a active component and a passive component.
- the passive component portion 134 can be used as the inductor of the chip package 100 .
- the chip package 100 of the present invention has the inductor function without needing a conventional independent inductor. As a result, both the assembly time of the chip package and the cost can be saved, since no typical inductor is needed.
- the passive component portion 134 and the connection portion 132 are formed simultaneously, such that the passive component portion 134 is formed on the isolation layer 120 that is on the second surface 113 of the substrate 112 .
- the required time for manufacturing the passive component portion 134 is saved.
- a printed circuit board for placing the chip package 100 does not need to reserve space and wires for disposing a typical inductor, thereby enhancing the design convenience.
- the shape of the passive component portion 134 is U-shaped, however, it is not a restriction of the present invention. Designers can design the layout scheme of the redistribution layer 130 according to the design requirement, to change the shape of the passive component portion 134 .
- the chip package 100 further includes a barrier layer 140 and a conductive structure 150 .
- the barrier layer 140 is located on the redistribution layer 130 and the isolation layer 120 that is on the second surface 113 .
- the barrier layer 140 has an opening 142 to expose the connection portion 132 .
- the conductive structure 150 is located on the connection portion 132 that is in the opening 142 of the barrier layer 140 , such that the conductive structure 150 is electrically connected to the electrical pad 114 through the connection portion 132 of the redistribution layer 130 .
- the conductive structure 150 may be a solder ball or a conductive bump of a ball grid array (BGA).
- the chip package 100 may selectively has a cavity 160 .
- the cavity 160 is located between the barrier layer 140 and the connection portion 132 that is in the through hole 115 .
- the manufacturing method of the chip package 100 will be described in the following descriptions.
- FIG. 3 is a flow chart of a manufacturing method of a chip package according to an embodiment of the present invention.
- the manufacturing method of the chip package includes the following steps.
- step S 1 a temporary adhesive layer is used to attach a carrier to a wafer.
- the wafer has a substrate, an electrical pad and a protection layer.
- the substrate has a first surface and an opposite second surface.
- the protection layer is located on the first surface, and the electrical pad is located in the protection layer.
- step S 2 the second surface of the substrate is etched to form a through hole in the substrate.
- step S 3 the protection layer in the through hole is etched, such that a concave hole is formed in the protection layer, and the electrical pad is exposed through the concave hole and the through hole.
- step S 4 an isolation layer is formed on the second surface, a sidewall of the through hole, and a sidewall of the concave hole.
- step S 5 a redistribution layer is formed on the isolation layer and the electrical pad.
- step S 6 the redistribution layer is patterned to simultaneously form a connection portion and a passive component portion in the redistribution layer.
- the connection portion is located on the isolation layer and in electrical contact with the electrical pad.
- the passive component portion is located on the isolation layer that is on the second surface, and an end of the passive component portion is connected to the connection portion that is on the second surface.
- FIG. 4 is a cross-sectional view of a wafer 110 a after being attached by a carrier 204 according to an embodiment of the present invention.
- FIG. 5 is a cross-sectional view of the substrate 112 shown in FIG. 4 after being ground.
- wafer 110 a is referred to as a semiconductor structure that includes plural chips 110 of FIG. 1 before a cutting process.
- the wafer 110 a has the substrate 112 , the electrical pad 114 , and the protection layer 116 .
- a temporary adhesive layer 202 is used to attach a carrier 204 onto a wafer 110 a .
- the carrier 204 may be made of a material including a glass, for providing the support strength of the wafer 110 a .
- the second surface 113 of the substrate 112 may be ground, such that the thickness of the substrate 112 is reduced from D 1 to D 2 .
- FIG. 6 is a cross-sectional view of the through hole 115 after being formed in the substrate 112 shown in FIG. 5 .
- FIG. 7 is a cross-sectional view of the concave hole 117 after being formed in the protection layer 116 shown in FIG. 6 .
- the second surface 113 of the substrate 112 may be etched, such that the through hole 115 which aligned with the electrical pad 114 is formed in the substrate 112 .
- the protection layer 116 in the through hole 115 is etched, such that a concave hole 117 aligned with the electrical pad 114 is formed in the protection layer 116 .
- the electrical pad 114 is exposed through the concave hole 117 and the through hole 115 .
- FIG. 8 is a cross-sectional view of the isolation layer 120 after being formed on the second surface 113 , the sidewall of the through hole 115 , and the sidewall of the concave hole 117 shown in FIG. 7 .
- FIG. 9 is a cross-sectional view of the redistribution layer 130 after being formed on the isolation layer 120 and the electrical pad 114 shown in FIG. 8 As shown in FIG. 8 and FIG. 9 , after the electrical pad 114 is exposed through the concave hole 117 and the through hole 115 , the isolation layer 120 may be formed on the second surface 113 of the substrate 112 , the sidewall of the second surface 113 , the sidewall of the through hole 115 , and on the sidewall of the concave hole 117 .
- the isolation layer 120 may be formed by a patterning process, such that at least one portion of the electrical pad 114 is covered by the isolation layer 120 .
- the redistribution layer 130 may be formed on the isolation layer 120 and the electrical pad 114 .
- the redistribution layer 130 is patterned to form the connection portion 132 and the passive component portion 134 simultaneously.
- the connection portion 132 is located on the isolation layer 120 and in electrical contact with the electrical pad 114 .
- the passive component portion 134 is located on the isolation layer 120 that is on the second surface 113 , and an end of the passive component portion 134 is connected to the connection portion 132 that is on the second surface 113 .
- FIG. 10 is a cross-sectional view of the conductive structure 150 after being formed on the redistribution layer 130 shown in FIG. 9 .
- the barrier layer 140 may be formed on the redistribution layer 130 and the isolation layer 120 that is on the second surface 113 .
- the barrier layer 140 is patterned to form an opening 142 , such that the connection portion 132 of the redistribution layer 130 is exposed through the opening 142 .
- the conductive structure 150 may be formed on the connection portion 132 that is in the opening 142 of the barrier layer 140 , such that the conductive structure 150 is electrically connected to the electrical pad 114 through the connection portion 132 .
- the carrier 204 , the wafer 110 a , the isolation layer 120 and the barrier layer 140 may be cut along line L-L.
- the temporary adhesive layer 202 may be irradiated with ultraviolet light, raise the temperature, or be immersed in a chemical liquid, such that the adhesion of the temporary adhesive layer 202 is removed. As a result, the carrier 204 can be removed and thereby forming the chip package 100 of FIG. 1 .
- FIG. 11A is a cross-sectional view of a chip package 100 a according to another embodiment of the present invention.
- FIG. 11B is a schematic view of the layout of the redistribution layer 130 of the chip package 100 a shown in FIG. 11A .
- the chip package 100 a includes the chip 110 , the isolation layer 120 and the redistribution layer 130 .
- the redistribution layer 130 includes the connection portion 132 and the passive component portion 134 .
- the difference between this embodiment and the embodiment shown in FIG. 1 and FIG. 2 is that herein the passive component portion 134 is planar spiral-shaped.
- the chip 110 has a conducting wire L 1 located on the protection layer 116 , and the conducting wire L 1 is connected to the electrical pad 114 and another adjacent electrical pad 114 .
- FIG. 12A is a cross-sectional view of a chip package 100 b according to further another embodiment of the present invention.
- FIG. 12B is a schematic view of the layout of the redistribution layer 130 of the chip package 100 b in FIG. 12A .
- the chip package 100 b includes the chip 110 , the isolation layer 120 , and the redistribution layer 130 .
- the redistribution layer 130 includes the connection portion 132 and the passive component portion 134 .
- the passive component portion 134 is three-dimensional spiral-shaped. That is to say, the passive component portion 134 is not at the same level.
- FIG. 12C is another embodiment of FIG. 12B .
- the chip package 100 b includes the chip 110 , the isolation layer 120 , and the redistribution layer 130 .
- the redistribution layer 130 includes the connection portion 132 and the passive component portion 134 .
- the chip 110 further includes a magnetic component 170 , and the magnetic component 170 is surrounded by the passive component portion 134 of the redistribution layer 130 .
- the magnetic component 170 can increase the inductance value of the chip package 100 b.
- FIG. 13 is a cross-sectional view of a chip package 100 c according to further another embodiment of the present invention.
- the chip package 100 c includes the chip 110 , the isolation layer 120 , and the redistribution layer 130 .
- the redistribution layer 130 includes the connection portion 132 and the passive component portion 134 .
- the chip 110 has the first electrical pad 114 .
- the chip 110 further includes a second electrical pad 114 a .
- the second electrical pad 114 a is located in the protection layer 116 and the first electrical pad 114 is located between the second electrical pad 114 a and the substrate 112 .
- the protection layer 116 has an opening 118 to expose the second electrical pad 114 a .
- the conductive structure 150 is located on the second electrical pad 114 a that is in the opening 118 of the protection layer 116 .
- the second electrical pad 114 a may be electrically connected to the first electrical pad 114 through a conductor that is in the protection layer 116 .
- FIG. 14 is a cross-sectional view of a chip package 100 d according to further another embodiment of the present invention.
- the chip package 100 d includes the chip 110 , the isolation layer 120 , and the redistribution layer 130 .
- the redistribution layer 130 includes the connection portion 132 and the passive component portion 134 .
- the chip package 100 d further includes a conductive layer 180 and a barrier layer 140 a .
- the conductive layer 180 is located on a surface 119 of the protection layer 116 facing away from the substrate 112 and on the second electrical pad 114 a that is in the opening 118 of the protection layer 116 .
- the barrier layer 140 a covers the conductive layer 180 and the protection layer 116 , and the barrier layer 140 a has an opening 142 a to expose the conductive layer 180 .
- the conductive structure 150 is located on a conductive layer 180 that is in the opening 142 a of the barrier layer 140 a , such that the conductive structure 150 is electrically connect to the second electrical pad 114 a through the conductive layer 180 .
- FIG. 15 is a flow chart of an operating method of a semiconductor electroplating system according to an embodiment of the present invention.
- step S 1 a two ends of at least one conductive device are respectively connected to two connecting points of a conducting ring.
- step S 2 a the wafer having the isolation layer is disposed into the conducting ring.
- step S 3 a the conducting ring is immersed in a plating solution.
- step S 4 a the conducting ring is energized to from the redistribution layer that is to be patterned on the isolation layer. A partial current passing through one of the connecting points transmits to the other connecting point through the conductive device.
- FIG. 16 is a top view of a semiconductor electroplating system 300 according to an embodiment of the present invention.
- FIG. 17 is a cross-sectional view of the semiconductor electroplating system 300 taken along line 17 - 17 shown in FIG. 16 .
- the semiconductor electroplating system 300 includes a conducting ring 310 and at least one conductive device 320 .
- the conducting ring 310 can be used to carry the semiconductor structure of FIG. 8 .
- the conducting ring 310 has at least two connecting points 318 a and 318 b .
- the connecting points 318 a and 318 b may be screws or blots, and the conductive device 320 may be an electric wire, but the present invention is not limited in this regard.
- two ends 332 and 324 of the conductive device 320 may be respectively connected to the two connecting points 318 a and 318 b of the conducting ring 310 , and the conductive device 320 is disposed along the edge of the conducting ring 310 .
- the wafer 110 a having the isolation layer 120 shown in FIG. 8 may be disposed in the conducting ring 310 .
- the conducting ring 310 has a top surface 312 , a sidewall 314 , and a supporting surface 316 which are sequentially connected.
- the connecting points 318 a and 318 b and the conductive device 320 are disposed on the top surface 312 of the conducting ring 310 .
- the sidewall 314 surrounds an accommodating space 311 , and the supporting surface 316 is protruded from the accommodating space 311 , such that the top surface 312 , the sidewall 314 , and the supporting surface 316 form a ladder structure.
- the accommodating space 311 can hold the wafer 110 a of FIG.
- the wafer 110 a can be disposed on the supporting surface 316 , such that the wafer 110 a is surrounded by the sidewall 314 .
- the first surface 111 of the wafer 110 a (front surface) faces the supporting surface 316 .
- the conducting ring 310 and the wafer 110 a that has the electrical pad 114 therein are immersed in a plating solution and are energized, such that the circuit can flow into the conducting ring 310 through the conducting wire 302 .
- the connecting point 318 a of the conducting ring 310 can be connected to the conducting wire 302 and to an end 332 of the conductive device 320 at the same time.
- FIG. 18 is a cross-sectional view of the redistribution layer 130 that is to be patterned after being formed on the isolation layer 120 shown in FIG. 8 through the semiconductor electroplating system 300 shown in FIG. 16 .
- the redistribution layer 130 that is to be patterned can be formed on the isolation layer 120 .
- the conductive device 320 can transmit a partial current that passes through the connecting point 318 a to another connecting point 318 b , such that the redistribution layer 130 on the second surface 113 (back surface) has a uniform thickness.
- the conducting ring 310 If there is no conductive device 320 disposed on the conducting ring 310 , while energizing, due to the impedance of the conducting ring 310 itself, and the distance which the current flows to the place adjacent to the connecting point 318 a of the conducting ring 310 is shorter than the distance which the current flows to the place adjacent to the connecting point 318 b of the conducting ring 310 , it is easy to cause the redistribution layer 130 adjacent to the connecting point 318 a is thicker than the redistribution layer 130 adjacent to the connecting point 318 b.
- the conductive device 320 on the conducting ring 310 has the function of dispersing the current.
- the conductive device 320 can lead a partial current that passes through the connecting point 318 a of the conducting ring 310 to a specific place (e.g., the connecting point 318 b ), such that the thickness of the redistribution layer 130 formed adjacent to the connecting point 318 a is reduced, and the thickness of the redistribution layer 130 formed adjacent to the connecting point 318 b is increased.
- the thickness uniformity of the redistribution layer 130 that is to be patterned can be improved.
- the standard deviation of each place of the redistribution layer 130 on the second surface 113 (back surface) of the wafer 110 a can be reduced to 0.2 ⁇ m to 0.4 ⁇ m.
- the designer can change the positions of the conductive device 320 and of the connecting points 318 a and 318 b on the top surface 312 of the conducting ring 310 , and the number of the conductive device 320 and of the connecting points 318 a and 318 b according to the design requirements.
- the passive component portion 134 of FIG. 9 would have a similar thickness, thereby ensuring the function of itself as an integrated passive device (IPD).
- IPD integrated passive device
- FIG. 19 is a top view of a semiconductor electroplating system 300 a according to an embodiment of the present invention.
- the semiconductor electroplating system 300 a includes the conducting ring 310 and conductive devices 320 a and 320 b .
- the difference between this embodiment and the embodiment shown in FIG. 16 is that herein the semiconductor electroplating system 300 a has two conductive devices 320 a , 320 b and five connecting points 318 c , 318 d , 318 e , 318 f , 318 g .
- the connecting point 318 c is connected to the conducting wire 302 which provides the current.
- Two ends 322 a and 324 a of the conductive device 320 a are respectively connected to the two connecting points 318 d , 318 e of the conducting ring 310 , and two ends 322 b , 324 b of the conductive device 320 b are respectively connected to the two connecting points 318 f and 318 g of the conducting ring 310 .
- the conductive device 320 a can lead a partial current that passes through the connecting point 318 d of the conducting ring 310 to the connecting point 318 e
- the conductive device 320 b can lead a partial current that passes through the connecting point 318 f of the conducting ring 310 to the connecting point 318 g , thereby reducing the thickness of the redistribution layer 130 formed adjacent to the connecting points 318 d and 318 f and increasing the thickness of the redistribution layer 130 formed adjacent to the connecting point 318 e and 318 g .
- the thickness uniformity of the redistribution layer 130 that is to be patterned is improved.
- FIG. 20 is a flow chart of an operating method of a semiconductor electroplating system according to an embodiment of the present invention
- step S 1 b two connecting points of two ends of at least one conductive piece are movably connected to a ring-shaped track of a conducting ring.
- the conductive piece overlaps a portion of the conducting ring.
- step S 2 b the wafer having the isolation layer is disposed in the conducting ring.
- step S 3 b the conducting ring is immersed in a plating solution.
- step S 4 b the conducting ring is energized to form the redistribution layer that is to be patterned on the isolation layer. A partial current passing through one of the connecting points transmits to the other connecting point through the conductive piece.
- FIG. 21 is a top view of a semiconductor electroplating system 300 b according to an embodiment of the present invention.
- the semiconductor electroplating system 300 b includes a conducting ring 310 a and at least one conductive piece 330 .
- the conducting ring 310 a can be used to carry semiconductor structure of FIG. 8 .
- the conducting ring 310 a has a ring-shaped track 313 .
- Each of the two ends 332 and 334 of the conductive piece 330 has a connecting point that is movably connected to the ring-shaped track 313 of the conducting ring 310 a .
- the connecting points of the two ends 332 and 334 of the conductive piece 330 may be protrusions, and the ring-shaped track 313 may be a slot that can be coupled to the protrusions, or, the connecting points of the two ends 332 and 334 of the conductive piece 330 may be metal wheels, and the ring-shaped track 313 may be a slot that can be coupled to the wheels.
- the conductive piece 330 After the conductive piece 330 is connected to the ring-shaped track 313 of the conducting ring 310 a , the conductive piece 330 overlaps a portion of the conducting ring 310 a , and the conductive piece 330 can be stressed to move on and along the ring-shaped track 313 in a clockwise direction D 3 or a counterclockwise direction D 4 .
- the wafer 110 a having the isolation layer 120 shown in FIG. 8 can be disposed in the conducting ring 310 a.
- the conducting ring 310 a has the top surface 312 , the sidewall 314 , and the supporting surface 316 which are sequentially connected.
- the conductive piece 330 and the ring-shaped track 313 are both disposed on the top surface 312 of the conducting ring 310 a .
- the sidewall 314 surrounds the accommodating space 311 , and the supporting surface 316 is protruding from the accommodating space 311 , such that the top surface 312 , the sidewall 314 , and the supporting surface 316 form a ladder structure.
- the accommodating space 311 can hold the wafer 110 a of FIG.
- the wafer 110 a can be disposed on the supporting surface 316 , such that the wafer 110 a is surrounded by the sidewall 314 .
- the first surface 111 of the wafer 110 a (front surface) faces the supporting surface 316 .
- the conducting ring 310 a and the wafer 110 a that has the isolation layer 120 may be immersed in a plating solution and energized, the circuit can flow into the conducting ring 310 a through the conducting wire 302 .
- the redistribution layer 130 that is to be patterned can be formed on the isolation layer 120 .
- the conductive piece 330 can transmit a partial current that passes through the connecting point of the end 332 to the connecting point of the other end 334 , such that the redistribution layer 130 on the second surface 113 (back surface) has a uniform thickness.
- the conductive piece 330 located on the conducting ring 310 a has the function of dispersing the current.
- the conductive piece 330 can lead a partial current that passes through the connecting point of one end 332 in contact with the conducting ring 310 a to a specific place (such as the connecting point of the other end 334 ), thereby reducing the thickness of the redistribution layer 130 formed adjacent to the end 332 of the conductive piece 330 and increasing the thickness of the redistribution layer 130 formed adjacent to the end 334 of the conductive piece 330 .
- the thickness uniformity of the redistribution layer 130 that is to be patterned can be improved.
- the designer may slide the conductive piece 330 on the ring-shaped track 313 of the top surface 312 of the conducting ring 310 a according to the design requirements, such that the positions of the two ends 332 and 334 of the conductive piece 330 on the top surface 312 are adjusted.
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Abstract
A semiconductor electroplating system includes a conducting ring and at least one conductive device. The conducting ring is used for carrying a wafer. The conducting ring has at least two connecting points. The wafer has a first surface and an opposite second surface. An isolation layer is located on the second surface. Two ends of the conductive device are respectively connected to the two connecting points of the conducting ring. When the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer. The conductive device is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.
Description
- This application claims priority to U.S. Provisional Application Ser. No. 62/153,400 filed Apr. 27, 2015, and Taiwan Application Serial Number 104126716, filed Aug. 17, 2015, the disclosures of which are incorporated herein by reference in their entireties.
- 1. Field of Invention
- The present invention relates to a semiconductor electroplating system.
- 2. Description of Related Art
- A typical RF sensor includes a chip package and passive components. The passive components can be, for example, inductors. And the chip package is used as an active component. Both the chip package and the inductors are disposed on a printed circuit board, and the inductors are placed outside the chip package.
- That is to say, after the chip package is manufactured, additional and independent inductors are required to be arranged on the printed circuit board to allow the RF sensor working properly. However, it leads to a lot of assembly time for the RF sensor, and makes it difficult to reduce the cost of the inductors. Moreover, additional space and circuits need to be reserved on the printed circuit board, thereby causing design inconvenience.
- An aspect of the present invention is to provide a chip package.
- According to an embodiment of the present invention, a chip package includes a chip, an isolation layer and a redistribution layer. The chip has a substrate, an electrical pad and a protection layer. The substrate has a first surface and an opposite second surface. The protection layer is located on the first surface, and the electrical pad is located in the protection layer. The substrate has a through hole, and the protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, a sidewall of the through hole, and a sidewall of the concave hole. The redistribution layer includes a connection portion and a passive component portion. The connection portion is located on the isolation layer and in electrical contact with the electrical pad. The passive component portion is located on the isolation layer that is on the second surface, and an end of the passive component portion is connected to the connection portion that is on the second surface.
- Another aspect of the present invention is to provide a manufacturing method of a chip package.
- According to an embodiment of the present invention, a manufacturing method of a chip package includes the following steps. The manufacturing method of a chip package includes the following steps. A temporary adhesive layer is used to attach a carrier to a wafer. The wafer has a substrate, an electrical pad and a protection layer. The substrate has a first surface and an opposite second surface. The protection layer is located on the first surface, and the electrical pad is located in the protection layer. The second surface of the substrate is etched to form a through hole in the substrate. The protection layer in the through hole is etched, such that a concave hole is formed in the protection layer, and the electrical pad is exposed through the concave hole and the through hole. An isolation layer is formed on the second surface, a sidewall of the through hole, and a sidewall of the concave hole. A redistribution layer is formed on the isolation layer and the electrical pad. The redistribution layer is patterned to simultaneously form a connection portion and a passive component portion in the redistribution layer. The connection portion is located on the isolation layer and in electrical contact with the electrical pad. The passive component portion is located on the isolation layer that is on the second surface, and an end of the passive component portion is connected to the connection portion that is on the second surface.
- In the aforementioned embodiments of the present invention, since the redistribution layer of the chip package has a passive component portion, the chip package thereby has both the functions of an active component and of an passive component. For example, the passive component portion can be used as the inductor of the chip package. While patterning the redistribution layer, both the passive component portion and the connection portion are formed simultaneously, such that the passive component portion is formed on the isolation layer that is on the second surface of the substrate. Hence, the required time for manufacturing the passive component portion may be saved. The chip package of the present invention may be used as a RF sensor which do not require a typical independent inductor but still has an inductor function. As a result, both the assembly time of the chip package and the cost can be saved, since no typical inductor is required. Besides, a printed circuit board for placing the chip package does not need to reserve space and wires for disposing the typical inductor, thereby enhancing the design convenience.
- Another aspect of the invention is to provide a semiconductor electroplating system.
- According to an embodiment of the present invention, a semiconductor electroplating system includes a conducting ring and at least one conductive device. The conducting ring is used for carrying a wafer. The conducting ring has at least two connecting points. The wafer has a first surface and an opposite second surface. An isolation layer is located on the second surface. Two ends of the conductive device are respectively connected to the two connecting points of the conducting ring. When the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer. The conductive device is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.
- Another aspect of the invention is to provide a semiconductor electroplating system.
- According to an embodiment of the present invention, a semiconductor electroplating system includes a conducting ring and at least one conductive piece. The conducting ring is used for carrying a wafer. The conducting ring has a ring-shaped track. The wafer has a first surface and an opposite second surface. The isolation layer is located on the second surface. Each of two ends of the conductive piece has a connecting point. Each of the connecting points is movably connected to the ring-shaped track of the conducting ring, and the conductive piece overlaps a portion of the conducting ring. When the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer. The conductive piece is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.
- It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.
- The invention can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
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FIG. 1 is a cross-sectional view of a chip package according to an embodiment of the present invention; -
FIG. 2 is a schematic view of a layout of a redistribution layer of the chip package shown inFIG. 1 ; -
FIG. 3 is a flow chart of a manufacturing method of a chip package according to an embodiment of the present invention; -
FIG. 4 is a cross-sectional view of a wafer after being attached by a carrier according to an embodiment of the present invention; -
FIG. 5 is a cross-sectional view of a substrate shown inFIG. 4 after being ground; -
FIG. 6 is a cross-sectional view of a through hole after being formed in the substrate shown inFIG. 5 ; -
FIG. 7 is a cross-sectional view of a concave hole after being formed in a protection layer shown inFIG. 6 ; -
FIG. 8 is a cross-sectional view of an isolation layer after being formed on a second surface, a sidewall of the through hole, and a sidewall of the concave hole shown inFIG. 7 ; -
FIG. 9 is a cross-sectional view of the redistribution layer after being formed on the isolation layer and the electrical pad shown inFIG. 8 ; -
FIG. 10 is a cross-sectional view of a conductive structure after being formed on the redistribution layer shown inFIG. 9 ; -
FIG. 11A is a cross-sectional view of a chip package according to another embodiment of the present invention; -
FIG. 11B is a schematic view of a layout of a redistribution layer of the chip package shown inFIG. 11A ; -
FIG. 12A is a cross-sectional view of a chip package according to further another embodiment of the present invention; -
FIG. 12B is a schematic view of a layout of a redistribution layer of the chip package inFIG. 12A ; -
FIG. 12C is another embodiment ofFIG. 12B ; -
FIG. 13 is a cross-sectional view of a chip package according to further another embodiment of the present invention; -
FIG. 14 is a cross-sectional view of a chip package according to further another embodiment of the present invention; -
FIG. 15 is a flow chart of an operating method of a semiconductor electroplating system according to an embodiment of the present invention; -
FIG. 16 is a top view of a semiconductor electroplating system according to an embodiment of the present invention; -
FIG. 17 is a cross-sectional view of the semiconductor electroplating system taken along line 17-17 shown inFIG. 16 ; -
FIG. 18 is a cross-sectional view of a redistribution layer that is to be patterned after being formed on an isolation layer shown inFIG. 8 through the semiconductor electroplating system shown inFIG. 16 ; -
FIG. 19 is a top view of a semiconductor electroplating system according to an embodiment of the present invention; -
FIG. 20 is a flow chart of an operating method of a semiconductor electroplating system according to an embodiment of the present invention; and -
FIG. 21 is a top view of a semiconductor electroplating system according to an embodiment of the present invention. - Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
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FIG. 1 is a cross-sectional view of achip package 100 according to an embodiment of the present invention.FIG. 2 is a schematic view of a layout of aredistribution layer 130 of thechip package 100 shown inFIG. 1 . As shown inFIG. 1 andFIG. 2 , thechip package 100 includes achip 110, anisolation layer 120, and a redistribution layer (RDL) 130. Thechip 110 has asubstrate 112, anelectrical pad 114 and aprotection layer 116. Thesubstrate 112 has afirst surface 111 and an oppositesecond surface 113. Theprotection layer 116 is located on thefirst surface 111. Theelectrical pad 114 is located in theprotection layer 116. Thesubstrate 112 has a throughhole 115, and theprotection layer 116 has aconcave hole 117, such that theelectrical pad 114 is exposed through theconcave hole 117 and the throughhole 115. Theisolation layer 120 is located on thesecond surface 113, the sidewall of the throughhole 115, and the sidewall of theconcave hole 117. Theredistribution layer 130 includes aconnection portion 132 and apassive component portion 134. Theconnection portion 132 is located on theisolation layer 120 and in electrical contact with theelectrical pad 114. Thepassive component portion 134 is located on theisolation layer 120 that is on thesecond surface 113, and an end of thepassive component portion 134 is connected to theconnection portion 132 that is on thesecond surface 113. - In this embodiment, the
chip package 100 may be a RF sensor, but the present invention is not limited in this regard. Thesubstrate 112 may be made of a material including silicon. Theprotection layer 116 may include inter-layer dielectric (ILD), inter-metal dielectric (IMD), and passivation layer. Theredistribution layer 130 may be made of a material including aluminum or copper, and the physical vapor deposition (PVD) method or the electroplating method may be used to form theredistribution layer 130 that covers theisolation layer 120 and theelectrical pad 114, then a patterning process is used to simultaneously form theconnection portion 132 and thepassive component portion 134 in theredistribution layer 130. The patterning process may include photolithography techniques, such as exposure, developing and etching. - Since the
redistribution layer 130 of thechip package 100 has apassive component portion 134, thechip package 100 thereby has both the function of a active component and a passive component. For instance, thepassive component portion 134 can be used as the inductor of thechip package 100. Thechip package 100 of the present invention has the inductor function without needing a conventional independent inductor. As a result, both the assembly time of the chip package and the cost can be saved, since no typical inductor is needed. - While patterning the
redistribution layer 130, thepassive component portion 134 and theconnection portion 132 are formed simultaneously, such that thepassive component portion 134 is formed on theisolation layer 120 that is on thesecond surface 113 of thesubstrate 112. Hence, the required time for manufacturing thepassive component portion 134 is saved. In addition, a printed circuit board for placing thechip package 100 does not need to reserve space and wires for disposing a typical inductor, thereby enhancing the design convenience. - In this embodiment, the shape of the
passive component portion 134 is U-shaped, however, it is not a restriction of the present invention. Designers can design the layout scheme of theredistribution layer 130 according to the design requirement, to change the shape of thepassive component portion 134. - The
chip package 100 further includes abarrier layer 140 and aconductive structure 150. Thebarrier layer 140 is located on theredistribution layer 130 and theisolation layer 120 that is on thesecond surface 113. Thebarrier layer 140 has anopening 142 to expose theconnection portion 132. Theconductive structure 150 is located on theconnection portion 132 that is in theopening 142 of thebarrier layer 140, such that theconductive structure 150 is electrically connected to theelectrical pad 114 through theconnection portion 132 of theredistribution layer 130. Theconductive structure 150 may be a solder ball or a conductive bump of a ball grid array (BGA). Moreover, thechip package 100 may selectively has acavity 160. Thecavity 160 is located between thebarrier layer 140 and theconnection portion 132 that is in the throughhole 115. - The manufacturing method of the
chip package 100 will be described in the following descriptions. -
FIG. 3 is a flow chart of a manufacturing method of a chip package according to an embodiment of the present invention. The manufacturing method of the chip package includes the following steps. In step S1, a temporary adhesive layer is used to attach a carrier to a wafer. The wafer has a substrate, an electrical pad and a protection layer. The substrate has a first surface and an opposite second surface. The protection layer is located on the first surface, and the electrical pad is located in the protection layer. Next, in step S2, the second surface of the substrate is etched to form a through hole in the substrate. Thereafter, in step S3, the protection layer in the through hole is etched, such that a concave hole is formed in the protection layer, and the electrical pad is exposed through the concave hole and the through hole. Next, in step S4, an isolation layer is formed on the second surface, a sidewall of the through hole, and a sidewall of the concave hole. Thereafter, in step S5, a redistribution layer is formed on the isolation layer and the electrical pad. Finally, in step S6, the redistribution layer is patterned to simultaneously form a connection portion and a passive component portion in the redistribution layer. The connection portion is located on the isolation layer and in electrical contact with the electrical pad. The passive component portion is located on the isolation layer that is on the second surface, and an end of the passive component portion is connected to the connection portion that is on the second surface. The details of the aforementioned steps will be described in the following descriptions. -
FIG. 4 is a cross-sectional view of awafer 110 a after being attached by acarrier 204 according to an embodiment of the present invention.FIG. 5 is a cross-sectional view of thesubstrate 112 shown inFIG. 4 after being ground. In the following description,wafer 110 a is referred to as a semiconductor structure that includesplural chips 110 ofFIG. 1 before a cutting process. Thewafer 110 a has thesubstrate 112, theelectrical pad 114, and theprotection layer 116. As shown inFIG. 4 andFIG. 5 ., a temporaryadhesive layer 202 is used to attach acarrier 204 onto awafer 110 a. Thecarrier 204 may be made of a material including a glass, for providing the support strength of thewafer 110 a. Next, thesecond surface 113 of thesubstrate 112 may be ground, such that the thickness of thesubstrate 112 is reduced from D1 to D2. -
FIG. 6 is a cross-sectional view of the throughhole 115 after being formed in thesubstrate 112 shown inFIG. 5 .FIG. 7 is a cross-sectional view of theconcave hole 117 after being formed in theprotection layer 116 shown inFIG. 6 . As shown inFIG. 6 andFIG. 7 , after the thickness of thesubstrate 112 is reduced, thesecond surface 113 of thesubstrate 112 may be etched, such that the throughhole 115 which aligned with theelectrical pad 114 is formed in thesubstrate 112. Next, theprotection layer 116 in the throughhole 115 is etched, such that aconcave hole 117 aligned with theelectrical pad 114 is formed in theprotection layer 116. As a result, theelectrical pad 114 is exposed through theconcave hole 117 and the throughhole 115. -
FIG. 8 is a cross-sectional view of theisolation layer 120 after being formed on thesecond surface 113, the sidewall of the throughhole 115, and the sidewall of theconcave hole 117 shown inFIG. 7 .FIG. 9 is a cross-sectional view of theredistribution layer 130 after being formed on theisolation layer 120 and theelectrical pad 114 shown inFIG. 8 As shown inFIG. 8 andFIG. 9 , after theelectrical pad 114 is exposed through theconcave hole 117 and the throughhole 115, theisolation layer 120 may be formed on thesecond surface 113 of thesubstrate 112, the sidewall of thesecond surface 113, the sidewall of the throughhole 115, and on the sidewall of theconcave hole 117. Theisolation layer 120 may be formed by a patterning process, such that at least one portion of theelectrical pad 114 is covered by theisolation layer 120. - After the
isolation layer 120 is formed, theredistribution layer 130 may be formed on theisolation layer 120 and theelectrical pad 114. Next, theredistribution layer 130 is patterned to form theconnection portion 132 and thepassive component portion 134 simultaneously. Theconnection portion 132 is located on theisolation layer 120 and in electrical contact with theelectrical pad 114. Thepassive component portion 134 is located on theisolation layer 120 that is on thesecond surface 113, and an end of thepassive component portion 134 is connected to theconnection portion 132 that is on thesecond surface 113. -
FIG. 10 is a cross-sectional view of theconductive structure 150 after being formed on theredistribution layer 130 shown inFIG. 9 . As shown inFIG. 9 andFIG. 10 , after theredistribution layer 130 is patterned to form theconnection portion 132 and thepassive component portion 134, thebarrier layer 140 may be formed on theredistribution layer 130 and theisolation layer 120 that is on thesecond surface 113. Next, thebarrier layer 140 is patterned to form anopening 142, such that theconnection portion 132 of theredistribution layer 130 is exposed through theopening 142. Then, theconductive structure 150 may be formed on theconnection portion 132 that is in theopening 142 of thebarrier layer 140, such that theconductive structure 150 is electrically connected to theelectrical pad 114 through theconnection portion 132. - After the
conductive structure 150 is formed, thecarrier 204, thewafer 110 a, theisolation layer 120 and thebarrier layer 140 may be cut along line L-L. Next, the temporaryadhesive layer 202 may be irradiated with ultraviolet light, raise the temperature, or be immersed in a chemical liquid, such that the adhesion of the temporaryadhesive layer 202 is removed. As a result, thecarrier 204 can be removed and thereby forming thechip package 100 ofFIG. 1 . - It is to be noted that the connection relationships and materials of the elements described above will not be repeated in the following description, and only aspects related to other types of chip package will be described.
-
FIG. 11A is a cross-sectional view of achip package 100 a according to another embodiment of the present invention.FIG. 11B is a schematic view of the layout of theredistribution layer 130 of thechip package 100 a shown inFIG. 11A . As shown inFIG. 11A andFIG. 11B . Thechip package 100 a includes thechip 110, theisolation layer 120 and theredistribution layer 130. Theredistribution layer 130 includes theconnection portion 132 and thepassive component portion 134. The difference between this embodiment and the embodiment shown inFIG. 1 andFIG. 2 is that herein thepassive component portion 134 is planar spiral-shaped. Thechip 110 has a conducting wire L1 located on theprotection layer 116, and the conducting wire L1 is connected to theelectrical pad 114 and another adjacentelectrical pad 114. -
FIG. 12A is a cross-sectional view of achip package 100 b according to further another embodiment of the present invention.FIG. 12B is a schematic view of the layout of theredistribution layer 130 of thechip package 100 b inFIG. 12A . As shown inFIG. 12A andFIG. 12B , thechip package 100 b includes thechip 110, theisolation layer 120, and theredistribution layer 130. Theredistribution layer 130 includes theconnection portion 132 and thepassive component portion 134. The difference between this embodiment and the embodiment shown inFIG. 1 andFIG. 2 is that herein thepassive component portion 134 is three-dimensional spiral-shaped. That is to say, thepassive component portion 134 is not at the same level. -
FIG. 12C is another embodiment ofFIG. 12B . As shown inFIG. 12A andFIG. 12C , thechip package 100 b includes thechip 110, theisolation layer 120, and theredistribution layer 130. Theredistribution layer 130 includes theconnection portion 132 and thepassive component portion 134. The difference between this embodiment and the embodiment shown inFIG. 12B is that herein thechip 110 further includes amagnetic component 170, and themagnetic component 170 is surrounded by thepassive component portion 134 of theredistribution layer 130. In this exemplary embodiment, themagnetic component 170 can increase the inductance value of thechip package 100 b. -
FIG. 13 is a cross-sectional view of achip package 100 c according to further another embodiment of the present invention. Thechip package 100 c includes thechip 110, theisolation layer 120, and theredistribution layer 130. Theredistribution layer 130 includes theconnection portion 132 and thepassive component portion 134. Thechip 110 has the firstelectrical pad 114. The difference between this embodiment and the embodiment shown inFIG. 1 is that herein thechip 110 further includes a secondelectrical pad 114 a. The secondelectrical pad 114 a is located in theprotection layer 116 and the firstelectrical pad 114 is located between the secondelectrical pad 114 a and thesubstrate 112. Moreover, theprotection layer 116 has anopening 118 to expose the secondelectrical pad 114 a. Theconductive structure 150 is located on the secondelectrical pad 114 a that is in theopening 118 of theprotection layer 116. The secondelectrical pad 114 a may be electrically connected to the firstelectrical pad 114 through a conductor that is in theprotection layer 116. -
FIG. 14 is a cross-sectional view of achip package 100 d according to further another embodiment of the present invention. Thechip package 100 d includes thechip 110, theisolation layer 120, and theredistribution layer 130. Theredistribution layer 130 includes theconnection portion 132 and thepassive component portion 134. The difference between this embodiment and the embodiment shown inFIG. 13 is that herein thechip package 100 d further includes aconductive layer 180 and abarrier layer 140 a. Theconductive layer 180 is located on asurface 119 of theprotection layer 116 facing away from thesubstrate 112 and on the secondelectrical pad 114 a that is in theopening 118 of theprotection layer 116. Thebarrier layer 140 a covers theconductive layer 180 and theprotection layer 116, and thebarrier layer 140 a has anopening 142 a to expose theconductive layer 180. Theconductive structure 150 is located on aconductive layer 180 that is in theopening 142 a of thebarrier layer 140 a, such that theconductive structure 150 is electrically connect to the secondelectrical pad 114 a through theconductive layer 180. - In the following description, a method for forming a redistribution layer that is to be patterned with a uniform thickness after the process of
FIG. 8 will be described. -
FIG. 15 is a flow chart of an operating method of a semiconductor electroplating system according to an embodiment of the present invention. After theisolation layer 120 ofFIG. 8 is formed, in step S1 a, two ends of at least one conductive device are respectively connected to two connecting points of a conducting ring. Next, in step S2 a, the wafer having the isolation layer is disposed into the conducting ring. In step S3 a, the conducting ring is immersed in a plating solution. Finally, in step S4 a, the conducting ring is energized to from the redistribution layer that is to be patterned on the isolation layer. A partial current passing through one of the connecting points transmits to the other connecting point through the conductive device. The details of the aforementioned steps will be described in the following descriptions. -
FIG. 16 is a top view of asemiconductor electroplating system 300 according to an embodiment of the present invention.FIG. 17 is a cross-sectional view of thesemiconductor electroplating system 300 taken along line 17-17 shown inFIG. 16 . As shown inFIG. 16 andFIG. 17 , thesemiconductor electroplating system 300 includes a conductingring 310 and at least oneconductive device 320. The conductingring 310 can be used to carry the semiconductor structure ofFIG. 8 . The conductingring 310 has at least two connectingpoints points conductive device 320 may be an electric wire, but the present invention is not limited in this regard. In operation, two ends 332 and 324 of theconductive device 320 may be respectively connected to the two connectingpoints ring 310, and theconductive device 320 is disposed along the edge of the conductingring 310. After thesemiconductor electroplating system 300 inFIG. 16 is assembled, thewafer 110 a having theisolation layer 120 shown inFIG. 8 may be disposed in the conductingring 310. - In this embodiment, the conducting
ring 310 has atop surface 312, asidewall 314, and a supportingsurface 316 which are sequentially connected. The connectingpoints conductive device 320 are disposed on thetop surface 312 of the conductingring 310. Thesidewall 314 surrounds anaccommodating space 311, and the supportingsurface 316 is protruded from theaccommodating space 311, such that thetop surface 312, thesidewall 314, and the supportingsurface 316 form a ladder structure. Theaccommodating space 311 can hold thewafer 110 a ofFIG. 8 , and thewafer 110 a can be disposed on the supportingsurface 316, such that thewafer 110 a is surrounded by thesidewall 314. Thefirst surface 111 of thewafer 110 a (front surface) faces the supportingsurface 316. - After the
wafer 110 a ofFIG. 8 is disposed in the conductingring 310, the conductingring 310 and thewafer 110 a that has theelectrical pad 114 therein are immersed in a plating solution and are energized, such that the circuit can flow into the conductingring 310 through theconducting wire 302. In this embodiment, the connectingpoint 318 a of the conductingring 310 can be connected to theconducting wire 302 and to anend 332 of theconductive device 320 at the same time. -
FIG. 18 is a cross-sectional view of theredistribution layer 130 that is to be patterned after being formed on theisolation layer 120 shown inFIG. 8 through thesemiconductor electroplating system 300 shown inFIG. 16 . As shown inFIG. 16 andFIG. 18 , after the conductingring 310 is energized, theredistribution layer 130 that is to be patterned can be formed on theisolation layer 120. Theconductive device 320 can transmit a partial current that passes through the connectingpoint 318 a to another connectingpoint 318 b, such that theredistribution layer 130 on the second surface 113 (back surface) has a uniform thickness. If there is noconductive device 320 disposed on the conductingring 310, while energizing, due to the impedance of the conductingring 310 itself, and the distance which the current flows to the place adjacent to the connectingpoint 318 a of the conductingring 310 is shorter than the distance which the current flows to the place adjacent to the connectingpoint 318 b of the conductingring 310, it is easy to cause theredistribution layer 130 adjacent to the connectingpoint 318 a is thicker than theredistribution layer 130 adjacent to the connectingpoint 318 b. - In this embodiment, the
conductive device 320 on the conductingring 310 has the function of dispersing the current. When thewafer 110 a ofFIG. 8 located in the conductingring 310 is immersed in the plating solution, theconductive device 320 can lead a partial current that passes through the connectingpoint 318 a of the conductingring 310 to a specific place (e.g., the connectingpoint 318 b), such that the thickness of theredistribution layer 130 formed adjacent to the connectingpoint 318 a is reduced, and the thickness of theredistribution layer 130 formed adjacent to the connectingpoint 318 b is increased. Hence, the thickness uniformity of theredistribution layer 130 that is to be patterned can be improved. As a result, the standard deviation of each place of theredistribution layer 130 on the second surface 113 (back surface) of thewafer 110 a can be reduced to 0.2 μm to 0.4 μm. The designer can change the positions of theconductive device 320 and of the connectingpoints top surface 312 of the conductingring 310, and the number of theconductive device 320 and of the connectingpoints - After the
redistribution layer 130 is patterned, thepassive component portion 134 ofFIG. 9 would have a similar thickness, thereby ensuring the function of itself as an integrated passive device (IPD). - It is to be noted that the connection relationships and materials of the elements described above will not be repeated in the following description, and only aspects related to other types of semiconductor electroplating system and operating method will be described.
-
FIG. 19 is a top view of asemiconductor electroplating system 300 a according to an embodiment of the present invention. Thesemiconductor electroplating system 300 a includes the conductingring 310 andconductive devices FIG. 16 is that herein thesemiconductor electroplating system 300 a has twoconductive devices connecting points point 318 c is connected to theconducting wire 302 which provides the current. Two ends 322 a and 324 a of theconductive device 320 a are respectively connected to the two connectingpoints ring 310, and twoends conductive device 320 b are respectively connected to the two connectingpoints ring 310. - In this embodiment, when the
wafer 110 a inFIG. 8 located in the conductingring 310 is immersed in the plating solution, theconductive device 320 a can lead a partial current that passes through the connectingpoint 318 d of the conductingring 310 to the connectingpoint 318 e, and theconductive device 320 b can lead a partial current that passes through the connectingpoint 318 f of the conductingring 310 to the connectingpoint 318 g, thereby reducing the thickness of theredistribution layer 130 formed adjacent to the connectingpoints redistribution layer 130 formed adjacent to the connectingpoint redistribution layer 130 that is to be patterned is improved. -
FIG. 20 is a flow chart of an operating method of a semiconductor electroplating system according to an embodiment of the present invention After theisolation layer 120 ofFIG. 8 is formed, in step S1 b, two connecting points of two ends of at least one conductive piece are movably connected to a ring-shaped track of a conducting ring. The conductive piece overlaps a portion of the conducting ring. Next, in step S2 b, the wafer having the isolation layer is disposed in the conducting ring. In step S3 b, the conducting ring is immersed in a plating solution. Finally, in step S4 b, the conducting ring is energized to form the redistribution layer that is to be patterned on the isolation layer. A partial current passing through one of the connecting points transmits to the other connecting point through the conductive piece. The details of the aforementioned steps will be disclosed in the following descriptions. -
FIG. 21 is a top view of asemiconductor electroplating system 300 b according to an embodiment of the present invention. Thesemiconductor electroplating system 300 b includes a conductingring 310 a and at least oneconductive piece 330. The conductingring 310 a can be used to carry semiconductor structure ofFIG. 8 . The conductingring 310 a has a ring-shapedtrack 313. Each of the two ends 332 and 334 of theconductive piece 330 has a connecting point that is movably connected to the ring-shapedtrack 313 of the conductingring 310 a. For instance, the connecting points of the two ends 332 and 334 of theconductive piece 330 may be protrusions, and the ring-shapedtrack 313 may be a slot that can be coupled to the protrusions, or, the connecting points of the two ends 332 and 334 of theconductive piece 330 may be metal wheels, and the ring-shapedtrack 313 may be a slot that can be coupled to the wheels. After theconductive piece 330 is connected to the ring-shapedtrack 313 of the conductingring 310 a, theconductive piece 330 overlaps a portion of the conductingring 310 a, and theconductive piece 330 can be stressed to move on and along the ring-shapedtrack 313 in a clockwise direction D3 or a counterclockwise direction D4. After thesemiconductor electroplating system 300 b ofFIG. 21 is assembled, thewafer 110 a having theisolation layer 120 shown inFIG. 8 can be disposed in the conductingring 310 a. - In this embodiment, the conducting
ring 310 a has thetop surface 312, thesidewall 314, and the supportingsurface 316 which are sequentially connected. Theconductive piece 330 and the ring-shapedtrack 313 are both disposed on thetop surface 312 of the conductingring 310 a. Thesidewall 314 surrounds theaccommodating space 311, and the supportingsurface 316 is protruding from theaccommodating space 311, such that thetop surface 312, thesidewall 314, and the supportingsurface 316 form a ladder structure. Theaccommodating space 311 can hold thewafer 110 a ofFIG. 8 , and thewafer 110 a can be disposed on the supportingsurface 316, such that thewafer 110 a is surrounded by thesidewall 314. Thefirst surface 111 of thewafer 110 a (front surface) faces the supportingsurface 316. - After the
wafer 110 a ofFIG. 8 is disposed in the conductingring 310 a, the conductingring 310 a and thewafer 110 a that has theisolation layer 120 may be immersed in a plating solution and energized, the circuit can flow into the conductingring 310 a through theconducting wire 302. - As shown in
FIG. 21 andFIG. 18 . After theconducting ring 310 a is energized, theredistribution layer 130 that is to be patterned can be formed on theisolation layer 120. Theconductive piece 330 can transmit a partial current that passes through the connecting point of theend 332 to the connecting point of theother end 334, such that theredistribution layer 130 on the second surface 113 (back surface) has a uniform thickness. In this embodiment, theconductive piece 330 located on the conductingring 310 a has the function of dispersing the current. When thewafer 110 a ofFIG. 8 located in the conductingring 310 a is immersed in the plating solution, theconductive piece 330 can lead a partial current that passes through the connecting point of oneend 332 in contact with the conductingring 310 a to a specific place (such as the connecting point of the other end 334), thereby reducing the thickness of theredistribution layer 130 formed adjacent to theend 332 of theconductive piece 330 and increasing the thickness of theredistribution layer 130 formed adjacent to theend 334 of theconductive piece 330. As a result, the thickness uniformity of theredistribution layer 130 that is to be patterned can be improved. - The designer may slide the
conductive piece 330 on the ring-shapedtrack 313 of thetop surface 312 of the conductingring 310 a according to the design requirements, such that the positions of the two ends 332 and 334 of theconductive piece 330 on thetop surface 312 are adjusted. - Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.
Claims (11)
1. A semiconductor electroplating system, comprising:
a conducting ring for carrying a wafer, and having at least two connecting points, wherein the wafer has a first surface and an opposite second surface, and an isolation layer is located on the second surface; and
at least one conductive device having two ends that are respectively connected to the connecting points of the conducting ring, wherein when the conducting ring is immersed in a plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer, wherein the conductive device is used for transmitting a partial current passing through one of the connecting points to the other connecting point.
2. The semiconductor electroplating system of claim 1 , wherein the conducting ring has a top surface, a sidewall, and a supporting surface which are sequentially connected, and the sidewall surrounds an accommodating space, and the supporting surface protrudes from the accommodating space, such that the top surface, the sidewall and the supporting surface form a ladder structure.
3. The semiconductor electroplating system of claim 2 , wherein the wafer is located on the supporting surface, and is surrounded by the sidewall.
4. The semiconductor electroplating system of claim 2 , wherein the first surface of the wafer faces the supporting surface.
5. The semiconductor electroplating system of claim 2 , wherein the connecting points and the conductive device are located on the top surface of the conducting ring.
6. The semiconductor electroplating system of claim 1 , wherein the conductive device is an electric wire.
7. A semiconductor electroplating system, comprising:
a conducting ring for carrying a wafer, and having a ring-shaped track, wherein the wafer has a first surface and an opposite second surface, and an isolation layer is located on the second surface; and
at least one conductive piece having two ends, wherein each of the ends has a connecting point which is movably connected to the ring-shaped track of the conducting ring, and the conductive piece overlaps a portion of the conducting ring; when the conducting ring is immersed in a plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer, wherein the conductive piece is used for transmitting a partial current passing through one of the connecting points to the other connecting point.
8. The semiconductor electroplating system of claim 7 , wherein the conducting ring has a top surface, a sidewall, and a supporting surface which are sequentially connected, and the sidewall surrounds an accommodating space, and the supporting surface protrudes from the accommodating space, such that the top surface, the sidewall and the supporting surface form a ladder structure.
9. The semiconductor electroplating system of claim 8 , wherein the wafer is located on the supporting surface, and is surrounded by the sidewall.
10. The semiconductor electroplating system of claim 8 , wherein the first surface of the wafer faces the supporting surface.
11. The semiconductor electroplating system of claim 8 , wherein the ring-shaped track is located on the top surface of the conducting ring, and the two ends of the conductive piece are movably disposed on the ring-shaped track.
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US10833040B2 (en) | 2017-12-19 | 2020-11-10 | Samsung Electronics Co., Ltd. | Semiconductor package |
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CN108074823A (en) * | 2016-11-14 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic device |
CN111009506B (en) * | 2018-10-08 | 2021-08-03 | 精材科技股份有限公司 | Chip package |
CN113539946B (en) * | 2020-04-16 | 2023-07-07 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
CN116130454A (en) * | 2021-11-12 | 2023-05-16 | 深南电路股份有限公司 | Circuit board preparation method and circuit board |
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CN201459271U (en) * | 2009-05-19 | 2010-05-12 | 上海新阳半导体材料股份有限公司 | Clamp for electroplating wafer |
US8692382B2 (en) * | 2010-03-11 | 2014-04-08 | Yu-Lin Yen | Chip package |
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US8779452B2 (en) * | 2010-09-02 | 2014-07-15 | Tzu-Hsiang HUNG | Chip package |
US8742564B2 (en) * | 2011-01-17 | 2014-06-03 | Bai-Yao Lou | Chip package and method for forming the same |
US8901701B2 (en) * | 2011-02-10 | 2014-12-02 | Chia-Sheng Lin | Chip package and fabrication method thereof |
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US8680647B2 (en) * | 2011-12-29 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with passive devices and methods of forming the same |
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CN104218036B (en) * | 2013-06-04 | 2017-05-03 | 华邦电子股份有限公司 | Semiconductor device and manufacture method thereof |
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- 2015-09-09 CN CN201510570170.8A patent/CN106098662B/en active Active
- 2015-09-09 CN CN201910017276.3A patent/CN109742064B/en active Active
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US20150122635A1 (en) * | 1999-05-18 | 2015-05-07 | Ebara Corporation | Semiconductor wafer holder and electroplating system for plating a semiconductor wafer |
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US10833040B2 (en) | 2017-12-19 | 2020-11-10 | Samsung Electronics Co., Ltd. | Semiconductor package |
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CN106098662B (en) | 2019-02-19 |
CN109742064A (en) | 2019-05-10 |
CN106098662A (en) | 2016-11-09 |
CN109742064B (en) | 2021-06-11 |
US20160315043A1 (en) | 2016-10-27 |
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