US20160300940A1 - Monolithic integrated circuit (mmic) structure having composite etch stop layer and method for forming such structure - Google Patents
Monolithic integrated circuit (mmic) structure having composite etch stop layer and method for forming such structure Download PDFInfo
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- US20160300940A1 US20160300940A1 US14/683,812 US201514683812A US2016300940A1 US 20160300940 A1 US20160300940 A1 US 20160300940A1 US 201514683812 A US201514683812 A US 201514683812A US 2016300940 A1 US2016300940 A1 US 2016300940A1
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- etch stop
- stop layer
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- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6672—High-frequency adaptations for passive devices for integrated passive components, e.g. semiconductor device with passive components only
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6683—High-frequency adaptations for monolithic microwave integrated circuit [MMIC]
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
Definitions
- This disclosure relates generally to a Monolithic Integrated Circuit (MMIC) Structure and to a method for selectively etching a dielectric layer using an underling etch stop layer to protect an underling active device passivation layer.
- MMIC Monolithic Integrated Circuit
- MMICs monolithic microwave integrated circuits
- PECVD plasma enhanced chemical vapor deposition
- the etch stop layer is formed as a composite structure, comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer.
- the etch stop layer described in the above referenced U.S. Patent Application Publication 2014/0284661 was subject to attack from other commonly used process chemicals in standard MMIC fabrication such as ammonia and photoresist developer.
- a buffer such as, for example, a silicon dioxide interlayer
- the residual etch stop material can be removed by timed exposure to ammonia since ammonia acts as a highly selective etchant to Atomic Layer Deposition (ALD) deposited aluminum oxide to PECVD nitride. This removal mitigates impact to RF performance of any residual dielectric associated with the etch-stop layer.
- ALD Atomic Layer Deposition
- the first etch stop layer is aluminum oxide.
- the buffer layer is silicon dioxide
- the second etch stop layer is aluminum oxide.
- the transistor device is a field effect transistor.
- the semiconductor layer is a semiconductor material.
- the passivation layer is silicon nitride.
- the dielectric layer is silicon nitride.
- the dielectric layer is Plasma Enhanced Chemical Vapor Deposited (PECVD) silicon nitride
- the first etch stop layer is an atomic layer deposited (ALD) layer.
- ALD atomic layer deposited
- the second etch stop layer is an atomic layer deposited (ALD) layer.
- FIGS. 1A-1N are simplified, cross sectional diagrams of an MMIC at various steps in the fabrication thereof in accordance with the disclosure.
- FIG. 1C ′ is an exploded view of a portion of an etch stop layer structure according to the disclosure used in the MMIC fabricated in accordance with FIGS. 1A-1N ;
- FIGS. 2A and 2B are simplified, cross sectional diagrams of an MMIC at various steps in the fabrication thereof in accordance with an alternate embodiment of the disclosure.
- a semiconductor structure 10 is shown having a substrate 11 , here for example silicon carbide with a GaN semiconductor layer 13 thereon and a additional semiconductor layer 12 on semiconductor layer 13 , layer 12 is here for example, a III-V semiconductor layer such as for example, here AlGaN. It should be understood that other semiconductors such GaAs, InP, for example, may be used on the suitable substrate.
- the semiconductor layer 12 has a transistor device, 14 , here for example a field effect transistor (FET) device formed therein using any conventional processing to provide source and drain electrodes 16 , 18 , respectively as shown, in ohmic contact with the semiconductor layer 12 and a T-shaped gate electrode 20 in Schottky contact with the semiconductor layer 12 and a passivation layer 22 , here disposed over the source and drain electrodes 16 and 18 , and a portion of the semiconductor 12 as shown.
- the passivation layer 22 is silicon nitride.
- the gate electrode 20 controls the flow of carriers in the semiconductors layers 12 , 13 between the source and drain electrodes. It is noted that the silicon nitride layer 22 is spaced from the bottom portion of the vertical sides of the T-shaped gate 20 .
- an additional layer 24 of silicon nitride is uniformly deposited over the entire structure shown in FIG. 1A , including the space in the layer 22 so that the additional layer abuts the bottom portion of the vertical sides of the T-shaped gate 20 .
- the layer 24 is a 200 Angstrom thick layer of PECVD silicon nitride to provide gate 20 passivation.
- an etch stop layer structure 26 is uniformly disposed by Atomic Layer Deposition (ALD) on the passivation layer 24 .
- the etch stop layer structure 26 is a composite layer having: a first etch stop layer 26 a of here for example, aluminum oxide, on the passivation layer 24 , a buffer layer 26 b of here for example silicon dioxide on the first etch stop layer 26 a, and a second etch stop layer 26 c of here for example aluminum oxide on the buffer layer 26 b, as shown in FIG. 1C ′.
- the first and second etch stop layers 26 a and 26 c are here for example, each 25 Angstrom thin layer of Atomic Layer Deposited (ALD) layer of aluminum oxide and layer 26 b is here for example, silicon dioxide having a thickness of, for example 10 Angstroms to 50 Angstroms.
- ALD Atomic Layer Deposited
- first level active device metallization processing begins by first forming a layer 27 of photoresist patterned as shown to have formed there-through windows 28 to expose portions of the etch-stop layer structure 26 and passivation layers 22 and 24 over the source and drain electrodes 16 , 18 while covering the other portions of the etch-stop layer 26 including the portion of the etch-stop layer 26 over the gate electrode 20 , as shown.
- the gate electrode 20 terminates in a conductive gate pad, not shown, (out of the plane shown in FIG. 1D ) and this conductive gate pad is also exposed by the windows 28 in the photoresist layer 27 .
- the structure with the windowed photoresist layer 27 is subjected to a dry, for example, plasma, or wet etch, to remove, in a first step, portions of the etch-stop layer 26 exposed by the windows 28 and then, in a second step, as shown in FIG. 1E , remove the portions of the underlying silicon nitride passivation layers 24 and 22 thereby exposing the source and drain electrodes 16 and 18 as well as the not shown, out of plane gate contact pad.
- the photoresist layer 27 ( FIG. 1D ) is then stripped using any conventional removal technique, thereby leaving the structure shown in FIG. 1E .
- a photoresist layer 30 is deposited and lithographically processed to have windows 32 formed therein to expose regions where a first level (level 1) metallization is to be formed.
- This level 1 metallization will be used to form interconnects for the source and drain electrodes 16 , 18 , the gate contact pad (not shown and referred to above) as well as bottom electrodes for capacitors, to be described, and microwave transmission lines and coplanar ground plane structures of the MMIC to be formed.
- metal 34 here for example, a stack of titanium/platinum/gold is deposited on the photoresist layer 30 ( FIG. 1F ) and through the windows 32 therein onto the aforementioned exposed source and drain electrodes 16 , 18 , on the aforementioned gate contact pad (not shown) as well as other portions here for example a portion 36 of the etch stop layer 26 where a capacitor is to be formed.
- the photoresist layer 30 ( FIG. 1F ) is then stripped from the surface along with any metal 34 on top of layer 30 using any conventional removal technique, here including an ammonia wash, thereby resulting in the metal 34 thereon being lifted off the structure resulting in the structure shown in FIG. 1G .
- a solvent pre-clean process is used to prepare the wafer surface for the PECVD silicon nitride layer 40 .
- Such pre-cleans use chemical agents such as trichloroethylene, acetone, isopropanol, methanol, ammonia, etc.
- the top-most aluminum oxide 26 c is attacked and is therefore compromised in its ability to act as a good etch stop layer in subsequent processing.
- the silicon dioxide layer 26 b acts to protect the bottommost aluminum oxide layer 26 c, allowing for good gate and gate channel protection during the etch to be described in connection with FIG. 1J . It is also noted that the portions of the second etch stop layer 26 c under the metal layer section 34 a of metal layer 34 where the bottom plate of a capacitor is to be formed in a manner to be described, remains as it is protected by the metal layer section 34 a.
- a photoresist layer 42 is deposited and photolithographically processed to have a window 44 formed therein, as shown in FIG. 1J , with the photoresist layer 42 remaining over the portions of metal 34 being used, as mentioned above, to provide a bottom plate 34 a for a capacitor to be formed.
- the structure is exposed to a dry etch, such as for example, a plasma etch such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP), using sulfur hexafluoride based plasma etchants, or a wet etch.
- RIE reactive ion etching
- ICP inductively coupled plasma etching
- the etch process etches away the exposed portions of the silicon nitride layer 40 at a rate significantly greater than that to the underlying portions of the aluminum oxide layer 26 a, here for example 100 times greater; thus the aluminum oxide layer 26 a is considered an etch stop layer since the etching stops at the aluminum oxide layer 26 a, as indicated in FIG. 1K after removal of the photoresist layer 42 .
- the same etch step that removes the exposed portions of the thick silicon nitride layer 40 also removes underlying portions of the silicon dioxide layer 26 b but the process still leaves the aluminum oxide layer 26 a, as shown in FIG. 1K .
- the metal 34 disposed on the source and drain electrodes 16 , 18 as well as the metal 34 disposed on the out of plane gate conductor pad (not shown) referred to above exposed by the window also acts as an etch stop).
- the second level (level 2) metallization process begins by depositing a photoresist layer 50 and pattering the photoresist layer 50 lithographically to have windows 52 formed there-through, as shown in FIG. 1L .
- the windows 52 expose the metal 34 used for the source and drain electrode 16 , 18 , the gate conductor pad (not shown and described above) and the portion of the silicon nitride dielectric layer 40 over the bottom metal plate 34 a to be used as the dielectric for the capacitor being formed.
- metal 56 here, for example, a stack of titanium/platinum/gold is deposited on the remaining portions of the photoresist layer 50 and on the metal 34 used on the source and drain electrodes 16 , 18 , the gate conductor pad (not shown and described above) and the portion of the silicon nitride dielectric layer 40 to be used for the capacitor being formed.
- the photoresist layer 50 FIG. 1
- any conventional removal technique here including an ammonia wash with the portions of the metal 56 thereon being lifted off the structure while the remaining portions of the metal 56 remain on the first-level metal 34 disposed on source and drain electrode metal 16 , 18 , the gate conductor pad (not shown and described above) and the portion of the silicon nitride dielectric disposed on first-level metal 34 , thereby completing the formation of the capacitor 60 , the upper plate being designated 56 a of the MMIC 62 ( FIG. 1M ).
- the aluminum oxide layer 26 a is removed from regions unprotected by metal 34 or silicon nitride layer 40 , as shown in FIG. 1N , using dilute ammonia. This eliminates the presence of the etch stop layer in the active regions of the MMIC, specifically in the entire region between source and drain contacts, with includes the surface above the transistor channel regions and around the entire gate electrode.
- the process described above may be modified so that the composite etch stop layer, shown in FIG. 1C ′, may be formed after the structure shown in FIG. 1G is formed rather than after the structure shown in FIG. 1B is formed.
- the modified process would result in the structure shown in FIG. 2A .
- the process described above in connection with FIG. 1N would therefore result in the structure shown in FIG. 2B .
Abstract
Description
- This disclosure relates generally to a Monolithic Integrated Circuit (MMIC) Structure and to a method for selectively etching a dielectric layer using an underling etch stop layer to protect an underling active device passivation layer.
- As is known in the art, as monolithic microwave integrated circuits (MMICs) are designed to operate at ever higher frequencies, the effects of dielectric loading on various MMIC conduction paths (including gates and transmission lines) becomes more pronounced. The minimization of such loading is critical to achieving the desired gain performance.
- As is also known in the art, plasma enhanced chemical vapor deposition (PECVD) is widely used for the deposition of silicon nitride, which may act as a passivation layer to passivate components, or act as a capacitor dielectric. This deposition technique however, coats regions of the MMIC where the presence of additional dielectric is not desired and adversely impacts device performance at the higher frequencies.
- As described in co-pending patent application, Ser. No. 13/849,858, filed Mar. 25, 2013, published in U.S. Patent Application Publication 2014/0284661, published Sep. 25, 2014, assigned to the same assignee as the present patent application, a method was disclosed for forming a semiconductor structure, the entire subject matter thereof being incorporated herein by reference. The method included: providing a semiconductor layer with a transistor device having a control electrode for controlling a flow of carriers between a first electrode and a second electrode; depositing a passivation layer over the first electrode, the second electrode and the control electrode; depositing an etch stop layer on the passivation layer, such etch stop layer being disposed over the control electrode; forming a dielectric layer over the etch stop layer; and etching a window through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode.
- In forming such structure it was discovered that chemicals used in the photolithographic processing effected the etch stop layer.
- In accordance with this disclosure, the etch stop layer is formed as a composite structure, comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. With such an arrangement, chemicals used in the photolithographic processing while effecting the second etch stop layer are prevented from effecting the first etch stop layer by the buffer layer.
- More particularly, it was found that the etch stop layer described in the above referenced U.S. Patent Application Publication 2014/0284661 was subject to attack from other commonly used process chemicals in standard MMIC fabrication such as ammonia and photoresist developer. Employing a buffer, such as, for example, a silicon dioxide interlayer, effectively creates a double-selective etch-stop layer that survives typical MMIC fabrication processing up to the point where etch-back is required. Post etch-back, it has been found that the residual etch stop material can be removed by timed exposure to ammonia since ammonia acts as a highly selective etchant to Atomic Layer Deposition (ALD) deposited aluminum oxide to PECVD nitride. This removal mitigates impact to RF performance of any residual dielectric associated with the etch-stop layer.
- In one embodiment, the first etch stop layer is aluminum oxide.
- In one embodiment the buffer layer is silicon dioxide;
- In one embodiment, the second etch stop layer is aluminum oxide.
- In one embodiment, the transistor device is a field effect transistor.
- In one embodiment, the semiconductor layer is a semiconductor material.
- In one embodiment, the passivation layer is silicon nitride.
- In one embodiment, the dielectric layer is silicon nitride.
- In one embodiment, the dielectric layer is Plasma Enhanced Chemical Vapor Deposited (PECVD) silicon nitride
- In one embodiment, the first etch stop layer is an atomic layer deposited (ALD) layer.
- In one embodiment, the second etch stop layer is an atomic layer deposited (ALD) layer.
- The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
-
FIGS. 1A-1N are simplified, cross sectional diagrams of an MMIC at various steps in the fabrication thereof in accordance with the disclosure. -
FIG. 1C ′ is an exploded view of a portion of an etch stop layer structure according to the disclosure used in the MMIC fabricated in accordance withFIGS. 1A-1N ; and -
FIGS. 2A and 2B are simplified, cross sectional diagrams of an MMIC at various steps in the fabrication thereof in accordance with an alternate embodiment of the disclosure. - Like reference symbols in the various drawings indicate like elements.
- Referring now to
FIG. 1A , asemiconductor structure 10 is shown having asubstrate 11, here for example silicon carbide with aGaN semiconductor layer 13 thereon and aadditional semiconductor layer 12 onsemiconductor layer 13,layer 12 is here for example, a III-V semiconductor layer such as for example, here AlGaN. It should be understood that other semiconductors such GaAs, InP, for example, may be used on the suitable substrate. Thesemiconductor layer 12 has a transistor device, 14, here for example a field effect transistor (FET) device formed therein using any conventional processing to provide source anddrain electrodes semiconductor layer 12 and a T-shaped gate electrode 20 in Schottky contact with thesemiconductor layer 12 and apassivation layer 22, here disposed over the source anddrain electrodes semiconductor 12 as shown. Here for example thepassivation layer 22 is silicon nitride. Thegate electrode 20 controls the flow of carriers in thesemiconductors layers silicon nitride layer 22 is spaced from the bottom portion of the vertical sides of the T-shaped gate 20. - Next, referring to
FIG. 1B , anadditional layer 24 of silicon nitride is uniformly deposited over the entire structure shown inFIG. 1A , including the space in thelayer 22 so that the additional layer abuts the bottom portion of the vertical sides of the T-shaped gate 20. Here, for example, thelayer 24 is a 200 Angstrom thick layer of PECVD silicon nitride to providegate 20 passivation. - Next, referring to
FIG. 1C , an etchstop layer structure 26 is uniformly disposed by Atomic Layer Deposition (ALD) on thepassivation layer 24. Here, the etchstop layer structure 26 is a composite layer having: a firstetch stop layer 26 a of here for example, aluminum oxide, on thepassivation layer 24, abuffer layer 26 b of here for example silicon dioxide on the firstetch stop layer 26 a, and a secondetch stop layer 26 c of here for example aluminum oxide on thebuffer layer 26 b, as shown inFIG. 1C ′. With such an arrangement, chemicals used in the photolithographic processing, to be described, while effecting the secondetch stop layer 26 c are prevented from effecting the firstetch stop layer 26 a by thebuffer layer 26 b. Here, the first and secondetch stop layers layer 26 b is here for example, silicon dioxide having a thickness of, for example 10 Angstroms to 50 Angstroms. - Next, referring to
FIG. 1D , first level active device metallization processing begins by first forming alayer 27 of photoresist patterned as shown to have formed there-throughwindows 28 to expose portions of the etch-stop layer structure 26 andpassivation layers drain electrodes stop layer 26 including the portion of the etch-stop layer 26 over thegate electrode 20, as shown. It is noted that thegate electrode 20 terminates in a conductive gate pad, not shown, (out of the plane shown inFIG. 1D ) and this conductive gate pad is also exposed by thewindows 28 in thephotoresist layer 27. The structure with the windowedphotoresist layer 27, as shown, is subjected to a dry, for example, plasma, or wet etch, to remove, in a first step, portions of the etch-stop layer 26 exposed by thewindows 28 and then, in a second step, as shown inFIG. 1E , remove the portions of the underlying siliconnitride passivation layers drain electrodes FIG. 1D ) is then stripped using any conventional removal technique, thereby leaving the structure shown inFIG. 1E . - Next, referring to
FIG. 1F , aphotoresist layer 30 is deposited and lithographically processed to havewindows 32 formed therein to expose regions where a first level (level 1) metallization is to be formed. Thislevel 1 metallization will be used to form interconnects for the source and drainelectrodes - Referring now also to
FIG. 1G ,metal 34, here for example, a stack of titanium/platinum/gold is deposited on the photoresist layer 30 (FIG. 1F ) and through thewindows 32 therein onto the aforementioned exposed source and drainelectrodes portion 36 of theetch stop layer 26 where a capacitor is to be formed. The photoresist layer 30 (FIG. 1F ) is then stripped from the surface along with anymetal 34 on top oflayer 30 using any conventional removal technique, here including an ammonia wash, thereby resulting in themetal 34 thereon being lifted off the structure resulting in the structure shown inFIG. 1G . - Next, exposed portions of the second
etch stop layer 26 c of ALD aluminum oxide layer are removed to clean the top surface of the wafer prior to depositing a PECVD silicon nitride layer 40 (FIG. 11 ). More particularly, prior to depositing the PECVDsilicon nitride layer 40, a solvent pre-clean process is used to prepare the wafer surface for the PECVDsilicon nitride layer 40. Such pre-cleans use chemical agents such as trichloroethylene, acetone, isopropanol, methanol, ammonia, etc. During the pre-clean procedure, thetop-most aluminum oxide 26 c is attacked and is therefore compromised in its ability to act as a good etch stop layer in subsequent processing. However, thesilicon dioxide layer 26 b acts to protect the bottommostaluminum oxide layer 26 c, allowing for good gate and gate channel protection during the etch to be described in connection withFIG. 1J . It is also noted that the portions of the secondetch stop layer 26 c under themetal layer section 34 a ofmetal layer 34 where the bottom plate of a capacitor is to be formed in a manner to be described, remains as it is protected by themetal layer section 34 a. - Next, a
photoresist layer 42 is deposited and photolithographically processed to have a window 44 formed therein, as shown inFIG. 1J , with thephotoresist layer 42 remaining over the portions ofmetal 34 being used, as mentioned above, to provide abottom plate 34 a for a capacitor to be formed. The structure is exposed to a dry etch, such as for example, a plasma etch such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP), using sulfur hexafluoride based plasma etchants, or a wet etch. It is noted that the etch process etches away the exposed portions of thesilicon nitride layer 40 at a rate significantly greater than that to the underlying portions of thealuminum oxide layer 26 a, here for example 100 times greater; thus thealuminum oxide layer 26 a is considered an etch stop layer since the etching stops at thealuminum oxide layer 26 a, as indicated inFIG. 1K after removal of thephotoresist layer 42. It is noted that the same etch step that removes the exposed portions of the thicksilicon nitride layer 40 also removes underlying portions of thesilicon dioxide layer 26 b but the process still leaves thealuminum oxide layer 26 a, as shown inFIG. 1K . (It is noted that themetal 34 disposed on the source and drainelectrodes metal 34 disposed on the out of plane gate conductor pad (not shown) referred to above exposed by the window also acts as an etch stop). - Next, the second level (level 2) metallization process begins by depositing a
photoresist layer 50 and pattering thephotoresist layer 50 lithographically to havewindows 52 formed there-through, as shown inFIG. 1L . Thewindows 52 expose themetal 34 used for the source and drainelectrode nitride dielectric layer 40 over thebottom metal plate 34 a to be used as the dielectric for the capacitor being formed.Next metal 56, here, for example, a stack of titanium/platinum/gold is deposited on the remaining portions of thephotoresist layer 50 and on themetal 34 used on the source and drainelectrodes nitride dielectric layer 40 to be used for the capacitor being formed. Next, the photoresist layer 50 (FIG. 1L ) is stripped using any conventional removal technique, here including an ammonia wash with the portions of themetal 56 thereon being lifted off the structure while the remaining portions of themetal 56 remain on the first-level metal 34 disposed on source and drainelectrode metal level metal 34, thereby completing the formation of thecapacitor 60, the upper plate being designated 56 a of the MMIC 62 (FIG. 1M ). - Next, the
aluminum oxide layer 26 a is removed from regions unprotected bymetal 34 orsilicon nitride layer 40, as shown inFIG. 1N , using dilute ammonia. This eliminates the presence of the etch stop layer in the active regions of the MMIC, specifically in the entire region between source and drain contacts, with includes the surface above the transistor channel regions and around the entire gate electrode. - It should be noted that the process described above may be modified so that the composite etch stop layer, shown in
FIG. 1C ′, may be formed after the structure shown inFIG. 1G is formed rather than after the structure shown inFIG. 1B is formed. In such case, structure after performing the process described above in connection withFIGS. 1H-1M , the modified process would result in the structure shown inFIG. 2A . The process described above in connection withFIG. 1N would therefore result in the structure shown inFIG. 2B . - A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, the method may be used with bipolar transistors. Accordingly, other embodiments are within the scope of the following claims.
Claims (19)
Priority Applications (3)
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US14/683,812 US9478652B1 (en) | 2015-04-10 | 2015-04-10 | Monolithic integrated circuit (MMIC) structure having composite etch stop layer and method for forming such structure |
PCT/US2016/026563 WO2016164666A1 (en) | 2015-04-10 | 2016-04-08 | Monolithic integrated circuit (mmic) structure having composite etch stop layer and method for forming such structure |
EP16717767.4A EP3281229B1 (en) | 2015-04-10 | 2016-04-08 | Monolithic integrated circuit (mmic) structure having composite etch stop layer and method for forming such structure |
Applications Claiming Priority (1)
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US14/683,812 US9478652B1 (en) | 2015-04-10 | 2015-04-10 | Monolithic integrated circuit (MMIC) structure having composite etch stop layer and method for forming such structure |
Publications (2)
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US20160300940A1 true US20160300940A1 (en) | 2016-10-13 |
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US20170104033A1 (en) * | 2015-10-13 | 2017-04-13 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method for the same |
JP2018073974A (en) * | 2016-10-28 | 2018-05-10 | 三菱電機株式会社 | Semiconductor device and method of manufacturing the same |
CN115440592A (en) * | 2022-09-01 | 2022-12-06 | 湖北九峰山实验室 | High electron mobility transistor and manufacturing method thereof |
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US10707089B2 (en) | 2018-03-27 | 2020-07-07 | Texas Instruments Incorporated | Dry etch process landing on metal oxide etch stop layer over metal layer and structure formed thereby |
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JP3375928B2 (en) | 2000-02-08 | 2003-02-10 | 富士通カンタムデバイス株式会社 | Semiconductor device |
JP5320689B2 (en) | 2007-05-10 | 2013-10-23 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
US9024324B2 (en) | 2012-09-05 | 2015-05-05 | Freescale Semiconductor, Inc. | GaN dual field plate device with single field plate metal |
US9082722B2 (en) | 2013-03-25 | 2015-07-14 | Raytheon Company | Monolithic integrated circuit (MMIC) structure and method for forming such structure |
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Cited By (3)
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US20170104033A1 (en) * | 2015-10-13 | 2017-04-13 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method for the same |
JP2018073974A (en) * | 2016-10-28 | 2018-05-10 | 三菱電機株式会社 | Semiconductor device and method of manufacturing the same |
CN115440592A (en) * | 2022-09-01 | 2022-12-06 | 湖北九峰山实验室 | High electron mobility transistor and manufacturing method thereof |
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US9478652B1 (en) | 2016-10-25 |
WO2016164666A1 (en) | 2016-10-13 |
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