US20160299848A1 - Deferred metadata initialization - Google Patents
Deferred metadata initialization Download PDFInfo
- Publication number
- US20160299848A1 US20160299848A1 US14/682,619 US201514682619A US2016299848A1 US 20160299848 A1 US20160299848 A1 US 20160299848A1 US 201514682619 A US201514682619 A US 201514682619A US 2016299848 A1 US2016299848 A1 US 2016299848A1
- Authority
- US
- United States
- Prior art keywords
- rgn
- metadata
- volume
- metadata track
- track
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1021—Hit rate improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/31—Providing disk cache in a specific location of a storage system
- G06F2212/313—In storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/608—Details relating to cache mapping
Definitions
- the present invention relates in general computing systems, and more particularly to, systems and methods for increased data management efficiency in computing storage environments.
- Computer systems In today's society, computer systems are commonplace. Computer systems may be found in the workplace, at home, or at school. Computer systems may include data storage systems, or disk storage systems, to process and store data. Contemporary computer storage systems are known to destage, and subsequently, demote storage tracks from cache to long-term storage devices so that there is sufficient room in the cache for data to be written.
- a Release Generation Number is associated with a volume, and an RGN is associated with a metadata track.
- RGN Release Generation Number
- the RGN associated with the volume is incremented.
- the RGN associated with the metadata track is updated to be consistent in generation with the RGN associated with the volume.
- the RGN of the metadata track is compared against the RGN of the volume, and the metadata track is initialized if a match is not found.
- FIG. 1 is an exemplary block diagram showing a hardware structure in which aspects of the present invention may be realized
- FIG. 2 is an exemplary block diagram showing a hardware structure of a data storage system in a computing environment, again in which aspects of the present invention may be realized;
- FIG. 3 is a flow chart diagram illustrating an exemplary method for deferred metadata initialization in a computing storage environment, again in which aspects of the present invention may be realized.
- FIG. 4 is a flow chart diagram of an additional exemplary method for deferred metadata initialization in a computing storage environment according to the present invention.
- a storage controller retains metadata to describe the location and properties of data, such as the data's format.
- This metadata may be cached, along with the data itself, in order for faster performance of the storage controller.
- One metadata track may include information for many individual data tracks. For example, metadata describing Count Key Data (CKD) information may include on average, information pertaining to a thousand data tracks.
- CKD Counter Key Data
- Initialization of this metadata currently may take a lengthy amount of time, as each metadata track needs to be written to storage. If the metadata is initialized as part of space released on a volume, then this space releasing process may also take a lengthy amount of time to complete. If the space is released as part of a data replication operation, such as flash copy establish, then these commands may time out. Space release operations, if drawn out, may degrade the performance of the computing storage environment by typing up resources, for example. A need exists for a mechanism whereby metadata initialization operations are not directly tied to storage space release operations.
- the mechanisms of the illustrated embodiments separate the metadata initialization operations normally tied to storage space release operations from those release operations.
- the mechanisms mark the volumes in a persistent state that require metadata track invalidation, and returns success to the client.
- the metadata is asynchronously invalidated for the volume. Once the metadata invalidation process is complete, the persistent state of the volume is restored. Any metadata accesses during the time the volume is in the aforementioned “metadata invalidation required” state will rebuild the metadata by examining associated customer data.
- a Release Generation Number may be associated with the storage volume and with every metadata track. Upon every release space operation, the RGN may be incremented. Further, upon metadata initialization, the RGN in the track is updated with the current RGN of the volume. Finally, for example, on a metadata access or metadata stage operation, the generation information of an instant metadata track is compared with the applicable generation information from the volume, here again by comparing the RGN of the metadata track to the RGN of the volume at a particular time. If the RGN information does not match, the metadata track is initialized.
- RGN Release Generation Number
- the space release operations By separating space release operations from those operations initializing metadata tracks, the space release operations, and consequently, metadata initialization operations, encumber less storage resources by, for example, completing in less time. The overall performance of the computing environment is thereby increased.
- system 100 comprises a memory 102 coupled to a cache 104 and a processor 110 via a bus 108 (e.g., a wired and/or wireless bus).
- bus 108 e.g., a wired and/or wireless bus
- Memory 102 may be any type of memory device known in the art or developed in the future. Examples of memory 102 include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the various embodiments of memory 102 , storage tracks are capable of being stored in memory 102 . Furthermore, each of the storage tracks can be staged or destaged from/to memory 102 from cache 104 when data is written to the storage tracks.
- Cache 104 in one embodiment, comprises a write cache partitioned into one or more ranks 106 , where each rank 106 includes one or more storage tracks.
- Cache 104 may be any cache known in the art or developed in the future.
- the storage tracks in each rank 106 are destaged to memory 102 in a foreground destaging process after the storage tracks have been written to. That is, the foreground destage process destages storage tracks from the rank(s) 106 to memory 102 while a host (not shown) is actively writing to various storage tracks in the ranks 106 of cache 104 . Ideally, a particular storage track is not being destaged when one or more hosts desire to write to the particular storage track, which is known as a destage conflict.
- processor 110 comprises or has access to a cache/data management module 112 , which comprises computer-readable code that, when executed by processor 110 , causes processor 110 to perform data management operations in accordance with aspects of the illustrated embodiments.
- processor 110 acts to initializing metadata in a computing storage environment by a processor.
- processor 110 may implement a Release Generation Number (RGN) that is associated with a volume, and an RGN is associated with a metadata track.
- RGN Release Generation Number
- the processor 110 may increment the RGN associated with the volume.
- the processor 110 may update the RGN associated with the metadata track to be consistent in generation with the RGN associated with the volume.
- the processor 110 may compare the RGN of the metadata track against the RGN of the volume, and the metadata track may then be initialized if a match is not found.
- Processor 110 assigns an RGN for each of a plurality of volumes and metadata tracks in the computing storage environment.
- processor 110 pursuant to incrementing the RGN associated with the volume, hardens, on a disk associated with the volume, generation information from the RGN.
- processor 110 pursuant to updating the RGH, updates a control block associated with the metadata track with generation information from the RGN.
- processor 110 if a match is found, saves generation information from the RGN of the metadata track in a control block associated with the metadata track.
- processor 110 in conjunction with the access of the metadata track, if the metadata is not found in cache, stages the metadata track to cache.
- processor 110 in conjunction with initializing the metadata, marks the metadata as modified in cache.
- FIG. 2 is a block diagram 200 illustrating an exemplary hardware structure of a data storage system in which aspects of the present invention may be implemented.
- Host computers 210 , 220 , 225 are shown, each acting as a central processing unit for performing data processing as part of a data storage system 200 .
- the cluster hosts/nodes (physical or virtual devices), 210 , 220 , and 225 may be one or more new physical devices or logical devices to accomplish the purposes of the present invention in the data storage system 200 .
- a Network (e.g., storage fabric) connection 260 may be a fibre channel fabric, a fibre channel point-to-point link, a fibre channel over ethernet fabric or point to point link, a FICON or ESCON I/O interface.
- the hosts, 210 , 220 , and 225 may be local or distributed among one or more locations and may be equipped with any type of fabric (or fabric channel) (not shown in FIG. 2 ) or network adapter 260 to the storage controller 240 , such as Fibre channel, FICON, ESCON, Ethernet, fiber optic, wireless, or coaxial adapters.
- Data storage system 200 is accordingly equipped with a suitable fabric (not shown in FIG. 2 ) or network adapter 260 to communicate.
- Data storage system 200 is depicted in FIG. 2 comprising storage controllers 240 and cluster hosts 210 , 220 , and 225 .
- the cluster hosts 210 , 220 , and 225 may include cluster nodes.
- storage controller 240 is shown in FIG. 2 as a single processing unit, including a microprocessor 242 , system memory 243 and nonvolatile storage (“NVS”) 216 , which will be described in more detail below. It is noted that in some embodiments, storage controller 240 is comprised of multiple processing units, each with their own processor complex and system memory, and interconnected by a dedicated network within data storage system 200 . Moreover, given the use of the storage fabric network connection 260 , additional architectural configurations may be employed by using the storage fabric 260 to connect multiple storage controllers 240 together with one or more cluster hosts 210 , 220 , and 225 connected to each storage controller 240 .
- system memory 243 of storage controller 240 includes operation software 250 and stores program instructions and data which the processor 242 may access for executing functions and method steps associated with executing the steps and methods of the present invention.
- system memory 243 may also include or be in communication with a cache 245 , also referred to herein as a “cache memory”, for buffering “write data” and “read data”, which respectively refer to write/read requests and their associated data.
- cache 245 is allocated in a device external to system memory 243 , yet remains accessible by microprocessor 242 and may serve to provide additional security against data loss, in addition to carrying out the operations as described herein.
- cache 245 may be implemented with a volatile memory and non-volatile memory and coupled to microprocessor 242 via a local bus (not shown in FIG. 2 ) for enhanced performance of data storage system 200 .
- the NVS 216 included in data storage controller is accessible by microprocessor 242 and serves to provide additional support for operations and execution as described in other figures.
- the NVS 216 may also referred to as a “persistent” cache, or “cache memory” and is implemented with nonvolatile memory that may or may not utilize external power to retain data stored therein.
- the NVS may be stored in and with the cache 245 for any purposes suited to accomplish the objectives of the present invention.
- a backup power source (not shown in FIG. 2 ), such as a battery, supplies NVS 216 with sufficient power to retain the data stored therein in case of power loss to data storage system 200 .
- the capacity of NVS 216 is less than or equal to the total capacity of cache 245 .
- the storage controller 240 may include a cache management module 112 .
- the cache management module 112 may incorporate internal memory (not shown) in which the destaging algorithm may store unprocessed, processed, or “semi-processed” data.
- the cache management module 112 may work in conjunction with each and every component of the storage controller 240 , the hosts 210 , 220 , 225 , and other storage controllers 240 and hosts 210 , 220 , and 225 that may be remotely connected via the storage fabric 260 .
- Cache management module 112 may be structurally one complete module or may be associated and/or included with other individual modules.
- Cache management module 112 may also be located in the cache 245 or other components of the storage controller 240 .
- the storage controller 240 includes a control switch 241 for controlling a protocol to control data transfer to or from the host computers 210 , 220 , 225 , a microprocessor 242 for controlling all the storage controller 240 , a nonvolatile control memory 243 for storing a microprogram (operation software) 250 for controlling the operation of storage controller 240 , cache 245 for temporarily storing (buffering) data, and buffers 244 for assisting the cache 245 to read and write data, and the cache management module 112 , in which information may be set.
- the multiple buffers 244 may be implemented to assist with the methods and steps as described herein.
- Method 300 begins (step 302 ).
- a Release Generation Number (RGN) is associated with a volume.
- RGN is associated with each metadata track in the volume (step 304 ).
- the RGN associated with the volume is incremented (step 306 ).
- the RGN associated with the metadata track is updated to be consistent in generation with the RGN associated with the volume (step 308 ).
- the method 300 then ends (step 310 ).
- FIG. 4 is a flow chart diagram illustrating additional exemplary metadata initialization functionality according to various aspects of the present invention.
- Method 400 begins (step 402 ) with the stage of an applicable metadata track to cache or an access of an applicable metadata track (step 404 ).
- the RGN number of in the metadata track is compared with the RGN of the volume that the metadata track is associated (step 406 ). If no match is found (i.e., the generations of the metadata track and the volume are inconsistent), the metadata track is initialized (step 410 ).
- the method 400 ends (step 412 ). Returning to step 408 , if a match is found, the method 400 ends (again, step 412 ).
- the present invention may be a system, a method, and/or a computer program product.
- the computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
- the computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device.
- the computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.
- a non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.
- RAM random access memory
- ROM read-only memory
- EPROM or Flash memory erasable programmable read-only memory
- SRAM static random access memory
- CD-ROM compact disc read-only memory
- DVD digital versatile disk
- memory stick a floppy disk
- a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon
- a computer readable storage medium is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
- Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network.
- the network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers.
- a network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
- Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages.
- the computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
- the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
- electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
- These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
- These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
- the computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
- each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s).
- the functions noted in the block may occur out of the order noted in the figures.
- two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
Description
- 1. Field of the Invention
- The present invention relates in general computing systems, and more particularly to, systems and methods for increased data management efficiency in computing storage environments.
- 2. Description of the Related Art
- In today's society, computer systems are commonplace. Computer systems may be found in the workplace, at home, or at school. Computer systems may include data storage systems, or disk storage systems, to process and store data. Contemporary computer storage systems are known to destage, and subsequently, demote storage tracks from cache to long-term storage devices so that there is sufficient room in the cache for data to be written.
- Various embodiments for initializing metadata in a computing storage environment by a processor are provided. A Release Generation Number (RGN) is associated with a volume, and an RGN is associated with a metadata track. Upon a release of storage space in the volume, the RGN associated with the volume is incremented. Upon an initialization of the metadata track, the RGN associated with the metadata track is updated to be consistent in generation with the RGN associated with the volume. Upon an access of the metadata track, the RGN of the metadata track is compared against the RGN of the volume, and the metadata track is initialized if a match is not found.
- In order that the advantages of the invention will be readily understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:
-
FIG. 1 is an exemplary block diagram showing a hardware structure in which aspects of the present invention may be realized; -
FIG. 2 is an exemplary block diagram showing a hardware structure of a data storage system in a computing environment, again in which aspects of the present invention may be realized; -
FIG. 3 is a flow chart diagram illustrating an exemplary method for deferred metadata initialization in a computing storage environment, again in which aspects of the present invention may be realized; and -
FIG. 4 is a flow chart diagram of an additional exemplary method for deferred metadata initialization in a computing storage environment according to the present invention. - A storage controller, among other computing components, retains metadata to describe the location and properties of data, such as the data's format. This metadata may be cached, along with the data itself, in order for faster performance of the storage controller. One metadata track may include information for many individual data tracks. For example, metadata describing Count Key Data (CKD) information may include on average, information pertaining to a thousand data tracks.
- Initialization of this metadata currently may take a lengthy amount of time, as each metadata track needs to be written to storage. If the metadata is initialized as part of space released on a volume, then this space releasing process may also take a lengthy amount of time to complete. If the space is released as part of a data replication operation, such as flash copy establish, then these commands may time out. Space release operations, if drawn out, may degrade the performance of the computing storage environment by typing up resources, for example. A need exists for a mechanism whereby metadata initialization operations are not directly tied to storage space release operations.
- The mechanisms of the illustrated embodiments separate the metadata initialization operations normally tied to storage space release operations from those release operations. In one exemplary embodiment, the mechanisms mark the volumes in a persistent state that require metadata track invalidation, and returns success to the client. In a subsequent step, the metadata is asynchronously invalidated for the volume. Once the metadata invalidation process is complete, the persistent state of the volume is restored. Any metadata accesses during the time the volume is in the aforementioned “metadata invalidation required” state will rebuild the metadata by examining associated customer data.
- To asynchronously invalidate metadata according to the embodiments of the present invention, several exemplary portions of functionality may be implemented as will be further described. First, a Release Generation Number (RGN) may be associated with the storage volume and with every metadata track. Upon every release space operation, the RGN may be incremented. Further, upon metadata initialization, the RGN in the track is updated with the current RGN of the volume. Finally, for example, on a metadata access or metadata stage operation, the generation information of an instant metadata track is compared with the applicable generation information from the volume, here again by comparing the RGN of the metadata track to the RGN of the volume at a particular time. If the RGN information does not match, the metadata track is initialized.
- By separating space release operations from those operations initializing metadata tracks, the space release operations, and consequently, metadata initialization operations, encumber less storage resources by, for example, completing in less time. The overall performance of the computing environment is thereby increased.
- Turning to
FIG. 1 , a block diagram of one embodiment of asystem 100 for data management incorporating various aspects of the present invention is illustrated. At least in the illustrated embodiment,system 100 comprises amemory 102 coupled to acache 104 and aprocessor 110 via a bus 108 (e.g., a wired and/or wireless bus). -
Memory 102 may be any type of memory device known in the art or developed in the future. Examples ofmemory 102 include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the various embodiments ofmemory 102, storage tracks are capable of being stored inmemory 102. Furthermore, each of the storage tracks can be staged or destaged from/tomemory 102 fromcache 104 when data is written to the storage tracks. -
Cache 104, in one embodiment, comprises a write cache partitioned into one ormore ranks 106, where eachrank 106 includes one or more storage tracks.Cache 104 may be any cache known in the art or developed in the future. - During operation, the storage tracks in each
rank 106 are destaged tomemory 102 in a foreground destaging process after the storage tracks have been written to. That is, the foreground destage process destages storage tracks from the rank(s) 106 tomemory 102 while a host (not shown) is actively writing to various storage tracks in theranks 106 ofcache 104. Ideally, a particular storage track is not being destaged when one or more hosts desire to write to the particular storage track, which is known as a destage conflict. - In various embodiments,
processor 110 comprises or has access to a cache/data management module 112, which comprises computer-readable code that, when executed byprocessor 110, causesprocessor 110 to perform data management operations in accordance with aspects of the illustrated embodiments. In the various embodiments,processor 110 acts to initializing metadata in a computing storage environment by a processor. In furtherance of this metadata initialization,processor 110 may implement a Release Generation Number (RGN) that is associated with a volume, and an RGN is associated with a metadata track. Upon a release of storage space in the volume, theprocessor 110 may increment the RGN associated with the volume. Upon an initialization of the metadata track, theprocessor 110 may update the RGN associated with the metadata track to be consistent in generation with the RGN associated with the volume. Upon an access of the metadata track, theprocessor 110 may compare the RGN of the metadata track against the RGN of the volume, and the metadata track may then be initialized if a match is not found. -
Processor 110, in other embodiments, assigns an RGN for each of a plurality of volumes and metadata tracks in the computing storage environment. - In other embodiments,
processor 110, pursuant to incrementing the RGN associated with the volume, hardens, on a disk associated with the volume, generation information from the RGN. - In other embodiments,
processor 110, pursuant to updating the RGH, updates a control block associated with the metadata track with generation information from the RGN. - In other embodiments,
processor 110, if a match is found, saves generation information from the RGN of the metadata track in a control block associated with the metadata track. - In still other embodiments,
processor 110, in conjunction with the access of the metadata track, if the metadata is not found in cache, stages the metadata track to cache. - Finally, in other embodiments,
processor 110, in conjunction with initializing the metadata, marks the metadata as modified in cache. -
FIG. 2 is a block diagram 200 illustrating an exemplary hardware structure of a data storage system in which aspects of the present invention may be implemented.Host computers data storage system 200. The cluster hosts/nodes (physical or virtual devices), 210, 220, and 225 may be one or more new physical devices or logical devices to accomplish the purposes of the present invention in thedata storage system 200. A Network (e.g., storage fabric)connection 260 may be a fibre channel fabric, a fibre channel point-to-point link, a fibre channel over ethernet fabric or point to point link, a FICON or ESCON I/O interface. The hosts, 210, 220, and 225 may be local or distributed among one or more locations and may be equipped with any type of fabric (or fabric channel) (not shown inFIG. 2 ) ornetwork adapter 260 to thestorage controller 240, such as Fibre channel, FICON, ESCON, Ethernet, fiber optic, wireless, or coaxial adapters.Data storage system 200 is accordingly equipped with a suitable fabric (not shown inFIG. 2 ) ornetwork adapter 260 to communicate.Data storage system 200 is depicted inFIG. 2 comprisingstorage controllers 240 and cluster hosts 210, 220, and 225. The cluster hosts 210, 220, and 225 may include cluster nodes. - To facilitate a clearer understanding of the methods described herein,
storage controller 240 is shown inFIG. 2 as a single processing unit, including amicroprocessor 242,system memory 243 and nonvolatile storage (“NVS”) 216, which will be described in more detail below. It is noted that in some embodiments,storage controller 240 is comprised of multiple processing units, each with their own processor complex and system memory, and interconnected by a dedicated network withindata storage system 200. Moreover, given the use of the storagefabric network connection 260, additional architectural configurations may be employed by using thestorage fabric 260 to connectmultiple storage controllers 240 together with one or more cluster hosts 210, 220, and 225 connected to eachstorage controller 240. - In some embodiments, the
system memory 243 ofstorage controller 240 includesoperation software 250 and stores program instructions and data which theprocessor 242 may access for executing functions and method steps associated with executing the steps and methods of the present invention. As shown inFIG. 2 ,system memory 243 may also include or be in communication with acache 245, also referred to herein as a “cache memory”, for buffering “write data” and “read data”, which respectively refer to write/read requests and their associated data. In one embodiment,cache 245 is allocated in a device external tosystem memory 243, yet remains accessible bymicroprocessor 242 and may serve to provide additional security against data loss, in addition to carrying out the operations as described herein. - In some embodiments,
cache 245 may be implemented with a volatile memory and non-volatile memory and coupled tomicroprocessor 242 via a local bus (not shown inFIG. 2 ) for enhanced performance ofdata storage system 200. TheNVS 216 included in data storage controller is accessible bymicroprocessor 242 and serves to provide additional support for operations and execution as described in other figures. TheNVS 216, may also referred to as a “persistent” cache, or “cache memory” and is implemented with nonvolatile memory that may or may not utilize external power to retain data stored therein. The NVS may be stored in and with thecache 245 for any purposes suited to accomplish the objectives of the present invention. In some embodiments, a backup power source (not shown inFIG. 2 ), such as a battery, suppliesNVS 216 with sufficient power to retain the data stored therein in case of power loss todata storage system 200. In certain embodiments, the capacity ofNVS 216 is less than or equal to the total capacity ofcache 245. - The
storage controller 240 may include acache management module 112. Thecache management module 112 may incorporate internal memory (not shown) in which the destaging algorithm may store unprocessed, processed, or “semi-processed” data. Thecache management module 112 may work in conjunction with each and every component of thestorage controller 240, thehosts other storage controllers 240 and hosts 210, 220, and 225 that may be remotely connected via thestorage fabric 260.Cache management module 112 may be structurally one complete module or may be associated and/or included with other individual modules.Cache management module 112 may also be located in thecache 245 or other components of thestorage controller 240. - The
storage controller 240 includes acontrol switch 241 for controlling a protocol to control data transfer to or from thehost computers microprocessor 242 for controlling all thestorage controller 240, anonvolatile control memory 243 for storing a microprogram (operation software) 250 for controlling the operation ofstorage controller 240,cache 245 for temporarily storing (buffering) data, and buffers 244 for assisting thecache 245 to read and write data, and thecache management module 112, in which information may be set. Themultiple buffers 244 may be implemented to assist with the methods and steps as described herein. - Turning now to
FIG. 3 , a flow chart diagram, illustrating ageneralized method 300 for data management, featuring aspects of metadata invalidation in accordance with the present invention, is depicted.Method 300 begins (step 302). A Release Generation Number (RGN) is associated with a volume. In addition, a RGN is associated with each metadata track in the volume (step 304). Upon a release of storage space in the volume, the RGN associated with the volume is incremented (step 306). Upon an initialization of the metadata track, the RGN associated with the metadata track is updated to be consistent in generation with the RGN associated with the volume (step 308). Themethod 300 then ends (step 310). -
FIG. 4 , following, is a flow chart diagram illustrating additional exemplary metadata initialization functionality according to various aspects of the present invention.Method 400 begins (step 402) with the stage of an applicable metadata track to cache or an access of an applicable metadata track (step 404). The RGN number of in the metadata track is compared with the RGN of the volume that the metadata track is associated (step 406). If no match is found (i.e., the generations of the metadata track and the volume are inconsistent), the metadata track is initialized (step 410). Themethod 400 ends (step 412). Returning to step 408, if a match is found, themethod 400 ends (again, step 412). - The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
- The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
- Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
- Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
- Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
- These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
- The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
- The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/682,619 US9483408B1 (en) | 2015-04-09 | 2015-04-09 | Deferred metadata initialization |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/682,619 US9483408B1 (en) | 2015-04-09 | 2015-04-09 | Deferred metadata initialization |
Publications (2)
Publication Number | Publication Date |
---|---|
US20160299848A1 true US20160299848A1 (en) | 2016-10-13 |
US9483408B1 US9483408B1 (en) | 2016-11-01 |
Family
ID=57111346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/682,619 Expired - Fee Related US9483408B1 (en) | 2015-04-09 | 2015-04-09 | Deferred metadata initialization |
Country Status (1)
Country | Link |
---|---|
US (1) | US9483408B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10210086B1 (en) | 2017-08-16 | 2019-02-19 | International Business Machines Corporation | Fast cache demotions in storage controllers with metadata |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5897661A (en) * | 1997-02-25 | 1999-04-27 | International Business Machines Corporation | Logical volume manager and method having enhanced update capability with dynamic allocation of storage and minimal storage of metadata information |
US7546288B2 (en) * | 2003-09-04 | 2009-06-09 | Microsoft Corporation | Matching media file metadata to standardized metadata |
US8359491B1 (en) * | 2004-03-30 | 2013-01-22 | Symantec Operating Corporation | Disaster recovery rehearsal using copy on write |
US7340652B2 (en) * | 2004-04-30 | 2008-03-04 | International Business Machines Corporation | Invalidation of storage control unit cache metadata |
US8856467B2 (en) * | 2004-11-18 | 2014-10-07 | International Business Machines Corporation | Management of metadata in a storage subsystem |
US7383404B2 (en) * | 2005-02-03 | 2008-06-03 | International Business Machines Corporation | Priority initialization system |
US7657550B2 (en) * | 2005-11-28 | 2010-02-02 | Commvault Systems, Inc. | User interfaces and methods for managing data in a metabase |
US8001339B1 (en) * | 2005-12-22 | 2011-08-16 | Storage Technology Corporation | Storage management policies in a virtual data storage system |
US8332581B2 (en) * | 2007-08-13 | 2012-12-11 | International Business Machines Corporation | Stale track initialization in a storage controller |
US7975169B2 (en) * | 2008-06-03 | 2011-07-05 | International Business Machines Corporation | Memory preserved cache to prevent data loss |
US8914567B2 (en) * | 2008-09-15 | 2014-12-16 | Vmware, Inc. | Storage management system for virtual machines |
KR101222129B1 (en) * | 2008-12-22 | 2013-01-15 | 한국전자통신연구원 | Metadata Server and Data Storage Disk Volumn Selecting Method Thereof |
US7930588B2 (en) | 2009-01-28 | 2011-04-19 | International Business Machines Corporation | Deferred volume metadata invalidation |
EP2476055B1 (en) * | 2009-09-08 | 2020-01-22 | SanDisk Technologies LLC | Apparatus, system, and method for caching data on a solid-state storage device |
US8578087B2 (en) * | 2010-02-02 | 2013-11-05 | International Business Machines Corporation | On demand conversion of standard logical volumes to thin-provisioned logical volumes |
US8380961B2 (en) * | 2010-08-18 | 2013-02-19 | International Business Machines Corporation | Methods and systems for formatting storage volumes |
US9009118B2 (en) * | 2010-10-20 | 2015-04-14 | Apple Inc. | Temporal metadata track |
US9116988B2 (en) * | 2010-10-20 | 2015-08-25 | Apple Inc. | Temporal metadata track |
US20140173223A1 (en) | 2011-12-13 | 2014-06-19 | Nathaniel S DeNeui | Storage controller with host collaboration for initialization of a logical volume |
US8909879B2 (en) | 2012-06-11 | 2014-12-09 | International Business Machines Corporation | Counter-based entry invalidation for metadata previous write queue |
-
2015
- 2015-04-09 US US14/682,619 patent/US9483408B1/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10210086B1 (en) | 2017-08-16 | 2019-02-19 | International Business Machines Corporation | Fast cache demotions in storage controllers with metadata |
US10671533B2 (en) | 2017-08-16 | 2020-06-02 | International Business Machines Corporation | Fast cache demotions in storage controllers with metadata |
Also Published As
Publication number | Publication date |
---|---|
US9483408B1 (en) | 2016-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9710398B2 (en) | RE-MRU of metadata tracks to reduce lock contention | |
US10157082B2 (en) | Preferential CPU utilization for tasks | |
US9665493B2 (en) | Increased cache performance with multi-level queues of complete tracks | |
US9772939B2 (en) | Heat-based key-value slot organization for flash-optimized data placement in multi-tiered storage systems | |
US9652406B2 (en) | MRU batching to reduce lock contention | |
US10120716B2 (en) | Task pooling and work affinity in data processing | |
US10860481B2 (en) | Data recovery method, data recovery system, and computer program product | |
US9405669B2 (en) | Recovery from cache and NVS out of sync | |
US20160139953A1 (en) | Preferential cpu utilization for tasks | |
US10031844B2 (en) | NVS thresholding for efficient data management | |
US10437730B2 (en) | Read cache synchronization in data replication environments | |
US9411738B2 (en) | Efficient processing of cache segment waiters | |
US9665492B2 (en) | Fuzzy counters for NVS to reduce lock contention | |
US9483408B1 (en) | Deferred metadata initialization | |
US9542331B2 (en) | Concurrent update of data in cache with destage to disk | |
US9280485B2 (en) | Efficient cache volume sit scans | |
US10671537B2 (en) | Reducing translation latency within a memory management unit using external caching structures | |
US10282138B2 (en) | Secondary read cache optimization in data replication environments | |
US20170228314A1 (en) | Copy-on-write in cache for ensuring data integrity in case of storage system failure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GRUSY, ELLEN J.;GUPTA, LOKESH M.;LOVRIEN, KURT A.;AND OTHERS;SIGNING DATES FROM 20150407 TO 20150409;REEL/FRAME:035371/0477 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20201101 |