US20160284665A1 - Semiconductor device package and method of manufacturing the same - Google Patents
Semiconductor device package and method of manufacturing the same Download PDFInfo
- Publication number
- US20160284665A1 US20160284665A1 US14/665,800 US201514665800A US2016284665A1 US 20160284665 A1 US20160284665 A1 US 20160284665A1 US 201514665800 A US201514665800 A US 201514665800A US 2016284665 A1 US2016284665 A1 US 2016284665A1
- Authority
- US
- United States
- Prior art keywords
- electrical component
- conductive frame
- top surface
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims description 29
- 238000009413 insulation Methods 0.000 claims description 7
- 239000012777 electrically insulating material Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000000615 nonconductor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54413—Marks applied to semiconductor devices or parts comprising digital information, e.g. bar codes, data matrix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present disclosure relates to a semiconductor device package and a method of manufacturing the same, and more particularly, to a semiconductor device package with a shielding cover and a manufacturing method thereof.
- Electromagnetic emissions can radiate from a source semiconductor device, and can be incident upon neighboring semiconductor devices. If the level of electromagnetic emissions at a neighboring semiconductor device is sufficiently high, these emissions can adversely affect the operation of the neighboring semiconductor device. This phenomenon is sometimes referred to as electromagnetic interference (EMI). Smaller sized semiconductor devices can exacerbate EMI by providing a higher density of semiconductor devices within an overall electronic system, and, thus, a higher level of undesired electromagnetic emissions at neighboring semiconductor devices.
- EMI electromagnetic interference
- shielding can be accomplished by including an electrically conductive casing or housing that is electrically grounded and is secured to an exterior of the package.
- an electrically conductive casing or housing that is electrically grounded and is secured to an exterior of the package.
- electromagnetic emissions from an interior of the package strike an inner surface of the casing, at least a portion of these emissions can be electrically shorted, thereby reducing the level of emissions that can pass through the casing and adversely affect neighboring semiconductor devices.
- electromagnetic emissions from a neighboring semiconductor device strike an outer surface of the casing, a similar electrical shorting can occur to reduce EMI of semiconductor devices within the package.
- EMI shielding increases the total size of a semiconductor device package, and thus it may not satisfy the demands brought on by developments in high density integrated circuits.
- a semiconductor device package includes a substrate, a first electrical component, a second electrical component, a conductive frame, and an electromagnetic interference shield.
- the substrate has a top surface.
- the first electrical component is disposed on the top surface of the substrate.
- the second electrical component is disposed on the top surface of the substrate.
- the second electrical component has a top surface.
- the conductive frame has a top portion and a rim substantially perpendicular to the top portion.
- the top portion has a top surface.
- the conductive frame is disposed on the top surface of the substrate to cover the first electrical component.
- the conductive frame defines at least one opening in the top portion of the conductive frame. The at least one opening exposes the second electrical component.
- the top surface of the top portion of the conductive frame is substantially coplanar with the top surface of the second electrical component.
- the electromagnetic interference shield is in contact with the top surface of the top portion of the conductive frame, an outer lateral surface of the rim of the conductive frame, and the top surface of the second electrical component.
- a method of manufacturing a semiconductor device package comprises: (a) providing a substrate having a top surface; (b) attaching a first electrical component and a second electrical component on the top surface of the substrate, the second electrical component having a top portion; (c) placing a conductive frame on the top surface of the substrate to cover the first electrical component, the conductive frame including a top portion and a rim substantially perpendicular to the top portion, the top portion having a top surface, the conductive frame defining at least one opening in the top portion of the conductive frame, the least one opening exposing the second electrical component, and the top surface of the top portion of the conductive frame being substantially coplanar with the top surface of the second electrical component; (d) placing an electromagnetic interference shield on the conductive frame in contact with the top surface of the top portion of the conductive frame, an outer lateral surface of the rim of the conductive frame, and the top surface of the second electrical component.
- FIG. 1A illustrates a cross-sectional view of a semiconductor device package in accordance with an embodiment of the present disclosure.
- FIG. 1B illustrates a top view of a semiconductor device package in accordance with an embodiment of the present disclosure.
- FIG. 2A , FIG. 2B and FIG. 2C illustrate a manufacturing process in accordance with an embodiment of the present disclosure.
- EMI shielding in the form of housings or casings increases the size of a semiconductor package, the use of such shielding is counter-indicated for implementation within small semiconductor devices.
- This disclosure describes techniques for EMI shielding suitable for smaller semiconductor device packages, which additionally reduces manufacturing costs.
- FIG. 1A illustrates a cross-sectional view of a semiconductor device package 1 in accordance with an embodiment of the present disclosure.
- the semiconductor device package 1 includes a substrate 10 , a plurality of active electrical components 12 , 12 ′, a plurality of other electrical components 13 , 23 , 33 , a conductive frame 14 , and an EMI shield 16 .
- the substrate 10 has a top surface 101 , a bottom surface 102 opposite to the top surface 101 and a lateral surface 103 .
- the lateral surface 103 is at a peripheral edge of the substrate 10 , and extends between the top surface 101 and the bottom surface 102 .
- the substrate 10 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate.
- the substrate 10 may include an interconnection structure (not shown in FIG. 1A ), such as a redistribution layer (RDL), for electrical connection between the electrical components 13 , 23 , 33 and/or the active electrical components 12 , 12 ′ mounted on a top surface 101 of the substrate 10 .
- RDL redistribution layer
- the active electrical component 12 is mounted on the top surface 101 of the substrate 10 .
- the active electrical component 12 may be a flip-chip type semiconductor device. According to another embodiment of the present disclosure, the active electrical component 12 may be a wire-bond type semiconductor device.
- the active electrical component 12 may be, for example, an integrated chip (IC) or a die.
- Electrical contacts 12 a of the active electrical component 12 are encapsulated by an underfill 11 which is used to protect the electrical contacts 12 a.
- the underfill 11 may be, for example, epoxy or other suitable material.
- the electrical components 13 , 23 , 33 are mounted on the top surface 101 of the substrate 10 .
- the electrical components 13 , 23 , 33 may be, for example, capacitors, resistors, inductors, or a combination thereof.
- the electrical component 13 has two electrical contacts (electrodes) 13 a and 13 b, each of which has a surface, respectively 13 a 1 , 13 b 1 .
- the conductive frame 14 has a top portion 141 , a rim (fence) 142 and at least one compartment 143 .
- the top portion 141 has a top surface 1411 .
- the rim 142 and the compartment 143 are substantially perpendicular to the top portion 141 .
- the conductive frame 14 is mounted on the top surface 101 of the substrate 10 to cover the active electrical components 12 , 12 ′ and the electrical component 33 .
- the top portion 141 of the conductive frame 14 has at least one opening 14 h to expose the electrical components 13 , 23 .
- the top surface 1411 of the top portion 141 of the conductive frame 14 is substantially coplanar with the surfaces 13 a 1 , 13 b 1 of the first electrical component 13 , which is the component which extends vertically the highest in the semiconductor device package 1 , where the term “vertically” refers to the orientation shown in FIG. 1A .
- the conductive frame 14 may include one or more metals, or a mixture, an alloy, or other combination thereof.
- the conductive frame 14 is mounted on the top surface 101 of the substrate 10 through a connection member 17 . That is, the conductive frame 14 is electrically connected to a grounding plane of the substrate 19 through the connection member 17 .
- the connection member 17 may be, for example, a conductive bonding material.
- the connection member 17 is separated from the active electrical component 12 by a distance D equal to or smaller than about 0.2 millimeter (mm), such as less than or equal to about 0.19 mm, about 0.18 mm, about 0.17 mm, about 0.16 mm, about 0.15 mm, about 0.14 mm, about 0.13 mm, about 0.12 mm, about 0.11 mm, or about 0.1 mm.
- the compartment 143 extends from the top portion 141 of the conductive frame 14 to separate the active electrical component 12 from the active electrical component 12 ′ disposed on the top surface 101 of the substrate 10 .
- the compartment 143 reduces the effect on the active electrical component 12 of electromagnetic emissions generated by the active electrical component 12 ′ (e.g. EMI or cross-talk), and vice versa.
- the compartment 143 can further separate a first set of electrical components 13 , 33 from a second set of electrical components 23 disposed on the top surface 101 of the substrate 10 , to reduce the effect on the electrical components 23 of electromagnetic emissions generated by the electrical components 13 , 33 , and vice versa.
- a first pattern 15 may be, for example, barcodes or other recognition codes (e.g., quick response (QR) code) that represent information corresponding to the semiconductor device package 1 , such as a serial number of the semiconductor device package 1 and a unit number of the substrate 10 .
- a first pattern 15 can be formed from the top surface 1411 into the top portion 141 of the conductive frame 14 .
- the top portion 141 of the conductive frame 14 is substantially coplanar with the top surface of the first pattern 15 and the EMI shield 16 directly contacts the first pattern 15 .
- the first pattern 15 can be formed by, for example, laser techniques or other suitable techniques.
- the EMI shield 16 is disposed on the external surface of the conductive frame 14 .
- the EMI shield 16 is in contact with the top surface 1411 of the top portion 141 of the conductive frame 14 , an outer lateral surface 1421 of the rim 142 of the conductive frame 14 and the surfaces 13 a 1 , 13 b 1 of the first electrical component 13 .
- the EMI shield 16 may be a conductive thin film, and may include, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni) or stainless steel, or a mixture, an alloy, or other combination thereof.
- the EMI shield 16 and the conductive frame 14 can reduce the effect on the active electrical components 12 , 12 ′ and the electrical components 13 , 23 , 33 disposed in the semiconductor device package 1 of electromagnetic emissions generated by semiconductor devices outside the semiconductor package 1 . Since the conductive frame 14 is grounded through the connection member 17 , and the EMI shield 16 directly contacts the conductive frame 14 , the EMI shield 16 is grounded through the conductive frame 14 .
- the EMI shield 16 has a top surface 161 , a bottom surface 162 opposite to the top surface 161 , and a lateral surface 163 .
- the lateral surface 103 of the substrate 10 extends horizontally beyond the lateral surface 163 of the EMI shield 16 , on one or both sides of the semiconductor package 1 , where the term “horizontally” is with respect to the orientation of the semiconductor package 1 illustrated by FIG. 1A .
- the lateral surface 163 of the EMI shield 16 is substantially coplanar with the lateral surface 103 of the substrate 10 , on one or both sides of the semiconductor package 1 .
- At least one insulation pad 173 is formed on the bottom surface 162 of the EMI shield 16 and contacts the surfaces 13 a 1 , 13 b 1 of the electrical component 13 , to electrically isolate the EMI shield 16 from the surfaces 13 a 1 , 13 b 1 of the electrical component 13 .
- the surfaces 13 a 1 , 13 b 1 of the electrical component 13 may be surfaces of electrical insulators positioned on contacts 13 a, 13 b respectively, and thus the EMI shield 16 can be in direct contact with the surfaces 13 a 1 , 13 b 1 of the electrical component 13 , and the insulation pad(s) 173 may be eliminated.
- the EMI shield 16 may include a single conductive layer.
- the EMI shield 16 may include several conductive layers formed of the same material or of different materials.
- each conductive layer may have a thickness of, for example, up to about 200 ⁇ m, up to about 150 ⁇ m, up to about 100 ⁇ m, up to about 50 ⁇ m, up to about 10 ⁇ m, up to about 5 ⁇ m, up to about 1 ⁇ m, or up to about 500 nm, and down to about 100 nm or less, down to about 50 nm or less, or down to about 10 nm or less.
- a second pattern 18 may be, for example, barcodes or other recognition codes that represent information corresponding to the semiconductor device package 1 , such as a shipment number of the semiconductor package 1 .
- the second pattern 18 can be formed from the top surface 161 into the EMI shield 16 . That is, the top surface of the second pattern 18 is coplanar with the top surface 161 of the EMI shield 16 .
- the second pattern 18 can be formed by, for example, laser techniques or other suitable techniques.
- a sticker including a barcode other code may be applied.
- a sticker may be applied to one or both of the top portion 141 of the conductive frame 14 and the top surface 161 of the EMI shield 16 .
- such a sticker may have a thickness of approximately 0.02 mm, which may result in an increase in a height of the semiconductor device package 1 . Therefore, forming the barcode or other code by using laser techniques can reduce a total height of the semiconductor device package 1 .
- FIG. 1B illustrates a top view of the semiconductor device package 1 in accordance with an embodiment of the present disclosure.
- the semiconductor device package 1 shown in FIG. 1B is similar to that shown in FIG. 1A , except that the EMI shield 16 is not included.
- the opening 14 h 1 is formed corresponding to the location of the component extending vertically the highest in the semiconductor package 1 , (e.g., electrical component 13 in FIG. 1A ), so that the bottom surface 162 of the EMI shield 16 is coplanar with the highest portion of that component.
- the EMI shield 16 is placed to cover a top surface of the semiconductor package device 1 along a plane.
- a total height of the semiconductor device package 1 depicted in FIGS. 1A and 1B may be reduced by at least about 0.25 mm, which may, in turn, reduce manufacturing costs.
- the openings 14 h 2 are formed in the conductive frame 14 taking into consideration a balancing of stresses on the conductive frame 14 .
- FIG. 2A , FIG. 2B and FIG. 2C illustrate a semiconductor manufacturing process in accordance with an embodiment of the present disclosure.
- a partial semiconductor device package 1 a is illustrated, including a substrate 10 .
- a plurality of active electrical components 12 , 12 ′ and a plurality of electrical components 13 , 23 , 33 are attached on a top surface 101 of the substrate 10 .
- a conductive frame 14 is positioned over and mounted on the top surface 101 of the substrate 10 through a connection member 17 .
- the connection member 17 may be, for example, a conductive bonding material.
- the conductive frame 14 has a top portion 141 , a rim 142 and at least one compartment 143 .
- the top portion 141 has a top surface 1411 .
- the rim 142 and the compartment 143 are substantially perpendicular to the top portion 141 .
- the conductive frame 14 covers the active electrical components 12 , 12 ′ and the electrical component 33 .
- the top portion 141 of the conductive frame 14 has at least one opening 14 h to expose the electrical components 13 , 23 .
- the top surface 1411 of the top portion 141 of the conductive frame 14 and the surfaces 13 a 1 , 13 b 1 of the first electrical component 13 which is the component which extends vertically the highest in the semiconductor device package 1 , are substantially coplanar.
- the compartment 143 extends from the top portion 141 of the conductive frame 14 to separate the active electrical component 12 from the active electrical component 12 ′ disposed on the top surface 101 of the substrate 10 , to decrease the amount of electromagnetic emissions of the active electrical component 12 reaching the active electrical component 12 ′, and to decrease the amount of electromagnetic emissions of the active electrical component 12 ′ reaching the active electrical component 12 .
- the compartment 143 can further separate a first set of electrical components (e.g., 13 , 33 ) from a second set of electrical components (e.g., 23 ) disposed on the top surface 101 of the substrate 10 .
- the active electrical components 12 , 12 ′, the electrical components 13 , 23 , 33 and the conductive frame 14 are secured or mounted on the top surface 101 of the substrate 10 by a surface mount technique. Then, a reflow process is performed, for example to form a metallic interconnect phase between under bump metallization and solder.
- a first pattern 15 (e.g., one or more barcodes or other recognition codes that represent information of the semiconductor device package 1 ) may be formed in or on the conductive frame 14 .
- the first pattern 15 may be formed from the top surface 1411 into the top portion 141 of the conductive frame 14 using for example, laser techniques or other suitable techniques.
- the first pattern 15 may be applied, such as by way of a sticker.
- the first pattern 15 may be scanned, and the scanned pattern or the information it represents may be stored in a storage device (not shown in FIG. 2B ).
- a stored image of the first pattern 15 may be mapped to relevant information of the semiconductor device package 1 a.
- an electrically insulating material is injected or dispensed through the openings 14 h of the conductive frame 14 to form an underfill 11 to encapsulate electrical contacts 12 a of the active electrical components 12 , 12 ′, thereby forming a partial semiconductor device package 1 b.
- Singulation may be performed to divide a strip of semiconductor device packages 1 b into a plurality of individual semiconductor device packages 1 b.
- the singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting means.
- an EMI shield 16 is formed on the external surface of the conductive frame 14 so as to be in contact with the top surface 1411 of the top portion 141 of the conductive frame 14 , an outer lateral surface 1421 of the rim 142 of the conductive frame 14 and the surfaces 13 a 1 , 13 b 1 of the electrical component 13 .
- the EMI shield 16 has a top surface 161 and a bottom surface 162 opposite to the top surface 161 .
- at least one insulation pad 173 is formed on the bottom surface 162 of the EMI shield 16 and is in contact with the surfaces 13 a 1 , 13 b 1 of the electrical component 13 , to electrically isolate the EMI shield 16 from the surfaces 13 a 1 , 13 b 1 of the electrical component 13 .
- the surfaces 13 a 1 , 13 b 1 of the electrical component 13 can be surfaces of an electrical insulator material, and thus the EMI shield 16 can be in direct contact with the surfaces 13 a 1 , 13 b 1 of the electrical component 13 , and the insulation pad(s) 173 eliminated.
- the EMI shield 16 may be deposited as a conductive thin film, and may include, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni) or stainless steel, or a mixture, an alloy, or other combination thereof.
- the EMI shield 16 may include a single conductive layer. In accordance with another embodiment of the present disclosure, the EMI shield 16 may include several conductive layers of either the same material or different materials.
- a second pattern 18 (e.g., barcodes or other codes that correspond to information related to the semiconductor device package 1 ), is formed or placed on the top surface 161 of the EMI shield 16 .
- the second pattern 18 can be formed from the top surface 161 into the EMI shield 16 to form the semiconductor device package 1 as described and illustrated with reference to FIG. 1A .
- the second pattern 18 can be formed, for example, using laser techniques or other suitable techniques.
- an electrically insulating material is introduced through the openings 14 h of the conductive frame 14 to form the underfill 11 .
- the conductive frame 14 , the active electrical components 12 , 12 ′, the electrical components 13 , 23 , 33 and the conductive frame 14 can be placed and mounted on the top surface 101 of the substrate 10 by a single surface mount process, followed by reflow.
- the underfill 11 would have to be introduced prior to the placement of the conductive frame 14 , and a subsequent second surface mount process and reflow would be included to place the conductive frame 14 on the substrate 10 .
- the use of openings 14 h in the conductive frame 14 allows for reduced manufacturing costs.
- connection member 17 may act as a stop for the underfill 11 .
- the connection member 17 may act as a stop for the underfill 11 .
- the conductive frame 14 had no openings 14 h, the underfill 11 would be introduced prior to mounting the conductive frame 14 to the substrate 10 .
- the semiconductor manufacturing process shown in FIG. 2A , FIG. 2B and FIG. 2C allows for a distance D between the edge of the active electrical component 12 and the connection member 17 to be less than about 0.2 mm.
- a distance which may be more than about 0.55 mm may be reserved from the edge of the active electrical component 12 to allow for the horizontal expansion of the underfill 11 .
- a space of about 0.55 mm or more would be reserved.
- the semiconductor manufacturing process shown in FIG. 2A , FIG. 2B and FIG. 2C may reduce the total width of the semiconductor device package 1 by at least about 0.35 mm on a side, which can, in turn, reduce manufacturing costs.
- the terms “substantially,” “substantial,” “approximately,” and “about” are used to denote small variations.
- the terms can refer to less than or equal to ⁇ 10%, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
- substantially coplanar can refer to two surfaces within micrometers ( ⁇ m) of lying along the same plane, such as within 100 ⁇ m, within 80 ⁇ m, within 60 ⁇ m, within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
- Two surfaces or components can be deemed to be “substantially perpendicular” if an angle therebetween is, for example, 90° ⁇ 10°, such as ⁇ 5°, ⁇ 4°, ⁇ 3°, ⁇ 2°, ⁇ 1°, ⁇ 0.5°, ⁇ 0.1°, or ⁇ 0.05°.
- the terms “substantially,” “substantial,” “approximately,” and “about” can refer to instances in which the event or circumstance occurs precisely, as well as instances in which the event or circumstance occurs to a close approximation.
Abstract
Description
- 1. Technical Field
- The present disclosure relates to a semiconductor device package and a method of manufacturing the same, and more particularly, to a semiconductor device package with a shielding cover and a manufacturing method thereof.
- 2. Description of the Related Art
- Semiconductor devices have become progressively more complex, driven at least in part by the demand for enhanced processing speeds and smaller sizes. Enhanced processing speeds tend to involve higher clock speeds, which can involve more frequent transitions between signal levels, which, in turn, can lead to a higher level of electromagnetic emissions at higher frequencies or shorter wavelengths. Electromagnetic emissions can radiate from a source semiconductor device, and can be incident upon neighboring semiconductor devices. If the level of electromagnetic emissions at a neighboring semiconductor device is sufficiently high, these emissions can adversely affect the operation of the neighboring semiconductor device. This phenomenon is sometimes referred to as electromagnetic interference (EMI). Smaller sized semiconductor devices can exacerbate EMI by providing a higher density of semiconductor devices within an overall electronic system, and, thus, a higher level of undesired electromagnetic emissions at neighboring semiconductor devices.
- One way to reduce EMI is to shield a set of semiconductor devices within a semiconductor device package. In particular, shielding can be accomplished by including an electrically conductive casing or housing that is electrically grounded and is secured to an exterior of the package. When electromagnetic emissions from an interior of the package strike an inner surface of the casing, at least a portion of these emissions can be electrically shorted, thereby reducing the level of emissions that can pass through the casing and adversely affect neighboring semiconductor devices. Similarly, when electromagnetic emissions from a neighboring semiconductor device strike an outer surface of the casing, a similar electrical shorting can occur to reduce EMI of semiconductor devices within the package.
- However, EMI shielding increases the total size of a semiconductor device package, and thus it may not satisfy the demands brought on by developments in high density integrated circuits.
- In accordance with an embodiment of the present disclosure, a semiconductor device package includes a substrate, a first electrical component, a second electrical component, a conductive frame, and an electromagnetic interference shield. The substrate has a top surface. The first electrical component is disposed on the top surface of the substrate. The second electrical component is disposed on the top surface of the substrate. The second electrical component has a top surface. The conductive frame has a top portion and a rim substantially perpendicular to the top portion. The top portion has a top surface. The conductive frame is disposed on the top surface of the substrate to cover the first electrical component. The conductive frame defines at least one opening in the top portion of the conductive frame. The at least one opening exposes the second electrical component. The top surface of the top portion of the conductive frame is substantially coplanar with the top surface of the second electrical component. The electromagnetic interference shield is in contact with the top surface of the top portion of the conductive frame, an outer lateral surface of the rim of the conductive frame, and the top surface of the second electrical component.
- In accordance with an embodiment of the present disclosure, a method of manufacturing a semiconductor device package comprises: (a) providing a substrate having a top surface; (b) attaching a first electrical component and a second electrical component on the top surface of the substrate, the second electrical component having a top portion; (c) placing a conductive frame on the top surface of the substrate to cover the first electrical component, the conductive frame including a top portion and a rim substantially perpendicular to the top portion, the top portion having a top surface, the conductive frame defining at least one opening in the top portion of the conductive frame, the least one opening exposing the second electrical component, and the top surface of the top portion of the conductive frame being substantially coplanar with the top surface of the second electrical component; (d) placing an electromagnetic interference shield on the conductive frame in contact with the top surface of the top portion of the conductive frame, an outer lateral surface of the rim of the conductive frame, and the top surface of the second electrical component.
-
FIG. 1A illustrates a cross-sectional view of a semiconductor device package in accordance with an embodiment of the present disclosure. -
FIG. 1B illustrates a top view of a semiconductor device package in accordance with an embodiment of the present disclosure. -
FIG. 2A ,FIG. 2B andFIG. 2C illustrate a manufacturing process in accordance with an embodiment of the present disclosure. - Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. The present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.
- Because EMI shielding in the form of housings or casings increases the size of a semiconductor package, the use of such shielding is counter-indicated for implementation within small semiconductor devices. This disclosure describes techniques for EMI shielding suitable for smaller semiconductor device packages, which additionally reduces manufacturing costs.
-
FIG. 1A illustrates a cross-sectional view of asemiconductor device package 1 in accordance with an embodiment of the present disclosure. Thesemiconductor device package 1 includes asubstrate 10, a plurality of activeelectrical components electrical components conductive frame 14, and anEMI shield 16. - The
substrate 10 has atop surface 101, abottom surface 102 opposite to thetop surface 101 and alateral surface 103. Thelateral surface 103 is at a peripheral edge of thesubstrate 10, and extends between thetop surface 101 and thebottom surface 102. Thesubstrate 10 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. Thesubstrate 10 may include an interconnection structure (not shown inFIG. 1A ), such as a redistribution layer (RDL), for electrical connection between theelectrical components electrical components top surface 101 of thesubstrate 10. - The active
electrical component 12 is mounted on thetop surface 101 of thesubstrate 10. The activeelectrical component 12 may be a flip-chip type semiconductor device. According to another embodiment of the present disclosure, the activeelectrical component 12 may be a wire-bond type semiconductor device. The activeelectrical component 12 may be, for example, an integrated chip (IC) or a die. -
Electrical contacts 12 a of the activeelectrical component 12 are encapsulated by anunderfill 11 which is used to protect theelectrical contacts 12 a. Theunderfill 11 may be, for example, epoxy or other suitable material. - The
electrical components top surface 101 of thesubstrate 10. Theelectrical components electrical component 13 has two electrical contacts (electrodes) 13 a and 13 b, each of which has a surface, respectively 13 a 1, 13b 1. - The
conductive frame 14 has atop portion 141, a rim (fence) 142 and at least onecompartment 143. Thetop portion 141 has atop surface 1411. Therim 142 and thecompartment 143 are substantially perpendicular to thetop portion 141. Theconductive frame 14 is mounted on thetop surface 101 of thesubstrate 10 to cover the activeelectrical components electrical component 33. Thetop portion 141 of theconductive frame 14 has at least oneopening 14 h to expose theelectrical components top surface 1411 of thetop portion 141 of theconductive frame 14 is substantially coplanar with thesurfaces 13 a 1, 13b 1 of the firstelectrical component 13, which is the component which extends vertically the highest in thesemiconductor device package 1, where the term “vertically” refers to the orientation shown inFIG. 1A . Theconductive frame 14 may include one or more metals, or a mixture, an alloy, or other combination thereof. - The
conductive frame 14 is mounted on thetop surface 101 of thesubstrate 10 through aconnection member 17. That is, theconductive frame 14 is electrically connected to a grounding plane of the substrate 19 through theconnection member 17. Theconnection member 17 may be, for example, a conductive bonding material. Theconnection member 17 is separated from the activeelectrical component 12 by a distance D equal to or smaller than about 0.2 millimeter (mm), such as less than or equal to about 0.19 mm, about 0.18 mm, about 0.17 mm, about 0.16 mm, about 0.15 mm, about 0.14 mm, about 0.13 mm, about 0.12 mm, about 0.11 mm, or about 0.1 mm. - The
compartment 143 extends from thetop portion 141 of theconductive frame 14 to separate the activeelectrical component 12 from the activeelectrical component 12′ disposed on thetop surface 101 of thesubstrate 10. Thecompartment 143 reduces the effect on the activeelectrical component 12 of electromagnetic emissions generated by the activeelectrical component 12′ (e.g. EMI or cross-talk), and vice versa. Thecompartment 143 can further separate a first set ofelectrical components electrical components 23 disposed on thetop surface 101 of thesubstrate 10, to reduce the effect on theelectrical components 23 of electromagnetic emissions generated by theelectrical components - A
first pattern 15 may be, for example, barcodes or other recognition codes (e.g., quick response (QR) code) that represent information corresponding to thesemiconductor device package 1, such as a serial number of thesemiconductor device package 1 and a unit number of thesubstrate 10. In one embodiment, afirst pattern 15 can be formed from thetop surface 1411 into thetop portion 141 of theconductive frame 14. In other words, thetop portion 141 of theconductive frame 14 is substantially coplanar with the top surface of thefirst pattern 15 and theEMI shield 16 directly contacts thefirst pattern 15. Thefirst pattern 15 can be formed by, for example, laser techniques or other suitable techniques. - The
EMI shield 16 is disposed on the external surface of theconductive frame 14. TheEMI shield 16 is in contact with thetop surface 1411 of thetop portion 141 of theconductive frame 14, an outerlateral surface 1421 of therim 142 of theconductive frame 14 and thesurfaces 13 a 1, 13b 1 of the firstelectrical component 13. TheEMI shield 16 may be a conductive thin film, and may include, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni) or stainless steel, or a mixture, an alloy, or other combination thereof. Accordingly, theEMI shield 16 and theconductive frame 14 can reduce the effect on the activeelectrical components electrical components semiconductor device package 1 of electromagnetic emissions generated by semiconductor devices outside thesemiconductor package 1. Since theconductive frame 14 is grounded through theconnection member 17, and theEMI shield 16 directly contacts theconductive frame 14, theEMI shield 16 is grounded through theconductive frame 14. - The
EMI shield 16 has atop surface 161, abottom surface 162 opposite to thetop surface 161, and alateral surface 163. In one embodiment, as illustrated inFIG. 1A , thelateral surface 103 of thesubstrate 10 extends horizontally beyond thelateral surface 163 of theEMI shield 16, on one or both sides of thesemiconductor package 1, where the term “horizontally” is with respect to the orientation of thesemiconductor package 1 illustrated byFIG. 1A . In another embodiment, thelateral surface 163 of theEMI shield 16 is substantially coplanar with thelateral surface 103 of thesubstrate 10, on one or both sides of thesemiconductor package 1. In one embodiment, at least oneinsulation pad 173 is formed on thebottom surface 162 of theEMI shield 16 and contacts thesurfaces 13 a 1, 13b 1 of theelectrical component 13, to electrically isolate theEMI shield 16 from thesurfaces 13 a 1, 13b 1 of theelectrical component 13. In another embodiment, thesurfaces 13 a 1, 13b 1 of theelectrical component 13 may be surfaces of electrical insulators positioned oncontacts EMI shield 16 can be in direct contact with thesurfaces 13 a 1, 13b 1 of theelectrical component 13, and the insulation pad(s) 173 may be eliminated. - The
EMI shield 16 may include a single conductive layer. In accordance with another embodiment of the present disclosure, theEMI shield 16 may include several conductive layers formed of the same material or of different materials. In some embodiments, each conductive layer may have a thickness of, for example, up to about 200 μm, up to about 150 μm, up to about 100 μm, up to about 50 μm, up to about 10 μm, up to about 5 μm, up to about 1 μm, or up to about 500 nm, and down to about 100 nm or less, down to about 50 nm or less, or down to about 10 nm or less. - A
second pattern 18 may be, for example, barcodes or other recognition codes that represent information corresponding to thesemiconductor device package 1, such as a shipment number of thesemiconductor package 1. In one embodiment, thesecond pattern 18 can be formed from thetop surface 161 into theEMI shield 16. That is, the top surface of thesecond pattern 18 is coplanar with thetop surface 161 of theEMI shield 16. Thesecond pattern 18 can be formed by, for example, laser techniques or other suitable techniques. - In some embodiments, rather than forming the
first pattern 15 and thesecond pattern 18, a sticker including a barcode other code may be applied. For example, a sticker may be applied to one or both of thetop portion 141 of theconductive frame 14 and thetop surface 161 of theEMI shield 16. However, such a sticker may have a thickness of approximately 0.02 mm, which may result in an increase in a height of thesemiconductor device package 1. Therefore, forming the barcode or other code by using laser techniques can reduce a total height of thesemiconductor device package 1. -
FIG. 1B illustrates a top view of thesemiconductor device package 1 in accordance with an embodiment of the present disclosure. Thesemiconductor device package 1 shown inFIG. 1B is similar to that shown inFIG. 1A , except that theEMI shield 16 is not included. Theopening 14h 1 is formed corresponding to the location of the component extending vertically the highest in thesemiconductor package 1, (e.g.,electrical component 13 inFIG. 1A ), so that thebottom surface 162 of theEMI shield 16 is coplanar with the highest portion of that component. In this way, in embodiments including theEMI shield 16, theEMI shield 16 is placed to cover a top surface of thesemiconductor package device 1 along a plane. By including theopening 14h 1 to expose the top portion of theelectrical component 13, a total height of thesemiconductor device package 1 depicted inFIGS. 1A and 1B may be reduced by at least about 0.25 mm, which may, in turn, reduce manufacturing costs. Theopenings 14 h 2 are formed in theconductive frame 14 taking into consideration a balancing of stresses on theconductive frame 14. -
FIG. 2A ,FIG. 2B andFIG. 2C illustrate a semiconductor manufacturing process in accordance with an embodiment of the present disclosure. - Referring to
FIG. 2A , a partialsemiconductor device package 1 a is illustrated, including asubstrate 10. A plurality of activeelectrical components electrical components top surface 101 of thesubstrate 10. - A
conductive frame 14 is positioned over and mounted on thetop surface 101 of thesubstrate 10 through aconnection member 17. Theconnection member 17 may be, for example, a conductive bonding material. - The
conductive frame 14 has atop portion 141, arim 142 and at least onecompartment 143. Thetop portion 141 has atop surface 1411. Therim 142 and thecompartment 143 are substantially perpendicular to thetop portion 141. Theconductive frame 14 covers the activeelectrical components electrical component 33. Thetop portion 141 of theconductive frame 14 has at least oneopening 14 h to expose theelectrical components top surface 1411 of thetop portion 141 of theconductive frame 14 and thesurfaces 13 a 1, 13b 1 of the firstelectrical component 13, which is the component which extends vertically the highest in thesemiconductor device package 1, are substantially coplanar. - The
compartment 143 extends from thetop portion 141 of theconductive frame 14 to separate the activeelectrical component 12 from the activeelectrical component 12′ disposed on thetop surface 101 of thesubstrate 10, to decrease the amount of electromagnetic emissions of the activeelectrical component 12 reaching the activeelectrical component 12′, and to decrease the amount of electromagnetic emissions of the activeelectrical component 12′ reaching the activeelectrical component 12. In another embodiment, thecompartment 143 can further separate a first set of electrical components (e.g., 13, 33) from a second set of electrical components (e.g., 23) disposed on thetop surface 101 of thesubstrate 10. - The active
electrical components electrical components conductive frame 14 are secured or mounted on thetop surface 101 of thesubstrate 10 by a surface mount technique. Then, a reflow process is performed, for example to form a metallic interconnect phase between under bump metallization and solder. - A first pattern 15 (e.g., one or more barcodes or other recognition codes that represent information of the semiconductor device package 1) may be formed in or on the
conductive frame 14. In one embodiment, thefirst pattern 15 may be formed from thetop surface 1411 into thetop portion 141 of theconductive frame 14 using for example, laser techniques or other suitable techniques. Alternatively, thefirst pattern 15 may be applied, such as by way of a sticker. Thefirst pattern 15 may be scanned, and the scanned pattern or the information it represents may be stored in a storage device (not shown inFIG. 2B ). In some embodiments, a stored image of thefirst pattern 15 may be mapped to relevant information of thesemiconductor device package 1 a. - Referring to
FIG. 2B , an electrically insulating material is injected or dispensed through theopenings 14 h of theconductive frame 14 to form anunderfill 11 to encapsulateelectrical contacts 12 a of the activeelectrical components semiconductor device package 1 b. - Singulation may be performed to divide a strip of
semiconductor device packages 1 b into a plurality of individualsemiconductor device packages 1 b. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting means. - Referring to
FIG. 2C , anEMI shield 16 is formed on the external surface of theconductive frame 14 so as to be in contact with thetop surface 1411 of thetop portion 141 of theconductive frame 14, an outerlateral surface 1421 of therim 142 of theconductive frame 14 and thesurfaces 13 a 1, 13b 1 of theelectrical component 13. - The
EMI shield 16 has atop surface 161 and abottom surface 162 opposite to thetop surface 161. In one embodiment, at least oneinsulation pad 173 is formed on thebottom surface 162 of theEMI shield 16 and is in contact with thesurfaces 13 a 1, 13b 1 of theelectrical component 13, to electrically isolate theEMI shield 16 from thesurfaces 13 a 1, 13b 1 of theelectrical component 13. In another embodiment, thesurfaces 13 a 1, 13b 1 of theelectrical component 13 can be surfaces of an electrical insulator material, and thus theEMI shield 16 can be in direct contact with thesurfaces 13 a 1, 13b 1 of theelectrical component 13, and the insulation pad(s) 173 eliminated. - The
EMI shield 16 may be deposited as a conductive thin film, and may include, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni) or stainless steel, or a mixture, an alloy, or other combination thereof. TheEMI shield 16 may include a single conductive layer. In accordance with another embodiment of the present disclosure, theEMI shield 16 may include several conductive layers of either the same material or different materials. - A second pattern 18 (e.g., barcodes or other codes that correspond to information related to the semiconductor device package 1), is formed or placed on the
top surface 161 of theEMI shield 16. In an embodiment, thesecond pattern 18 can be formed from thetop surface 161 into theEMI shield 16 to form thesemiconductor device package 1 as described and illustrated with reference toFIG. 1A . Thesecond pattern 18 can be formed, for example, using laser techniques or other suitable techniques. - As described with respect to
FIG. 2B , an electrically insulating material is introduced through theopenings 14 h of theconductive frame 14 to form theunderfill 11. Accordingly, theconductive frame 14, the activeelectrical components electrical components conductive frame 14 can be placed and mounted on thetop surface 101 of thesubstrate 10 by a single surface mount process, followed by reflow. By way of contrast, ifconductive frame 14 did not haveopenings 14 h, theunderfill 11 would have to be introduced prior to the placement of theconductive frame 14, and a subsequent second surface mount process and reflow would be included to place theconductive frame 14 on thesubstrate 10. Thus, the use ofopenings 14 h in theconductive frame 14 allows for reduced manufacturing costs. - Additionally, because the
underfill 11 is formed subsequent to the connection of theconductive frame 14 and theconnection member 17, theconnection member 17 may act as a stop for theunderfill 11. By way of contrast, if theconductive frame 14 had noopenings 14 h, theunderfill 11 would be introduced prior to mounting theconductive frame 14 to thesubstrate 10. The semiconductor manufacturing process shown inFIG. 2A ,FIG. 2B andFIG. 2C allows for a distance D between the edge of the activeelectrical component 12 and theconnection member 17 to be less than about 0.2 mm. By contrast, if theconductive frame 14 had noopenings 14 h, so that theunderfill 11 was applied prior to the mounting of theconductive frame 14, a distance which may be more than about 0.55 mm may be reserved from the edge of the activeelectrical component 12 to allow for the horizontal expansion of theunderfill 11. In other words, to prevent theunderfill 11 from expanding to occupy the space where theconnection member 17 is to be formed subsequently, a space of about 0.55 mm or more would be reserved. Thus, the semiconductor manufacturing process shown inFIG. 2A ,FIG. 2B andFIG. 2C may reduce the total width of thesemiconductor device package 1 by at least about 0.35 mm on a side, which can, in turn, reduce manufacturing costs. - As used herein, the terms “substantially,” “substantial,” “approximately,” and “about” are used to denote small variations. For example, the terms can refer to less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along the same plane, such as within 100 μm, within 80 μm, within 60 μm, within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane. Two surfaces or components can be deemed to be “substantially perpendicular” if an angle therebetween is, for example, 90°±10°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°. When used in conjunction with an event or circumstance, the terms “substantially,” “substantial,” “approximately,” and “about” can refer to instances in which the event or circumstance occurs precisely, as well as instances in which the event or circumstance occurs to a close approximation.
- Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It can be understood that such range formats are used for convenience and brevity, and should be understood flexibly to include not only numerical values explicitly specified as limits of a range, but also all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
- While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It can be clearly understood by those skilled in the art that various changes may be made, and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus, due to variables in manufacturing processes and such. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it can be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
Claims (20)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/665,800 US9437576B1 (en) | 2015-03-23 | 2015-03-23 | Semiconductor device package and method of manufacturing the same |
TW105108864A TWI562323B (en) | 2015-03-23 | 2016-03-22 | Semiconductor device package and method of manufacturing the same |
CN201710733607.4A CN107644853B (en) | 2015-03-23 | 2016-03-22 | Semiconductor device package and method of manufacturing the same |
CN201610164166.6A CN105990318B (en) | 2015-03-23 | 2016-03-22 | Semiconductor device packages and its manufacture method |
US15/228,957 US9553072B2 (en) | 2015-03-23 | 2016-08-04 | Semiconductor device package and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/665,800 US9437576B1 (en) | 2015-03-23 | 2015-03-23 | Semiconductor device package and method of manufacturing the same |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/228,957 Continuation US9553072B2 (en) | 2015-03-23 | 2016-08-04 | Semiconductor device package and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US9437576B1 US9437576B1 (en) | 2016-09-06 |
US20160284665A1 true US20160284665A1 (en) | 2016-09-29 |
Family
ID=56878427
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/665,800 Active US9437576B1 (en) | 2015-03-23 | 2015-03-23 | Semiconductor device package and method of manufacturing the same |
US15/228,957 Active US9553072B2 (en) | 2015-03-23 | 2016-08-04 | Semiconductor device package and method of manufacturing the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/228,957 Active US9553072B2 (en) | 2015-03-23 | 2016-08-04 | Semiconductor device package and method of manufacturing the same |
Country Status (3)
Country | Link |
---|---|
US (2) | US9437576B1 (en) |
CN (2) | CN105990318B (en) |
TW (1) | TWI562323B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170245361A1 (en) * | 2016-01-06 | 2017-08-24 | Nokomis, Inc. | Electronic device and methods to customize electronic device electromagnetic emissions |
KR20210022815A (en) * | 2019-08-20 | 2021-03-04 | 삼성디스플레이 주식회사 | Electronic apparatus and method of manufacturing the same |
US11254093B2 (en) * | 2019-02-12 | 2022-02-22 | Samsung Display Co., Ltd. | Liner and display device including the same |
TWI837845B (en) | 2021-09-30 | 2024-04-01 | 日商芝浦機械電子裝置股份有限公司 | Film forming method, resin layer forming device, film forming device, and circuit board with electromagnetic wave shield |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9461001B1 (en) | 2015-07-22 | 2016-10-04 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same |
US9659878B2 (en) * | 2015-10-20 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level shielding in multi-stacked fan out packages and methods of forming same |
TWI622149B (en) | 2017-01-03 | 2018-04-21 | 力成科技股份有限公司 | Manufacturing method of package structure |
TWI612638B (en) * | 2017-01-25 | 2018-01-21 | 矽品精密工業股份有限公司 | Electronic package and method for fabricating the same |
US10950555B2 (en) | 2017-03-30 | 2021-03-16 | Intel Corporation | Ultra-low profile package shielding technique using magnetic and conductive layers for integrated switching voltage regulator |
TWI624915B (en) * | 2017-04-25 | 2018-05-21 | 力成科技股份有限公司 | Packaging structure |
CN107481977B (en) * | 2017-08-21 | 2020-02-07 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level fan-out type packaging structure and packaging method |
US11830859B2 (en) * | 2021-08-30 | 2023-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and method for forming the same |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5917708A (en) * | 1997-03-24 | 1999-06-29 | Qualcomm Incorporated | EMI shield apparatus for printed wiring board |
US5844784A (en) * | 1997-03-24 | 1998-12-01 | Qualcomm Incorporated | Brace apparatus and method for printed wiring board assembly |
US7161252B2 (en) * | 2002-07-19 | 2007-01-09 | Matsushita Electric Industrial Co., Ltd. | Module component |
JP4178880B2 (en) * | 2002-08-29 | 2008-11-12 | 松下電器産業株式会社 | Module parts |
US6781231B2 (en) | 2002-09-10 | 2004-08-24 | Knowles Electronics Llc | Microelectromechanical system package with environmental and interference shield |
US6933173B2 (en) * | 2003-05-30 | 2005-08-23 | Texas Instruments Incorporated | Method and system for flip chip packaging |
JP4453509B2 (en) * | 2004-10-05 | 2010-04-21 | パナソニック株式会社 | High-frequency module with shield case and electronic equipment using this high-frequency module |
US7629674B1 (en) | 2004-11-17 | 2009-12-08 | Amkor Technology, Inc. | Shielded package having shield fence |
JP5051532B2 (en) | 2007-10-18 | 2012-10-17 | 日本電気株式会社 | Electronic component and method for arranging shield case and chip component |
US7683469B2 (en) * | 2008-05-30 | 2010-03-23 | Stats Chippac Ltd. | Package-on-package system with heat spreader |
US20100110656A1 (en) * | 2008-10-31 | 2010-05-06 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US7934306B2 (en) * | 2009-01-12 | 2011-05-03 | Tong Hsing Electric Industries, Ltd. | Method for packaging micro electromechanical systems microphone |
CN101800215B (en) | 2009-02-11 | 2012-07-04 | 日月光半导体制造股份有限公司 | Wireless communication module package structure |
US20100207257A1 (en) * | 2009-02-17 | 2010-08-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
JP5375311B2 (en) * | 2009-04-28 | 2013-12-25 | オムロン株式会社 | Electronic component mounting apparatus and manufacturing method thereof |
US8064202B2 (en) * | 2010-02-24 | 2011-11-22 | Monolithic Power Systems, Inc. | Sandwich structure with double-sided cooling and EMI shielding |
US20110254111A1 (en) * | 2010-04-19 | 2011-10-20 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd | Packaged acoustic transducer device with shielding from electromagnetic interference |
US8551799B2 (en) * | 2010-05-06 | 2013-10-08 | Stmicroelectronics S.R.L. | Encapsulated micro-electro-mechanical device, in particular a MEMS acoustic transducer |
TWI540698B (en) * | 2010-08-02 | 2016-07-01 | 日月光半導體製造股份有限公司 | Semiconductor package and manufacturing method thereof |
CN101937905B (en) * | 2010-08-23 | 2012-09-05 | 日月光半导体制造股份有限公司 | Semiconductor encapsulating part and manufacture method thereof |
US8691626B2 (en) * | 2010-09-09 | 2014-04-08 | Advanced Micro Devices, Inc. | Semiconductor chip device with underfill |
US8861221B2 (en) * | 2010-09-24 | 2014-10-14 | Stats Chippac Ltd. | Integrated circuit packaging system with a shield and method of manufacture thereof |
US8877567B2 (en) * | 2010-11-18 | 2014-11-04 | Stats Chippac, Ltd. | Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die |
US8564125B2 (en) * | 2011-09-02 | 2013-10-22 | Stats Chippac Ltd. | Integrated circuit packaging system with embedded thermal heat shield and method of manufacture thereof |
US8653634B2 (en) * | 2012-06-11 | 2014-02-18 | Advanced Semiconductor Engineering, Inc. | EMI-shielded semiconductor devices and methods of making |
US8987872B2 (en) * | 2013-03-11 | 2015-03-24 | Qualcomm Incorporated | Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages |
US9144183B2 (en) * | 2013-07-31 | 2015-09-22 | Universal Scientific Industrial (Shanghai) Co., Ltd. | EMI compartment shielding structure and fabricating method thereof |
CN104347533B (en) * | 2013-08-01 | 2020-05-26 | 日月光半导体制造股份有限公司 | Semiconductor package and method of manufacturing the same |
-
2015
- 2015-03-23 US US14/665,800 patent/US9437576B1/en active Active
-
2016
- 2016-03-22 CN CN201610164166.6A patent/CN105990318B/en active Active
- 2016-03-22 CN CN201710733607.4A patent/CN107644853B/en active Active
- 2016-03-22 TW TW105108864A patent/TWI562323B/en active
- 2016-08-04 US US15/228,957 patent/US9553072B2/en active Active
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170245361A1 (en) * | 2016-01-06 | 2017-08-24 | Nokomis, Inc. | Electronic device and methods to customize electronic device electromagnetic emissions |
US11254093B2 (en) * | 2019-02-12 | 2022-02-22 | Samsung Display Co., Ltd. | Liner and display device including the same |
KR20210022815A (en) * | 2019-08-20 | 2021-03-04 | 삼성디스플레이 주식회사 | Electronic apparatus and method of manufacturing the same |
KR102652484B1 (en) * | 2019-08-20 | 2024-03-29 | 삼성디스플레이 주식회사 | Electronic apparatus and method of manufacturing the same |
TWI837845B (en) | 2021-09-30 | 2024-04-01 | 日商芝浦機械電子裝置股份有限公司 | Film forming method, resin layer forming device, film forming device, and circuit board with electromagnetic wave shield |
Also Published As
Publication number | Publication date |
---|---|
CN107644853B (en) | 2020-05-15 |
CN107644853A (en) | 2018-01-30 |
US9553072B2 (en) | 2017-01-24 |
TW201642434A (en) | 2016-12-01 |
CN105990318B (en) | 2017-08-22 |
TWI562323B (en) | 2016-12-11 |
US9437576B1 (en) | 2016-09-06 |
US20160343672A1 (en) | 2016-11-24 |
CN105990318A (en) | 2016-10-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9553072B2 (en) | Semiconductor device package and method of manufacturing the same | |
US10784208B2 (en) | Semiconductor package device and method of manufacturing the same | |
US9190367B1 (en) | Semiconductor package structure and semiconductor process | |
US8350367B2 (en) | Semiconductor device packages with electromagnetic interference shielding | |
US7989928B2 (en) | Semiconductor device packages with electromagnetic interference shielding | |
US7829981B2 (en) | Semiconductor device packages with electromagnetic interference shielding | |
US8022511B2 (en) | Semiconductor device packages with electromagnetic interference shielding | |
US8410584B2 (en) | Semiconductor device packages with electromagnetic interference shielding | |
US8212339B2 (en) | Semiconductor device packages with electromagnetic interference shielding | |
US7198987B1 (en) | Overmolded semiconductor package with an integrated EMI and RFI shield | |
US10332848B2 (en) | Semiconductor package device and method of manufacturing the same | |
US11152320B2 (en) | Semiconductor package structure and method of the same | |
US10756025B2 (en) | Semiconductor package device and method of manufacturing the same | |
CN107946287B (en) | Semiconductor packaging device and manufacturing method thereof | |
US20230187387A1 (en) | Semiconductor device package and method of manufacturing the same | |
US10062649B2 (en) | Package substrate | |
US10373883B2 (en) | Semiconductor package device and method of manufacturing the same | |
US11302647B2 (en) | Semiconductor device package including conductive layers as shielding and method of manufacturing the same | |
US10804172B2 (en) | Semiconductor package device with thermal conducting material for heat dissipation | |
US11887967B2 (en) | Semiconductor device package and method of manufacturing the same | |
US20180240738A1 (en) | Electronic package and fabrication method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YANG, TAU-JING;HUANG, KUO-FENG;NIEN, WEI YU;REEL/FRAME:035234/0877 Effective date: 20150312 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |