US20160277032A1 - Power generating circuit, frequency generating circuit and frequency control system - Google Patents
Power generating circuit, frequency generating circuit and frequency control system Download PDFInfo
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- US20160277032A1 US20160277032A1 US14/822,042 US201514822042A US2016277032A1 US 20160277032 A1 US20160277032 A1 US 20160277032A1 US 201514822042 A US201514822042 A US 201514822042A US 2016277032 A1 US2016277032 A1 US 2016277032A1
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- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 230000003247 decreasing effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 4
- 238000001914 filtration Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
- H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
Definitions
- Taiwan Patent Application No. 104108852 filed on Mar. 19, 2015, from which this application claims priority, are incorporated herein by reference.
- the present invention generally relates to a frequency control system, and more particularly to a small-area, low-power and anti-power-noise frequency control system.
- a phase-locked loop is commonly used in electronic devices such as communication devices or computers to detect frequency or phase, or to perform frequency multiplication.
- a delay-locked loop being similar to the PLL, utilizes a delay line instead of a voltage-controlled oscillator, and may be adopted to reduce clock skew in digital circuits.
- a large capacitor is required to implement a filtering circuit in the conventional PLL, and thus occupies large circuit area.
- the conventional PLL or DLL consumes large current and thus cannot be adapted to mobile or hand-held electronic devices. Further, the conventional PLL or DLL is liable to power noise, and therefore suffers low output accuracy.
- a frequency control system includes a power generating circuit and a frequency generating circuit.
- the power generating circuit includes an up transistor circuit, a down transistor circuit and a capacitor, the up transistor circuit and the down transistor circuit being connected in series and having a node situated therebetween, the capacitor being electrically coupled between the node and ground, a stable voltage being generated at the node.
- the frequency generating circuit includes a digital-to-analog converter (DAC), a current source/sink circuit, a voltage-controlled oscillator (VCO) and a digital controller.
- DAC digital-to-analog converter
- VCO voltage-controlled oscillator
- the DAC receives the stable voltage as a power, and outputs an analog signal;
- the current source/sink circuit receives the analog signal and outputs a control voltage;
- the VCO receives the control voltage and according generates a frequency signal;
- the digital controller receives the frequency signal and a reference signal, according to which a digital signal is generated and fed to an input end of the DAC.
- FIG. 1 shows a block diagram illustrating a frequency control system according to one embodiment of the present invention
- FIG. 2A to FIG. 2C show circuit diagrams exemplifying the up transistor circuit and the down transistor circuit of FIG. 1 ;
- FIG. 3 shows an equivalent circuit diagram of the power generating circuit of FIG. 1 ;
- FIG. 4 shows a circuit diagram illustrating the voltage-controlled oscillator of FIG. 1 ;
- FIG. 5A shows a flow diagram of the digital controller of FIG. 1 ;
- FIG. 5B shows a timing diagram exemplifying a reference signal and a frequency signal.
- FIG. 1 shows a block diagram illustrating a frequency control system 100 according to one embodiment of the present invention.
- the frequency control system 100 includes a power generating circuit 11 and a frequency generating circuit 12 .
- the power generating circuit 11 generates a stable voltage V LPF , which is provided as a power to a portion of the frequency generating circuit 12 .
- the frequency generating circuit 12 also called frequency multiplication circuit, is used to generate a frequency signal F OUT .
- the power generating circuit 11 of the embodiment may include an up transistor circuit 111 and a down transistor circuit 112 , which are connected in series and electrically coupled between an original power VDD and ground.
- a node P is situated between the up transistor circuit 111 and the down transistor circuit 112 .
- the up transistor circuit 111 and the down transistor circuit 112 constitute a voltage divider, which provides the table voltage V LPF at the node P.
- the up transistor circuit 111 may include at least one transistor such as a P-type metal-oxide-semiconductor (MOS) transistor, and the down transistor circuit 112 may include at least one transistor such as an N-type MOS transistor.
- the power generating circuit 11 may further include a capacitor C LPF , which is electrically coupled between the node P and ground.
- the transistors of the up transistor circuit 111 and the down transistor circuit 112 may be diode-connected, or may operate in a cut-off or sub-threshold region.
- diode-connected means connecting a drain and a gate of the transistor.
- Operating in a cut-off region or sub-threshold region means connecting a source and a gate of the transistor.
- FIG. 2A shows a circuit diagram exemplifying the up transistor circuit 111 and the down transistor circuit 112 of FIG. 1 .
- the up transistor circuit 111 and the down transistor circuit 112 each includes a diode-connected transistor.
- FIG. 2B shows another circuit diagram exemplifying the up transistor circuit 111 and the down transistor circuit 112 of FIG. 1 .
- the up transistor circuit 111 and the down transistor circuit 112 each includes a transistor that operates in a cut-off region.
- FIG. 2C shows a further circuit diagram exemplifying the up transistor circuit 111 and the down transistor circuit 112 of FIG. 1 .
- the up transistor circuit 111 includes two diode-connected transistors that are connected in series
- the down transistor circuit 112 includes a transistor operating in a cut-off region and a diode-connected transistor, which are connected in series.
- FIG. 3 shows an equivalent circuit diagram of the power generating circuit 11 .
- the diode-connected transistor or the transistor operating in a cut-off region or sub-threshold region of the up transistor circuit 111 may be equivalent to an up equivalent resistor R U with large resistance (e.g., millions to trillions ohms).
- the down transistor circuit 112 may be equivalent to a down equivalent resistor R D with large resistance.
- the up equivalent resistor R U and the down equivalent resistor R D constitute a low-pass filter (LPF), which filters out noise of the original power VDD, therefore generating the stable voltage V LPF with reduced noise or even without noise.
- LPF low-pass filter
- the original power VDD may possess noise spanning from high frequency to low frequency. Accordingly, it is preferred in the embodiment to select a substantially low cut-off frequency f C .
- f C 1/(2 ⁇ RC)
- the resistance R of the up equivalent resistor R U and the capacitance C of the capacitor C LPF should be large. As a capacitor in an integrated circuit occupies a substantial area, the capacitance of the capacitor should not be large.
- the up equivalent resistor R U of the embodiment has large resistance; a low cut-off frequency f C can thus be obtained with low capacitance of the capacitor C LPF .
- the up equivalent resistor R U of the embodiment is made up of transistor(s), which occupy a small circuit area.
- a resistor for example, a poly resistor, using 0.18 ⁇ m complementary metal-oxide-semiconductor (CMOS) process, occupies 100000 ⁇ m 2 .
- CMOS complementary metal-oxide-semiconductor
- a transistor that is diode-connected or operates in a cut-off region or sub-threshold region with width of 0.3 ⁇ m and length of 10 ⁇ m may result in tens of millions ohms.
- the frequency generating circuit 12 may include a first unity-gain buffer 121 , also called voltage follower, which receives the stable voltage V LPF generated from the power generating circuit 11 , and feeds the stable voltage V LPF as a power to a digital-to-analog converter (DAC) 122 .
- the first unity-gain buffer 121 may include an operational amplifier (OP) having an output end connected to an inverting input end, and a non-inverting input end receiving the stable voltage V LPF .
- the operational amplifier may use the original power VDD as a power.
- the stable voltage V LPF generated from the power generating circuit 11 is directly provided as a power to the DAC 122 without using the first unity-gain buffer 121 .
- the frequency generating circuit 12 may further include a current source/sink circuit 123 , which receives an analog signal A outputted from the DAC 122 , and outputs a control voltage V C to control a voltage-controlled oscillator (VCO) 124 .
- the current source/sink circuit 123 may include a second unity-gain buffer, which may compose a structure the same as the first unity-gain buffer 121 , details of which are thus omitted for brevity.
- the VCO 124 receives the control voltage V C outputted from the current source/sink circuit 123 , and accordingly generates the frequency signal F OUT .
- FIG. 4 shows a circuit diagram illustrating the VCO 124 of FIG. 1 .
- the VCO 124 of the embodiment may include a plurality of (e.g., odd number of) inverters 1241 , which are connected in parallel to form a ring oscillator.
- Each inverter 1241 includes series-connected P-type transistor and N-type transistor, which are electrically coupled between the control voltage V C and ground.
- the frequency of the frequency signal F OUT may be increased by raising the control voltage V C , and may be decreased by lowering the control voltage V C .
- the frequency generating circuit 12 may further include a digital controller 125 , which receives the frequency signal F OUT (e.g., with high frequency) and a reference signal F IN (e.g., with low frequency), according to which a digital signal D is generated and fed to an input end of the DAC 122 , thereby controlling the DAC 122 to increase or decrease the analog signal A (or the control voltage V C ). Accordingly, the frequency of the frequency signal F OUT may thus be controlled.
- the reference signal F IN may be provided by a crystal oscillator (not shown) or other reference-frequency generators.
- the digital controller 125 may be powered by the original power VDD.
- FIG. 5A shows a flow diagram of the digital controller 125 of FIG. 1 .
- the reference signal F IN and the frequency signal F OUT are inputted.
- FIG. 5B shows a timing diagram exemplifying a low-frequency reference signal F IN and a high-frequency frequency signal F OUT .
- the frequency signal F OUT are counted to result in an amount, which is then compared with a predetermined number N. If the amount is equal to N, proceed to step 53 , in which the digital signal D (or the control voltage V C ) is maintained.
- step 54 in which the digital signal D is changed to adjust the control voltage V C . For example, if the amount is less than the predetermined N, the digital signal D is increased; if the amount is greater than the predetermined N, the digital signal D is decreased.
- the power generating circuit 11 may generate an anti-power-noise stable voltage V LPF , such that the operation of the frequency generating circuit 12 (particularly the DAC 122 ) may not be liable to power noise.
- the up transistor circuit 111 and the down transistor circuit 112 with high resistance are made up of transistors, they occupy small circuit area.
- a large capacitor is required to implement a filtering circuit in the conventional PLL.
- the composing blocks of the frequency control system 100 of the embodiment consume low power. For an output frequency of 72 mega Hz using 0.18 ⁇ m process, for example, each composing block consumes a current of about 10 ⁇ A and an entire system consumes a current less than 100 ⁇ A.
- the conventional PLL or DLL using the same process will consume a current of about 1 mA.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Oscillators With Electromechanical Resonators (AREA)
Abstract
Description
- The entire contents of Taiwan Patent Application No. 104108852, filed on Mar. 19, 2015, from which this application claims priority, are incorporated herein by reference.
- 1. Field of the Invention
- The present invention generally relates to a frequency control system, and more particularly to a small-area, low-power and anti-power-noise frequency control system.
- 2. Description of Related Art
- A phase-locked loop (PLL) is commonly used in electronic devices such as communication devices or computers to detect frequency or phase, or to perform frequency multiplication. A delay-locked loop (DLL), being similar to the PLL, utilizes a delay line instead of a voltage-controlled oscillator, and may be adopted to reduce clock skew in digital circuits.
- A large capacitor is required to implement a filtering circuit in the conventional PLL, and thus occupies large circuit area. Moreover, the conventional PLL or DLL consumes large current and thus cannot be adapted to mobile or hand-held electronic devices. Further, the conventional PLL or DLL is liable to power noise, and therefore suffers low output accuracy.
- A need has thus arisen to propose a novel frequency control system to overcome disadvantages of conventional systems, and may be adapted to mobile or hand-held electronic devices having limited resources or being liable to noise.
- In view of the foregoing, it is an object of the embodiment of the present invention to provide a frequency control system to reduce the effect of power noise, to decrease circuit area and/or to cut down power consumption.
- According to one embodiment, a frequency control system includes a power generating circuit and a frequency generating circuit. The power generating circuit includes an up transistor circuit, a down transistor circuit and a capacitor, the up transistor circuit and the down transistor circuit being connected in series and having a node situated therebetween, the capacitor being electrically coupled between the node and ground, a stable voltage being generated at the node. The frequency generating circuit includes a digital-to-analog converter (DAC), a current source/sink circuit, a voltage-controlled oscillator (VCO) and a digital controller. The DAC receives the stable voltage as a power, and outputs an analog signal; the current source/sink circuit receives the analog signal and outputs a control voltage; the VCO receives the control voltage and according generates a frequency signal; and the digital controller receives the frequency signal and a reference signal, according to which a digital signal is generated and fed to an input end of the DAC.
-
FIG. 1 shows a block diagram illustrating a frequency control system according to one embodiment of the present invention; -
FIG. 2A toFIG. 2C show circuit diagrams exemplifying the up transistor circuit and the down transistor circuit ofFIG. 1 ; -
FIG. 3 shows an equivalent circuit diagram of the power generating circuit ofFIG. 1 ; -
FIG. 4 shows a circuit diagram illustrating the voltage-controlled oscillator ofFIG. 1 ; -
FIG. 5A shows a flow diagram of the digital controller ofFIG. 1 ; and -
FIG. 5B shows a timing diagram exemplifying a reference signal and a frequency signal. -
FIG. 1 shows a block diagram illustrating afrequency control system 100 according to one embodiment of the present invention. In the embodiment, thefrequency control system 100 includes apower generating circuit 11 and afrequency generating circuit 12. Specifically, thepower generating circuit 11 generates a stable voltage VLPF, which is provided as a power to a portion of thefrequency generating circuit 12. The frequency generatingcircuit 12, also called frequency multiplication circuit, is used to generate a frequency signal FOUT. - The
power generating circuit 11 of the embodiment may include an uptransistor circuit 111 and adown transistor circuit 112, which are connected in series and electrically coupled between an original power VDD and ground. A node P is situated between the uptransistor circuit 111 and thedown transistor circuit 112. The uptransistor circuit 111 and thedown transistor circuit 112 constitute a voltage divider, which provides the table voltage VLPF at the node P. The uptransistor circuit 111 may include at least one transistor such as a P-type metal-oxide-semiconductor (MOS) transistor, and thedown transistor circuit 112 may include at least one transistor such as an N-type MOS transistor. Thepower generating circuit 11 may further include a capacitor CLPF, which is electrically coupled between the node P and ground. - In the embodiment, the transistors of the up
transistor circuit 111 and thedown transistor circuit 112 may be diode-connected, or may operate in a cut-off or sub-threshold region. In the specification, diode-connected means connecting a drain and a gate of the transistor. Operating in a cut-off region or sub-threshold region means connecting a source and a gate of the transistor.FIG. 2A shows a circuit diagram exemplifying the uptransistor circuit 111 and thedown transistor circuit 112 ofFIG. 1 . In this example, the uptransistor circuit 111 and thedown transistor circuit 112 each includes a diode-connected transistor.FIG. 2B shows another circuit diagram exemplifying the uptransistor circuit 111 and thedown transistor circuit 112 ofFIG. 1 . In this example, the uptransistor circuit 111 and thedown transistor circuit 112 each includes a transistor that operates in a cut-off region.FIG. 2C shows a further circuit diagram exemplifying the uptransistor circuit 111 and thedown transistor circuit 112 ofFIG. 1 . In this example, the uptransistor circuit 111 includes two diode-connected transistors that are connected in series, and thedown transistor circuit 112 includes a transistor operating in a cut-off region and a diode-connected transistor, which are connected in series. -
FIG. 3 shows an equivalent circuit diagram of thepower generating circuit 11. The diode-connected transistor or the transistor operating in a cut-off region or sub-threshold region of the uptransistor circuit 111 may be equivalent to an up equivalent resistor RU with large resistance (e.g., millions to trillions ohms). Similarly, thedown transistor circuit 112 may be equivalent to a down equivalent resistor RD with large resistance. The up equivalent resistor RU and the down equivalent resistor RD constitute a low-pass filter (LPF), which filters out noise of the original power VDD, therefore generating the stable voltage VLPF with reduced noise or even without noise. - In general, the original power VDD may possess noise spanning from high frequency to low frequency. Accordingly, it is preferred in the embodiment to select a substantially low cut-off frequency fC. According to the relationship of fC=1/(2πRC), the resistance R of the up equivalent resistor RU and the capacitance C of the capacitor CLPF should be large. As a capacitor in an integrated circuit occupies a substantial area, the capacitance of the capacitor should not be large. As mentioned above, the up equivalent resistor RU of the embodiment has large resistance; a low cut-off frequency fC can thus be obtained with low capacitance of the capacitor CLPF.
- As discussed above, the up equivalent resistor RU of the embodiment is made up of transistor(s), which occupy a small circuit area. By the contrary, a resistor, for example, a poly resistor, using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process, occupies 100000 μm2. For the same process, a transistor that is diode-connected or operates in a cut-off region or sub-threshold region with width of 0.3 μm and length of 10 μm may result in tens of millions ohms.
- Referring to
FIG. 1 , thefrequency generating circuit 12 may include a first unity-gain buffer 121, also called voltage follower, which receives the stable voltage VLPF generated from thepower generating circuit 11, and feeds the stable voltage VLPF as a power to a digital-to-analog converter (DAC) 122. In the embodiment, the first unity-gain buffer 121 may include an operational amplifier (OP) having an output end connected to an inverting input end, and a non-inverting input end receiving the stable voltage VLPF. The operational amplifier may use the original power VDD as a power. In another embodiment, the stable voltage VLPF generated from thepower generating circuit 11 is directly provided as a power to theDAC 122 without using the first unity-gain buffer 121. - The
frequency generating circuit 12 may further include a current source/sink circuit 123, which receives an analog signal A outputted from theDAC 122, and outputs a control voltage VC to control a voltage-controlled oscillator (VCO) 124. In the embodiment, the current source/sink circuit 123 may include a second unity-gain buffer, which may compose a structure the same as the first unity-gain buffer 121, details of which are thus omitted for brevity. - The
VCO 124 receives the control voltage VC outputted from the current source/sink circuit 123, and accordingly generates the frequency signal FOUT.FIG. 4 shows a circuit diagram illustrating theVCO 124 ofFIG. 1 . TheVCO 124 of the embodiment may include a plurality of (e.g., odd number of)inverters 1241, which are connected in parallel to form a ring oscillator. Eachinverter 1241 includes series-connected P-type transistor and N-type transistor, which are electrically coupled between the control voltage VC and ground. The frequency of the frequency signal FOUT may be increased by raising the control voltage VC, and may be decreased by lowering the control voltage VC. - The
frequency generating circuit 12 may further include adigital controller 125, which receives the frequency signal FOUT (e.g., with high frequency) and a reference signal FIN (e.g., with low frequency), according to which a digital signal D is generated and fed to an input end of theDAC 122, thereby controlling theDAC 122 to increase or decrease the analog signal A (or the control voltage VC). Accordingly, the frequency of the frequency signal FOUT may thus be controlled. In one embodiment, the reference signal FIN may be provided by a crystal oscillator (not shown) or other reference-frequency generators. Thedigital controller 125 may be powered by the original power VDD. -
FIG. 5A shows a flow diagram of thedigital controller 125 ofFIG. 1 . First, instep 51, the reference signal FIN and the frequency signal FOUT are inputted.FIG. 5B shows a timing diagram exemplifying a low-frequency reference signal FIN and a high-frequency frequency signal FOUT. Subsequently, instep 52, during a period of the reference signal FIN, the frequency signal FOUT are counted to result in an amount, which is then compared with a predetermined number N. If the amount is equal to N, proceed to step 53, in which the digital signal D (or the control voltage VC) is maintained. If the amount is not equal to N, proceed to step 54, in which the digital signal D is changed to adjust the control voltage VC. For example, if the amount is less than the predetermined N, the digital signal D is increased; if the amount is greater than the predetermined N, the digital signal D is decreased. - According to the embodiment discussed above, the
power generating circuit 11 may generate an anti-power-noise stable voltage VLPF, such that the operation of the frequency generating circuit 12 (particularly the DAC 122) may not be liable to power noise. Moreover, as the uptransistor circuit 111 and thedown transistor circuit 112 with high resistance are made up of transistors, they occupy small circuit area. By contrary, a large capacitor is required to implement a filtering circuit in the conventional PLL. Further, the composing blocks of thefrequency control system 100 of the embodiment consume low power. For an output frequency of 72 mega Hz using 0.18 μm process, for example, each composing block consumes a current of about 10 μA and an entire system consumes a current less than 100 μA. On the contrary, the conventional PLL or DLL using the same process will consume a current of about 1 mA. - Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.
Claims (26)
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TW104108852A TWI565244B (en) | 2015-03-19 | 2015-03-19 | Power generating circuit, frequency generating circuit and frequency control system |
TW104108852A | 2015-03-19 | ||
TW104108852 | 2015-03-19 |
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US9432027B1 US9432027B1 (en) | 2016-08-30 |
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US11569838B2 (en) | 2020-04-09 | 2023-01-31 | Analog Devices International Unlimited Company | High efficiency current source/sink DAC |
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JPS59218042A (en) * | 1983-05-26 | 1984-12-08 | Toshiba Corp | Semiconductor integrated circuit |
US5684481A (en) * | 1994-03-18 | 1997-11-04 | Analog Devices | Rail-to-rail DAC drive circuit |
JPH11103015A (en) * | 1997-09-26 | 1999-04-13 | Sanyo Electric Co Ltd | Semiconductor device |
JP4046752B2 (en) * | 2006-05-09 | 2008-02-13 | シャープ株式会社 | POWER CIRCUIT DEVICE AND ELECTRONIC DEVICE HAVING THE POWER CIRCUIT DEVICE |
US8334725B2 (en) * | 2007-04-11 | 2012-12-18 | Mediatek Inc. | Circuit and method for controlling mixed mode controlled oscillator and CDR circuit using the same |
JP2009005288A (en) * | 2007-06-25 | 2009-01-08 | Sanyo Electric Co Ltd | Clock generating circuit |
US7777577B2 (en) * | 2007-09-28 | 2010-08-17 | Texas Instruments Incorporated | Dual path phase locked loop (PLL) with digitally programmable damping |
TWI344754B (en) * | 2008-03-28 | 2011-07-01 | Faraday Tech Corp | Tuning circuit, integrated circuit applying the same, and signal filtering method |
JP5247513B2 (en) * | 2009-02-12 | 2013-07-24 | 株式会社沖データ | Power supply device and image forming apparatus |
JP5760697B2 (en) * | 2010-10-27 | 2015-08-12 | 日本電波工業株式会社 | Signal level adjusting device and high frequency equipment |
JP5665571B2 (en) * | 2011-01-28 | 2015-02-04 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit and operation method thereof |
US8362848B2 (en) * | 2011-04-07 | 2013-01-29 | Qualcomm Incorporated | Supply-regulated VCO architecture |
US8878614B2 (en) * | 2012-02-28 | 2014-11-04 | Megachips Corporation | Phase-locked loop |
EP2796945A1 (en) * | 2013-04-24 | 2014-10-29 | Asahi Kasei Microdevices Corporation | Time-to-digital conversion with analog dithering |
US9595955B2 (en) * | 2014-08-08 | 2017-03-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including power storage elements and switches |
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US11569838B2 (en) | 2020-04-09 | 2023-01-31 | Analog Devices International Unlimited Company | High efficiency current source/sink DAC |
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CN106160734A (en) | 2016-11-23 |
TWI565244B (en) | 2017-01-01 |
US9432027B1 (en) | 2016-08-30 |
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