US20160203982A1 - Method of forming trenches - Google Patents
Method of forming trenches Download PDFInfo
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- US20160203982A1 US20160203982A1 US14/636,200 US201514636200A US2016203982A1 US 20160203982 A1 US20160203982 A1 US 20160203982A1 US 201514636200 A US201514636200 A US 201514636200A US 2016203982 A1 US2016203982 A1 US 2016203982A1
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000000463 material Substances 0.000 claims abstract description 47
- 125000006850 spacer group Chemical group 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 38
- 241000206607 Porphyra umbilicalis Species 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 239000012044 organic layer Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 19
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
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- -1 SiON Chemical compound 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000003610 charcoal Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 238000004377 microelectronic Methods 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Definitions
- the present invention is related to a method of forming trenches, and more particularly, to a method of forming trenches by using reverse sidewall image transfer (reverse STI) technology.
- reverse STI reverse sidewall image transfer
- the integrated circuit layout is first designed and formed as a photo-mask pattern.
- the photo-mask pattern is then proportionally transferred to a photoresist layer positioned on the semiconductor wafer.
- the present invention therefore provides a method of forming trenches with smaller size and a width of the formed trench can be controlled precisely.
- the present invention provides a method of forming trenches.
- a mandrel layer is formed on a substrate, wherein the mandrel layer comprises a stop layer and a sacrificial layer.
- a spacer is formed on at least a sidewall of the mandrel layer, following by forming a material layer on the substrate for covering the spacer and the mandrel layer. After performing a removing process to remove apart of the material layer, a part of the spacer and the sacrificial layer; the spacer is removed to form at least one first trench in the remaining material layer and the mandrel.
- the present invention provides a method of forming trenches.
- the width of the trench can be accurately formed.
- a CMP process is preferably used to increase the reliability of the manufacturing process and to improve product yield.
- FIG. 1 to FIG. 10 show schematic diagrams of method of forming trenches according to one embodiment of the present invention.
- a substrate 300 is provided to serve as a base for forming devices, components, or circuits.
- the substrate 300 is preferably composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layered materials thereof.
- the semiconductor substrate 300 may also be composed of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs.
- the semiconductor substrate 300 is depicted as a bulk semiconductor substrate, the arrangement of a semiconductor on an insulator substrate, such as silicon-on-insulator (SOI) substrates, is also suitable for the semiconductor substrate 300 .
- the substrate 300 can include one or a plurality of dielectric layers in which one or a plurality of microelectronic components are disposed therein, such as a complementary metal oxide semiconductor (CMOS) or a photo-diode, or even a metal interconnection system.
- CMOS complementary metal oxide semiconductor
- photo-diode or even a metal interconnection system.
- the substrate 300 can include a mask layer (not shown) or a material layer (not shown) so other semiconductor manufacturing process can be performed followed by the method of forming trenches of the present invention to form devices in the substrate 300 , for example, a dual sidewall image transfer (dual SIT) process.
- a liner layer 302 and a mask layer 304 can be formed sequentially on the substrate 300 .
- the mask layer 304 can be any material that is suitable for severing as a mask in an etching process, such as SiN, SiON, SiC or advanced pattern film (APF) provided by Applied Material Corporation.
- the liner layer 302 is used to provide additional adhesion or buffer between the substrate 300 and the mask layer 304 .
- the liner layer 302 can be SiO 2 , but is not limited thereto. In another embodiment, the liner layer 302 can be omitted.
- the mandrel layer 312 is formed on the mask layer 304 .
- the mandrel layer 312 comprises a sacrificial layer 310 , a stop layer 308 and a support layer 306 .
- the sacrificial layer 306 includes poly-silicon or amorphous silicon;
- the stop layer 308 includes silicon nitride (SiN), silicon oxynitride (SiON), titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof;
- the support layer 306 includes a material the same or different from that of the sacrificial layer 310 . In one embodiment, the support layer 306 may be omitted.
- the method of forming the mandrel layer 312 includes forming a support material layer (not shown), a stop material layer (not shown) and a sacrificial material layer (not shown) sequentially on the substrate 300 , and performing a photo-etching-process (PEP) to pattern said mandrel layer 312 , which therefore comprises at least one vertically aligned sidewall.
- the support layer 306 has a first thickness T 1
- the stop layer 308 has a second thickness T 2
- the sacrificial layer 310 has a third thickness T 3 .
- a spacer material layer 313 is formed conformally on the mandrel layer 312 , to preferably cover a sidewall and a top surface of the mandrel layer 312 .
- the spacer material layer 313 includes, for example, silicon oxide, silicon nitride, high temperature oxide (HTO) or silicon nitride formed with hexachlorodisilane (Si 2 Cl 6 ) (“HCD-SiN”), but is not limited thereto.
- an anisotropical etch step is performed to form the spacer layer 314 .
- the spacer layer 314 is formed only on the sidewalls of the mandrel layer 312 .
- the spacer 314 has a curved cross-section with a width increasing from top to bottom.
- spacer 314 with a predetermined thickness remains on the top surface of the mandrel 312 .
- the anisotropic etching step can be omitted so the spacer 314 on the sidewall of the mandrel 312 has a uniform thickness.
- a material layer 316 is formed comprehensively on the substrate 300 .
- the material layer 316 is filled into the space between each mandrel layer 312 , therefore covering the spacer 314 and the mandrel layer 312 .
- the material layer 316 is made of different material from that of the stop layer 308 in the mandrel layer 312 , so the removing speeds of the material layer 316 and the stop layer 308 are significantly different in one removing process.
- the material layer 316 for example, includes silicon oxide, silicon nitride or organic material such as photoresist, and is not limited thereto.
- a removing process is carried out for removing a part of the material layer 316 , a part of the spacer 314 and complete removing the sacrificial layer 310 .
- the removing process stops on the stop layer 308 in the mandrel layer 312 and preferably does not remove or removes a very small portion of the stop layer 308 .
- the removing speed of the stop layer 308 in the removing process is much smaller than those of the material layer 316 , the spacer 314 and the sacrificial layer 310 .
- the removing process includes a chemical mechanical polishing (CMP) step
- the stop layer 308 has a polishing selectivity with respected to the material layer 316 , the spacer 314 and the sacrificial layer 310 .
- CMP chemical mechanical polishing
- a top surface of the remaining material layer 316 ′ is leveled with a top surface of the spacer 314 ′ and a top surface of the stop layer 308 .
- the spacer 314 ′ has a width W in the top surface and a width W′ in the bottom surface, wherein the width W is smaller than the width W. It is noted that when in the embodiment that the anisotropical etching process is omitted, the width W is substantially equal to the width W′, as shown in FIG. 7 .
- the spacer 314 ′ is completely removed, and a first trench 318 is formed between the mandrel layer 312 (including the stop layer 308 , or the stop layer 308 and the support layer 306 ) and the material layer 316 ′.
- the mask layer 304 is exposed by the first trench 318 .
- the material of the spacer 314 ′ preferably has a removing selectivity with respect to the stop layer 308 , the material layer 318 ′, as well as the mask layer 304 .
- the formed first trench 318 has a shape corresponding to the contour of the spacer 314 ′.
- the first trench 318 can have a width W at the opening and a width W′ in the bottom surface. In the present embodiment, the width W is smaller than the width W′.In another embodiment of FIG. 7 , they may be equal.
- the mask layer 304 and the liner layer 302 are patterned, forming a second trench 320 in the mask layer 304 and the liner layer 302 .
- the second trench 320 corresponds to the first trench 318 .
- the second trench 320 has a width W. Then, the material layer 316 ′ and the mandrel layer 312 are completely removed.
- the substrate 300 is patterned, thereby forming at least one third trench 322 in the substrate 300 .
- the third trench 322 has a width W.
- the third trench 322 can be used as a part of various semiconductor elements, e.g., a shallow trench isolation (STI) by filling an insulating material therein, or a metal interconnection system by filling a metal therein.
- STI shallow trench isolation
- the formed third trench 322 can be subjected to other semiconductor process depending on the design of the product or the process.
- a spacer can be formed on the sidewall of the third trench 322 and an etching process can be performed by to pattern the substrate, so a trench with finer width can be obtained.
- a material layer can be filled into the third trench 322 and the substrate 300 other than the material layer is removed, such that the material layer can be used as a part of a semiconductor device.
- the removing process preferably comprises chemical mechanical polishing process. Comparing to conventional etching back process, a more flat surface can be obtained and the width W of the spacer 314 ′ can be obtained predictably. Therefore, the first trench 318 , the second trench 320 and the third trench 322 can also include the width W.
- the width W of the spacer 314 ′ in FIG. 6 can be well controlled.
- a ratio of the height of the top surface of the stop layer 308 (T 1 +T 2 ) and the total height of the mandrel layer 312 (T 1 +T 2 +T 3 ) is substantially equal to a ratio of the width W of the top surface of the spacer 314 ′ and the width W′ of the bottom surface of the spacer 314 ′.
- the mask layer 304 and the liner layer 302 can be omitted.
- the removing process in FIG. 6 can directly use the material layer 316 ′ and the stop layer 308 as a mask to pattern the substrate 300 , thereby forming the third trench 322 .
- the present invention provides a method of forming trenches.
- the width of the trench can be accurately formed.
- a CMP process is preferably used to increase the reliability of the manufacturing process and to improve product yield.
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Abstract
Description
- 1. Field of the Invention
- The present invention is related to a method of forming trenches, and more particularly, to a method of forming trenches by using reverse sidewall image transfer (reverse STI) technology.
- 2. Description of the Prior Art
- In semiconductor manufacturing processes, in order to transfer an integrated circuit layout onto a semiconductor wafer, the integrated circuit layout is first designed and formed as a photo-mask pattern. The photo-mask pattern is then proportionally transferred to a photoresist layer positioned on the semiconductor wafer.
- In recent years, with the increasing miniaturization of semiconductor devices, the design rule of line width and space between lines or devices becomes finer, for example down to feature sizes of 65 nanometers (nm), 45 nm and even to 32 nm, making the spacer between semiconductor devices smaller. However, due to the optical proximity effect, the spacer is about to meet the physical restriction in a lithography process. Hence, the researchers are devoted to develop methods to form semiconductor devices with finer size.
- The present invention therefore provides a method of forming trenches with smaller size and a width of the formed trench can be controlled precisely.
- According to one embodiment, the present invention provides a method of forming trenches. First, a mandrel layer is formed on a substrate, wherein the mandrel layer comprises a stop layer and a sacrificial layer. A spacer is formed on at least a sidewall of the mandrel layer, following by forming a material layer on the substrate for covering the spacer and the mandrel layer. After performing a removing process to remove apart of the material layer, a part of the spacer and the sacrificial layer; the spacer is removed to form at least one first trench in the remaining material layer and the mandrel.
- The present invention provides a method of forming trenches. By using the multi-layered mandrel layer, the width of the trench can be accurately formed. A CMP process is preferably used to increase the reliability of the manufacturing process and to improve product yield.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 toFIG. 10 show schematic diagrams of method of forming trenches according to one embodiment of the present invention. - To provide a better understanding of the presented invention, preferred embodiments will be made in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.
- Please refer to
FIG. 1 toFIG. 10 , which show schematic diagrams of method of forming trenches according to one embodiment of the present invention. As shown inFIG. 1 , asubstrate 300 is provided to serve as a base for forming devices, components, or circuits. Thesubstrate 300 is preferably composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layered materials thereof. Thesemiconductor substrate 300 may also be composed of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs. Although thesemiconductor substrate 300 is depicted as a bulk semiconductor substrate, the arrangement of a semiconductor on an insulator substrate, such as silicon-on-insulator (SOI) substrates, is also suitable for thesemiconductor substrate 300. In another embodiment, thesubstrate 300 can include one or a plurality of dielectric layers in which one or a plurality of microelectronic components are disposed therein, such as a complementary metal oxide semiconductor (CMOS) or a photo-diode, or even a metal interconnection system. In another embodiment, thesubstrate 300 can include a mask layer (not shown) or a material layer (not shown) so other semiconductor manufacturing process can be performed followed by the method of forming trenches of the present invention to form devices in thesubstrate 300, for example, a dual sidewall image transfer (dual SIT) process. After providing thesubstrate 300, aliner layer 302 and amask layer 304 can be formed sequentially on thesubstrate 300. Themask layer 304 can be any material that is suitable for severing as a mask in an etching process, such as SiN, SiON, SiC or advanced pattern film (APF) provided by Applied Material Corporation. Theliner layer 302 is used to provide additional adhesion or buffer between thesubstrate 300 and themask layer 304. In one embodiment, theliner layer 302 can be SiO2, but is not limited thereto. In another embodiment, theliner layer 302 can be omitted. - As shown in
FIG. 2 , at least onemandrel layer 312 is formed on themask layer 304. In one embodiment, themandrel layer 312 comprises asacrificial layer 310, astop layer 308 and asupport layer 306. In one embodiment, thesacrificial layer 306 includes poly-silicon or amorphous silicon; thestop layer 308 includes silicon nitride (SiN), silicon oxynitride (SiON), titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof; thesupport layer 306 includes a material the same or different from that of thesacrificial layer 310. In one embodiment, thesupport layer 306 may be omitted. The method of forming themandrel layer 312, for example, includes forming a support material layer (not shown), a stop material layer (not shown) and a sacrificial material layer (not shown) sequentially on thesubstrate 300, and performing a photo-etching-process (PEP) to pattern saidmandrel layer 312, which therefore comprises at least one vertically aligned sidewall. In one embodiment, thesupport layer 306 has a first thickness T1, thestop layer 308 has a second thickness T2, and thesacrificial layer 310 has a third thickness T3. - Next, as shown in
FIG. 3 , aspacer material layer 313 is formed conformally on themandrel layer 312, to preferably cover a sidewall and a top surface of themandrel layer 312. In one embodiment, thespacer material layer 313 includes, for example, silicon oxide, silicon nitride, high temperature oxide (HTO) or silicon nitride formed with hexachlorodisilane (Si2Cl6) (“HCD-SiN”), but is not limited thereto. - Follow-up, as shown in
FIG. 4 , an anisotropical etch step is performed to form thespacer layer 314. In one embodiment, thespacer layer 314 is formed only on the sidewalls of themandrel layer 312. Thespacer 314 has a curved cross-section with a width increasing from top to bottom. In another embodiment,spacer 314 with a predetermined thickness remains on the top surface of themandrel 312. In another embodiment, the anisotropic etching step can be omitted so thespacer 314 on the sidewall of themandrel 312 has a uniform thickness. - As shown in
FIG. 5 , amaterial layer 316 is formed comprehensively on thesubstrate 300. Preferably, thematerial layer 316 is filled into the space between eachmandrel layer 312, therefore covering thespacer 314 and themandrel layer 312. Thematerial layer 316 is made of different material from that of thestop layer 308 in themandrel layer 312, so the removing speeds of thematerial layer 316 and thestop layer 308 are significantly different in one removing process. In one embodiment, thematerial layer 316, for example, includes silicon oxide, silicon nitride or organic material such as photoresist, and is not limited thereto. - As shown in
FIG. 6 , a removing process is carried out for removing a part of thematerial layer 316, a part of thespacer 314 and complete removing thesacrificial layer 310. In one embodiment, the removing process stops on thestop layer 308 in themandrel layer 312 and preferably does not remove or removes a very small portion of thestop layer 308. Precisely speaking, the removing speed of thestop layer 308 in the removing process is much smaller than those of thematerial layer 316, thespacer 314 and thesacrificial layer 310. In one embodiment, the removing process includes a chemical mechanical polishing (CMP) step, and thestop layer 308 has a polishing selectivity with respected to thematerial layer 316, thespacer 314 and thesacrificial layer 310. After the CMP step, a top surface of theremaining material layer 316′ is leveled with a top surface of thespacer 314′ and a top surface of thestop layer 308. Thespacer 314′ has a width W in the top surface and a width W′ in the bottom surface, wherein the width W is smaller than the width W. It is noted that when in the embodiment that the anisotropical etching process is omitted, the width W is substantially equal to the width W′, as shown inFIG. 7 . - As shown in
FIG. 8 , thespacer 314′ is completely removed, and afirst trench 318 is formed between the mandrel layer 312 (including thestop layer 308, or thestop layer 308 and the support layer 306) and thematerial layer 316′. Preferably, themask layer 304 is exposed by thefirst trench 318. Considering the accuracy of this removing process, the material of thespacer 314′ preferably has a removing selectivity with respect to thestop layer 308, thematerial layer 318′, as well as themask layer 304. The formedfirst trench 318 has a shape corresponding to the contour of thespacer 314′. For instance, thefirst trench 318 can have a width W at the opening and a width W′ in the bottom surface. In the present embodiment, the width W is smaller than the width W′.In another embodiment ofFIG. 7 , they may be equal. - As shown in
FIG. 9 , by using thematerial layer 316′ and thestop layer 308 as a mask, themask layer 304 and theliner layer 302 are patterned, forming asecond trench 320 in themask layer 304 and theliner layer 302. Thesecond trench 320 corresponds to thefirst trench 318. In one embodiment, thesecond trench 320 has a width W. Then, thematerial layer 316′ and themandrel layer 312 are completely removed. - As shown in
FIG. 10 , by using the patternedmask layer 304′ as a mask, thesubstrate 300 is patterned, thereby forming at least onethird trench 322 in thesubstrate 300. Thethird trench 322 has a width W. Thethird trench 322 can be used as a part of various semiconductor elements, e.g., a shallow trench isolation (STI) by filling an insulating material therein, or a metal interconnection system by filling a metal therein. To one skilled in the art, the formedthird trench 322 can be subjected to other semiconductor process depending on the design of the product or the process. For example, a spacer can be formed on the sidewall of thethird trench 322 and an etching process can be performed by to pattern the substrate, so a trench with finer width can be obtained. Alternatively, a material layer can be filled into thethird trench 322 and thesubstrate 300 other than the material layer is removed, such that the material layer can be used as a part of a semiconductor device. - It is one salient feature of the present invention to use a multi-layered structure of the
mandrel layer 312, for example, including asupport layer 306, astop layer 308, and asacrificial layer 310. Thestop layer 308 and thesacrificial layer 310 have different materials. In the removing process as shown inFIG. 6 , the removing process preferably comprises chemical mechanical polishing process. Comparing to conventional etching back process, a more flat surface can be obtained and the width W of thespacer 314′ can be obtained predictably. Therefore, thefirst trench 318, thesecond trench 320 and thethird trench 322 can also include the width W. Further, by controlling the thickness of each layer in the mandrel layer 312 (the first thickness T1 of thesupport layer 306, the second thickness T2 of thestop layer 308, the third thickness T3 of the sacrificial layer 310) , and/or the shape ofspacer 314 shrinking from bottom to top, the width W of thespacer 314′ inFIG. 6 can be well controlled. The larger the ratio of the first thickness T1 plus the second thickness T2 and thetotal mandrel layer 312, the smaller the width W is; conversely, the smaller the ratio of the first thickness T1 plus the second thickness T2 and thetotal mandrel layer 312, the larger the width W is. In other words, a ratio of the height of the top surface of the stop layer 308 (T1+T2) and the total height of the mandrel layer 312 (T1+T2+T3) is substantially equal to a ratio of the width W of the top surface of thespacer 314′ and the width W′ of the bottom surface of thespacer 314′. In one embodiment, the first thickness is the same as the second thickness plus the third thickness (T1=T2+T3) . In another embodiment when omitting thesupport layer 306, the second thickness is equal to the third thickness (T2=T3). - Further, in another embodiment, the
mask layer 304 and theliner layer 302 can be omitted. As such, in the step ofFIG. 6 , the removing process inFIG. 6 can directly use thematerial layer 316′ and thestop layer 308 as a mask to pattern thesubstrate 300, thereby forming thethird trench 322. - In summary, the present invention provides a method of forming trenches. By using the multi-layered mandrel layer, the width of the trench can be accurately formed. A CMP process is preferably used to increase the reliability of the manufacturing process and to improve product yield.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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