US20160154761A9 - METHOD OF CONNECTING A PCIe BUS EXTENSION SYSTEM - Google Patents
METHOD OF CONNECTING A PCIe BUS EXTENSION SYSTEM Download PDFInfo
- Publication number
- US20160154761A9 US20160154761A9 US14/175,627 US201414175627A US2016154761A9 US 20160154761 A9 US20160154761 A9 US 20160154761A9 US 201414175627 A US201414175627 A US 201414175627A US 2016154761 A9 US2016154761 A9 US 2016154761A9
- Authority
- US
- United States
- Prior art keywords
- pcie
- interface card
- cable
- interface
- motherboard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000002093 peripheral effect Effects 0.000 claims abstract description 46
- 238000003780 insertion Methods 0.000 abstract description 2
- 230000037431 insertion Effects 0.000 abstract description 2
- 230000001902 propagating effect Effects 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/185—Mounting of expansion boards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
Definitions
- the present invention generally relates to PCI Express (PCIe) technology, and in particular a PCIe bus extension system and method for adapting PCIe technology to current and future computer systems.
- PCIe PCI Express
- PCIe formerly known as 3 rd generation I/O (3GIO)
- 3GIO peripheral component interconnect
- PCIe uses multiple lanes in parallel for each link, wherein each link constitutes a serial point-to-point connection comprising differential pairs for sending and receiving data in full duplex mode.
- the currently prevalent PCIe 2.x standard features 500 MB/sec bandwidth per differential pair. In a PCIe 8x configuration (eight lanes), this results in a maximum of 8 GBs data transfers using concurrent send and receive transactions.
- the bandwidth of each PCIe link may be linearly scaled by adding signal pairs into a multi-lane configuration that can be custom tailored to the target (peripheral) device. Likewise, a multi-lane link may be split into several different targets. The width of each link or sub-link is negotiated at the initialization of each peripheral. At the end-point, the data that can be viewed as a byte stream are assembled/disassembled into the different lanes by the physical layer.
- PCIe As an interconnect, it appears an unnecessary limitation to confine target devices to the physical location of an expansion card that is inserted into a PCIe slot of a computer. Rather, given space constraints as well as power and thermal management concerns, it would be advantageous to have target devices moved away from the motherboard and provide a high speed data link (HSDL) via dedicated cabling between an adapter card and the peripheral target device.
- HSDL high speed data link
- U.S. Published Patent Application No. 2008/0244141 shows such a configuration using a dedicated PCIe expansion cable in pass-through mode.
- a dedicated PCIe cable form factor has been defined by the PCI Express Special Interest Group (PCIeSIG) to allow creation of easy to install PCIe devices without limitations by form factor constraints.
- the cable receptacle is either a dedicated port on the motherboard requiring potentially costly redesign of the motherboard, or the interface is located on a dedicated expansion card to facilitate the integration of the PCIe cable.
- the cable receptacle in order to satisfy electrical specifications, including length to connect to peripheral devices at a substantial distance (up to 25 ft (8 meters)) from the host system, the cable itself requires a bulky design which adds undesirable cost.
- PCIe devices in their current form including the integration of all components and necessary cooling, as for example in the case of graphics cards, are limited by rigid design specifications. These constraints, including thermal and power envelope as well as space requirements, complicate the ability to provide flexible implementations of devices that connect to a computer system through a PCIe interface. As such, it would be desirable to enable functional interfacing of a PCIe device with a PCIe bus, but allowing for the device to be located remote from the PCIe interface on the motherboard, and more preferably without the requirement that the device occupies internal space within the computer enclosure.
- the present invention provides a PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system.
- a method of connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system includes installing a PCIe interface card in an enclosure of the computer system.
- the PCIe interface card is installed to have an edge connector thereof functionally connected with a motherboard within the enclosure, the PCIe interface card having a logic integrated circuit to functionally connect PCIe signals transmitted from the motherboard to an interface port on the PCIe interface card and functionally connect PCIe signals transmitted from the interface port to the motherboard.
- a PCIe-compliant peripheral device is then connected to the PCIe interface card with a cable configured for complete crossover of all of the PCIe signals.
- the cable is connected to the interface port of the PCIe interface card and to an interface port of the PCIe-compliant peripheral device that is functionally identical to the interface port on the PCIe interface card, but with a mirror-symmetric pinout to receive clock and data signals from the PCIe interface card and to send data signals to the PCIe interface card.
- the PCIe signals are then transmitted between the motherboard and the PCIe-compliant peripheral device through the cable and the interface port on the PCIe interface card.
- the PCIe signals are transmitted over multiple parallel PCIe lanes to define a single channel transferred over the cable in full duplex mode.
- the PCIe-compliant peripheral device does not receive power through the PCIe interface card or cable.
- the PCIe interface card has at least one interface port and an edge connector configured to interface with a PCIe expansion slot.
- the connector is functionally connected with a motherboard within the enclosure.
- the PCIe interface card further has a logic integrated circuit that functionally connects PCIe signals transmitted from the motherboard to the interface port and functionally connects PCIe signals transmitted from the interface port to the motherboard.
- the extension system further includes a PCIe-compliant peripheral device having an interface port that is functionally identical to the interface port on the PCIe interface card, but with a mirror-symmetric pinout to receive clock and data signals from the PCIe interface card and to send data signals to the PCIe interface card.
- a cable connects the interface port of the PCIe interface card to the interface port of the PCIe-compliant peripheral device.
- the cable is configured for complete crossover of all of the PCIe signals and the interface port of the PCIe interface card is adapted to transmit the PCIe signals over multiple parallel PCIe lanes to define a single channel transferred over the cable in full duplex mode.
- the PCIe-compliant peripheral device does not receive power through the PCIe interface card or the cable.
- the PCIe interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the PCIe interface card, an interface port configured to mate with a connector of a cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the interface port and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard.
- the interface port of the PCIe interface card is adapted to communicate the clock and data PCIe signals of multiple PCIe lanes in full duplex mode to a PCIe-compliant peripheral device when connected by a cable to the interface port of the PCIe interface card through an interface port of the PCIe-compliant peripheral device that has a mirror-symmetric pinout to the interface port of the PCIe interface card but lacks means for transmitting power therethrough.
- the invention is adapted to use a cable that provides a functional interconnect high speed data link (HSDL) channel through which all signals of multiple parallel lanes of data are transferred in full duplex mode between the PCIe interface card and a PCIe-compliant peripheral device.
- HSDL high speed data link
- this capability is able to provide a scaled-down, inexpensive solution for interconnecting the PCIe bus on a standard motherboard with one or more PCIe-compliant peripheral devices that may be within an enclosure of the computer system but remote from a motherboard within the enclosure, or external but in close proximity to the enclosure.
- FIG. 1 schematically represents a functional diagram of a PCIe bus extension system, in which a PCIe interface card is installed in a host computer and connected with a cable to a PCIe-compliant peripheral device containing four solid-state drives in accordance with an embodiment of the invention.
- FIG. 2A represents a PCIe interface card of a type suitable for use in the PCIe bus extension system of FIG. 1 , in which the interface card is equipped with four female mini-SAS 4i connectors in accordance with an embodiment of the invention.
- FIG. 2B represents a PCIe interface card similar to that of FIG. 2A , but equipped with a single female mini-SAS 4i connector in accordance with another embodiment of the invention.
- FIG. 2C represents a more detailed view of a female mini-SAS 4i connector of the type shown as being mounted on the PCIe interface cards of FIGS. 2A and 2B .
- FIG. 2D represents a cable of a type suitable for use in the PCIe bus extension system of FIG. 1 , in which the cable has a complementary male mini-SAS 4i connector configured for connecting with the female mini-SAS 4i connectors of FIGS. 2A through 2C .
- FIG. 3 schematically represents a functional diagram of a PCIe bus extension system similar to that of FIG. 1 , further configured to arbitrate a single channel through a PCIe switch over multiple mini SA 4 i interface ports.
- FIG. 4 schematically represents a clock forwarding scheme suitable for use with PCIe bus extension system of FIG. 1 .
- FIG. 1 schematically represents a PCIe bus extension system 10 according to an embodiment of the invention.
- the system 10 is represented as being used with a host computer 12 and as including a PCIe interface card 14 that has been installed within an enclosure 16 in the computer 12 .
- the interface card 14 is connected with a cable 18 to one of any number of PCIe-compliant peripheral devices 20 that are compatible with PCIe technology.
- the peripheral device 20 is represented as including a Serial ATA (SATA)-based solid state drive (SSD) controller 21 for controlling four solid-state drives (SSDs) 22 .
- SATA Serial ATA
- SSD solid state drive
- the interface card 14 and cable 18 are preferably configured to provide a high speed data link (HSDL) between the computer 12 and the peripheral device 20 .
- HSDL high speed data link
- Particularly preferred PCIe-compliant peripheral devices 20 include NAND flash-based mass storage devices capable of interfacing with a PCIe bus through suitable logic. More generally, the peripheral devices 20 can be PCIe first generation or second generation compliant, preferably using a 5 gbps (PCIe 2.x compliant) data rate. As represented in FIG. 1 , a nonlimiting example of a suitable logic is a four-port PCI-based SATA controller 21 that fans out into the four SATA SSDs 22 , which may comprise an array of NAND flash-based mass storage devices located at the back end of the logic. The SATA controller 21 serves as host bus adapter for the SATA SSDs 22 used as the permanent storage media. As represented in FIG.
- the PCIe signals can be converted into PCI-X signals with a converter 23 , for example, using a Pericom PI7C9X130PCI Express to PCI-X Reversible Bridge, which then connects to the SATA controller 21 .
- a converter 23 for example, using a Pericom PI7C9X130PCI Express to PCI-X Reversible Bridge, which then connects to the SATA controller 21 .
- Other mapping strategies and non-volatile memory technologies could be used.
- FIGS. 2A and 2B represent two embodiments of the PCIe interface card 14 of FIG. 1 .
- the interface card 14 is equipped with four interface ports 24
- the card 14 represented in FIG. 2B is equipped with a single interface port 24 .
- Each card 14 comprises a printed circuit board 26 , a bracket 34 for mounting the circuit board 26 within the computer enclosure 16 , and an edge connector 28 configured to connect the interface card 14 with a PCIe expansion slot (not shown) on a motherboard 30 mounted within the enclosure 16 ( FIG. 1 ).
- the connector 28 could be functionally connected to the PCIe expansion slot on the motherboard 30 through a PCIe riser card (not shown) within the enclosure 16 .
- FIG. 2C provides a more detailed view of a female connector 25 that forms part of each interface port 24 on the interface cards 14 of FIGS. 2A and 2B
- FIG. 2D represents one end of the cable 18 and a male connector 32 affixed thereto for connecting to the female connector 25 of the interface card 14
- the female connector 25 and its complementary male connector 32 are preferably compliant with Small Form Factor (SFF) committee specifications SFF-8086 (currently Rev 2.3) and SFF-8087 (currently Rev. 2.4), which specify what is generally known as the mini Serial Attached SCSI (SAS) form factor, including the form factor known as mini-SAS 4i (wide compact internal connector).
- SAS Serial Attached SCSI
- the interconnection between the PCIe interface card 14 and the PCIe-compliant peripheral device 20 of FIG. 1 is made through an extension of the PCIe bus of the motherboard 30 using a flexible cable 18 that can be of a type that is commercially available (“off-the-shelf”) and conforms to existing industry standards.
- the cable 18 is a standard mini-SAS 4i cable having male connectors 32 at each end that are configured for mating with a female connector 25 of the interface card 14 and a similar-configured female connector of a PCIe interface port 40 of the peripheral device 20 .
- PCIe functionality and protocol can be maintained throughout the entire configuration so that the interconnection is completely transparent to the host computer 10 . In other words, the host computer 10 does not know whether the peripheral devices 20 are connected through the cable 18 or plugged directly into the PCIe interface slot on the motherboard 30 .
- the interface card 14 serves to connect the signal traces of the PCIe expansion slot on the motherboard 30 to the PCIe-compliant peripheral device 20 , and in particular the control, data and clock signals transmitted between the motherboard 30 and the SSDs 22 controlled by the four-port SATA controller 21 .
- the interface card 14 connects four PCIe lanes originating on the motherboard 30 to four PCIe lanes in the interface port 24 , from where they are transferred through the cable 18 to the receiving port 40 on the peripheral device 20 .
- possible signal attenuation and delays stemming from the use of the cable 18 can be compensated for by the use of an integrated PCIe re-driver integrated circuit (not shown) of a type known in the art.
- FIG. 1 represents the simplest case, in which the four PCIe lanes are physically combined into a single HSDL channel formed by the cable 18 , resulting in the PCIe signals being transmitted over the cable 18 in full duplex mode.
- the data traces can be routed through the re-driver IC, which acts as a transmit/receive amplifier between the edge connector and the upstream female connectors 25 .
- FIG. 3 represents a situation in which the four PCIe lanes from the motherboard 30 are split over four HSDL channels with four PCIe lanes, each of which uses a PCIe switch 42 on the interface card 14 to arbitrate the signals for a total of sixteen PCIe lanes over the four interface ports 24 .
- Each interface port 24 then connects via a cable 18 to one of the ports 40 on the peripheral devices 20 .
- the peripheral devices 20 will have their own intrinsic latencies, especially if they are NAND flash-based storage devices with access latencies in the order of 100 to 200 ⁇ sec.
- the arbitration latencies of the PCIe switch 42 typically on the order of 150 ns or less, will not constitute any significant bottleneck.
- FIG. 4 represents a clock forwarding scheme suitable for use with PCIe bus extension system of FIG. 1 .
- the reference clock signal acquired from the motherboard 30 can be amplified through a zero-delay clock buffer 36 and forwarded to one or more interface ports 24 of the interface card 14 using high speed current steering logic (HCSL), which in the embodiment of FIG. 4 includes an in-series resistor of about 33.2 Ohms and a termination to ground resistor of about 49.9 Ohm (both 1% tolerance).
- HCSL high speed current steering logic
- 120 interface serial clock (SCL) and data (SDA) are routed through the mini-SAS connectors 25 and 32 .
- a device present input can be established through a dedicated PRESENT# pin and a fundamental reset (PERST#) output can be used to reset a peripheral device 20 .
- pulling the PRESENT# low to indicate the presence of a device 20 can be used to generate a visual indicator of the electrical connection of the device 20 to the interface card 14 in form of an LED.
- the pinout of a female mini-SAS i4 connector used as the interface port 40 of the peripheral devices 20 is given in Table 2.
- pin names (signals) identified in Tables 1 and 2 are provided in Table 3. For all differential pairs, “p” is positive and “n” is negative.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Human Computer Interaction (AREA)
- Information Transfer Systems (AREA)
- Bus Control (AREA)
Abstract
Description
- This application is a division patent application of co-pending U.S. patent application Ser. No. 13/205,300, filed Aug. 8, 2011, which claims the benefit of U.S. Provisional Application No. 61/371,325, filed Aug. 6, 2010, the contents of which are incorporated herein by reference.
- The present invention generally relates to PCI Express (PCIe) technology, and in particular a PCIe bus extension system and method for adapting PCIe technology to current and future computer systems.
- PCIe, formerly known as 3rd generation I/O (3GIO), has replaced the former peripheral component interconnect (PCI) parallel multi-drop bus as the main interconnect within current computer systems. In contrast to PCI, PCIe uses multiple lanes in parallel for each link, wherein each link constitutes a serial point-to-point connection comprising differential pairs for sending and receiving data in full duplex mode.
- The currently prevalent PCIe 2.x standard features 500 MB/sec bandwidth per differential pair. In a PCIe 8x configuration (eight lanes), this results in a maximum of 8 GBs data transfers using concurrent send and receive transactions. The bandwidth of each PCIe link may be linearly scaled by adding signal pairs into a multi-lane configuration that can be custom tailored to the target (peripheral) device. Likewise, a multi-lane link may be split into several different targets. The width of each link or sub-link is negotiated at the initialization of each peripheral. At the end-point, the data that can be viewed as a byte stream are assembled/disassembled into the different lanes by the physical layer.
- Given the high bandwidth and flexibility of the PCIe as an interconnect, it appears an unnecessary limitation to confine target devices to the physical location of an expansion card that is inserted into a PCIe slot of a computer. Rather, given space constraints as well as power and thermal management concerns, it would be advantageous to have target devices moved away from the motherboard and provide a high speed data link (HSDL) via dedicated cabling between an adapter card and the peripheral target device. U.S. Published Patent Application No. 2008/0244141 shows such a configuration using a dedicated PCIe expansion cable in pass-through mode. Likewise, a dedicated PCIe cable form factor has been defined by the PCI Express Special Interest Group (PCIeSIG) to allow creation of easy to install PCIe devices without limitations by form factor constraints. In either case, the cable receptacle is either a dedicated port on the motherboard requiring potentially costly redesign of the motherboard, or the interface is located on a dedicated expansion card to facilitate the integration of the PCIe cable. However, in order to satisfy electrical specifications, including length to connect to peripheral devices at a substantial distance (up to 25 ft (8 meters)) from the host system, the cable itself requires a bulky design which adds undesirable cost.
- In view of the above, PCIe devices in their current form, including the integration of all components and necessary cooling, as for example in the case of graphics cards, are limited by rigid design specifications. These constraints, including thermal and power envelope as well as space requirements, complicate the ability to provide flexible implementations of devices that connect to a computer system through a PCIe interface. As such, it would be desirable to enable functional interfacing of a PCIe device with a PCIe bus, but allowing for the device to be located remote from the PCIe interface on the motherboard, and more preferably without the requirement that the device occupies internal space within the computer enclosure.
- The present invention provides a PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system.
- According to a first aspect of the invention, a method of connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system includes installing a PCIe interface card in an enclosure of the computer system. The PCIe interface card is installed to have an edge connector thereof functionally connected with a motherboard within the enclosure, the PCIe interface card having a logic integrated circuit to functionally connect PCIe signals transmitted from the motherboard to an interface port on the PCIe interface card and functionally connect PCIe signals transmitted from the interface port to the motherboard. A PCIe-compliant peripheral device is then connected to the PCIe interface card with a cable configured for complete crossover of all of the PCIe signals. The cable is connected to the interface port of the PCIe interface card and to an interface port of the PCIe-compliant peripheral device that is functionally identical to the interface port on the PCIe interface card, but with a mirror-symmetric pinout to receive clock and data signals from the PCIe interface card and to send data signals to the PCIe interface card. The PCIe signals are then transmitted between the motherboard and the PCIe-compliant peripheral device through the cable and the interface port on the PCIe interface card. The PCIe signals are transmitted over multiple parallel PCIe lanes to define a single channel transferred over the cable in full duplex mode. The PCIe-compliant peripheral device does not receive power through the PCIe interface card or cable.
- According to a second aspect of the invention, a PCIe bus extension system for connecting a PCIe-compliant peripheral device to a PCIe bus of the computer system includes a PCIe interface card within an enclosure of the computer system. The PCIe interface card has at least one interface port and an edge connector configured to interface with a PCIe expansion slot. The connector is functionally connected with a motherboard within the enclosure. The PCIe interface card further has a logic integrated circuit that functionally connects PCIe signals transmitted from the motherboard to the interface port and functionally connects PCIe signals transmitted from the interface port to the motherboard. The extension system further includes a PCIe-compliant peripheral device having an interface port that is functionally identical to the interface port on the PCIe interface card, but with a mirror-symmetric pinout to receive clock and data signals from the PCIe interface card and to send data signals to the PCIe interface card. A cable connects the interface port of the PCIe interface card to the interface port of the PCIe-compliant peripheral device. The cable is configured for complete crossover of all of the PCIe signals and the interface port of the PCIe interface card is adapted to transmit the PCIe signals over multiple parallel PCIe lanes to define a single channel transferred over the cable in full duplex mode. However, the PCIe-compliant peripheral device does not receive power through the PCIe interface card or the cable.
- Another aspect of the invention is a PCIe interface card for a PCIe bus of a computer system. The PCIe interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the PCIe interface card, an interface port configured to mate with a connector of a cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the interface port and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface port of the PCIe interface card is adapted to communicate the clock and data PCIe signals of multiple PCIe lanes in full duplex mode to a PCIe-compliant peripheral device when connected by a cable to the interface port of the PCIe interface card through an interface port of the PCIe-compliant peripheral device that has a mirror-symmetric pinout to the interface port of the PCIe interface card but lacks means for transmitting power therethrough.
- According to the above, the invention is adapted to use a cable that provides a functional interconnect high speed data link (HSDL) channel through which all signals of multiple parallel lanes of data are transferred in full duplex mode between the PCIe interface card and a PCIe-compliant peripheral device. According to a preferred aspect of the invention, this capability is able to provide a scaled-down, inexpensive solution for interconnecting the PCIe bus on a standard motherboard with one or more PCIe-compliant peripheral devices that may be within an enclosure of the computer system but remote from a motherboard within the enclosure, or external but in close proximity to the enclosure.
- Other aspects and advantages of this invention will be better appreciated from the following detailed description.
-
FIG. 1 schematically represents a functional diagram of a PCIe bus extension system, in which a PCIe interface card is installed in a host computer and connected with a cable to a PCIe-compliant peripheral device containing four solid-state drives in accordance with an embodiment of the invention. -
FIG. 2A represents a PCIe interface card of a type suitable for use in the PCIe bus extension system ofFIG. 1 , in which the interface card is equipped with four female mini-SAS 4i connectors in accordance with an embodiment of the invention. -
FIG. 2B represents a PCIe interface card similar to that ofFIG. 2A , but equipped with a single female mini-SAS 4i connector in accordance with another embodiment of the invention. -
FIG. 2C represents a more detailed view of a female mini-SAS 4i connector of the type shown as being mounted on the PCIe interface cards ofFIGS. 2A and 2B . -
FIG. 2D represents a cable of a type suitable for use in the PCIe bus extension system ofFIG. 1 , in which the cable has a complementary male mini-SAS 4i connector configured for connecting with the female mini-SAS 4i connectors ofFIGS. 2A through 2C . -
FIG. 3 schematically represents a functional diagram of a PCIe bus extension system similar to that ofFIG. 1 , further configured to arbitrate a single channel through a PCIe switch over multiple mini SA 4 i interface ports. -
FIG. 4 schematically represents a clock forwarding scheme suitable for use with PCIe bus extension system ofFIG. 1 . - The Figures represent certain aspects of a system capable of providing flexible configurations for connecting PCIe-compliant peripheral devices to a host computer system using a cable that connects the peripheral devices to a PCIe bus on a motherboard of the computer system. As known in the art, the PCIe protocol allows for concurrent send and receive transfers over dedicated differential signaling pairs of wires in full duplex mode. PCIe signals are routed from a PCIe expansion slot on the motherboard through a PCIe interface (expansion) card via an edge connector of the interface card. The edge connector of the PCIe interface card typically uses a 4-lane interface, though other interface configurations such as PCIe x1, x8 or x16 are possible. As will be discussed in more detail below, the system is advantageously able to make use of standard and relatively low-cost cables and connectors that are mounted on an adapted circuit board so that the pinout connectivity on the interface card and peripheral device have a mirrored configuration.
-
FIG. 1 schematically represents a PCIebus extension system 10 according to an embodiment of the invention. Thesystem 10 is represented as being used with ahost computer 12 and as including aPCIe interface card 14 that has been installed within anenclosure 16 in thecomputer 12. Theinterface card 14 is connected with acable 18 to one of any number of PCIe-compliantperipheral devices 20 that are compatible with PCIe technology. In the embodiment ofFIG. 1 , theperipheral device 20 is represented as including a Serial ATA (SATA)-based solid state drive (SSD)controller 21 for controlling four solid-state drives (SSDs) 22. Theinterface card 14 andcable 18 are preferably configured to provide a high speed data link (HSDL) between thecomputer 12 and theperipheral device 20. - Particularly preferred PCIe-compliant
peripheral devices 20 include NAND flash-based mass storage devices capable of interfacing with a PCIe bus through suitable logic. More generally, theperipheral devices 20 can be PCIe first generation or second generation compliant, preferably using a 5 gbps (PCIe 2.x compliant) data rate. As represented inFIG. 1 , a nonlimiting example of a suitable logic is a four-port PCI-basedSATA controller 21 that fans out into the fourSATA SSDs 22, which may comprise an array of NAND flash-based mass storage devices located at the back end of the logic. TheSATA controller 21 serves as host bus adapter for theSATA SSDs 22 used as the permanent storage media. As represented inFIG. 1 , the PCIe signals can be converted into PCI-X signals with aconverter 23, for example, using a Pericom PI7C9X130PCI Express to PCI-X Reversible Bridge, which then connects to theSATA controller 21. Other mapping strategies and non-volatile memory technologies could be used. -
FIGS. 2A and 2B represent two embodiments of thePCIe interface card 14 ofFIG. 1 . InFIG. 2A , theinterface card 14 is equipped with fourinterface ports 24, whereas thecard 14 represented inFIG. 2B is equipped with asingle interface port 24. Eachcard 14 comprises a printedcircuit board 26, abracket 34 for mounting thecircuit board 26 within thecomputer enclosure 16, and anedge connector 28 configured to connect theinterface card 14 with a PCIe expansion slot (not shown) on amotherboard 30 mounted within the enclosure 16 (FIG. 1 ). Alternatively, it is foreseeable that theconnector 28 could be functionally connected to the PCIe expansion slot on themotherboard 30 through a PCIe riser card (not shown) within theenclosure 16. -
FIG. 2C provides a more detailed view of afemale connector 25 that forms part of eachinterface port 24 on theinterface cards 14 ofFIGS. 2A and 2B , andFIG. 2D represents one end of thecable 18 and amale connector 32 affixed thereto for connecting to thefemale connector 25 of theinterface card 14. Thefemale connector 25 and its complementarymale connector 32 are preferably compliant with Small Form Factor (SFF) committee specifications SFF-8086 (currently Rev 2.3) and SFF-8087 (currently Rev. 2.4), which specify what is generally known as the mini Serial Attached SCSI (SAS) form factor, including the form factor known as mini-SAS 4i (wide compact internal connector). As such, the term “mini-SAS” is used herein to define connectors that meet the SFF-8086 and SFF-8087 specifications, and particular example of which is the mini-SAS 4i form factor. Additionally, thecable 18 can be an SFF-8087 compliant internal straight termination cable. As such, theconnectors cable 18 can be referred to as mini-SAS connectors and cable, though it should be understood that other types of connectors and cables could be developed and for use with the invention that are compatible with PCIe technology. As mini-SAS connectors, eachconnector 25 has up to four differential signaling pairs for both transmitting and receiving data, along with a differential reference clock signal pair, a fundamental reset and an I2C interface for serial clock and data. In the form of a mini-SAS cable, thecable 18 is configured to have a “backplane to controller” pinout to achieve complete crossover of all signals, in other words, all thirty-six signals of a mini-SAS 4i connectors cross over. Thecable 18 should meet or exceed the electrical specifications defined in the SAS-1.1 standard, and typically will be limited to lengths of about 0.5 meter (about 20 inches). Notably, power is not transferred from themotherboard 30 to theperipheral devices 20 through theconnectors 25 of theinterface ports 24. Mini-SAS connectors and cables are known in the art and therefore, aside from the above, will not be discussed in any further details. - In view of the above, the interconnection between the
PCIe interface card 14 and the PCIe-compliantperipheral device 20 ofFIG. 1 is made through an extension of the PCIe bus of themotherboard 30 using aflexible cable 18 that can be of a type that is commercially available (“off-the-shelf”) and conforms to existing industry standards. In the example given, thecable 18 is a standard mini-SAS 4i cable havingmale connectors 32 at each end that are configured for mating with afemale connector 25 of theinterface card 14 and a similar-configured female connector of aPCIe interface port 40 of theperipheral device 20. PCIe functionality and protocol can be maintained throughout the entire configuration so that the interconnection is completely transparent to thehost computer 10. In other words, thehost computer 10 does not know whether theperipheral devices 20 are connected through thecable 18 or plugged directly into the PCIe interface slot on themotherboard 30. - Based on the configuration of the
system 10 andcards 14 discussed above, theinterface card 14 serves to connect the signal traces of the PCIe expansion slot on themotherboard 30 to the PCIe-compliantperipheral device 20, and in particular the control, data and clock signals transmitted between themotherboard 30 and theSSDs 22 controlled by the four-port SATA controller 21. In the embodiment ofFIG. 1 , theinterface card 14 connects four PCIe lanes originating on themotherboard 30 to four PCIe lanes in theinterface port 24, from where they are transferred through thecable 18 to the receivingport 40 on theperipheral device 20. On theinterface card 14, possible signal attenuation and delays stemming from the use of thecable 18 can be compensated for by the use of an integrated PCIe re-driver integrated circuit (not shown) of a type known in the art. -
FIG. 1 represents the simplest case, in which the four PCIe lanes are physically combined into a single HSDL channel formed by thecable 18, resulting in the PCIe signals being transmitted over thecable 18 in full duplex mode. The data traces can be routed through the re-driver IC, which acts as a transmit/receive amplifier between the edge connector and the upstreamfemale connectors 25.FIG. 3 represents a situation in which the four PCIe lanes from themotherboard 30 are split over four HSDL channels with four PCIe lanes, each of which uses aPCIe switch 42 on theinterface card 14 to arbitrate the signals for a total of sixteen PCIe lanes over the fourinterface ports 24. Eachinterface port 24 then connects via acable 18 to one of theports 40 on theperipheral devices 20. Typically, theperipheral devices 20 will have their own intrinsic latencies, especially if they are NAND flash-based storage devices with access latencies in the order of 100 to 200 μsec. The arbitration latencies of thePCIe switch 42, typically on the order of 150 ns or less, will not constitute any significant bottleneck. -
FIG. 4 represents a clock forwarding scheme suitable for use with PCIe bus extension system ofFIG. 1 . In the illustrated example, the reference clock signal acquired from themotherboard 30 can be amplified through a zero-delay clock buffer 36 and forwarded to one ormore interface ports 24 of theinterface card 14 using high speed current steering logic (HCSL), which in the embodiment ofFIG. 4 includes an in-series resistor of about 33.2 Ohms and a termination to ground resistor of about 49.9 Ohm (both 1% tolerance). - In addition to the PCIe clock and data signals, 120 interface serial clock (SCL) and data (SDA) are routed through the
mini-SAS connectors peripheral device 20. In the preferred embodiment, pulling the PRESENT# low to indicate the presence of adevice 20 can be used to generate a visual indicator of the electrical connection of thedevice 20 to theinterface card 14 in form of an LED. - A complete listing of the pinout (pin layout) of a female mini-SAS i4 connector used as the
connector 25 of theinterface port 24 on theinterface card 14 is given in Table 1. -
TABLE 1 HOST SIDE CONNECTOR PINOUT Pin # Pin Name Pin # Pin Name A1 GROUND B1 GROUND A2 PETp0 B2 PERp0 A3 PETn0 B3 PERn0 A4 GROUND B4 GROUND A5 PETp1 B5 PERp1 A6 PETn1 B6 PERn1 A7 GROUND B7 GROUND A8 GROUND B8 PERST# A9 REFCLK+ B9 PRESENT# A10 REFCLK− B10 SCL A11 GROUND B11 SDA A12 GROUND B12 GROUND A13 PETp2 B13 PERp2 A14 PETn2 B14 PERn2 A15 GROUND B15 GROUND A16 PETp3 B16 PERp3 A17 PETn3 B17 PERn3 A18 GROUND B18 GROUND - The pinout of a female mini-SAS i4 connector used as the
interface port 40 of theperipheral devices 20 is given in Table 2. -
TABLE 2 DRIVE SIDE CONNECTOR PINOUT Pin Pin Name Pin Pin Name A1 GROUND B1 GROUND A2 PERp0 B2 PETp0 A3 PERn0 B3 PETn0 A4 GROUND B4 GROUND A5 PERp1 B5 PETp1 A6 PERn1 B6 PETn1 A7 GROUND B7 GROUND A8 PERST# B8 GROUND A9 PRESENT B9 REFCLK A10 SCL B10 REFCLK− A11 SDA B11 GROUND A12 GROUND B12 GROUND A13 PERp2 B13 PETp2 A14 PERn2 B14 PETn2 A15 GROUND B15 GROUND A16 PERp3 B16 PETp3 A17 PERn3 B17 PETn3 A18 GROUND B18 GROUND - The definitions for the pin names (signals) identified in Tables 1 and 2 are provided in Table 3. For all differential pairs, “p” is positive and “n” is negative.
-
TABLE 3 PIN DEFINITIONS Pin Name Direction Definition PETp0/PETn0 I Transmitter differential pair, Lane 0 PETp1/PETn1 I Transmitter differential pair, Lane 1PETp2/PETn2 I Transmitter differential pair, Lane 2 PETp3/PETn3 I Transmitter differential pair, Lane 3 PERp0/PERn O Receiver differential pair, Lane 0 PERp1/PERn O Receiver differential pair, Lane 1PERp2/PERn O Receiver differential pair, Lane 2 PERp3/PERn O Receiver differential pair, Lane 3 REFCLK+/− O Reference Clock differential pair PERST# O, OD Fundamental reset (low true) PRESENT# I, OD Drive present indicator (low true) SCL O, OD I2C interface serial clock SDA I/O, OD I2C interface serial data GROUND System digital ground *I = input to host system O = output from host system I/O = bidirectional signal OD = open drain - While certain components have been disclosed for the PCIe bus extension system of this invention, it is foreseeable that functionally-equivalent components could be used or subsequently developed to perform the intended functions of the disclosed components. For example, future PCIe standards may require higher pin count connectors that would have to be addressed by the HSDL channel connectors and cables. Furthermore, future revisions of high speed data link (HSDL) technology will embrace PCIe 3.x and future revisions of the PCIe standard. Therefore, while the invention has been described in terms of particular embodiments, it is apparent that other forms could be adopted by one skilled in the art, and the scope of the invention is to be limited only by the following claims.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/175,627 US9477630B2 (en) | 2010-08-06 | 2014-02-07 | Method of connecting a PCIe bus extension system |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US37132510P | 2010-08-06 | 2010-08-06 | |
US13/205,300 US8693208B2 (en) | 2010-08-06 | 2011-08-08 | PCIe bus extension system, method and interfaces therefor |
US14/175,627 US9477630B2 (en) | 2010-08-06 | 2014-02-07 | Method of connecting a PCIe bus extension system |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/205,300 Division US8693208B2 (en) | 2010-08-06 | 2011-08-08 | PCIe bus extension system, method and interfaces therefor |
Publications (3)
Publication Number | Publication Date |
---|---|
US20140156897A1 US20140156897A1 (en) | 2014-06-05 |
US20160154761A9 true US20160154761A9 (en) | 2016-06-02 |
US9477630B2 US9477630B2 (en) | 2016-10-25 |
Family
ID=45556022
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/205,300 Active 2032-04-18 US8693208B2 (en) | 2010-08-06 | 2011-08-08 | PCIe bus extension system, method and interfaces therefor |
US14/175,627 Active US9477630B2 (en) | 2010-08-06 | 2014-02-07 | Method of connecting a PCIe bus extension system |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/205,300 Active 2032-04-18 US8693208B2 (en) | 2010-08-06 | 2011-08-08 | PCIe bus extension system, method and interfaces therefor |
Country Status (1)
Country | Link |
---|---|
US (2) | US8693208B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160142099A1 (en) * | 2014-11-14 | 2016-05-19 | International Business Machines Corporation | Tracking asset computing devices |
US20160147699A1 (en) * | 2014-11-26 | 2016-05-26 | Dell Products, L.P. | Method and system for a flexible interconnect media in a point-to-point topography |
CN110647487A (en) * | 2019-08-09 | 2020-01-03 | 烽火通信科技股份有限公司 | Local Bus interface expansion device of PowerPC under pluggable expansion card structure |
Families Citing this family (69)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101569071B1 (en) * | 2009-04-20 | 2015-11-17 | 삼성전자주식회사 | Apparatus for transmitting PCI express signal and image forming apparatus using the same |
CN102650677B (en) * | 2011-02-25 | 2016-02-03 | 温州大学 | PCI-E signal-testing apparatus |
CN102955497A (en) * | 2011-08-18 | 2013-03-06 | 鸿富锦精密工业(深圳)有限公司 | Mainboard provided with solid-state drive |
CN103064814A (en) * | 2011-10-21 | 2013-04-24 | 鸿富锦精密工业(深圳)有限公司 | Electronic device with plurality of interfaces |
US20130179622A1 (en) * | 2012-01-06 | 2013-07-11 | Gary L. Pratt | System and method for transmitting and receiving data using an industrial expansion bus |
US9141152B2 (en) * | 2012-05-04 | 2015-09-22 | Hewlett-Packard Devlopment Company, L.P. | Interface card mount |
CN102819500B (en) * | 2012-07-20 | 2016-01-20 | 腾讯科技(深圳)有限公司 | A kind of method and device creating peripheral equipment control interface |
CN103593014A (en) * | 2012-08-16 | 2014-02-19 | 鸿富锦精密工业(武汉)有限公司 | Circuit board connecting structure |
US20140087570A1 (en) * | 2012-09-21 | 2014-03-27 | Lsi Corporation | Cable exit methods for pcie cards |
CN103901946A (en) * | 2012-12-26 | 2014-07-02 | 鸿富锦精密工业(武汉)有限公司 | Mainboard |
CN103927281A (en) * | 2013-01-15 | 2014-07-16 | 华硕电脑股份有限公司 | Transmission interface detection system and transmission interface detection method |
US20140244889A1 (en) * | 2013-02-27 | 2014-08-28 | Wilocity Ltd. | Pci-e reference clock passive splitter and method thereof |
US9142921B2 (en) | 2013-02-27 | 2015-09-22 | Molex Incorporated | High speed bypass cable for use with backplanes |
TWI482034B (en) * | 2013-05-17 | 2015-04-21 | Wistron Corp | Interface card |
US20140365699A1 (en) * | 2013-06-11 | 2014-12-11 | Allied Telesis Holdings Kabushiki Kaisha | Adapter card for thin computing devices |
TWM472234U (en) | 2013-06-26 | 2014-02-11 | Ioi Technology Corp | PCI-E expanding system |
US9671836B2 (en) * | 2013-07-10 | 2017-06-06 | Bae Systems Information And Electronic Systems Integration Inc. | Data storage transfer archive repository |
CN104345834B (en) * | 2013-08-08 | 2018-09-14 | 鸿富锦精密电子(天津)有限公司 | Expansion card |
US9582453B2 (en) | 2013-08-15 | 2017-02-28 | Western Digital Technologies, Inc. | I/O card architecture based on a common controller |
US9236674B2 (en) * | 2013-09-03 | 2016-01-12 | Josef Rabinovitz | Interface card assembly for use in a bus extension system |
US20150085868A1 (en) * | 2013-09-25 | 2015-03-26 | Cavium, Inc. | Semiconductor with Virtualized Computation and Switch Resources |
US9928198B2 (en) * | 2013-11-22 | 2018-03-27 | Oracle International Corporation | Adapter card with a computer module form factor |
US20150261710A1 (en) * | 2014-03-14 | 2015-09-17 | Emilio Billi | Low-profile half length pci express form factor embedded pci express multi ports switch and related accessories |
US9870335B2 (en) * | 2014-04-03 | 2018-01-16 | International Business Machines Corporation | Implementing sideband control structure for PCIE cable cards and IO expansion enclosures |
US9529743B2 (en) * | 2014-09-08 | 2016-12-27 | Quanta Computer Inc. | Flexible PCIe routing |
US9747240B2 (en) | 2014-10-24 | 2017-08-29 | Cisco Technology, Inc. | Dynamic connection of PCIe devices and functions to an array of hosts |
US9927851B2 (en) * | 2014-11-26 | 2018-03-27 | Hewlett Packard Enterprise Development Lp | Storage drive carrier module |
KR20170102011A (en) | 2015-01-11 | 2017-09-06 | 몰렉스 엘엘씨 | A wire-to-board connector suitable for use in a bypass routing assembly |
KR102299742B1 (en) | 2015-01-11 | 2021-09-09 | 몰렉스 엘엘씨 | Circuit board bypass assemblies and components therefor |
WO2016122505A1 (en) | 2015-01-29 | 2016-08-04 | Hewlett-Packard Development Company, L.P. | Memory card expansion |
US10353442B2 (en) | 2015-01-30 | 2019-07-16 | Hewlett-Packard Development Company, L.P. | Expansion slot interface |
US20160259754A1 (en) | 2015-03-02 | 2016-09-08 | Samsung Electronics Co., Ltd. | Hard disk drive form factor solid state drive multi-card adapter |
CN106033396A (en) * | 2015-03-10 | 2016-10-19 | 鸿富锦精密工业(深圳)有限公司 | A data storage device and a data transmission system with the same |
WO2016179263A1 (en) * | 2015-05-04 | 2016-11-10 | Molex, Llc | Computing device using bypass assembly |
US10117603B2 (en) | 2015-06-27 | 2018-11-06 | Intel Corporation | Field-of-view ocular and facial alignment guides |
CN106339343B (en) * | 2015-07-10 | 2021-03-26 | 爱思开海力士有限公司 | Quick peripheral component interconnection card |
CN105045350A (en) * | 2015-07-13 | 2015-11-11 | 浪潮电子信息产业股份有限公司 | PCIE (Peripheral Component Interface Express) extension method and PCIE extension system |
US9407022B1 (en) * | 2015-08-14 | 2016-08-02 | Amphenol East Asia Electronic Technology (Shen Zhen) Co., Ltd. | Unitary interface used for PCI-E SAS |
US9652000B1 (en) * | 2015-11-05 | 2017-05-16 | Super Micro Computer Inc. | Converter |
US9941643B2 (en) | 2015-12-26 | 2018-04-10 | Intel Corporation | Connectors with switchable terminal loads |
KR102092627B1 (en) | 2016-01-11 | 2020-03-24 | 몰렉스 엘엘씨 | Route assembly and system using same |
US11151300B2 (en) | 2016-01-19 | 2021-10-19 | Molex, Llc | Integrated routing assembly and system using same |
US10528509B2 (en) | 2016-01-29 | 2020-01-07 | Hewlett Packard Enterprise Development Lp | Expansion bus devices comprising retimer switches |
JP2017174693A (en) * | 2016-03-24 | 2017-09-28 | キヤノン株式会社 | Electronic apparatus |
US9946313B2 (en) | 2016-05-26 | 2018-04-17 | Dell Products, Lp | Peripheral card holder for an information handling system |
US9960811B1 (en) | 2016-10-27 | 2018-05-01 | Hewlett Packard Enterprise Development Lp | DC bias signals isolatable from transmission protocols |
US10310585B2 (en) | 2016-10-27 | 2019-06-04 | Qualcomm Incorporated | Replacement physical layer (PHY) for low-speed peripheral component interconnect (PCI) express (PCIe) systems |
TWM539644U (en) * | 2016-11-15 | 2017-04-11 | 映奧股份有限公司 | Storage module installed multiple M.2 SSDs |
US10977202B2 (en) * | 2017-01-28 | 2021-04-13 | Hewlett-Packard Development Company, L.P. | Adaptable connector with external I/O port |
EP3385855A1 (en) | 2017-04-07 | 2018-10-10 | Hewlett-Packard Development Company L.P. | Input/output modules |
CN107102709B (en) * | 2017-04-28 | 2019-08-27 | 郑州云海信息技术有限公司 | A kind of reliability devices improving multiserver administration signal |
CN107092570A (en) * | 2017-05-27 | 2017-08-25 | 郑州云海信息技术有限公司 | The adaptive configuring method and system of a kind of onboard M.2 hard disk of server |
US10963035B2 (en) | 2017-10-11 | 2021-03-30 | Qualcomm Incorporated | Low power PCIe |
FR3074930B1 (en) * | 2017-12-08 | 2019-11-15 | Ecrin Systems | COMPUTER, THE CENTRAL UNIT HAS A MINI SAS HD BASE FOR A CONNECTION TO AN EXTENSION CARD |
TWI663505B (en) * | 2018-05-28 | 2019-06-21 | 凌華科技股份有限公司 | Function module board |
TWI662417B (en) * | 2018-05-31 | 2019-06-11 | 緯創資通股份有限公司 | Switch card and server |
US11051422B2 (en) * | 2018-09-14 | 2021-06-29 | Hewlett Packard Enterprise Development Lp | Modular server design |
CN109471763B (en) * | 2018-11-01 | 2022-02-18 | 郑州云海信息技术有限公司 | Method, device, equipment and system for grabbing trace of NVME (network video management entity) hard disk |
US10585833B1 (en) * | 2019-01-28 | 2020-03-10 | Quanta Computer Inc. | Flexible PCIe topology |
US10958003B2 (en) * | 2019-08-09 | 2021-03-23 | Intel Corporation | Interleaved card/riser connection assembly for compact card integration |
US10951325B1 (en) | 2020-03-19 | 2021-03-16 | Dell Products L.P. | Use of siilicon photonics (SiP) for computer network interfaces |
CN112256618B (en) * | 2020-10-23 | 2022-10-21 | 新华三信息安全技术有限公司 | Mapping relation determining method and device |
US11695229B1 (en) * | 2021-02-19 | 2023-07-04 | Xilinx, Inc. | Auxiliary power connector PCB |
CN113886304B (en) * | 2021-09-06 | 2024-06-18 | 山东浪潮科学研究院有限公司 | Measurement and control backplate of PXIe |
CN114282487B (en) * | 2021-11-25 | 2024-02-02 | 苏州浪潮智能科技有限公司 | Method, system and device for UPI compatibility PCIE on PCB |
CN114201431A (en) * | 2021-12-30 | 2022-03-18 | 井芯微电子技术(天津)有限公司 | PCIe interface interfacing apparatus |
US11687130B1 (en) * | 2022-01-14 | 2023-06-27 | Dell Products L.P. | Heater apparatus-integrated peripheral component interconnect card for a computing device |
CN114676082B (en) * | 2022-03-25 | 2023-08-29 | 苏州浪潮智能科技有限公司 | Ampere server interface expansion structure and configuration method |
CN115344520B (en) * | 2022-10-18 | 2023-03-24 | 苏州浪潮智能科技有限公司 | Method and device for using PCIe interface compatible with silver fir card, storage medium and equipment |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080155156A1 (en) * | 2006-12-20 | 2008-06-26 | Kip Mussatt | Bridgeless switchless PCIe expansion |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080065805A1 (en) * | 2006-09-11 | 2008-03-13 | Cameo Communications, Inc. | PCI-Express multimode expansion card and communication device having the same |
US8520563B2 (en) * | 2008-06-02 | 2013-08-27 | Panasonic Corporation | Interface device, communications system, non-volatile storage device, communication mode switching method and integrated circuit |
US8446729B2 (en) * | 2009-03-23 | 2013-05-21 | Ocz Technology Group Inc. | Modular mass storage system and method therefor |
US20120260015A1 (en) * | 2011-04-07 | 2012-10-11 | Raphael Gay | Pci express port bifurcation systems and methods |
-
2011
- 2011-08-08 US US13/205,300 patent/US8693208B2/en active Active
-
2014
- 2014-02-07 US US14/175,627 patent/US9477630B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080155156A1 (en) * | 2006-12-20 | 2008-06-26 | Kip Mussatt | Bridgeless switchless PCIe expansion |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160142099A1 (en) * | 2014-11-14 | 2016-05-19 | International Business Machines Corporation | Tracking asset computing devices |
US9641218B2 (en) * | 2014-11-14 | 2017-05-02 | International Business Machines Corporation | Tracking asset computing devices |
US20160147699A1 (en) * | 2014-11-26 | 2016-05-26 | Dell Products, L.P. | Method and system for a flexible interconnect media in a point-to-point topography |
US10628366B2 (en) * | 2014-11-26 | 2020-04-21 | Dell Products, L.P. | Method and system for a flexible interconnect media in a point-to-point topography |
CN110647487A (en) * | 2019-08-09 | 2020-01-03 | 烽火通信科技股份有限公司 | Local Bus interface expansion device of PowerPC under pluggable expansion card structure |
Also Published As
Publication number | Publication date |
---|---|
US20120033370A1 (en) | 2012-02-09 |
US8693208B2 (en) | 2014-04-08 |
US20140156897A1 (en) | 2014-06-05 |
US9477630B2 (en) | 2016-10-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9477630B2 (en) | Method of connecting a PCIe bus extension system | |
US8151018B2 (en) | Dual-mode data transfer of uncompressed multimedia contents or data communications | |
US8090263B2 (en) | System and method for expanding PCIe compliant signals over a fiber optic medium with no latency | |
US9236674B2 (en) | Interface card assembly for use in a bus extension system | |
KR100887790B1 (en) | Multiple graphics adapter connection systems | |
TWI603202B (en) | Apparatuses and systems with redirection of lane resources | |
US20090271556A1 (en) | Connecting multiple peripheral interfaces into one attachment point | |
US10162784B2 (en) | Adapter for transmitting signals | |
US9734113B2 (en) | Peripheral component interconnect express (PCI-E) signal transmission apparatus and image forming apparatus using the same | |
TWI652565B (en) | Expansion slot interface | |
WO2012022015A1 (en) | Adapter card for converting pci express x1 to cpci express x1 | |
CN204904151U (en) | Built -in switching card | |
CN204883525U (en) | External switching card | |
TW201635156A (en) | Bidirectional lane routing | |
EP3637270A1 (en) | External electrical connector and computer system | |
US6065079A (en) | Apparatus for switching a bus power line to a peripheral device to ground in response to a signal indicating single ended configuration of the bus | |
CN108170619A (en) | A kind of expanding unit of PCIe device | |
US10754810B2 (en) | Interposer for peripheral component interconnect express generation 4 | |
US20090185559A1 (en) | Integration module for universal serial bus | |
US8751695B2 (en) | Hybrid storage device and electronic system using the same | |
US8677159B2 (en) | System and method for extending the USB power signal | |
US9785203B1 (en) | Flex cable interface | |
US8107245B1 (en) | Proximity active connector and cable | |
CN100347911C (en) | Universal serial bus connector | |
KR100775961B1 (en) | Universal Serial BUS Interface Device of Processor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: OCZ STORAGE SOLUTIONS INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:REINKE, KARL;KIM, DOKYUN;ALLEN, WILLIAM J.;REEL/FRAME:036947/0509 Effective date: 20110830 |
|
AS | Assignment |
Owner name: TOSHIBA CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OCZ STORAGE SOLUTIONS, INC.;REEL/FRAME:038434/0371 Effective date: 20160330 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: TOSHIBA MEMORY CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TOSHIBA CORPORATION;REEL/FRAME:043620/0430 Effective date: 20170706 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
AS | Assignment |
Owner name: K.K. PANGEA, JAPAN Free format text: MERGER;ASSIGNOR:TOSHIBA MEMORY CORPORATION;REEL/FRAME:055659/0471 Effective date: 20180801 Owner name: TOSHIBA MEMORY CORPORATION, JAPAN Free format text: CHANGE OF NAME AND ADDRESS;ASSIGNOR:K.K. PANGEA;REEL/FRAME:055669/0401 Effective date: 20180801 Owner name: KIOXIA CORPORATION, JAPAN Free format text: CHANGE OF NAME AND ADDRESS;ASSIGNOR:TOSHIBA MEMORY CORPORATION;REEL/FRAME:055669/0001 Effective date: 20191001 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |