US20160149642A1 - Driver Chip for Minimizing Transmission Impairments and for Boosting Signal Transmission Rates - Google Patents
Driver Chip for Minimizing Transmission Impairments and for Boosting Signal Transmission Rates Download PDFInfo
- Publication number
- US20160149642A1 US20160149642A1 US14/548,836 US201414548836A US2016149642A1 US 20160149642 A1 US20160149642 A1 US 20160149642A1 US 201414548836 A US201414548836 A US 201414548836A US 2016149642 A1 US2016149642 A1 US 2016149642A1
- Authority
- US
- United States
- Prior art keywords
- signal
- tapped delay
- driver chip
- optical
- taps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
- H04B10/2589—Bidirectional transmission
- H04B10/25891—Transmission components
-
- H04B10/2504—
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
- H04B10/2507—Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
- H04B10/2575—Radio-over-fibre, e.g. radio frequency signal modulated onto an optical carrier
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/58—Compensation for non-linear transmitter output
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2210/00—Indexing scheme relating to optical transmission systems
- H04B2210/25—Distortion or dispersion compensation
- H04B2210/254—Distortion or dispersion compensation before the transmission line, i.e. pre-compensation
Definitions
- the present invention pertains generally to systems and methods for transporting an optical signal over a fiber optic. More particularly, the present invention pertains to systems and methods for shaping an electrical signal, to compensate for impairments, distortions and mismatch values that are introduced into the electrical signal during its conversion into an optical signal and its subsequent transmission over an optical fiber.
- the present invention is particularly, but not exclusively, useful for systems and methods that employ tapped delay equalizers having weighted taps to compensate for impedance mismatch impairments, electrical pre-distortions and transmission line losses during an optical signal transmission.
- Tapped delay equalizers are well known in pertinent signal processing technologies as being an effective means for shaping electrical signals. They are widely used in a variety of electric/optical environments, and they are employed for a plethora of different purposes.
- the electrical/optical environment of interest involves the transmission of optical signals over a fiber optic.
- a purpose here is to provide an effective driver chip for use in a system that includes Electrical/Optical (E/O) and Optical/Electrical (O/E) converters, which will optimize the quality of signal transmissions.
- E/O Electrical/Optical
- O/E Optical/Electrical
- ISI InterSymbol Interference
- the present invention also recognizes that an “eye diagram,” of a type well known in the pertinent art, can be used to monitor the design, the signal-to-noise ratio (SNR), and the testing or reconfiguration of an analog tapped delay equalizer.
- SNR signal-to-noise ratio
- an optimal operation for the driver chip is indicated when the “eye” of the eye diagram is open to its greatest extent.
- an object of the present invention to provide a system and method for simultaneously minimizing operational and architectural impairments during the transmission of an optical signal over an optical fiber.
- Another object of the present invention is to establish tap weights for the tapped delay equalizer of a driver chip that can be controlled to minimize impairments and distortions to an output signal that are caused by transmission line losses and impedance mismatches, as well as other electrical and photonic impairments.
- Another object of the present invention is to optimize bandwidth and ISI performance.
- Yet another object of the present invention is to provide a driver chip for use in optimizing the transmission of an optical signal over an optical fiber that is easy to use, is simple to implement, and is comparatively cost effective.
- a driver chip for transmitting optical signals over an optical fiber.
- the driver chip is designed and configured to minimize impairments to signal transmissions, and to thereby optimize the quality of these transmissions.
- the driver chip includes, in combination: an analog tapped delay equalizer, an amplifier with gain and bias control, and control circuitry for maintaining an operation of the driver chip. It is an important aspect of the present invention that minimizing impairments and optimizing signal quality is accomplished simultaneously by providing a proper operating configuration of the tap weights for the tapped delay equalizer.
- the input signal for the driver chip will be a digital signal.
- a digitally modulated signal has a characteristic symbol rate, R s .
- this symbol rate, R s is equal to the number of symbol changes (i.e. waveform changes or signaling events) that are made per second.
- FFE Feed Forward Equalizer
- a tapped delay equalizer needs to be programmed (configured) for compliance with the symbol rate, R s , of the digitally modulated input signal.
- additional considerations include the time delay, d n , between adjacent taps, and the number of taps per symbol, N.
- time delay, d n will be less than the symbol time duration, T.
- the number of taps, n, that are used with the tapped delay equalizer (FFE) will need to be three or more (n ⁇ 3).
- the tapped delay equalizer is positioned on the driver chip to receive an input digital signal.
- the equalizer receiving this input digital signal will have an n-number of taps, and a time delay, d n , between adjacent taps can be established as desired for the particular chip.
- d n ⁇ T.
- d n is constant.
- d n is preferably the same between all adjacent taps (i.e.
- the amplifier of the driver chip is connected with the tap delay equalizer for receiving the compensated signal. Further, in this combination, the amplifier provides gain for the signal, and it includes a biasing element to bias the compensated signal. Thus, bulky external bias circuitry is eliminated. Further, this on-chip control is provided to control average power and to stabilize laser operation.
- the general, overall purpose here is to create an electrical output signal for the driver chip which has a proper operating point.
- control circuitry is provided on, or off, the driver chip to interconnect with the other components.
- the connection between the amplifier and the control circuitry, either on or off the chip, is used to control a gain and a bias for the amplifier.
- its connection with the tapped delay equalizer is provided to control tap weights for individual taps of the tapped delay filter.
- the driver chip will normally be electronically connected to an Electrical/Optical (E/O) converter which will convert the electrical output signal into an optical signal, ⁇ .
- E/O Electrical/Optical
- a low-pass filter can be inserted between the driver chip and the E/O converter to achieve the required spectrum shaping using fewer filter taps during a transmission of the optical signal, ⁇ , over an optical fiber.
- these components i.e. the E/O converter, the low-pass filter, and the fiber optic
- these components i.e. the E/O converter, the low-pass filter, and the fiber optic
- the taps of the tapped delay equalizer are weighted. Specifically, this is done to minimize impairments to the output signal that may be caused by distortions, line losses and mismatch values that are introduced during creation of the optical signal, ⁇ . As intended for the present invention, however, the taps can also be weighted to achieve other purposes.
- an eye diagram can be used to verify its optimal operation.
- FIG. 1 is a schematic presentation of a driver chip in accordance with the present invention
- FIG. 2 is a detailed presentation of operational components of the driver chip in combination with system components required for transmission of an optical signal
- FIG. 3 is a schematic presentation of a typical electrical environment for the driver chip of the present invention, illustrating an impairment requiring mismatch compensation from the driver chip;
- FIG. 4 is an exemplary graph of tap locations and respective tap weights presented on a time line for a 9 tap Gaussian equalizer employing 2-tap/symbol;
- FIG. 5A is a representative eye diagram of an exemplary optical transmission system without equalization
- FIG. 5B is a representative eye diagram of the same optical transmission system considered for FIG. 5A which results when the system is equalized by a 3 tap Gaussian equalizer employing 1-tap/symbol;
- FIG. 5C is a representative eye diagram of the same optical transmission system considered for FIGS. 5A and 5B which results when the system is equalized by a 9 tap Gaussian equalizer employing 2-taps/symbol.
- a driver chip in accordance with the present invention is shown and is generally designated 10 .
- the essential components of the driver chip 10 include: a tapped delay equalizer 12 (e.g. Feed Forward Equalizer [FFE]); an amplifier 14 with an Electrical/Optical (E/O) bias; and a control circuitry 16 .
- FIG. 1 indicates that an input signal 18 is fed directly to the tapped delay equalizer 12 , and that a compensated signal 20 is created as an output of the driver chip 10 .
- both the tapped delay equalizer 12 and the amplifier 14 are controlled by the circuitry 16 .
- control circuitry 16 shown in FIG. 1 is an integral component of the driver chip 10 , it will be appreciated by the skilled artisan that the control circuitry 16 can properly operate while separated from the substrate of driver chip 10 .
- FIG. 2 A system which establishes architecture for incorporating the driver chip 10 is shown in FIG. 2 , where the system is generally designated 22 .
- an input device 24 is provided to generate the input signal 18 .
- FIG. 2 shows that the tapped delay equalizer 12 has an n-number of taps, a n , with a time delay, d n , between adjacent taps (e.g. a n and a n+1 ).
- d n time delay between adjacent taps
- the control circuitry 16 includes an equalizer control 26 that is connected directly to each of the taps, a n , and a bias/gain control 28 that is connected directly to the amplifier 14 .
- FIG. 2 further indicates that in the system 22 , the driver chip 10 can be connected to a low pass filter 30 to achieve the required spectrum shaping using fewer filter taps.
- an E/O device (converter) 32 is shown for converting the compensated signal 20 into an optical signal, ⁇ .
- a fiber optic (transmission medium) 34 is shown for use in transporting the optical signal, ⁇ , to an Optical/Electrical (O/E) device 36 (see FIG. 3 ) where it is reconverted to an electrical signal for further processing.
- O/E Optical/Electrical
- FIG. 3 is provided to illustrate an exemplary impedance mismatch 40 which requires compensation by the driver chip 10 of the present invention.
- the impedance mismatch 40 is shown to be the result of reflections that will occur between the driver chip 10 and the E/O device 32 of the system 22 .
- the letter L shown in FIG. 3 indicates that a time delay can occur or develop between the E/O driver chip 10 and the E/O device 32 . When this happens, the resultant separation will cause a round trip delay of 2L for any reflections between the driver chip 10 and the E/O device 32 . As is well known, these reflections will create an impairment.
- the present invention recognizes that such an impairment can be compensated for using the tapped delay equalizer 12 of the driver chip 10 when the 2L delay is less than about one half of the total tapped delay of the tapped delay equalizer (FFE) 12 .
- the present invention envisions being able to provide a substantial correction for impedance mismatch (ISI) impairments when 2L ⁇ d n /2.
- an overarching purpose for the driver chip 10 is to minimize all forms of impairments in the system 22 , and to optimize the signal quality provided by the system 22 .
- this is achieved by establishing a proper weighting configuration for the taps, a n , in the tapped delay equalizer 12 , and by maintaining a proper operating point for the E/O device 32 .
- a detailed description of pertinent transmission characteristics for a tapped delay equalizer (FFE) 12 of the present invention is presented as a schema 42 in FIG. 4 .
- the time duration, T, for each symbol is established based on characteristics of the input signal 18 and its symbol rate, R s .
- N the time duration
- d n T/2 (i.e. d n ⁇ T).
- the same organization for tap location pertains for the remaining symbols T 2 et seq.
- a shaping of the input signal 18 is accomplished for the purpose of minimizing the effect of impairments on the output compensated signal 20 .
- this is done to minimize the effect of impairments caused by all sources required for the optical transmission of the input signal 18 .
- these impairments can include: 1) transmission line losses, along with impedance mismatch distortions that are introduced at interfaces between system components (e.g. driver chip, E/O converter, fiber optic, and O/E converter); 2) electrical and photonic signal distortions caused by impairments such as amplitude and group delay distortions, photon—carrier lifetime effects, and fiber dispersion; and 3) other additional impairments from signal characteristics that can be attributed to slow rise/fall time, and laser relaxation peak effect.
- compensation for these impairments is done by appropriately weighting the samples a n taken from the various taps of the tapped delay equalizer (FFE) 12 .
- FFE tapped delay equalizer
- programming of the tapped delay equalizer 12 is done by first creating a test model of the intended signal transmission system.
- this will include the driver chip 10 together with selected associated components, such as the E/O device 32 , the low pass filter 30 (optional), the transmission medium 34 (e.g. fiber optic), and the O/E device 36 .
- the collective response of components in a signal transmission system is monitored, and respective gains are set for the taps a n of the tapped delay equalizer 12 to minimize impairments caused by these components.
- the collective response is monitored using an eye diagram 44 of a type well known in the pertinent art.
- the eye diagram 44 is preferably taken at the output of the O/E device 36 . This positioning, however, is only exemplary. Moreover, it is to be appreciated that, regardless where the eye diagram 44 is placed, the compensation to be provided by the driver chip 10 will extend to all components throughout the particular signal transmission system.
- FIGS. 5A-C an operational validation of the driver chip 10 for the present invention is evidenced by sequentially presenting the results from a same optical transmission system.
- the results from using three different configurations for the tapped delay equalizer 12 of the driver chip 10 are shown.
- the eye diagram 44 shown in FIG. 5A resulted when there was no equalization for the optical transmission system.
Abstract
Description
- The present invention pertains generally to systems and methods for transporting an optical signal over a fiber optic. More particularly, the present invention pertains to systems and methods for shaping an electrical signal, to compensate for impairments, distortions and mismatch values that are introduced into the electrical signal during its conversion into an optical signal and its subsequent transmission over an optical fiber. The present invention is particularly, but not exclusively, useful for systems and methods that employ tapped delay equalizers having weighted taps to compensate for impedance mismatch impairments, electrical pre-distortions and transmission line losses during an optical signal transmission.
- Tapped delay equalizers are well known in pertinent signal processing technologies as being an effective means for shaping electrical signals. They are widely used in a variety of electric/optical environments, and they are employed for a plethora of different purposes. For the present invention, the electrical/optical environment of interest involves the transmission of optical signals over a fiber optic. Accordingly, a purpose here is to provide an effective driver chip for use in a system that includes Electrical/Optical (E/O) and Optical/Electrical (O/E) converters, which will optimize the quality of signal transmissions.
- From a system perspective, it happens there are many ways in which a signal can be distorted and corrupted as it is being processed and transmitted. To some extent, but not entirely, the source and effect of these distortions and corruptions (i.e. impairments) are known, or can be predicted. Thus, they can be at least partially compensated for. For instance, these impairments can include: 1) transmission line losses, along with impedance mismatch distortions such as InterSymbol Interference (ISI) that can be introduced at interfaces between system components (e.g. driver chip, E/O converter, fiber optic, and O/E converter); 2) electrical and photonic signal distortions caused by impairments such as amplitude and group delay distortions, photon—carrier lifetime effects, and fiber dispersion; and 3) other additional impairments from signal characteristics that can be attributed to slow rise/fall time and laser relaxation peak effect and E/O device parasitics. The present invention, however, recognizes that all of the various impairments noted above can be collectively compensated for by the employment and proper configuration of an analog tapped delay equalizer.
- The present invention also recognizes that an “eye diagram,” of a type well known in the pertinent art, can be used to monitor the design, the signal-to-noise ratio (SNR), and the testing or reconfiguration of an analog tapped delay equalizer. When monitored, an optimal operation for the driver chip is indicated when the “eye” of the eye diagram is open to its greatest extent.
- With the above in mind, it is an object of the present invention to provide a system and method for simultaneously minimizing operational and architectural impairments during the transmission of an optical signal over an optical fiber. Another object of the present invention is to establish tap weights for the tapped delay equalizer of a driver chip that can be controlled to minimize impairments and distortions to an output signal that are caused by transmission line losses and impedance mismatches, as well as other electrical and photonic impairments. Another object of the present invention is to optimize bandwidth and ISI performance. Yet another object of the present invention is to provide a driver chip for use in optimizing the transmission of an optical signal over an optical fiber that is easy to use, is simple to implement, and is comparatively cost effective.
- In accordance with the present invention, a driver chip is provided for transmitting optical signals over an optical fiber. For purposes of this invention, the driver chip is designed and configured to minimize impairments to signal transmissions, and to thereby optimize the quality of these transmissions. Structurally, the driver chip includes, in combination: an analog tapped delay equalizer, an amplifier with gain and bias control, and control circuitry for maintaining an operation of the driver chip. It is an important aspect of the present invention that minimizing impairments and optimizing signal quality is accomplished simultaneously by providing a proper operating configuration of the tap weights for the tapped delay equalizer. Typically, the input signal for the driver chip will be a digital signal.
- As is well known in the pertinent art, a digitally modulated signal has a characteristic symbol rate, Rs. By definition, this symbol rate, Rs, is equal to the number of symbol changes (i.e. waveform changes or signaling events) that are made per second. For a digital signal transmission, wherein each symbol has a time duration, T, the symbol rate is equal to the reciprocal of T (i.e. Rs=1/T). This relationship becomes particularly important when signal shaping is to be accomplished using an analog Feed Forward Equalizer (FFE), i.e. a tapped delay equalizer.
- For purposes of the present invention, a tapped delay equalizer needs to be programmed (configured) for compliance with the symbol rate, Rs, of the digitally modulated input signal. In this context, additional considerations include the time delay, dn, between adjacent taps, and the number of taps per symbol, N. In general, for a preferred embodiment of the present invention, time delay, dn, will be less than the symbol time duration, T. Thus, there will always be at least one tap per symbol (i.e. N>1). Preferably, the number of taps, n, that are used with the tapped delay equalizer (FFE) will need to be three or more (n≧3). For the many reasons set forth elsewhere herein, a preferred embodiment of the present invention will include a tapped delay equalizer having two taps per symbol (N=2) and a total of nine taps (n=9).
- In light of the above, the tapped delay equalizer is positioned on the driver chip to receive an input digital signal. As envisioned for the present invention and indicated above, the input digital signal may be of any type well known in the pertinent art, and as mentioned above it will be characterized by a symbol rate, Rs, where there is a time duration, T, for each symbol (i.e. Rs=1/T). The equalizer receiving this input digital signal will have an n-number of taps, and a time delay, dn, between adjacent taps can be established as desired for the particular chip. Importantly, dn<T. Preferably, dn is constant. Moreover, although dn is preferably the same between all adjacent taps (i.e. dn−1=dn=dn+1), depending on the needs of the particular system, this may not necessarily be so (i.e. dn−1≠dn and/or dn≠dn+1). In any event, the tapped delay equalizer is employed to modify the input digital signal, and to thereby create a compensated signal.
- On the driver chip, the amplifier of the driver chip is connected with the tap delay equalizer for receiving the compensated signal. Further, in this combination, the amplifier provides gain for the signal, and it includes a biasing element to bias the compensated signal. Thus, bulky external bias circuitry is eliminated. Further, this on-chip control is provided to control average power and to stabilize laser operation. The general, overall purpose here is to create an electrical output signal for the driver chip which has a proper operating point.
- In addition to the tapped delay equalizer and the amplifier, control circuitry is provided on, or off, the driver chip to interconnect with the other components. In detail, the connection between the amplifier and the control circuitry, either on or off the chip, is used to control a gain and a bias for the amplifier. On the other hand, its connection with the tapped delay equalizer is provided to control tap weights for individual taps of the tapped delay filter.
- In a larger context, as part of a system, the driver chip will normally be electronically connected to an Electrical/Optical (E/O) converter which will convert the electrical output signal into an optical signal, λ. Also, in such a system, a low-pass filter can be inserted between the driver chip and the E/O converter to achieve the required spectrum shaping using fewer filter taps during a transmission of the optical signal, λ, over an optical fiber. In each instance, as noted above, these components (i.e. the E/O converter, the low-pass filter, and the fiber optic) will introduce impairments that need to be considered for compensation by analog FFE of the driver chip.
- For an operation of the driver chip, the taps of the tapped delay equalizer are weighted. Specifically, this is done to minimize impairments to the output signal that may be caused by distortions, line losses and mismatch values that are introduced during creation of the optical signal, λ. As intended for the present invention, however, the taps can also be weighted to achieve other purposes.
- During a setup of the driver chip of the present invention, an eye diagram can be used to verify its optimal operation.
- The novel features of this invention, as well as the invention itself, both as to its structure and its operation, will be best understood from the accompanying drawings, taken in conjunction with the accompanying description, in which similar reference characters refer to similar parts, and in which:
-
FIG. 1 is a schematic presentation of a driver chip in accordance with the present invention; -
FIG. 2 is a detailed presentation of operational components of the driver chip in combination with system components required for transmission of an optical signal; -
FIG. 3 is a schematic presentation of a typical electrical environment for the driver chip of the present invention, illustrating an impairment requiring mismatch compensation from the driver chip; -
FIG. 4 is an exemplary graph of tap locations and respective tap weights presented on a time line for a 9 tap Gaussian equalizer employing 2-tap/symbol; -
FIG. 5A is a representative eye diagram of an exemplary optical transmission system without equalization; -
FIG. 5B is a representative eye diagram of the same optical transmission system considered forFIG. 5A which results when the system is equalized by a 3 tap Gaussian equalizer employing 1-tap/symbol; and -
FIG. 5C is a representative eye diagram of the same optical transmission system considered forFIGS. 5A and 5B which results when the system is equalized by a 9 tap Gaussian equalizer employing 2-taps/symbol. - Referring initially to
FIG. 1 , a driver chip in accordance with the present invention is shown and is generally designated 10. As shown, the essential components of thedriver chip 10 include: a tapped delay equalizer 12 (e.g. Feed Forward Equalizer [FFE]); anamplifier 14 with an Electrical/Optical (E/O) bias; and acontrol circuitry 16. Further,FIG. 1 indicates that aninput signal 18 is fed directly to the tappeddelay equalizer 12, and that a compensatedsignal 20 is created as an output of thedriver chip 10. In this process, both the tappeddelay equalizer 12 and theamplifier 14 are controlled by thecircuitry 16. Note: althoughcontrol circuitry 16 shown inFIG. 1 is an integral component of thedriver chip 10, it will be appreciated by the skilled artisan that thecontrol circuitry 16 can properly operate while separated from the substrate ofdriver chip 10. - A system which establishes architecture for incorporating the
driver chip 10 is shown inFIG. 2 , where the system is generally designated 22. InFIG. 2 it will be seen that aninput device 24 is provided to generate theinput signal 18. As envisioned for the present invention, theinput signal 18 will be either linear or digital. In either case, it will be characterized by a symbol rate, Rs, having a time duration, T, for each symbol of the signal 18 (i.e. Rs=1/T). - In detail,
FIG. 2 shows that the tappeddelay equalizer 12 has an n-number of taps, an, with a time delay, dn, between adjacent taps (e.g. an and an+1). Importantly, as noted above, in the relationship between the taps, an, of the tappeddelay equalizer 12 and the symbol rate, Rs, of thedigital input signal 18, it is necessary that dn be less than T, (dn<T). Additionally,FIG. 2 shows that thecontrol circuitry 16 includes anequalizer control 26 that is connected directly to each of the taps, an, and a bias/gain control 28 that is connected directly to theamplifier 14. -
FIG. 2 further indicates that in thesystem 22, thedriver chip 10 can be connected to alow pass filter 30 to achieve the required spectrum shaping using fewer filter taps. Additionally, an E/O device (converter) 32 is shown for converting the compensatedsignal 20 into an optical signal, λ. To achieve the purpose of the present invention, a fiber optic (transmission medium) 34 is shown for use in transporting the optical signal, λ, to an Optical/Electrical (O/E) device 36 (seeFIG. 3 ) where it is reconverted to an electrical signal for further processing. -
FIG. 3 is provided to illustrate anexemplary impedance mismatch 40 which requires compensation by thedriver chip 10 of the present invention. In this example, theimpedance mismatch 40 is shown to be the result of reflections that will occur between thedriver chip 10 and the E/O device 32 of thesystem 22. In detail, the letter L shown inFIG. 3 indicates that a time delay can occur or develop between the E/O driver chip 10 and the E/O device 32. When this happens, the resultant separation will cause a round trip delay of 2L for any reflections between thedriver chip 10 and the E/O device 32. As is well known, these reflections will create an impairment. The present invention, however, recognizes that such an impairment can be compensated for using the tappeddelay equalizer 12 of thedriver chip 10 when the 2L delay is less than about one half of the total tapped delay of the tapped delay equalizer (FFE) 12. Stated differently, the present invention envisions being able to provide a substantial correction for impedance mismatch (ISI) impairments when 2L≦Σdn/2. - As will be appreciated by anyone skilled in the pertinent art, there will likely be many other examples of impedance mismatches in the
system 22, in addition to theimpedance mismatch 40 illustrated inFIG. 3 . Indeed, an overarching purpose for thedriver chip 10 is to minimize all forms of impairments in thesystem 22, and to optimize the signal quality provided by thesystem 22. For the present invention, this is achieved by establishing a proper weighting configuration for the taps, an, in the tappeddelay equalizer 12, and by maintaining a proper operating point for the E/O device 32. - A detailed description of pertinent transmission characteristics for a tapped delay equalizer (FFE) 12 of the present invention is presented as a schema 42 in
FIG. 4 . With reference toFIG. 4 it is to be appreciated that the schema 42 for the represented tap delayed equalizer (FFE) 12 has nine taps (i.e. n=9). In this example, as described above, the time duration, T, for each symbol is established based on characteristics of theinput signal 18 and its symbol rate, Rs. With this in mind, recall that for any modulateddigital input signal 18, Rs and T are reciprocally related (i.e. T=1/Rs). - As represented in
FIG. 4 , the exemplary tapped delay equalizer (FFE) 12 has two taps per symbol (e.g. taps n=1 and n=2). Accordingly, respectively weighted samples a1 and a2 are both taken together in the first symbol having the time duration T1. In this example, N=2. As further shown in this example, dn=T/2 (i.e. dn<T). The same organization for tap location pertains for the remaining symbols T2 et seq. - In accordance with the present invention, a shaping of the
input signal 18 is accomplished for the purpose of minimizing the effect of impairments on the output compensatedsignal 20. Importantly, this is done to minimize the effect of impairments caused by all sources required for the optical transmission of theinput signal 18. As noted above, these impairments can include: 1) transmission line losses, along with impedance mismatch distortions that are introduced at interfaces between system components (e.g. driver chip, E/O converter, fiber optic, and O/E converter); 2) electrical and photonic signal distortions caused by impairments such as amplitude and group delay distortions, photon—carrier lifetime effects, and fiber dispersion; and 3) other additional impairments from signal characteristics that can be attributed to slow rise/fall time, and laser relaxation peak effect. In particular, compensation for these impairments is done by appropriately weighting the samples an taken from the various taps of the tapped delay equalizer (FFE) 12. - As envisioned for the present invention, programming of the tapped
delay equalizer 12 is done by first creating a test model of the intended signal transmission system. For the present invention this will include thedriver chip 10 together with selected associated components, such as the E/O device 32, the low pass filter 30 (optional), the transmission medium 34 (e.g. fiber optic), and the O/E device 36. In this programming process, the collective response of components in a signal transmission system is monitored, and respective gains are set for the taps an of the tappeddelay equalizer 12 to minimize impairments caused by these components. Specifically, as intended for the present invention, the collective response is monitored using an eye diagram 44 of a type well known in the pertinent art. - In
FIG. 3 , it will be seen that the eye diagram 44 is preferably taken at the output of the O/E device 36. This positioning, however, is only exemplary. Moreover, it is to be appreciated that, regardless where the eye diagram 44 is placed, the compensation to be provided by thedriver chip 10 will extend to all components throughout the particular signal transmission system. - Referring to
FIGS. 5A-C , an operational validation of thedriver chip 10 for the present invention is evidenced by sequentially presenting the results from a same optical transmission system. In sequence, the results from using three different configurations for the tappeddelay equalizer 12 of thedriver chip 10 are shown. The eye diagram 44 shown inFIG. 5A resulted when there was no equalization for the optical transmission system. InFIG. 5B , a system that has been equalized by a 3-tap (n=3) tappeddelay equalizer 12, and that uses the conventional spacing of one tap per symbol, resulted in an eye diagram 44′ which shows some slight improvement over the uncompensated eye diagram 44 ofFIG. 5A . Eye diagram 44″ inFIG. 5C , however, which resulted from the use of a 9-tap (n=9) tappeddelay equalizer 12 with two taps per symbol, as disclosed and discussed above for a preferred embodiment of the present invention, shows a marked improvement over the less compensated configurations of tappeddelay equalizer 12 shown inFIGS. 5A and 5B . - While the particular Driver Chip for Minimizing Transmission Impairments and for Boosting Signal Transmission Rates as herein shown and disclosed in detail is fully capable of obtaining the objects and providing the advantages herein before stated, it is to be understood that it is merely illustrative of the presently preferred embodiments of the invention and that no limitations are intended to the details of construction or design herein shown other than as described in the appended claims.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/548,836 US9344192B1 (en) | 2014-11-20 | 2014-11-20 | Driver chip for minimizing transmission impairments and for boosting signal transmission rates |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/548,836 US9344192B1 (en) | 2014-11-20 | 2014-11-20 | Driver chip for minimizing transmission impairments and for boosting signal transmission rates |
Publications (2)
Publication Number | Publication Date |
---|---|
US9344192B1 US9344192B1 (en) | 2016-05-17 |
US20160149642A1 true US20160149642A1 (en) | 2016-05-26 |
Family
ID=55920227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/548,836 Active 2034-12-02 US9344192B1 (en) | 2014-11-20 | 2014-11-20 | Driver chip for minimizing transmission impairments and for boosting signal transmission rates |
Country Status (1)
Country | Link |
---|---|
US (1) | US9344192B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9762417B1 (en) * | 2016-09-28 | 2017-09-12 | Integra Research And Development, Llc | Adaptive equalization for vestigial sideband (VSB) transmissions |
US20230086636A1 (en) * | 2013-04-05 | 2023-03-23 | International Business Machines Corporation | System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks |
Family Cites Families (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3488586A (en) | 1965-06-02 | 1970-01-06 | Gen Electric | Frequency modulated light coupled data link |
US3794841A (en) | 1972-07-25 | 1974-02-26 | L Cosentino | Light coupling data transfer system |
US4812641A (en) | 1987-02-03 | 1989-03-14 | General Electric Company | High power optical fiber failure detection system |
US5191459A (en) | 1989-12-04 | 1993-03-02 | Scientific-Atlanta, Inc. | Method and apparatus for transmitting broadband amplitude modulated radio frequency signals over optical links |
JP3205127B2 (en) | 1993-06-22 | 2001-09-04 | キヤノン株式会社 | Communication control method and device |
US6334219B1 (en) | 1994-09-26 | 2001-12-25 | Adc Telecommunications Inc. | Channel selection for a hybrid fiber coax network |
US5541951A (en) | 1994-11-14 | 1996-07-30 | Intelligent Surgical Lasers, Inc. | Device and method for high-power end pumping |
US5596436A (en) | 1995-07-14 | 1997-01-21 | The Regents Of The University Of California | Subcarrier multiplexing with dispersion reduction and direct detection |
US5777768A (en) | 1995-09-01 | 1998-07-07 | Astroterra Corporation | Multiple transmitter laser link |
US5680104A (en) | 1996-05-31 | 1997-10-21 | Volution | Fiber optic security system |
US5871449A (en) | 1996-12-27 | 1999-02-16 | Brown; David Lloyd | Device and method for locating inflamed plaque in an artery |
US6101216A (en) * | 1997-10-03 | 2000-08-08 | Rockwell International Corporation | Splitterless digital subscriber line communication system |
US6118131A (en) | 1998-05-11 | 2000-09-12 | Astro Terra Corporation | Directional optics for a system for directing a laser beam toward an active area |
US6091074A (en) | 1998-05-11 | 2000-07-18 | Astroterra Corporation | System for directing a laser beam toward an active area |
US6353490B1 (en) | 1999-05-12 | 2002-03-05 | Quintech, Inc. | C/N performance of broadband two-way transmission of RF signals over transmission mediums with limited bandwidth |
US20060165413A1 (en) | 1999-05-24 | 2006-07-27 | Broadband Royalty Corporation | DWDM CATV return system with up-converters to prevent fiber crosstalk |
US7088921B1 (en) | 1999-06-11 | 2006-08-08 | Lucent Technologies Inc. | System for operating an Ethernet data network over a passive optical network access system |
US6493485B1 (en) | 1999-08-03 | 2002-12-10 | Astro Terra Corporation | Systems and methods for aligning a laser beam with an optical fiber |
EP1204227B1 (en) | 1999-08-13 | 2006-12-27 | Fujitsu Limited | Optical communication system and terminal device |
US7146103B2 (en) | 1999-12-29 | 2006-12-05 | Forster Energy Llc | Optical communications using multiplexed single sideband transmission and heterodyne detection |
GB2359636B (en) | 2000-02-22 | 2002-05-01 | Marconi Comm Ltd | Wavelength selective optical filter |
US6760371B1 (en) * | 2000-03-22 | 2004-07-06 | The Boeing Company | Method and apparatus implementation of a zero forcing equalizer |
US6944403B2 (en) | 2000-06-09 | 2005-09-13 | Shlomo Margalit | MEMS based over-the-air optical data transmission system |
US20020012495A1 (en) | 2000-06-29 | 2002-01-31 | Hiroyuki Sasai | Optical transmission system for radio access and high frequency optical transmitter |
US20020076132A1 (en) | 2000-12-15 | 2002-06-20 | Peral Eva M. | Optical filter for simultaneous single sideband modulation and wavelength stabilization |
US6686800B2 (en) | 2001-02-13 | 2004-02-03 | Quantum Applied Science And Research, Inc. | Low noise, electric field sensor |
US6538789B2 (en) | 2001-04-03 | 2003-03-25 | Lightwave Solutions, Inc. | Optical linearizer for fiber communications |
US6928248B2 (en) | 2001-05-30 | 2005-08-09 | Optical Access, Inc. | Optical communications system with back-up link |
US7209442B1 (en) | 2001-06-27 | 2007-04-24 | Cisco Technology, Inc. | Packet fiber node |
EP1330061A1 (en) | 2002-01-11 | 2003-07-23 | Alcatel | Optical filter and transmission system incorporating an optical filter |
JP2004172237A (en) | 2002-11-18 | 2004-06-17 | Sharp Corp | Optical transmission control unit |
KR100557144B1 (en) | 2004-01-12 | 2006-03-03 | 삼성전자주식회사 | Ethernet Passive Optical Network for Convergence of Broadcasting and Telecommunication By Using Time Dividing Multiplex |
KR100671052B1 (en) | 2005-06-13 | 2007-01-17 | 한국전자통신연구원 | An Optical transceiver having a function of multiplexing in hybrid fiber coaxial network |
US8335226B2 (en) | 2005-08-03 | 2012-12-18 | Broadcom Corporation | Systems and methods to transmit information among a plurality of physical upstream channels |
US9559871B2 (en) * | 2006-01-10 | 2017-01-31 | Alcatel-Lucent Usa Inc. | Composite channel equalization of a wideband wireless communication system |
US7825836B1 (en) * | 2006-07-13 | 2010-11-02 | Marvell International, Ltd | Limit equalizer output based timing loop |
US7525460B1 (en) * | 2006-07-13 | 2009-04-28 | Marvell International Ltd. | Timing loop based on analog to digital converter output and method of use |
US20100329680A1 (en) | 2007-10-29 | 2010-12-30 | Marco Presi | Optical networks |
US8032029B2 (en) | 2008-02-20 | 2011-10-04 | Harmonic Inc. | Four wave mixing suppression |
US8131156B2 (en) | 2008-05-01 | 2012-03-06 | Nec Laboratories America, Inc. | Centralized lightwave WDM-PON employing intensity modulated downstream and upstream |
US8385401B2 (en) * | 2008-10-20 | 2013-02-26 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd | Equalizer and method for performing equalization |
US8135288B2 (en) | 2009-02-03 | 2012-03-13 | The Boeing Company | System and method for a photonic system |
US9350451B2 (en) | 2009-04-22 | 2016-05-24 | Broadcom Corporation | Signal detection for optical transmitters in networks with optical combining |
US8260153B2 (en) * | 2009-12-10 | 2012-09-04 | Alcatel Lucent | Method and apparatus for polarization-division-multiplexed optical coherent receivers |
US8463137B2 (en) | 2010-09-27 | 2013-06-11 | Titan Photonics, Inc. | System and method for transmissions via RF over glass |
US8463124B2 (en) | 2010-12-28 | 2013-06-11 | Titan Photonics, Inc. | Passive optical network with sub-octave transmission |
US8483566B2 (en) | 2011-03-10 | 2013-07-09 | Titan Photonics, Inc. | Sub-octave RF stacking for optical transport and de-stacking for distribution |
US8804808B1 (en) * | 2014-01-14 | 2014-08-12 | The Aerospace Corporation | Dynamic equalization systems and methods for use with a receiver for a multipath channel |
US9735867B2 (en) * | 2014-04-25 | 2017-08-15 | Arris Enterprises Llc | Microreflection delay estimation in a CATV network |
-
2014
- 2014-11-20 US US14/548,836 patent/US9344192B1/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230086636A1 (en) * | 2013-04-05 | 2023-03-23 | International Business Machines Corporation | System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks |
US9762417B1 (en) * | 2016-09-28 | 2017-09-12 | Integra Research And Development, Llc | Adaptive equalization for vestigial sideband (VSB) transmissions |
Also Published As
Publication number | Publication date |
---|---|
US9344192B1 (en) | 2016-05-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10547387B2 (en) | Transition based feedforward equalization method and apparatus implemented with lookup table circuits | |
US9705708B1 (en) | Integrated circuit with continuously adaptive equalization circuitry | |
US7940839B2 (en) | Fully adaptive equalization for high loss communications channels | |
US7949041B2 (en) | Methods and circuits for asymmetric distribution of channel equalization between devices | |
US9071479B2 (en) | High-speed parallel decision feedback equalizer | |
US8054876B2 (en) | Active delay line | |
US20040001540A1 (en) | Method and apparatus for channel equalization | |
US8873615B2 (en) | Method and controller for equalizing a received serial data stream | |
US9306780B2 (en) | Optical transmission for binary and duobinary modulation formats | |
US8817867B1 (en) | Adaptive continuous time linear equalizer | |
EP1392013A2 (en) | Hybrid adaptive equalizer for optical communication systems | |
US20210044086A1 (en) | Non-linear filter for dml | |
JPWO2012029613A1 (en) | DIGITAL FILTER DEVICE, DIGITAL FILTERING METHOD, AND DIGITAL FILTER DEVICE CONTROL PROGRAM | |
US10523471B2 (en) | Look ahead based method and apparatus for equalizing pulse amplitude modulation electronic signals | |
US20150312056A1 (en) | Apparatus and methods for estimating optical ethernet data sequences | |
US20150063828A1 (en) | Generalized Transmit Pre-Coding for Optical and Backplane Channels | |
US20200084069A1 (en) | Clockless decision feedback equalization (dfe) for multi-level signals | |
US9344192B1 (en) | Driver chip for minimizing transmission impairments and for boosting signal transmission rates | |
KR102241380B1 (en) | Optical communication method and device | |
EP1553742B1 (en) | Receiver for optical signals comprising a Viterbi equalizer and an analog electronic equalizer | |
US9231713B2 (en) | Method for designing an analog Nyquist filter | |
US20150312061A1 (en) | Decision-feedback analyzer and methods for operating the same | |
US10187234B1 (en) | Decision feedback equalizers and methods of decision feedback equalization | |
US8270461B2 (en) | Signal processing device and signal processing method utilized in communication system | |
Zerna et al. | Integrated PAM2 decision feedback equalizer for Gigabit Ethernet over standard SI-POF using red LED |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TITAN PHOTONICS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUN, CHEN-KUO;HUNTLEY, PAUL N.;GHIASI, ALI;AND OTHERS;SIGNING DATES FROM 20141201 TO 20150112;REEL/FRAME:034978/0177 |
|
AS | Assignment |
Owner name: CHEN, CHARLIE, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TITAN PHOTONICS, INC.;REEL/FRAME:035397/0126 Effective date: 20150410 |
|
AS | Assignment |
Owner name: TIOPTICS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, CHARLIE;REEL/FRAME:037790/0035 Effective date: 20160208 |
|
AS | Assignment |
Owner name: INTEGRA RESEARCH AND DEVELOPMENT, LLC, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TIOPTICS, INC.;REEL/FRAME:037792/0447 Effective date: 20160222 |
|
AS | Assignment |
Owner name: INTEGRA RESEARCH AND DEVELOPMENT, LLC, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TIOPTICS, INC.;REEL/FRAME:037935/0420 Effective date: 20160208 |
|
AS | Assignment |
Owner name: INTEGRA RESEARCH AND DEVELOPMENT, LLC, NEW YORK Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S ADDRESS PREVIOUSLY RECORDED ON REEL 037935 FRAME 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:TIOPTICS, INC.;REEL/FRAME:038131/0112 Effective date: 20160208 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: TIOPTICS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEGRA RESEARCH AND DEVELOPMENT, LLC;REEL/FRAME:043813/0661 Effective date: 20171003 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2551); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2552); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY Year of fee payment: 8 |