US20160126324A1 - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- US20160126324A1 US20160126324A1 US14/529,772 US201414529772A US2016126324A1 US 20160126324 A1 US20160126324 A1 US 20160126324A1 US 201414529772 A US201414529772 A US 201414529772A US 2016126324 A1 US2016126324 A1 US 2016126324A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 238000002955 isolation Methods 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims description 30
- 239000004020 conductor Substances 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 142
- 239000000758 substrate Substances 0.000 description 32
- 229910052751 metal Inorganic materials 0.000 description 26
- 239000002184 metal Substances 0.000 description 26
- 239000003990 capacitor Substances 0.000 description 15
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 15
- 238000002161 passivation Methods 0.000 description 12
- 239000010931 gold Substances 0.000 description 11
- 238000000059 patterning Methods 0.000 description 11
- 239000011651 chromium Substances 0.000 description 10
- 238000000151 deposition Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 239000010936 titanium Substances 0.000 description 10
- 239000003989 dielectric material Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- SZVJSHCCFOBDDC-UHFFFAOYSA-N ferrosoferric oxide Chemical compound O=[Fe]O[Fe]O[Fe]=O SZVJSHCCFOBDDC-UHFFFAOYSA-N 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- JPJALAQPGMAKDF-UHFFFAOYSA-N selenium dioxide Chemical compound O=[Se]=O JPJALAQPGMAKDF-UHFFFAOYSA-N 0.000 description 8
- AKEJUJNQAAGONA-UHFFFAOYSA-N sulfur trioxide Chemical compound O=S(=O)=O AKEJUJNQAAGONA-UHFFFAOYSA-N 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 239000012212 insulator Substances 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 239000011733 molybdenum Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910000458 iridium tetroxide Inorganic materials 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 229910001927 ruthenium tetroxide Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ODINCKMPIJJUCX-UHFFFAOYSA-N Calcium oxide Chemical compound [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 239000005751 Copper oxide Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910000431 copper oxide Inorganic materials 0.000 description 2
- YWEUIGNSBFLMFL-UHFFFAOYSA-N diphosphonate Chemical compound O=P(=O)OP(=O)=O YWEUIGNSBFLMFL-UHFFFAOYSA-N 0.000 description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000003487 electrochemical reaction Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000001182 laser chemical vapour deposition Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 2
- 229910000480 nickel oxide Inorganic materials 0.000 description 2
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 2
- 229910052762 osmium Inorganic materials 0.000 description 2
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 2
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- DLYUQMMRRRQYAE-UHFFFAOYSA-N phosphorus pentoxide Inorganic materials O1P(O2)(=O)OP3(=O)OP1(=O)OP2(=O)O3 DLYUQMMRRRQYAE-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910001930 tungsten oxide Inorganic materials 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000005686 electrostatic field Effects 0.000 description 1
- 238000004050 hot filament vapor deposition Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
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- H—ELECTRICITY
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Definitions
- Wafer level packaging (WLP) technology has been gaining popularity since the electronic components are being designed to be lighter, smaller, more multifunctional, more powerful, more reliable and less expensive.
- the WLP technology combines dies having different functionalities at a wafer level, and is widely applied in order to meet continuous demands toward the miniaturization and higher functions of the electronic components.
- a substrate in WLP technology raises concerns about how to increase the number of the electric components, especially at the peripheral region of such substrate.
- the electric components on the substrate with WLP technology are too crowded to locate any more components in peripheral region of the substrate.
- improvements in the method for a WLP continue to be sought.
- FIG. 1 is a top view of a semiconductor structure according to some embodiments of the present disclosure
- FIG. 2 is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure
- FIG. 3 is a cross-sectional view of a semiconductor structure according to certain embodiments of the present disclosure.
- FIG. 4 is a cross-sectional view of a semiconductor structure according to another embodiments of the present disclosure.
- FIG. 5 is a cross-sectional view of a semiconductor structure according to other embodiments of the present disclosure.
- FIG. 6 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present disclosure.
- FIG. 7 is a cross-sectional view of a semiconductor structure according to some certain embodiments of the present disclosure.
- FIG. 8 is a cross-sectional view of a semiconductor structure according to alternative embodiments of the present disclosure.
- FIG. 9 is a schematic view of a semiconductor structure according to the embodiment of FIG. 8 ;
- FIG. 10 is a flowchart of a method in fabricating a semiconductor structure according to some embodiments of the present disclosure.
- FIGS. 11 to 19 are cross-sectional views corresponding to various operations 1100 to 1400 in FIG. 10 .
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- a semiconductor device includes a circuit region, a seal ring region, and an assembly isolation region between the circuit region and the seal ring region. Those traces in the circuit region and the seal ring region are rerouted or extended into the assembly isolation region so as to form several electric components in the assembly isolation region. Thus, extending the number of the electric components, especially at peripheral region of the substrate, is available.
- the traces respectively extended from the circuit region and the seal ring region interlace with each other so as to form an electric component, such as a capacitor.
- those traces are electrically connected with each other so as to form an alternative component such as an inductor at peripheral region of the substrate.
- the number of the electric components extends at peripheral substrate for different applications.
- a “substrate” refers to a bulk substrate on which various layers and device structure are formed.
- the bulk substrate includes silicon or a compound semiconductor, such as Ga As, InP, Si/Ge, or SiC.
- the layers include dielectric layers, doped layers, polysilicon layers or conductive layers.
- the device structures include transistors, resistors, and/or capacitors, which may be interconnected through an interconnect layer to additionally integrated circuits.
- the bulk substrate includes a wafer such as a polished wafer, an epi wafer, an argon anneal wafer, a hai wafer and a silicon on insulator (SOI) wafer.
- SOI silicon on insulator
- deposit refers to operations of depositing materials on a substrate using a vapor phase of a material to be deposited, a precursor of the material, an electrochemical reaction, or sputtering/reactive sputtering.
- Depositions using a vapor phase of a material include any operations such as, but not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD).
- Examples of vapor deposition methods include hot filament CVD, rf-CVD, laser CVD (LCVD), conformal diamond coating operations, metal-organic CVD (MOCVD), thermal evaporation PVD, ionized metal PVD (IMPVD), electron beam PVD (EBPVD), reactive PVD, atomic layer deposition (ALD), plasma enhanced CVD (PECVD), high density plasma CVD (HDPCVD), low pressure CVD (LPCVD), and the like.
- Examples of deposition using electrochemical reaction include electroplating, electro-less plating, and the like.
- Other examples of deposition include pulse laser deposition (PLD), and atomic layer deposition (ALD).
- a “mask layer” recited in the present disclosure is an object of a patterning operation.
- the patterning operation includes various steps and operations and varies in accordance with features of embodiments.
- a patterning operation patterns an existing film or layer.
- the patterning operation includes forming a mask on the existing film or layer and removing the unmasked portion of the film or layer with an etch or other removal operations.
- the mask layer is a photo resist or a hardmask.
- a patterning operation directly forms a patterned layer on a surface.
- the patterning operation includes forming a photosensitive film on the surface, conducting a photolithography operation and a developing operation. The remaining photosensitive film may be removed or retained and integrated into the package.
- FIG. 1 a top plan view of a semiconductor structure 10 is illustrated including an integrated circuit (IC) die at a circuit region 11 of the structure 10 , a seal ring region 13 , and an assembly isolation region 12 therebetween according to various aspects of the present disclosure.
- Alternative cross-sectional views of the structure 10 along line A-A′ are illustrated in FIGS. 2 to 8 according to embodiments of the present disclosure.
- the semiconductor structure 10 includes a semiconductor substrate 110 such as a silicon substrate (e.g., a p-doped substrate or an n-doped substrate) locating at the seal ring region 13 , the assembly isolation region 12 and the circuit region 11 .
- the seal ring region 13 is formed around the circuit region 11 , and the seal ring region 13 is for forming a seal ring structure thereon and the circuit region 11 is for forming at least a transistor device therein.
- the substrate 110 includes silicon germanium, gallium arsenic, or other suitable semiconductor materials.
- the substrate 110 further includes doped regions, such as a P-well, an N-well, and/or a doped active region such as a P+ doped active region.
- the substrate 110 may further include other features such as a buried layer, and/or an epitaxy layer.
- the substrate 110 may be a semiconductor on insulator such as silicon on insulator (SOI).
- the semiconductor substrate 110 may include a doped epitaxy layer, a gradient semiconductor layer, and/or may further include a semiconductor layer overlying another semiconductor layer of a different type such as a silicon layer on a silicon germanium layer.
- the substrate 110 may include a multilayer silicon structure or a silicon substrate may include a multilayer compound semiconductor configuration.
- the semiconductor structure 10 further includes dummy gate or gate layer 14 a overlying the substrate 110 , and the gate layer 14 a is formed from various material layers and by various etching/patterning techniques.
- the gate layer 14 a is made of semiconductive materials such as polysilicon, silane (SiH 4 ), di-silane (Si 2 H 6 ), or di-clorsilane (SiCl 2 H 4 ) so as to be operated as a conductive layer under certain condition.
- an insulator layer 141 is formed between the substrate 110 and the gate layer 14 a .
- the insulator layer 141 may be a dummy dielectric layer formed on the substrate 110 .
- the insulator layer 141 is made of dielectric materials such as silicon dioxide (SiO 2 ), phosphorus pentoxide (P 4 O 10 ), selenium dioxide (SeO 2 ), sulfur trioxide (SO 3 ) or metal oxide.
- metal oxide examples include zinc oxide (ZnO), aluminium oxide (Al 2 O 3 ), iron(II,III) oxide (Fe 3 O 4 ), calcium oxide (CaO), ruthenium tetroxide (RuO 4 ), osmium(VIII) oxide (OsO 4 ), iridium tetroxide (IrO 4 ), indium tin oxide (In 2 O 3 :SnO 2 ), xenon tetroxide (XeO 4 ), nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, tungsten oxide, tantalum oxide, molybdenum oxide and copper oxide.
- Contact plugs 16 are formed in an inter-layer dielectric (ILD) 15 and electrically coupled to the gate layer 14 a in the circuit region 11 .
- the contact plugs 16 are made of conductive materials such as Aluminum (Al), Chromium (Cr), Gold (Au), Molybdenum (Mo), Platinum (Pt), Tantalum (Ta), Titanium (Ti), Silver (Ag), Copper (Cu), Tungsten (W) and/or alloy thereof.
- the semiconductor structure 10 further includes contact bars 21 , which are formed in the ILD 15 in the seal ring region 13 .
- the contact bar 21 is electrically coupled between an active region on the substrate 110 and a seal ring structure 50 above the contact bar 21 .
- the contact bars 21 are formed of conductive materials such as Aluminum (Al), Chromium (Cr), Gold (Au), Molybdenum (Mo), Platinum (Pt), Tantalum (Ta), Titanium (Ti), Silver (Ag), Copper (Cu), Tungsten (W) and/or alloy thereof.
- the seal ring structure 50 in the seal ring region 13 includes various stacked conductive layers 51 and via layers 61 disposed through inter-metal dielectrics (IMDs) 18 .
- Those conductive layers 51 and via layers 61 allow to conduct electric currents.
- the conductive layers 51 and via layers 61 may include current conducting traces therein. These traces are made of semiconductive or conductive material. For example, traces are formed of semiconductive materials such as polysilicon, silane (SiH 4 ), di-silane (Si 2 H 6 ), or di-clorsilane (SiCl 2 H 4 ) so as to be operated as a conductive layer under certain condition.
- traces may be made of conductive materials such as Aluminum (Al), Chromium (Cr), Gold (Au), Molybdenum (Mo), Platinum (Pt), Tantalum (Ta), Titanium (Ti), Silver (Ag), Copper (Cu), Tungsten (W) and/or alloy thereof.
- the seal ring structure 50 has a width between about 5 ⁇ m and about 15 ⁇ m as well as the width of the seal ring region 13 .
- one of the conductive layers 51 extends from the seal ring region 13 into the assembly isolation region 12 , while the gate layer 14 a and the insulator layer 141 extend from the circuit region 11 into the assembly isolation region 12 .
- the conductive layer 51 and the gate layer 14 a respectively includes a portion extending into the assembly isolation region 12 thereby forming an electric component 81 in the assembly isolation region 12 .
- ILD 15 is between the extended portions of the conductive layer 51 and the dummy gate 14 a .
- the electric component 81 is a capacitor in which two electrodes are formed by the extended portions of the conductive layer 51 and the dummy gate 14 a .
- several capacitors are formed by similar approach and further constructing some serial or parallel capacitor configuration.
- Interconnect structure 17 disposed over the contact plug 16 and the ILD 15 , includes metal layers 171 and vias 172 therein.
- the interconnect structure 17 is electrically coupled to the gate layer 14 a through the contact plug 16 .
- the interconnect structure 17 includes several conductive layers 171 , namely M 1 , M 2 , . . . to M top , wherein conductive layer M 1 is the metal layer immediately on ILD 15 , while conductive layer M top is the top metal layer that is under the metal pad 41 .
- a dielectric layer 43 is disposed between the top metal layer M top and the metal pad 41 , which are formed in subsequent operations. Via 431 is within the dielectric layer 43 for electrical coupling between the top metal layer M top and the metal pad 41 .
- Conductive layers M 1 through M top are formed in IMDs 18 , which are formed of oxides such as Un-doped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), low-k dielectric materials, or the like.
- the low-k dielectric materials may have k values lower than about 3.8, although the dielectric materials of IMDs 18 may also be close to about 3.8. In some embodiments, the k values of the low-k dielectric materials are lower than about 3.0, and may be lower than about 2.5.
- Conductive layers 171 and vias 172 refer to the collection of the conductive lines or current conducting traces in the same layer and hence, the conductive layers 171 and vias 172 are capable of conducting electric current.
- Conductive layers 171 and vias 172 are formed of substantially pure copper (for example, with a weight percentage of copper being greater than about 90 percent, or greater than about 95 percent) or copper alloys.
- the vias 172 are formed in the single and/or dual damascene structure.
- the conductive layers 171 and vias 172 may be, or may not be, substantially free from aluminum.
- one of the conductive layers 51 extending into the assembly isolation region 12 , is electrically coupled with an extended portion 173 of the conductive layer M 1 to form an electric component 81 in the assembly isolation region 12 .
- the coupling extended conductive traces in the assembly isolation region 12 may be a capacitor.
- the extended portion 511 of the conductive layer 51 is above the extended portion 173 of the conductive layer M 1 and separated by the IMD 18 located therebetween and hence, charges are stored in the electric component 81 .
- the electric component 81 is an indicator to detect the deviation of the composed elements.
- thickness of one element, IMD 18 may affect the capacitance of the electric component 81 . Therefore, the capacitance measured on the electric component 81 can reflect the thickness of the IMD 18 . In some examples, greater than 0.5% deviation from IMD 18 target thickness can be detected through measuring the capacitance of electric component 81 .
- electric component 81 is electrically coupled to a semiconductor device 14 in the circuit region 11 through the interconnect structure 17 .
- the semiconductor device 14 is formed on the substrate 110 and may be either an NMOS device (e.g., nFET) or a PMOS device (e.g., pFET).
- the semiconductor structure 10 may further include isolation structures, such as shallow trench isolation (STI) features or LOCOS features formed in the substrate 110 for isolating the device 14 from other regions of the substrate 110 .
- STI shallow trench isolation
- FIG. 4 a cross-sectional view is illustrated of another embodiment of semiconductor structure 10 .
- One of the via layers 61 extends into the assembly isolation region 12
- one of vias 172 extends into the same region 12 to mutually form an electric component 81 , such as a capacitor.
- the capacitor includes the extended portion 611 of the via layer 61 , the extended portion 174 of the via 172 , and a layer of high-k dielectric 19 .
- the extended portion 611 of the via layer 61 is under and separated from the extended portion 174 of the via 172 by the high-k dielectric 19 .
- the high-k dielectric 19 materials have k values greater than about 3.9, although the dielectric materials of high-k dielectric 19 may also be from about 3.9 to about 30.
- the thickness of the via 172 or the via layer 61 is between about 2.0 k ⁇ and about 3.5 k ⁇ . However, since the high-k dielectric 19 is disposed between the via 172 and the via layer 61 , the thickness of either the via 172 or the via layer 61 is capable of being reduced and still perform its function as well as the capacitor with original thickness.
- the thickness-reduced via 172 of via layer 61 have a thickness between about 1.5 k ⁇ and about 2.8 k ⁇ . In certain embodiments, the thickness of either the via 172 or the via layer 61 is between about 1.2 k ⁇ and about 1.8 k ⁇ .
- FIG. 5 a cross-sectional view is illustrated of another embodiment of semiconductor structure 10 .
- a metal pad 41 is formed above the interconnect structure 17 and especially on the dielectric layer 43 .
- a portion 411 of the metal pad 41 extends into the assembly isolation region 12 .
- the via layer 61 extends into the assembly isolation region 12 and is separated from the metal pad 41 by the IMD 18 so as to form a passive two-terminal electric component 81 such as a capacitor.
- the capacitor is used to store charges.
- the electric component 81 is electrically coupled to the contact bar 21 through the seal ring structure 50 .
- the metal pad 41 is electrically coupled to the semiconductor device 14 , for example, through underlying interconnect structure 17 . In other words, a circuit between the device 14 and the passive component 81 is formed.
- the metal pad 41 are formed of conductive materials such as Aluminum (Al), Chromium (Cr), Gold (Au), Molybdenum (Mo), Platinum (Pt), Tantalum (Ta), Titanium (Ti), Nickel (Ni), Silver (Ag), Copper (Cu), Tungsten (W) and/or alloy thereof.
- the semiconductor structure 10 further includes conductive pad 71 disposed over the dielectric layer 43 where a via 432 is disposed for electrically coupling between the conductive pad 71 and the conductive layers 51 so as to electrically couple the conductive pad 71 to the interconnect structure 17 .
- the extending portion 711 of the conductive pad 71 covers a portion 174 of the via 172 extending into the assembly isolation region 12 , but does not directly contact the via 172 .
- a layer of IMD 18 separates the conductive pad 71 from the via 172 thereby forming an electric component 81 such as a capacitor.
- the electric component 81 is electrically coupled to the underlying device 14 and the seal ring structure 50 , respectively.
- the conductive pad 71 includes two portions, 71 a and 71 b .
- the portion 71 a is at an exterior side of the seal ring region 13 closer to the chip edge and scribe line and the portion 71 b is at an interior side of the seal ring region 13 closer to the circuit region 11 .
- the portion 71 b is rerouted into the assembly isolation region 12 so as to define the electric component 81 with the underlying portion 174 of the via 172 .
- the portions 71 a and 71 b are directly covered by a passivation layer 40 to be free from moisture.
- the portions 71 a and 71 b are formed of conductive materials such as Aluminum (Al), Chromium (Cr), Gold (Au), Molybdenum (Mo), Platinum (Pt), Tantalum (Ta), Titanium (Ti), Nickel (Ni), Silver (Ag), Copper (Cu), Tungsten (W) and/or alloy thereof.
- conductive materials such as Aluminum (Al), Chromium (Cr), Gold (Au), Molybdenum (Mo), Platinum (Pt), Tantalum (Ta), Titanium (Ti), Nickel (Ni), Silver (Ag), Copper (Cu), Tungsten (W) and/or alloy thereof.
- Passivation layer 40 is formed over the seal ring structure 50 and the interconnect structure 17 . Particularly, the passivation layer 40 is on a portion of the metal pad 41 , a portion of conductive layer 51 , a portion of metal layer M top , and the IMD 18 .
- the passivation layer 40 is formed of dielectric materials such as silicon nitride, silicon dioxide (SiO 2 ), phosphorus pentoxide (P 4 O 10 ), selenium dioxide (SeO 2 ), sulfur trioxide (SO 3 ) or metal oxide.
- metal oxide examples include zinc oxide (ZnO), aluminium oxide (Al 2 O 3 ), iron(II,III) oxide (Fe 3 O 4 ), calcium oxide (CaO), ruthenium tetroxide (RuO 4 ), osmium(VIII) oxide (OsO 4 ), iridium tetroxide (IrO 4 ), indium tin oxide (In 2 O 3 :SnO 2 ), xenon tetroxide (XeO 4 ), nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, tungsten oxide, tantalum oxide, molybdenum oxide and copper oxide.
- the dielectric layer 42 is over the passivation layer 40 and covers a portion of the metal pad 41 . Both of the passivation 40 and the dielectric layer 42 are patterned in order to have a recess to expose a portion of the metal pad 41 .
- the exposed metal pad 41 serves as an electrical contact between the device 14 and other conductive trace, for example, a post passivation interconnect (PPI) 31 .
- the dielectric layer 42 is also over the conductive pad 71 and the seal ring structure 50 .
- the dielectric layer 42 is formed of a polymeric material such as epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like.
- the PPI 31 is on the dielectric layer 42 and routes into the assembly isolation region 12 so as to be electrically coupled with the underlying current conducting trace 511 , which is extended from the conductive layer 51 .
- the extended portion 311 of PPI 31 and the extended portion 511 of the conductive layer 51 define an electric component 81 .
- the electric component 81 is a capacitor.
- the dielectric within the capacitor includes two layers, the passivation layer 40 and the dielectric layer 42 , both of which are used to maintain the electrostatic field between the PPI 31 and the conductive layer 51 .
- the PPI 31 extends into the recess of the passivation layer 40 and the dielectric layer 42 .
- the extending portion 312 of the PPI 31 may line the bottom and sidewalls of the recess and electrically couple to the metal pad 41 .
- the electric component 81 is electrically coupled to the device 14 through the underlying the interconnect structure 17 .
- the PPI 31 is formed of conductive material such as gold, silver, copper, nickel, tungsten, aluminum, and/or alloys thereof.
- Conductive pad 71 is distributed under a polymer layer 90 , which surrounds a portion of the bump 91 .
- the conductive pad 71 includes several segments, 71 a , 71 b , 71 c and 71 d . Segments 71 a and 71 b and are located in the seal ring region 13 and segments 71 c and 71 d are located in in the assembly isolation region 12 .
- Segment 71 a is at an exterior side above the seal ring structure 50 and closer to the chip edge or scribe line.
- Segment 71 d is at an inner side of the assembly isolation region 12 and closer to the circuit region 11 .
- the semiconductor structure 10 further includes a conductive via 631 and a conductive feature 63 , which is formed at the same layer with the top conductive layer 51 and the metal layer M top .
- the conductive feature 63 is electrically connected to the conductive pad 71 through the conductive via 631 , which is within the dielectric layer 43 .
- a conductive layer M 3 extends into the assembly isolation region 12 .
- a contact via 60 is electrically connected between the conductive structure 63 and the conductive layer M 3 so as to form an electric component, such as an inductor.
- the conductive pad 71 is patterned in an inductor configuration such as a coil or a spiral as shown in FIG. 9 .
- the conductive layer 51 and/or the conductive layer M 3 are extended into the assembly isolation region 12 to form a dual coil structure in a same layer.
- a method for manufacturing a semiconductor structure which includes several electric components in the assembly isolation region, is designed for extending the number of electric components around the die.
- the method includes a number of operations and the description and illustrations are not deemed as a limitation as the order of the operations.
- FIG. 10 is a diagram of a method 1000 for fabricating a semiconductor structure in accordance with some embodiments of the present disclosure.
- the method 1000 includes several operations, which are discussed in detail with reference to FIGS. 5 to 19 .
- a circuit region, a seal ring region and an assembly isolation region are defined, wherein the assembly isolation region is between the circuit region and the seal ring region.
- a first current conducting trace is routed from the circuit region into the assembly isolation region.
- a second current conducting trace is routed from the seal ring region into the assembly isolation region.
- the first current conducting trace and the second current conducting trace are coupled to form an electric component.
- FIGS. 11 to 19 have been simplified for a better understanding of the inventive concepts of the present disclosure.
- elements with same labeling numbers as those in FIGS. 1 to 9 are previously discussed with reference thereto and are not repeated here for simplicity.
- the inter-layer dielectric (ILD) 15 is formed on the semiconductor substrate 110 through any suitable techniques such as a high aspect ratio process (HARP) and/or a high density plasma (HDP) CVD operation.
- the contact plugs 16 and the contact bars 21 are formed in the ILD 15 in order to be electrically coupled to conductive features (not shown).
- the formation of the contact plugs 16 and the contact bars 21 includes, for example, etching ILD 15 to form openings through a mask layer, and filling a conductive material into the openings.
- a planarization may then be performed to remove excess conductive material over ILD 15 , and the remaining conductive material in the openings forms the contact plugs 16 and the contact bars 21 .
- the region where the contact plugs 16 locate is defined as the circuit region 11 and the region where the contact bars locate is defined as the seal ring region.
- the assembly isolation region 12 is defined between the circuit region 11 and the seal ring region 13 .
- a conductive layer is blanket deposited on ILD 15 .
- the conductive layer may include at least one film and be formed by deposition such as sputtering, vaporization, or other suitable methods.
- a hybrid deposition method including CVD (Chemical Vapor Deposition) and PVD (Physical Vapor Deposition) is introduced for the deposition.
- CVD Chemical Vapor Deposition
- PVD Physical Vapor Deposition
- the inter-metal dielectrics (IMDs) 18 are formed on the conductive layers M 1 and 51 through any suitable techniques such as a high aspect ratio process (HARP) and/or a high density plasma (HDP) CVD operation.
- vias 172 and via layers 61 formed in the IMDs 18 are electrically coupled to the contact plugs 16 and the contact bars 21 , respectively.
- the formation of the vias 172 and the via layers 61 includes, for example, etching IMDs 18 to form openings through a mask layer, and filling a conductive material into the openings. A planarization may then be performed to remove excess conductive material over IMDs 18 , and the remaining conductive material in the openings forms the vias 172 and the via layers 61 .
- another conductive layer M 2 and 51 and another via 172 and via layer 61 are formed as previously discussed so as to fabricate a part of the interconnect structure 17 and the seal ring structure 50 , respectively.
- a current conducting trace of the conductive layer M 3 routing from the circuit region 11 into the assembly isolation region 12 is formed by the previously mentioned operations such as metal deposition, photolithography, patterning, and etching techniques.
- the contact via 60 is formed in the assembly isolation region 12 and the via 172 and via layer 61 are simultaneously formed in the circuit region 11 and the seal ring region 13 .
- the contact via 60 , the via 172 and the via layer 61 are formed by the previously identified operations such as etching, metal depositing, and chemical mechanical polishing techniques.
- the conductive feature 63 and the conductive via 631 in the assembly isolation region 12 are formed by the previously discussed operations such as metal deposition, photolithography, patterning, and etching techniques.
- the conductive feature 63 is electrically connected with the contact via 60 in the assembly isolation region 12 .
- the contact via 60 and the conductive via 631 are optional. Without the contact via 60 and the conductive via 631 , the conductive layer M 3 is still capable of forming other type of the electric component such as a capacitor.
- the top metal pad 41 and the conductive pad 71 are patterned over the interconnect structure 17 and the seal ring structure 50 by using conventional photolithography, patterning, and etching techniques.
- the pattern of the conductive pad 71 includes several segments, 71 a , 71 b , 71 c , and 71 d as illustrated in FIG. 9 .
- the conductive pad 71 is electrically connected to the interconnect structure 17 through the conductive feature 63 , the contact via 60 and the conductive via 631 so as to form an electric component 82 , such as an inductor
- the passivation layer 40 is deposited by any suitable techniques such as a high aspect ratio process (HARP) and/or a high density plasma (HDP) CVD operation.
- a portion of the passivation layer 40 is removed by using photolithography with a photoresist layer and etching techniques.
- the photolithography operation may include spin-coating, soft-baking, exposure, post-backing, developing, rinsing, drying and other suitable operation.
- the dielectric layer 42 is disposed on the passivation layer 40 by using spin-coating techniques. A portion of the dielectric layer 42 , atop the pad 41 , is removed to form a recess in subsequent operations.
- the removing operation may be implemented by exposure, developing, rinsing, drying and other suitable operations.
- the PPI 31 is disposed on the dielectric layer 42 and the recess to form an electrical connection with the metal pad 41 .
- the bump 91 is located on a portion of the PPI 31 by traditional bump-planting techniques. Subsequently, after the polymer layer 90 covers the dielectric layer 42 , the PPI 31 and a portion of the bump 91 through spin-coating techniques, the semiconductor structure 10 as previously shown in FIG. 8 is completed.
- a semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region.
- the circuit region includes a first conductive layer.
- the seal ring region includes a second conductive layer.
- the assembly isolation region is between the circuit region and the seal ring region.
- the first conductive layer and the second conductive layer respectively includes a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.
- a semiconductor structure includes a circuit region, and a seal ring region.
- the seal ring region surrounds the circuit region and is separated from the circuit region by an assembly isolation region.
- the first current conducting trace is in the circuit region and a second current conducting trace is in the seal ring region.
- the first current conducting trace and the second current conducting trace respectively extend into the assembly isolation region and mutually form an electric component.
- a method for fabricating a semiconductor structure includes defining a circuit region, a seal ring region, and an assembly isolation region between the circuit region and the seal ring region. The method also includes routing a first current conducting trace from the circuit region into the assembly isolation region. The method also includes routing a second current conducting trace from the seal ring region into the assembly isolation region. The method also includes coupling the first current conducting trace and the second current conducting trace to form an electric component.
- first,” “second,” or the like are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc.
- a first channel and a second channel generally correspond to channel A and channel B or two different or two identical channels or the same channel.
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Abstract
The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.
Description
- Presently, electronic equipment is essential for many modern applications. Therefore, consumers are increasingly demanding more processing power, lower electrical power usage and cheaper devices. As the electronic industry strives to meet these demands and more complicated and denser configurations, miniaturization will result in an extension of the number of chips per wafer and the number of transistors per chip, as well as a reduction in power usage. Wafer level packaging (WLP) technology has been gaining popularity since the electronic components are being designed to be lighter, smaller, more multifunctional, more powerful, more reliable and less expensive. The WLP technology combines dies having different functionalities at a wafer level, and is widely applied in order to meet continuous demands toward the miniaturization and higher functions of the electronic components.
- A substrate in WLP technology raises concerns about how to increase the number of the electric components, especially at the peripheral region of such substrate. In contrast to a traditional packaging technology, the electric components on the substrate with WLP technology are too crowded to locate any more components in peripheral region of the substrate. Thus, improvements in the method for a WLP continue to be sought.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
- A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures, and:
-
FIG. 1 is a top view of a semiconductor structure according to some embodiments of the present disclosure; -
FIG. 2 is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure; -
FIG. 3 is a cross-sectional view of a semiconductor structure according to certain embodiments of the present disclosure; -
FIG. 4 is a cross-sectional view of a semiconductor structure according to another embodiments of the present disclosure; -
FIG. 5 is a cross-sectional view of a semiconductor structure according to other embodiments of the present disclosure; -
FIG. 6 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present disclosure; -
FIG. 7 is a cross-sectional view of a semiconductor structure according to some certain embodiments of the present disclosure; -
FIG. 8 is a cross-sectional view of a semiconductor structure according to alternative embodiments of the present disclosure; -
FIG. 9 is a schematic view of a semiconductor structure according to the embodiment ofFIG. 8 ; -
FIG. 10 is a flowchart of a method in fabricating a semiconductor structure according to some embodiments of the present disclosure; and -
FIGS. 11 to 19 are cross-sectional views corresponding tovarious operations 1100 to 1400 inFIG. 10 . - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- In the present disclosure, routing additional traces, which conducts electric current, enables a formation of additional electric components. A semiconductor device includes a circuit region, a seal ring region, and an assembly isolation region between the circuit region and the seal ring region. Those traces in the circuit region and the seal ring region are rerouted or extended into the assembly isolation region so as to form several electric components in the assembly isolation region. Thus, extending the number of the electric components, especially at peripheral region of the substrate, is available.
- In various embodiments, the traces respectively extended from the circuit region and the seal ring region interlace with each other so as to form an electric component, such as a capacitor. In some embodiments, those traces are electrically connected with each other so as to form an alternative component such as an inductor at peripheral region of the substrate. Thus, the number of the electric components extends at peripheral substrate for different applications.
- As used herein, a “substrate” refers to a bulk substrate on which various layers and device structure are formed. In some embodiments, the bulk substrate includes silicon or a compound semiconductor, such as Ga As, InP, Si/Ge, or SiC. Examples of the layers include dielectric layers, doped layers, polysilicon layers or conductive layers. Examples of the device structures include transistors, resistors, and/or capacitors, which may be interconnected through an interconnect layer to additionally integrated circuits. In some embodiments, the bulk substrate includes a wafer such as a polished wafer, an epi wafer, an argon anneal wafer, a hai wafer and a silicon on insulator (SOI) wafer.
- As used herein, “deposition” refers to operations of depositing materials on a substrate using a vapor phase of a material to be deposited, a precursor of the material, an electrochemical reaction, or sputtering/reactive sputtering. Depositions using a vapor phase of a material include any operations such as, but not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD). Examples of vapor deposition methods include hot filament CVD, rf-CVD, laser CVD (LCVD), conformal diamond coating operations, metal-organic CVD (MOCVD), thermal evaporation PVD, ionized metal PVD (IMPVD), electron beam PVD (EBPVD), reactive PVD, atomic layer deposition (ALD), plasma enhanced CVD (PECVD), high density plasma CVD (HDPCVD), low pressure CVD (LPCVD), and the like. Examples of deposition using electrochemical reaction include electroplating, electro-less plating, and the like. Other examples of deposition include pulse laser deposition (PLD), and atomic layer deposition (ALD).
- As used herein, a “mask layer” recited in the present disclosure is an object of a patterning operation. The patterning operation includes various steps and operations and varies in accordance with features of embodiments. In some embodiments, a patterning operation patterns an existing film or layer. The patterning operation includes forming a mask on the existing film or layer and removing the unmasked portion of the film or layer with an etch or other removal operations. The mask layer is a photo resist or a hardmask. In some embodiments, a patterning operation directly forms a patterned layer on a surface. The patterning operation includes forming a photosensitive film on the surface, conducting a photolithography operation and a developing operation. The remaining photosensitive film may be removed or retained and integrated into the package.
- Referring to
FIG. 1 , a top plan view of asemiconductor structure 10 is illustrated including an integrated circuit (IC) die at acircuit region 11 of thestructure 10, aseal ring region 13, and anassembly isolation region 12 therebetween according to various aspects of the present disclosure. Alternative cross-sectional views of thestructure 10 along line A-A′ are illustrated inFIGS. 2 to 8 according to embodiments of the present disclosure. - Referring now to
FIG. 2 in conjunction withFIG. 1 , a cross-sectional view is illustrated of an embodiment ofsemiconductor structure 10. Thesemiconductor structure 10 includes asemiconductor substrate 110 such as a silicon substrate (e.g., a p-doped substrate or an n-doped substrate) locating at theseal ring region 13, theassembly isolation region 12 and thecircuit region 11. In some embodiments, theseal ring region 13 is formed around thecircuit region 11, and theseal ring region 13 is for forming a seal ring structure thereon and thecircuit region 11 is for forming at least a transistor device therein. - The
substrate 110 includes silicon germanium, gallium arsenic, or other suitable semiconductor materials. Thesubstrate 110 further includes doped regions, such as a P-well, an N-well, and/or a doped active region such as a P+ doped active region. Thesubstrate 110 may further include other features such as a buried layer, and/or an epitaxy layer. Furthermore, thesubstrate 110 may be a semiconductor on insulator such as silicon on insulator (SOI). In other embodiments, thesemiconductor substrate 110 may include a doped epitaxy layer, a gradient semiconductor layer, and/or may further include a semiconductor layer overlying another semiconductor layer of a different type such as a silicon layer on a silicon germanium layer. In some embodiments, thesubstrate 110 may include a multilayer silicon structure or a silicon substrate may include a multilayer compound semiconductor configuration. - The
semiconductor structure 10 further includes dummy gate orgate layer 14 a overlying thesubstrate 110, and thegate layer 14 a is formed from various material layers and by various etching/patterning techniques. Thegate layer 14 a is made of semiconductive materials such as polysilicon, silane (SiH4), di-silane (Si2H6), or di-clorsilane (SiCl2H4) so as to be operated as a conductive layer under certain condition. - In some embodiments, an
insulator layer 141, including a high k dielectric layer and/or a barrier layer, is formed between thesubstrate 110 and thegate layer 14 a. Theinsulator layer 141 may be a dummy dielectric layer formed on thesubstrate 110. Theinsulator layer 141 is made of dielectric materials such as silicon dioxide (SiO2), phosphorus pentoxide (P4O10), selenium dioxide (SeO2), sulfur trioxide (SO3) or metal oxide. Examples of the metal oxide are selected from zinc oxide (ZnO), aluminium oxide (Al2O3), iron(II,III) oxide (Fe3O4), calcium oxide (CaO), ruthenium tetroxide (RuO4), osmium(VIII) oxide (OsO4), iridium tetroxide (IrO4), indium tin oxide (In2O3:SnO2), xenon tetroxide (XeO4), nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, tungsten oxide, tantalum oxide, molybdenum oxide and copper oxide. - Contact plugs 16 are formed in an inter-layer dielectric (ILD) 15 and electrically coupled to the
gate layer 14 a in thecircuit region 11. The contact plugs 16 are made of conductive materials such as Aluminum (Al), Chromium (Cr), Gold (Au), Molybdenum (Mo), Platinum (Pt), Tantalum (Ta), Titanium (Ti), Silver (Ag), Copper (Cu), Tungsten (W) and/or alloy thereof. - The
semiconductor structure 10 further includes contact bars 21, which are formed in theILD 15 in theseal ring region 13. Thecontact bar 21 is electrically coupled between an active region on thesubstrate 110 and aseal ring structure 50 above thecontact bar 21. The contact bars 21 are formed of conductive materials such as Aluminum (Al), Chromium (Cr), Gold (Au), Molybdenum (Mo), Platinum (Pt), Tantalum (Ta), Titanium (Ti), Silver (Ag), Copper (Cu), Tungsten (W) and/or alloy thereof. - In some embodiments, the
seal ring structure 50 in theseal ring region 13 includes various stackedconductive layers 51 and vialayers 61 disposed through inter-metal dielectrics (IMDs) 18. Thoseconductive layers 51 and vialayers 61 allow to conduct electric currents. Theconductive layers 51 and vialayers 61 may include current conducting traces therein. These traces are made of semiconductive or conductive material. For example, traces are formed of semiconductive materials such as polysilicon, silane (SiH4), di-silane (Si2H6), or di-clorsilane (SiCl2H4) so as to be operated as a conductive layer under certain condition. Alternatively, traces may be made of conductive materials such as Aluminum (Al), Chromium (Cr), Gold (Au), Molybdenum (Mo), Platinum (Pt), Tantalum (Ta), Titanium (Ti), Silver (Ag), Copper (Cu), Tungsten (W) and/or alloy thereof. In certain embodiments, theseal ring structure 50 has a width between about 5 μm and about 15 μm as well as the width of theseal ring region 13. - In some embodiments, as in
FIG. 2 , one of theconductive layers 51 extends from theseal ring region 13 into theassembly isolation region 12, while thegate layer 14 a and theinsulator layer 141 extend from thecircuit region 11 into theassembly isolation region 12. In other words, theconductive layer 51 and thegate layer 14 a respectively includes a portion extending into theassembly isolation region 12 thereby forming anelectric component 81 in theassembly isolation region 12.ILD 15 is between the extended portions of theconductive layer 51 and thedummy gate 14 a. In some embodiments, theelectric component 81 is a capacitor in which two electrodes are formed by the extended portions of theconductive layer 51 and thedummy gate 14 a. In some embodiments, several capacitors are formed by similar approach and further constructing some serial or parallel capacitor configuration. - Referring to
FIG. 3 in conjunction withFIG. 1 , a cross-sectional view is illustrated of another embodiment ofsemiconductor structure 10.Interconnect structure 17, disposed over thecontact plug 16 and theILD 15, includesmetal layers 171 and vias 172 therein. Theinterconnect structure 17 is electrically coupled to thegate layer 14 a through thecontact plug 16. Particularly, theinterconnect structure 17 includes severalconductive layers 171, namely M1, M2, . . . to Mtop, wherein conductive layer M1 is the metal layer immediately onILD 15, while conductive layer Mtop is the top metal layer that is under themetal pad 41. Adielectric layer 43 is disposed between the top metal layer Mtop and themetal pad 41, which are formed in subsequent operations. Via 431 is within thedielectric layer 43 for electrical coupling between the top metal layer Mtop and themetal pad 41. Conductive layers M1 through Mtop are formed inIMDs 18, which are formed of oxides such as Un-doped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), low-k dielectric materials, or the like. The low-k dielectric materials may have k values lower than about 3.8, although the dielectric materials ofIMDs 18 may also be close to about 3.8. In some embodiments, the k values of the low-k dielectric materials are lower than about 3.0, and may be lower than about 2.5. -
Conductive layers 171 and vias 172 refer to the collection of the conductive lines or current conducting traces in the same layer and hence, theconductive layers 171 and vias 172 are capable of conducting electric current.Conductive layers 171 and vias 172 are formed of substantially pure copper (for example, with a weight percentage of copper being greater than about 90 percent, or greater than about 95 percent) or copper alloys. Thevias 172 are formed in the single and/or dual damascene structure. Theconductive layers 171 and vias 172 may be, or may not be, substantially free from aluminum. - In some embodiments, one of the
conductive layers 51, extending into theassembly isolation region 12, is electrically coupled with anextended portion 173 of the conductive layer M1 to form anelectric component 81 in theassembly isolation region 12. The coupling extended conductive traces in theassembly isolation region 12 may be a capacitor. Theextended portion 511 of theconductive layer 51 is above theextended portion 173 of the conductive layer M1 and separated by theIMD 18 located therebetween and hence, charges are stored in theelectric component 81. For some embodiments, theelectric component 81 is an indicator to detect the deviation of the composed elements. For example, thickness of one element,IMD 18, may affect the capacitance of theelectric component 81. Therefore, the capacitance measured on theelectric component 81 can reflect the thickness of theIMD 18. In some examples, greater than 0.5% deviation fromIMD 18 target thickness can be detected through measuring the capacitance ofelectric component 81. - In some embodiments,
electric component 81 is electrically coupled to asemiconductor device 14 in thecircuit region 11 through theinterconnect structure 17. Thesemiconductor device 14 is formed on thesubstrate 110 and may be either an NMOS device (e.g., nFET) or a PMOS device (e.g., pFET). In this case, thesemiconductor structure 10 may further include isolation structures, such as shallow trench isolation (STI) features or LOCOS features formed in thesubstrate 110 for isolating thedevice 14 from other regions of thesubstrate 110. - Referring to
FIG. 4 in conjunction withFIG. 1 , a cross-sectional view is illustrated of another embodiment ofsemiconductor structure 10. One of the via layers 61 extends into theassembly isolation region 12, while one ofvias 172 extends into thesame region 12 to mutually form anelectric component 81, such as a capacitor. The capacitor includes theextended portion 611 of the vialayer 61, theextended portion 174 of the via 172, and a layer of high-k dielectric 19. Particularly, theextended portion 611 of the vialayer 61 is under and separated from theextended portion 174 of the via 172 by the high-k dielectric 19. The high-k dielectric 19 materials have k values greater than about 3.9, although the dielectric materials of high-k dielectric 19 may also be from about 3.9 to about 30. - In some embodiments, the thickness of the via 172 or the via
layer 61 is between about 2.0 kÅ and about 3.5 kÅ. However, since the high-k dielectric 19 is disposed between the via 172 and the vialayer 61, the thickness of either the via 172 or the vialayer 61 is capable of being reduced and still perform its function as well as the capacitor with original thickness. The thickness-reduced via 172 of vialayer 61 have a thickness between about 1.5 kÅ and about 2.8 kÅ. In certain embodiments, the thickness of either the via 172 or the vialayer 61 is between about 1.2 kÅ and about 1.8 kÅ. - Referring to
FIG. 5 in conjunction withFIG. 1 , a cross-sectional view is illustrated of another embodiment ofsemiconductor structure 10. Ametal pad 41 is formed above theinterconnect structure 17 and especially on thedielectric layer 43. Aportion 411 of themetal pad 41 extends into theassembly isolation region 12. The vialayer 61 extends into theassembly isolation region 12 and is separated from themetal pad 41 by theIMD 18 so as to form a passive two-terminalelectric component 81 such as a capacitor. The capacitor is used to store charges. In some embodiments, theelectric component 81 is electrically coupled to thecontact bar 21 through theseal ring structure 50. - The
metal pad 41 is electrically coupled to thesemiconductor device 14, for example, throughunderlying interconnect structure 17. In other words, a circuit between thedevice 14 and thepassive component 81 is formed. In certain embodiments, themetal pad 41 are formed of conductive materials such as Aluminum (Al), Chromium (Cr), Gold (Au), Molybdenum (Mo), Platinum (Pt), Tantalum (Ta), Titanium (Ti), Nickel (Ni), Silver (Ag), Copper (Cu), Tungsten (W) and/or alloy thereof. - Referring to
FIG. 6 in conjunction withFIG. 1 , a cross-sectional view is illustrated of another embodiment ofsemiconductor structure 10. Thesemiconductor structure 10 further includesconductive pad 71 disposed over thedielectric layer 43 where a via 432 is disposed for electrically coupling between theconductive pad 71 and theconductive layers 51 so as to electrically couple theconductive pad 71 to theinterconnect structure 17. In some embodiments, the extendingportion 711 of theconductive pad 71 covers aportion 174 of the via 172 extending into theassembly isolation region 12, but does not directly contact the via 172. A layer ofIMD 18 separates theconductive pad 71 from the via 172 thereby forming anelectric component 81 such as a capacitor. Theelectric component 81 is electrically coupled to theunderlying device 14 and theseal ring structure 50, respectively. - In some embodiments, the
conductive pad 71 includes two portions, 71 a and 71 b. Theportion 71 a is at an exterior side of theseal ring region 13 closer to the chip edge and scribe line and theportion 71 b is at an interior side of theseal ring region 13 closer to thecircuit region 11. In this case, theportion 71 b is rerouted into theassembly isolation region 12 so as to define theelectric component 81 with theunderlying portion 174 of thevia 172. In addition, theportions passivation layer 40 to be free from moisture. - In certain embodiments, the
portions - Referring to
FIG. 7 in conjunction withFIG. 1 , a cross-sectional view is illustrated of another embodiment ofsemiconductor structure 10.Passivation layer 40 is formed over theseal ring structure 50 and theinterconnect structure 17. Particularly, thepassivation layer 40 is on a portion of themetal pad 41, a portion ofconductive layer 51, a portion of metal layer Mtop, and theIMD 18. In certain embodiments, thepassivation layer 40 is formed of dielectric materials such as silicon nitride, silicon dioxide (SiO2), phosphorus pentoxide (P4O10), selenium dioxide (SeO2), sulfur trioxide (SO3) or metal oxide. Examples of the metal oxide are selected from zinc oxide (ZnO), aluminium oxide (Al2O3), iron(II,III) oxide (Fe3O4), calcium oxide (CaO), ruthenium tetroxide (RuO4), osmium(VIII) oxide (OsO4), iridium tetroxide (IrO4), indium tin oxide (In2O3:SnO2), xenon tetroxide (XeO4), nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, tungsten oxide, tantalum oxide, molybdenum oxide and copper oxide. - In some embodiments, the
dielectric layer 42 is over thepassivation layer 40 and covers a portion of themetal pad 41. Both of thepassivation 40 and thedielectric layer 42 are patterned in order to have a recess to expose a portion of themetal pad 41. The exposedmetal pad 41 serves as an electrical contact between thedevice 14 and other conductive trace, for example, a post passivation interconnect (PPI) 31. In addition, thedielectric layer 42 is also over theconductive pad 71 and theseal ring structure 50. In certain embodiments, thedielectric layer 42 is formed of a polymeric material such as epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like. - The
PPI 31 is on thedielectric layer 42 and routes into theassembly isolation region 12 so as to be electrically coupled with the underlying current conductingtrace 511, which is extended from theconductive layer 51. Theextended portion 311 ofPPI 31 and theextended portion 511 of theconductive layer 51 define anelectric component 81. In some embodiments, theelectric component 81 is a capacitor. The dielectric within the capacitor includes two layers, thepassivation layer 40 and thedielectric layer 42, both of which are used to maintain the electrostatic field between thePPI 31 and theconductive layer 51. - In some embodiments, the
PPI 31 extends into the recess of thepassivation layer 40 and thedielectric layer 42. The extendingportion 312 of thePPI 31 may line the bottom and sidewalls of the recess and electrically couple to themetal pad 41. In other words, theelectric component 81 is electrically coupled to thedevice 14 through the underlying theinterconnect structure 17. In certain embodiments, thePPI 31 is formed of conductive material such as gold, silver, copper, nickel, tungsten, aluminum, and/or alloys thereof. - Referring to
FIG. 8 in conjunction withFIG. 1 , a cross-sectional view is illustrated of another embodiment ofsemiconductor structure 10.Conductive pad 71 is distributed under apolymer layer 90, which surrounds a portion of thebump 91. Theconductive pad 71 includes several segments, 71 a, 71 b, 71 c and 71 d.Segments seal ring region 13 andsegments assembly isolation region 12.Segment 71 a is at an exterior side above theseal ring structure 50 and closer to the chip edge or scribe line.Segment 71 d is at an inner side of theassembly isolation region 12 and closer to thecircuit region 11. - The
semiconductor structure 10 further includes a conductive via 631 and aconductive feature 63, which is formed at the same layer with the topconductive layer 51 and the metal layer Mtop. Theconductive feature 63 is electrically connected to theconductive pad 71 through the conductive via 631, which is within thedielectric layer 43. A conductive layer M3 extends into theassembly isolation region 12. A contact via 60 is electrically connected between theconductive structure 63 and the conductive layer M3 so as to form an electric component, such as an inductor. In this case, theconductive pad 71 is patterned in an inductor configuration such as a coil or a spiral as shown inFIG. 9 . In some embodiments, theconductive layer 51 and/or the conductive layer M3 are extended into theassembly isolation region 12 to form a dual coil structure in a same layer. - A method for manufacturing a semiconductor structure, which includes several electric components in the assembly isolation region, is designed for extending the number of electric components around the die. The method includes a number of operations and the description and illustrations are not deemed as a limitation as the order of the operations.
-
FIG. 10 is a diagram of amethod 1000 for fabricating a semiconductor structure in accordance with some embodiments of the present disclosure. Themethod 1000 includes several operations, which are discussed in detail with reference toFIGS. 5 to 19 . Atoperation 1100, a circuit region, a seal ring region and an assembly isolation region are defined, wherein the assembly isolation region is between the circuit region and the seal ring region. Atoperation 1200, a first current conducting trace is routed from the circuit region into the assembly isolation region. Atoperation 1300, a second current conducting trace is routed from the seal ring region into the assembly isolation region. Atoperation 1400, the first current conducting trace and the second current conducting trace are coupled to form an electric component. -
FIGS. 11 to 19 have been simplified for a better understanding of the inventive concepts of the present disclosure. InFIGS. 11 to 19 , elements with same labeling numbers as those inFIGS. 1 to 9 are previously discussed with reference thereto and are not repeated here for simplicity. - Referring to
FIG. 11 ,semiconductor substrate 110 with thedevice 14 is received. The inter-layer dielectric (ILD) 15 is formed on thesemiconductor substrate 110 through any suitable techniques such as a high aspect ratio process (HARP) and/or a high density plasma (HDP) CVD operation. The contact plugs 16 and the contact bars 21 are formed in theILD 15 in order to be electrically coupled to conductive features (not shown). In certain embodiments, the formation of the contact plugs 16 and the contact bars 21 includes, for example,etching ILD 15 to form openings through a mask layer, and filling a conductive material into the openings. A planarization may then be performed to remove excess conductive material overILD 15, and the remaining conductive material in the openings forms the contact plugs 16 and the contact bars 21. The region where the contact plugs 16 locate is defined as thecircuit region 11 and the region where the contact bars locate is defined as the seal ring region. In addition, theassembly isolation region 12 is defined between thecircuit region 11 and theseal ring region 13. - Referring to
FIG. 12 , a conductive layer is blanket deposited onILD 15. The conductive layer may include at least one film and be formed by deposition such as sputtering, vaporization, or other suitable methods. In some embodiments, a hybrid deposition method including CVD (Chemical Vapor Deposition) and PVD (Physical Vapor Deposition) is introduced for the deposition. Subsequently, by using conventional photolithography, patterning, and etching techniques, the conductive layers M1 and 51 are patterned in thecircuit region 11 and theseal ring region 13, respectively. And then, the inter-metal dielectrics (IMDs) 18 are formed on the conductive layers M1 and 51 through any suitable techniques such as a high aspect ratio process (HARP) and/or a high density plasma (HDP) CVD operation. Next, vias 172 and vialayers 61 formed in theIMDs 18 are electrically coupled to the contact plugs 16 and the contact bars 21, respectively. In certain embodiments, the formation of thevias 172 and the via layers 61 includes, for example, etchingIMDs 18 to form openings through a mask layer, and filling a conductive material into the openings. A planarization may then be performed to remove excess conductive material overIMDs 18, and the remaining conductive material in the openings forms thevias 172 and the via layers 61. - Referring to
FIG. 13 , similarly, another conductive layer M2 and 51 and another via 172 and vialayer 61 are formed as previously discussed so as to fabricate a part of theinterconnect structure 17 and theseal ring structure 50, respectively. - Referring to
FIG. 14 , a current conducting trace of the conductive layer M3 routing from thecircuit region 11 into theassembly isolation region 12 is formed by the previously mentioned operations such as metal deposition, photolithography, patterning, and etching techniques. In addition, the contact via 60 is formed in theassembly isolation region 12 and the via 172 and vialayer 61 are simultaneously formed in thecircuit region 11 and theseal ring region 13. The contact via 60, the via 172 and the vialayer 61 are formed by the previously identified operations such as etching, metal depositing, and chemical mechanical polishing techniques. - Referring to
FIG. 15 , theconductive feature 63 and the conductive via 631 in theassembly isolation region 12 are formed by the previously discussed operations such as metal deposition, photolithography, patterning, and etching techniques. Theconductive feature 63 is electrically connected with the contact via 60 in theassembly isolation region 12. In some embodiments, the contact via 60 and the conductive via 631 are optional. Without the contact via 60 and the conductive via 631, the conductive layer M3 is still capable of forming other type of the electric component such as a capacitor. - Referring to
FIG. 16 , thetop metal pad 41 and theconductive pad 71 are patterned over theinterconnect structure 17 and theseal ring structure 50 by using conventional photolithography, patterning, and etching techniques. The pattern of theconductive pad 71 includes several segments, 71 a, 71 b, 71 c, and 71 d as illustrated inFIG. 9 . Theconductive pad 71 is electrically connected to theinterconnect structure 17 through theconductive feature 63, the contact via 60 and the conductive via 631 so as to form anelectric component 82, such as an inductor - Referring to
FIG. 17 , thepassivation layer 40 is deposited by any suitable techniques such as a high aspect ratio process (HARP) and/or a high density plasma (HDP) CVD operation. In addition, a portion of thepassivation layer 40 is removed by using photolithography with a photoresist layer and etching techniques. The photolithography operation may include spin-coating, soft-baking, exposure, post-backing, developing, rinsing, drying and other suitable operation. - Referring to
FIG. 18 , thedielectric layer 42 is disposed on thepassivation layer 40 by using spin-coating techniques. A portion of thedielectric layer 42, atop thepad 41, is removed to form a recess in subsequent operations. The removing operation may be implemented by exposure, developing, rinsing, drying and other suitable operations. - Referring to
FIG. 19 , thePPI 31 is disposed on thedielectric layer 42 and the recess to form an electrical connection with themetal pad 41. Thebump 91 is located on a portion of thePPI 31 by traditional bump-planting techniques. Subsequently, after thepolymer layer 90 covers thedielectric layer 42, thePPI 31 and a portion of thebump 91 through spin-coating techniques, thesemiconductor structure 10 as previously shown inFIG. 8 is completed. - In some embodiments, a semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively includes a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.
- In some embodiments, a semiconductor structure includes a circuit region, and a seal ring region. The seal ring region surrounds the circuit region and is separated from the circuit region by an assembly isolation region. The first current conducting trace is in the circuit region and a second current conducting trace is in the seal ring region. The first current conducting trace and the second current conducting trace respectively extend into the assembly isolation region and mutually form an electric component.
- In some embodiments, a method for fabricating a semiconductor structure includes defining a circuit region, a seal ring region, and an assembly isolation region between the circuit region and the seal ring region. The method also includes routing a first current conducting trace from the circuit region into the assembly isolation region. The method also includes routing a second current conducting trace from the seal ring region into the assembly isolation region. The method also includes coupling the first current conducting trace and the second current conducting trace to form an electric component.
- Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
- Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed as to imply that these operations are necessarily order dependent. Alternative ordering will be appreciated by one skilled in the art having the benefit of this description. Further, it will be understood that not all operations are necessarily present in each embodiment provided herein. It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments.
- Further, unless specified otherwise, “first,” “second,” or the like are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc. For example, a first channel and a second channel generally correspond to channel A and channel B or two different or two identical channels or the same channel.
- As used in this application, or is intended to mean an inclusive or rather than an exclusive “or”. In addition, “a” and an as used in this application are generally to be construed to mean one or more unless specified otherwise or clear from context to be directed to a singular form. Furthermore, to the extent that “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to “comprising”.
Claims (26)
1. A semiconductor structure, comprising:
a circuit region including a first conductive layer;
a seal ring region including a second conductive layer; and
an assembly isolation region between the circuit region and the seal ring region, wherein the first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region,
wherein one end of the electric component is in the seal ring region and the other end of the electric component is in the circuit region.
2. (canceled)
3. The semiconductor structure of claim 1 , further comprising a dielectric between the extended portion of the first conductive layer and the extended portion of the second conductive layer.
4. The semiconductor structure of claim 3 , wherein a thickness uniformity of the dielectric is within about 0.5%.
5. The semiconductor structure of claim 1 , wherein the first conductive layer is an interconnect of the circuit region.
6. (canceled)
7. (canceled)
8. The semiconductor structure of claim 1 , wherein the extended portion of the second conductive layer is above the extended portion of the first conductive layer.
9. The semiconductor structure of claim 1 , wherein the electric component is an inductor.
10. A semiconductor structure, comprising:
a circuit region;
a seal ring region surrounding the circuit region and separated from the circuit region by an assembly isolation region; and
a first current conducting trace in the circuit region and a second current conducting trace in the seal ring region, wherein the first current conducting trace and the second current conducting trace respectively extend into the assembly isolation region and mutually form an electric component,
wherein one end of the electric component is in the seal ring region and the other end of the electric component is in the circuit region.
11. The semiconductor structure of claim 10 , wherein the first current conducting trace is a semiconductive or conductive material.
12. (canceled)
13. The semiconductor structure of claim 10 , wherein the second current conducting trace is a semiconductive or conductive material.
14. The semiconductor structure of claim 13 , wherein the second current conducting trace includes silicon, copper, tungsten, or aluminum.
15. The semiconductor structure of claim 10 , wherein the first current conducting trace is electrically coupled to the second current conducting trace.
16. The semiconductor structure of claim 10 , wherein the first current conducting trace and the second current conducting trace respectively extend into the assembly isolation region in a coil configuration.
17. (canceled)
18. A method for manufacturing a semiconductor structure, comprising:
defining a circuit region, a seal ring region, and an assembly isolation region between the circuit region and the seal ring region;
routing a first current conducting trace from the circuit region into the assembly isolation region;
routing a second current conducting trace from the seal ring region into the assembly isolation region; and
coupling the first current conducting trace and the second current conducting trace to form an electric component,
wherein one end of the electric component is routed in the seal ring region and the other end of the electric component is routed in the circuit region.
19. (canceled)
20. (canceled)
21. The semiconductor structure of claim 1 , wherein the second conductive layer comprises segments located in the seal ring region and the assembly isolation region.
22. The semiconductor structure of claim 1 , wherein the second conductive layer extends into the assembly isolation region in a coil configuration.
23. The semiconductor structure of claim 10 , wherein the first current conducting trace comprises an interconnect of the circuit region.
24. The semiconductor structure of claim 23 , wherein the second current conducting trace comprises a conductive pad over an extended portion of the interconnect structure.
25. The method of claim 18 , wherein the coupling the first current conducting trace and the second current conducting trace comprises forming a via layer partially positioned in the assembly isolation region.
26. The method of claim 25 , wherein the forming the via layer comprises forming a via in the circuit region, a via in the seal ring region, and a via in the assembly isolation region.
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US20190237553A1 (en) | 2019-08-01 |
US11177355B2 (en) | 2021-11-16 |
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